1 /* SPDX-License-Identifier: BSD-3-Clause
5 #ifndef _PFE_HIF_LIB_H_
6 #define _PFE_HIF_LIB_H_
8 #define HIF_CL_REQ_TIMEOUT 10
12 REQUEST_CL_REGISTER = 0,
13 REQUEST_CL_UNREGISTER,
18 /* Event to indicate that client rx queue is reached water mark level */
20 /* Event to indicate that, packet received for client */
22 /* Event to indicate that, packet tx done for client */
27 /*structure to store client queue info */
29 /*structure to store client queue info */
30 struct hif_client_rx_queue {
31 struct rx_queue_desc *base;
40 struct hif_client_tx_queue {
41 struct tx_queue_desc *base;
46 unsigned long jiffies_last_packet;
65 struct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];
66 struct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];
67 int (*event_handler)(void *data, int event, int qno);
68 unsigned long queue_mask[HIF_EVENT_MAX];
74 * Client specific shared memory
75 * It contains number of Rx/Tx queues, base addresses and queue sizes
77 struct hif_client_shm {
78 u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */
79 unsigned long rx_qbase; /*Rx queue base address */
80 u32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */
81 unsigned long tx_qbase; /* Tx queue base address */
82 u32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */
85 /*Client shared memory ctrl bit description */
86 #define CLIENT_CTRL_RX_Q_CNT_OFST 0
87 #define CLIENT_CTRL_TX_Q_CNT_OFST 8
88 #define CLIENT_CTRL_RX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \
90 #define CLIENT_CTRL_TX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \
94 * Shared memory used to communicate between HIF driver and host/client drivers
95 * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be
96 * initialized with host buffers and buffers count in the pool.
97 * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT.
101 u32 rx_buf_pool_cnt; /*Number of rx buffers available*/
102 /*Rx buffers required to initialize HIF rx descriptors */
103 struct rte_mempool *pool;
104 void *rx_buf_pool[HIF_RX_DESC_NT];
105 unsigned long g_client_status[2]; /*Global client status bit mask */
106 /* Client specific shared memory */
107 struct hif_client_shm client[HIF_CLIENTS_MAX];
110 #define CL_DESC_OWN BIT(31)
111 /* This sets owner ship to HIF driver */
112 #define CL_DESC_LAST BIT(30)
113 /* This indicates last packet for multi buffers handling */
114 #define CL_DESC_FIRST BIT(29)
115 /* This indicates first packet for multi buffers handling */
117 #define CL_DESC_BUF_LEN(x) ((x) & 0xFFFF)
118 #define CL_DESC_FLAGS(x) (((x) & 0xF) << 16)
119 #define CL_DESC_GET_FLAGS(x) (((x) >> 16) & 0xF)
121 struct rx_queue_desc {
123 u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
127 struct tx_queue_desc {
129 u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
132 /* HIF Rx is not working properly for 2-byte aligned buffers and
133 * ip_header should be 4byte aligned for better iperformance.
134 * "ip_header = 64 + 6(hif_header) + 14 (MAC Header)" will be 4byte aligned.
135 * In case HW parse support:
136 * "ip_header = 64 + 6(hif_header) + 16 (parse) + 14 (MAC Header)" will be
139 #define PFE_HIF_SIZE sizeof(struct hif_hdr)
141 #ifdef RTE_LIBRTE_PFE_SW_PARSE
142 #define PFE_PKT_HEADER_SZ PFE_HIF_SIZE
144 #define PFE_PKT_HEADER_SZ (PFE_HIF_SIZE + sizeof(struct pfe_parse))
147 #define MAX_L2_HDR_SIZE 14 /* Not correct for VLAN/PPPoE */
148 #define MAX_L3_HDR_SIZE 20 /* Not correct for IPv6 */
149 #define MAX_L4_HDR_SIZE 60 /* TCP with maximum options */
150 #define MAX_HDR_SIZE (MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE \
152 /* Used in page mode to clamp packet size to the maximum supported by the hif
153 *hw interface (<16KiB)
155 #define MAX_PFE_PKT_SIZE 16380UL
157 extern unsigned int emac_txq_cnt;
159 int pfe_hif_lib_init(struct pfe *pfe);
160 void pfe_hif_lib_exit(struct pfe *pfe);
162 #endif /* _PFE_HIF_LIB_H_ */