2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include <rte_memzone.h>
10 #include <rte_errno.h>
15 #include "ecore_iov_api.h"
16 #include "ecore_mcp_api.h"
17 #include "ecore_l2_api.h"
19 /* Array of memzone pointers */
20 static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE];
21 /* Counter to track current memzone allocated */
22 uint16_t ecore_mz_count;
24 unsigned long qede_log2_align(unsigned long n)
26 unsigned long ret = n ? 1 : 0;
27 unsigned long _n = n >> 1;
40 u32 qede_osal_log2(u32 val)
50 inline void qede_set_bit(u32 nr, unsigned long *addr)
52 __sync_fetch_and_or(addr, (1UL << nr));
55 inline void qede_clr_bit(u32 nr, unsigned long *addr)
57 __sync_fetch_and_and(addr, ~(1UL << nr));
60 inline bool qede_test_bit(u32 nr, unsigned long *addr)
65 res = ((*addr) & (1UL << nr)) != 0;
70 static inline u32 qede_ffb(unsigned long word)
72 unsigned long first_bit;
74 first_bit = __builtin_ffsl(word);
75 return first_bit ? (first_bit - 1) : OSAL_BITS_PER_UL;
78 inline u32 qede_find_first_bit(unsigned long *addr, u32 limit)
82 OSAL_BUILD_BUG_ON(!limit);
83 nwords = (limit - 1) / OSAL_BITS_PER_UL + 1;
84 for (i = 0; i < nwords; i++)
88 return (i == nwords) ? limit : i * OSAL_BITS_PER_UL + qede_ffb(addr[i]);
91 static inline u32 qede_ffz(unsigned long word)
93 unsigned long first_zero;
95 first_zero = __builtin_ffsl(~word);
96 return first_zero ? (first_zero - 1) : OSAL_BITS_PER_UL;
99 inline u32 qede_find_first_zero_bit(unsigned long *addr, u32 limit)
103 OSAL_BUILD_BUG_ON(!limit);
104 nwords = (limit - 1) / OSAL_BITS_PER_UL + 1;
105 for (i = 0; i < nwords && ~(addr[i]) == 0; i++);
106 return (i == nwords) ? limit : i * OSAL_BITS_PER_UL + qede_ffz(addr[i]);
109 void qede_vf_fill_driver_data(struct ecore_hwfn *hwfn,
110 __rte_unused struct vf_pf_resc_request *resc_req,
111 struct ecore_vf_acquire_sw_info *vf_sw_info)
113 vf_sw_info->os_type = VFPF_ACQUIRE_OS_LINUX_USERSPACE;
114 vf_sw_info->override_fw_version = 1;
117 void *osal_dma_alloc_coherent(struct ecore_dev *p_dev,
118 dma_addr_t *phys, size_t size)
120 const struct rte_memzone *mz;
121 char mz_name[RTE_MEMZONE_NAMESIZE];
122 uint32_t core_id = rte_lcore_id();
123 unsigned int socket_id;
125 if (ecore_mz_count >= RTE_MAX_MEMZONE) {
126 DP_ERR(p_dev, "Memzone allocation count exceeds %u\n",
132 OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
133 snprintf(mz_name, sizeof(mz_name) - 1, "%lx",
134 (unsigned long)rte_get_timer_cycles());
135 if (core_id == (unsigned int)LCORE_ID_ANY)
136 core_id = rte_get_master_lcore();
137 socket_id = rte_lcore_to_socket_id(core_id);
138 mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
139 RTE_MEMZONE_IOVA_CONTIG, RTE_CACHE_LINE_SIZE);
141 DP_ERR(p_dev, "Unable to allocate DMA memory "
142 "of size %zu bytes - %s\n",
143 size, rte_strerror(rte_errno));
148 ecore_mz_mapping[ecore_mz_count++] = mz;
149 DP_VERBOSE(p_dev, ECORE_MSG_SP,
150 "Allocated dma memory size=%zu phys=0x%lx"
151 " virt=%p core=%d\n",
152 mz->len, (unsigned long)mz->iova, mz->addr, core_id);
156 void *osal_dma_alloc_coherent_aligned(struct ecore_dev *p_dev,
157 dma_addr_t *phys, size_t size, int align)
159 const struct rte_memzone *mz;
160 char mz_name[RTE_MEMZONE_NAMESIZE];
161 uint32_t core_id = rte_lcore_id();
162 unsigned int socket_id;
164 if (ecore_mz_count >= RTE_MAX_MEMZONE) {
165 DP_ERR(p_dev, "Memzone allocation count exceeds %u\n",
171 OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
172 snprintf(mz_name, sizeof(mz_name) - 1, "%lx",
173 (unsigned long)rte_get_timer_cycles());
174 if (core_id == (unsigned int)LCORE_ID_ANY)
175 core_id = rte_get_master_lcore();
176 socket_id = rte_lcore_to_socket_id(core_id);
177 mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
178 RTE_MEMZONE_IOVA_CONTIG, align);
180 DP_ERR(p_dev, "Unable to allocate DMA memory "
181 "of size %zu bytes - %s\n",
182 size, rte_strerror(rte_errno));
187 ecore_mz_mapping[ecore_mz_count++] = mz;
188 DP_VERBOSE(p_dev, ECORE_MSG_SP,
189 "Allocated aligned dma memory size=%zu phys=0x%lx"
190 " virt=%p core=%d\n",
191 mz->len, (unsigned long)mz->iova, mz->addr, core_id);
195 void osal_dma_free_mem(struct ecore_dev *p_dev, dma_addr_t phys)
199 for (j = 0 ; j < ecore_mz_count; j++) {
200 if (phys == ecore_mz_mapping[j]->iova) {
201 DP_VERBOSE(p_dev, ECORE_MSG_SP,
202 "Free memzone %s\n", ecore_mz_mapping[j]->name);
203 rte_memzone_free(ecore_mz_mapping[j]);
208 DP_ERR(p_dev, "Unexpected memory free request\n");
211 #ifdef CONFIG_ECORE_ZIPPED_FW
212 u32 qede_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len,
213 u8 *input_buf, u32 max_size, u8 *unzip_buf)
217 p_hwfn->stream->next_in = input_buf;
218 p_hwfn->stream->avail_in = input_len;
219 p_hwfn->stream->next_out = unzip_buf;
220 p_hwfn->stream->avail_out = max_size;
222 rc = inflateInit2(p_hwfn->stream, MAX_WBITS);
226 "zlib init failed, rc = %d\n", rc);
230 rc = inflate(p_hwfn->stream, Z_FINISH);
231 inflateEnd(p_hwfn->stream);
233 if (rc != Z_OK && rc != Z_STREAM_END) {
235 "FW unzip error: %s, rc=%d\n", p_hwfn->stream->msg,
240 return p_hwfn->stream->total_out / 4;
245 qede_get_mcp_proto_stats(struct ecore_dev *edev,
246 enum ecore_mcp_protocol_type type,
247 union ecore_mcp_protocol_stats *stats)
249 struct ecore_eth_stats lan_stats;
251 if (type == ECORE_MCP_LAN_STATS) {
252 ecore_get_vport_stats(edev, &lan_stats);
255 stats->lan_stats.ucast_rx_pkts = lan_stats.common.rx_ucast_pkts;
256 stats->lan_stats.ucast_tx_pkts = lan_stats.common.tx_ucast_pkts;
258 stats->lan_stats.fcs_err = -1;
260 DP_INFO(edev, "Statistics request type %d not supported\n",
266 qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)
271 case ECORE_HW_ERR_FAN_FAIL:
272 strcpy(err_str, "Fan Failure");
274 case ECORE_HW_ERR_MFW_RESP_FAIL:
275 strcpy(err_str, "MFW Response Failure");
277 case ECORE_HW_ERR_HW_ATTN:
278 strcpy(err_str, "HW Attention");
280 case ECORE_HW_ERR_DMAE_FAIL:
281 strcpy(err_str, "DMAE Failure");
283 case ECORE_HW_ERR_RAMROD_FAIL:
284 strcpy(err_str, "Ramrod Failure");
286 case ECORE_HW_ERR_FW_ASSERT:
287 strcpy(err_str, "FW Assertion");
290 strcpy(err_str, "Unknown");
293 DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str);
294 ecore_int_attn_clr_enable(p_hwfn->p_dev, true);
297 u32 qede_crc32(u32 crc, u8 *ptr, u32 length)
303 for (i = 0; i < 8; i++)
304 crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);