2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
10 #define __COMMON_HSI__
11 /********************************/
12 /* PROTOCOL COMMON FW CONSTANTS */
13 /********************************/
15 /* Temporarily here should be added to HSI automatically by resource allocation
18 #define T_TEST_AGG_INT_TEMP 6
19 #define M_TEST_AGG_INT_TEMP 8
20 #define U_TEST_AGG_INT_TEMP 6
21 #define X_TEST_AGG_INT_TEMP 14
22 #define Y_TEST_AGG_INT_TEMP 4
23 #define P_TEST_AGG_INT_TEMP 4
25 #define X_FINAL_CLEANUP_AGG_INT 1
27 #define EVENT_RING_PAGE_SIZE_BYTES 4096
29 #define NUM_OF_GLOBAL_QUEUES 128
30 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
32 #define ISCSI_CDU_TASK_SEG_TYPE 0
33 #define FCOE_CDU_TASK_SEG_TYPE 0
34 #define RDMA_CDU_TASK_SEG_TYPE 1
36 #define FW_ASSERT_GENERAL_ATTN_IDX 32
38 #define MAX_PINNED_CCFC 32
40 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3
42 /* Queue Zone sizes in bytes */
43 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/
44 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX
45 *producer of VFs in backward compatibility
48 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/
49 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/
50 #define YSTORM_QZONE_SIZE 0
51 #define PSTORM_QZONE_SIZE 0
53 /*Log of mstorm default VF zone size.*/
54 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
55 /*Maximum number of RX queues that can be allocated to VF by default*/
56 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
57 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone
58 * size. Up to 96 VF supported in this mode
60 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
61 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size.
62 * Up to 48 VF supported in this mode
64 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
67 /********************************/
68 /* CORE (LIGHT L2) FW CONSTANTS */
69 /********************************/
71 #define CORE_LL2_MAX_RAMROD_PER_CON 8
72 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096
73 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096
74 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096
75 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1
77 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12
79 #define CORE_SPQE_PAGE_SIZE_BYTES 4096
81 #define MAX_NUM_LL2_RX_QUEUES 32
82 #define MAX_NUM_LL2_TX_STATS_COUNTERS 32
85 /****************************************************************************/
86 /* Include firmware version number only- do not add constants here to avoid */
87 /* redundunt compilations */
88 /****************************************************************************/
91 #define FW_MAJOR_VERSION 8
92 #define FW_MINOR_VERSION 14
93 #define FW_REVISION_VERSION 6
94 #define FW_ENGINEERING_VERSION 0
96 /***********************/
97 /* COMMON HW CONSTANTS */
98 /***********************/
101 #define MAX_NUM_PORTS_K2 (4)
102 #define MAX_NUM_PORTS_BB (2)
103 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
105 #define MAX_NUM_PFS_K2 (16)
106 #define MAX_NUM_PFS_BB (8)
107 #define MAX_NUM_PFS (MAX_NUM_PFS_K2)
108 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
110 #define MAX_NUM_VFS_BB (120)
111 #define MAX_NUM_VFS_K2 (192)
112 #define E4_MAX_NUM_VFS (MAX_NUM_VFS_K2)
114 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
115 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)
116 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + E4_MAX_NUM_VFS)
118 /* in both BB and K2, the VF number starts from 16. so for arrays containing all
119 * possible PFs and VFs - we need a constant for this size
121 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)
122 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2)
123 #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + E4_MAX_NUM_VFS)
125 #define MAX_NUM_VPORTS_K2 (208)
126 #define MAX_NUM_VPORTS_BB (160)
127 #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2)
129 #define MAX_NUM_L2_QUEUES_K2 (320)
130 #define MAX_NUM_L2_QUEUES_BB (256)
131 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2)
133 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
135 #define NUM_PHYS_TCS_4PORT_K2 (4)
136 #define NUM_OF_PHYS_TCS (8)
138 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)
139 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
141 #define LB_TC (NUM_OF_PHYS_TCS)
143 /* Num of possible traffic priority values */
144 #define NUM_OF_PRIO (8)
146 #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
147 #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
148 #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
149 #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
152 #define E4_NUM_OF_CONNECTION_TYPES (8)
153 #define NUM_OF_TASK_TYPES (8)
154 #define NUM_OF_LCIDS (320)
155 #define NUM_OF_LTIDS (320)
158 #define MASTER_CLK_FREQ_E4 (375e6)
159 #define STORM_CLK_FREQ_E4 (1000e6)
160 #define CLK25M_CLK_FREQ_E4 (25e6)
162 /* Global PXP windows (GTT) */
163 #define NUM_OF_GTT 19
164 #define GTT_DWORD_SIZE_BITS 10
165 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2)
166 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS)
169 #define TOOLS_VERSION 10
174 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
175 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
177 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
178 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
186 #define DQ_DEMS_LEGACY 0
187 #define DQ_DEMS_TOE_MORE_TO_SEND 3
188 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4
189 #define DQ_DEMS_ROCE_CQ_CONS 7
191 /* XCM agg val selection (HW) */
192 #define DQ_XCM_AGG_VAL_SEL_WORD2 0
193 #define DQ_XCM_AGG_VAL_SEL_WORD3 1
194 #define DQ_XCM_AGG_VAL_SEL_WORD4 2
195 #define DQ_XCM_AGG_VAL_SEL_WORD5 3
196 #define DQ_XCM_AGG_VAL_SEL_REG3 4
197 #define DQ_XCM_AGG_VAL_SEL_REG4 5
198 #define DQ_XCM_AGG_VAL_SEL_REG5 6
199 #define DQ_XCM_AGG_VAL_SEL_REG6 7
201 /* XCM agg val selection (FW) */
202 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \
203 DQ_XCM_AGG_VAL_SEL_WORD2
204 #define DQ_XCM_ETH_TX_BD_CONS_CMD \
205 DQ_XCM_AGG_VAL_SEL_WORD3
206 #define DQ_XCM_CORE_TX_BD_CONS_CMD \
207 DQ_XCM_AGG_VAL_SEL_WORD3
208 #define DQ_XCM_ETH_TX_BD_PROD_CMD \
209 DQ_XCM_AGG_VAL_SEL_WORD4
210 #define DQ_XCM_CORE_TX_BD_PROD_CMD \
211 DQ_XCM_AGG_VAL_SEL_WORD4
212 #define DQ_XCM_CORE_SPQ_PROD_CMD \
213 DQ_XCM_AGG_VAL_SEL_WORD4
214 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
215 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
216 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
217 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
218 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
219 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
220 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
221 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
222 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
223 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
224 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
225 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
227 /* UCM agg val selection (HW) */
228 #define DQ_UCM_AGG_VAL_SEL_WORD0 0
229 #define DQ_UCM_AGG_VAL_SEL_WORD1 1
230 #define DQ_UCM_AGG_VAL_SEL_WORD2 2
231 #define DQ_UCM_AGG_VAL_SEL_WORD3 3
232 #define DQ_UCM_AGG_VAL_SEL_REG0 4
233 #define DQ_UCM_AGG_VAL_SEL_REG1 5
234 #define DQ_UCM_AGG_VAL_SEL_REG2 6
235 #define DQ_UCM_AGG_VAL_SEL_REG3 7
237 /* UCM agg val selection (FW) */
238 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2
239 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3
240 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0
241 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2
243 /* TCM agg val selection (HW) */
244 #define DQ_TCM_AGG_VAL_SEL_WORD0 0
245 #define DQ_TCM_AGG_VAL_SEL_WORD1 1
246 #define DQ_TCM_AGG_VAL_SEL_WORD2 2
247 #define DQ_TCM_AGG_VAL_SEL_WORD3 3
248 #define DQ_TCM_AGG_VAL_SEL_REG1 4
249 #define DQ_TCM_AGG_VAL_SEL_REG2 5
250 #define DQ_TCM_AGG_VAL_SEL_REG6 6
251 #define DQ_TCM_AGG_VAL_SEL_REG9 7
253 /* TCM agg val selection (FW) */
254 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1
255 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0
257 /* XCM agg counter flag selection (HW) */
258 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
259 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
260 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2
261 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3
262 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4
263 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5
264 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6
265 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7
267 /* XCM agg counter flag selection (FW) */
268 #define DQ_XCM_ETH_DQ_CF_CMD (1 << \
269 DQ_XCM_AGG_FLG_SHIFT_CF18)
270 #define DQ_XCM_CORE_DQ_CF_CMD (1 << \
271 DQ_XCM_AGG_FLG_SHIFT_CF18)
272 #define DQ_XCM_ETH_TERMINATE_CMD (1 << \
273 DQ_XCM_AGG_FLG_SHIFT_CF19)
274 #define DQ_XCM_CORE_TERMINATE_CMD (1 << \
275 DQ_XCM_AGG_FLG_SHIFT_CF19)
276 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << \
277 DQ_XCM_AGG_FLG_SHIFT_CF22)
278 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << \
279 DQ_XCM_AGG_FLG_SHIFT_CF22)
280 #define DQ_XCM_ETH_TPH_EN_CMD (1 << \
281 DQ_XCM_AGG_FLG_SHIFT_CF23)
282 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
283 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
284 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
285 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23)
286 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
287 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
289 /* UCM agg counter flag selection (HW) */
290 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0
291 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1
292 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2
293 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3
294 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4
295 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5
296 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6
297 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7
299 /* UCM agg counter flag selection (FW) */
300 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
301 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
302 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
303 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
304 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3)
305 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
306 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
308 /* TCM agg counter flag selection (HW) */
309 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0
310 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1
311 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2
312 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3
313 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4
314 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5
315 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6
316 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7
318 /* TCM agg counter flag selection (FW) */
319 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
320 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2)
321 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
322 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
323 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
324 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
325 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
326 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
328 /* PWM address mapping */
329 #define DQ_PWM_OFFSET_DPM_BASE 0x0
330 #define DQ_PWM_OFFSET_DPM_END 0x27
331 #define DQ_PWM_OFFSET_XCM16_BASE 0x40
332 #define DQ_PWM_OFFSET_XCM32_BASE 0x44
333 #define DQ_PWM_OFFSET_UCM16_BASE 0x48
334 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C
335 #define DQ_PWM_OFFSET_UCM16_4 0x50
336 #define DQ_PWM_OFFSET_TCM16_BASE 0x58
337 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C
338 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68
339 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69
340 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
342 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
343 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
344 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4)
345 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2)
346 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
347 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
348 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
350 #define DQ_REGION_SHIFT (12)
353 #define DQ_DPM_WQE_BUFF_SIZE (320)
355 /* Conn type ranges */
356 #define DQ_CONN_TYPE_RANGE_SHIFT (4)
362 /* number of TX queues in the QM */
363 #define MAX_QM_TX_QUEUES_K2 512
364 #define MAX_QM_TX_QUEUES_BB 448
365 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
367 /* number of Other queues in the QM */
368 #define MAX_QM_OTHER_QUEUES_BB 64
369 #define MAX_QM_OTHER_QUEUES_K2 128
370 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
372 /* number of queues in a PF queue group */
373 #define QM_PF_QUEUE_GROUP_SIZE 8
375 /* the size of a single queue element in bytes */
376 #define QM_PQ_ELEMENT_SIZE 4
378 /* base number of Tx PQs in the CM PQ representation.
379 * should be used when storing PQ IDs in CM PQ registers and context
381 #define CM_TX_PQ_BASE 0x200
383 /* number of global Vport/QCN rate limiters */
384 #define MAX_QM_GLOBAL_RLS 256
386 /* QM registers data */
387 #define QM_LINE_CRD_REG_WIDTH 16
388 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1))
389 #define QM_BYTE_CRD_REG_WIDTH 24
390 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1))
391 #define QM_WFQ_CRD_REG_WIDTH 32
392 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1))
393 #define QM_RL_CRD_REG_WIDTH 32
394 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1))
400 #define CAU_FSM_ETH_RX 0
401 #define CAU_FSM_ETH_TX 1
403 /* Number of Protocol Indices per Status Block */
404 #define PIS_PER_SB 12
406 /* fsm is stopped or not valid for this sb */
407 #define CAU_HC_STOPPED_STATE 3
408 /* fsm is working without interrupt coalescing for this sb*/
409 #define CAU_HC_DISABLE_STATE 4
410 /* fsm is working with interrupt coalescing for this sb*/
411 #define CAU_HC_ENABLE_STATE 0
418 #define MAX_SB_PER_PATH_K2 (368)
419 #define MAX_SB_PER_PATH_BB (288)
420 #define MAX_TOT_SB_PER_PATH \
423 #define MAX_SB_PER_PF_MIMD 129
424 #define MAX_SB_PER_PF_SIMD 64
425 #define MAX_SB_PER_VF 64
427 /* Memory addresses on the BAR for the IGU Sub Block */
428 #define IGU_MEM_BASE 0x0000
430 #define IGU_MEM_MSIX_BASE 0x0000
431 #define IGU_MEM_MSIX_UPPER 0x0101
432 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
434 #define IGU_MEM_PBA_MSIX_BASE 0x0200
435 #define IGU_MEM_PBA_MSIX_UPPER 0x0202
436 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
438 #define IGU_CMD_INT_ACK_BASE 0x0400
439 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
440 MAX_TOT_SB_PER_PATH - \
442 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
444 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
445 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
446 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
448 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3
449 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4
450 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5
451 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
453 #define IGU_CMD_PROD_UPD_BASE 0x0600
454 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
455 MAX_TOT_SB_PER_PATH - \
457 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
463 /* Bars for Blocks */
464 #define PXP_BAR_GRC 0
465 #define PXP_BAR_TSDM 0
466 #define PXP_BAR_USDM 0
467 #define PXP_BAR_XSDM 0
468 #define PXP_BAR_MSDM 0
469 #define PXP_BAR_YSDM 0
470 #define PXP_BAR_PSDM 0
471 #define PXP_BAR_IGU 0
475 #define PXP_NUM_PF_WINDOWS 12
476 #define PXP_PER_PF_ENTRY_SIZE 8
477 #define PXP_NUM_GLOBAL_WINDOWS 243
478 #define PXP_GLOBAL_ENTRY_SIZE 4
479 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4
480 #define PXP_PF_WINDOW_ADMIN_START 0
481 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000
482 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \
483 PXP_PF_WINDOW_ADMIN_LENGTH - 1)
484 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0
485 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \
486 PXP_PER_PF_ENTRY_SIZE)
487 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \
488 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
489 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200
490 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \
491 PXP_GLOBAL_ENTRY_SIZE)
492 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
493 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
494 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
495 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0
496 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4
497 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8
498 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc
500 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000
501 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS
502 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000
503 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
504 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
505 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
506 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \
507 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \
508 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
510 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
511 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
512 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS
513 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000
514 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
515 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
516 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
517 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
518 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
519 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
522 /*#define PXP_BAR0_START_GRC 0x1000 */
523 /*#define PXP_BAR0_GRC_LENGTH 0xBFF000 */
524 #define PXP_BAR0_START_GRC 0x0000
525 #define PXP_BAR0_GRC_LENGTH 0x1C00000
526 #define PXP_BAR0_END_GRC \
527 (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1)
529 #define PXP_BAR0_START_IGU 0x1C00000
530 #define PXP_BAR0_IGU_LENGTH 0x10000
531 #define PXP_BAR0_END_IGU \
532 (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1)
534 #define PXP_BAR0_START_TSDM 0x1C80000
535 #define PXP_BAR0_SDM_LENGTH 0x40000
536 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
537 #define PXP_BAR0_END_TSDM \
538 (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1)
540 #define PXP_BAR0_START_MSDM 0x1D00000
541 #define PXP_BAR0_END_MSDM \
542 (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1)
544 #define PXP_BAR0_START_USDM 0x1D80000
545 #define PXP_BAR0_END_USDM \
546 (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1)
548 #define PXP_BAR0_START_XSDM 0x1E00000
549 #define PXP_BAR0_END_XSDM \
550 (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1)
552 #define PXP_BAR0_START_YSDM 0x1E80000
553 #define PXP_BAR0_END_YSDM \
554 (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1)
556 #define PXP_BAR0_START_PSDM 0x1F00000
557 #define PXP_BAR0_END_PSDM \
558 (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1)
560 #define PXP_BAR0_FIRST_INVALID_ADDRESS \
561 (PXP_BAR0_END_PSDM + 1)
563 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
564 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
567 #define PXP_NUM_ILT_RECORDS_BB 7600
568 #define PXP_NUM_ILT_RECORDS_K2 11000
569 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
573 #define PXP_QUEUES_ZONE_MAX_NUM 320
581 #define PRM_DMA_PAD_BYTES_NUM 2
587 #define SDM_OP_GEN_TRIG_NONE 0
588 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1
589 #define SDM_OP_GEN_TRIG_AGG_INT 2
590 #define SDM_OP_GEN_TRIG_LOADER 4
591 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
592 #define SDM_OP_GEN_TRIG_RELEASE_THREAD 7
594 /***********************************************************/
595 /* Completion types */
596 /***********************************************************/
598 #define SDM_COMP_TYPE_NONE 0
599 #define SDM_COMP_TYPE_WAKE_THREAD 1
600 #define SDM_COMP_TYPE_AGG_INT 2
601 /* Send direct message to local CM and/or remote CMs. Destinations are defined
602 * by vector in CompParams.
604 #define SDM_COMP_TYPE_CM 3
605 #define SDM_COMP_TYPE_LOADER 4
606 /* Send direct message to PXP (like "internal write" command) to write to remote
607 * Storm RAM via remote SDM
609 #define SDM_COMP_TYPE_PXP 5
610 /* Indicate error per thread */
611 #define SDM_COMP_TYPE_INDICATE_ERROR 6
612 #define SDM_COMP_TYPE_RELEASE_THREAD 7
613 /* Write to local RAM as a completion */
614 #define SDM_COMP_TYPE_RAM 8
621 /* Number of PBF command queue lines. Each line is 32B. */
622 #define PBF_MAX_CMD_LINES 3328
624 /* Number of BTB blocks. Each block is 256B. */
625 #define BTB_MAX_BLOCKS 1440
631 #define PRS_GFT_CAM_LINES_NO_MATCH 31
632 /* Async data KCQ CQE */
634 /* Context ID of the connection */
636 /* Task Id of the task (for error that happened on a a task) */
638 /* error code - relevant only if the opcode indicates its an error */
640 /* internal fw debug parameter */
645 * Interrupt coalescing TimeSet
647 struct coalescing_timeset {
649 /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */
650 #define COALESCING_TIMESET_TIMESET_MASK 0x7F
651 #define COALESCING_TIMESET_TIMESET_SHIFT 0
652 /* Only if this flag is set, timeset will take effect */
653 #define COALESCING_TIMESET_VALID_MASK 0x1
654 #define COALESCING_TIMESET_VALID_SHIFT 7
657 struct common_queue_zone {
658 __le16 ring_drv_data_consumer;
663 * ETH Rx producers data
665 struct eth_rx_prod_data {
666 __le16 bd_prod /* BD producer. */;
667 __le16 cqe_prod /* CQE producer. */;
671 __le32 lo /* low word for reg-pair */;
672 __le32 hi /* high word for reg-pair */;
676 * Event Ring VF-PF Channel data
678 struct vf_pf_channel_eqe_data {
679 struct regpair msg_addr /* VF-PF message address */;
682 struct iscsi_eqe_data {
683 __le32 cid /* Context ID of the connection */;
684 /* Task Id of the task (for error that happened on a a task) */;
686 /* error code - relevant only if the opcode indicates its an error */
688 u8 error_pdu_opcode_reserved;
689 /* The processed PDUs opcode on which happened the error - updated for specific
690 * error codes, by default=0xFF
692 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
693 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0
694 /* Indication for driver is the error_pdu_opcode field has valid value */
695 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1
696 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6
697 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1
698 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
702 * Event Ring malicious VF data
704 struct malicious_vf_eqe_data {
705 u8 vfId /* Malicious VF ID */;
706 u8 errId /* Malicious VF error */;
711 * Event Ring initial cleanup data
713 struct initial_cleanup_eqe_data {
721 union event_ring_data {
722 u8 bytes[8] /* Byte Array */;
723 struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */;
724 struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */;
725 struct regpair roceHandle /* Dedicated field for RDMA data */;
726 struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */;
727 struct initial_cleanup_eqe_data vf_init_cleanup
728 /* VF Initial Cleanup data */;
730 /* Event Ring Entry */
731 struct event_ring_entry {
732 u8 protocol_id /* Event Protocol ID */;
733 u8 opcode /* Event Opcode */;
734 __le16 reserved0 /* Reserved */;
735 __le16 echo /* Echo value from ramrod data on the host */;
736 u8 fw_return_code /* FW return code for SP ramrods */;
738 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */
739 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
740 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
741 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
742 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
743 union event_ring_data data;
746 /* Multi function mode */
748 ERROR_MODE /* Unsupported mode */,
749 MF_OVLAN /* Multi function based on outer VLAN */,
750 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */,
754 /* Per-protocol connection types */
756 PROTOCOLID_ISCSI /* iSCSI */,
757 PROTOCOLID_FCOE /* FCoE */,
758 PROTOCOLID_ROCE /* RoCE */,
759 PROTOCOLID_CORE /* Core (light L2, slow path core) */,
760 PROTOCOLID_ETH /* Ethernet */,
761 PROTOCOLID_IWARP /* iWARP */,
762 PROTOCOLID_TOE /* TOE */,
763 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */,
764 PROTOCOLID_COMMON /* ProtocolCommon */,
765 PROTOCOLID_TCP /* TCP */,
774 struct ustorm_eth_queue_zone {
775 /* Rx interrupt coalescing TimeSet */
776 struct coalescing_timeset int_coalescing_timeset;
781 struct ustorm_queue_zone {
782 struct ustorm_eth_queue_zone eth;
783 struct common_queue_zone common;
786 /* status block structure */
787 struct cau_pi_entry {
789 /* A per protocol indexPROD value. */
790 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
791 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
792 /* This value determines the TimeSet that the PI is associated with */
793 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
794 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
795 /* Select the FSM within the SB */
796 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
797 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
798 /* Select the FSM within the SB */
799 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF
800 #define CAU_PI_ENTRY_RESERVED_SHIFT 24
803 /* status block structure */
804 struct cau_sb_entry {
806 /* The SB PROD index which is sent to the IGU. */
807 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
808 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0
809 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */
810 #define CAU_SB_ENTRY_STATE0_SHIFT 24
811 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */
812 #define CAU_SB_ENTRY_STATE1_SHIFT 28
814 /* Indicates the RX TimeSet that this SB is associated with. */
815 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
816 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
817 /* Indicates the TX TimeSet that this SB is associated with. */
818 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
819 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
820 /* This value will determine the RX FSM timer resolution in ticks */
821 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
822 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
823 /* This value will determine the TX FSM timer resolution in ticks */
824 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
825 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
826 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
827 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
828 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1
829 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26
830 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
831 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
832 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise
833 * the STAG will be equal to all ones.
835 #define CAU_SB_ENTRY_TPH_MASK 0x1
836 #define CAU_SB_ENTRY_TPH_SHIFT 31
839 /* core doorbell data */
840 struct core_db_data {
842 /* destination of doorbell (use enum db_dest) */
843 #define CORE_DB_DATA_DEST_MASK 0x3
844 #define CORE_DB_DATA_DEST_SHIFT 0
845 /* aggregative command to CM (use enum db_agg_cmd_sel) */
846 #define CORE_DB_DATA_AGG_CMD_MASK 0x3
847 #define CORE_DB_DATA_AGG_CMD_SHIFT 2
848 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */
849 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4
850 #define CORE_DB_DATA_RESERVED_MASK 0x1
851 #define CORE_DB_DATA_RESERVED_SHIFT 5
852 /* aggregative value selection */
853 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
854 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
855 /* bit for every DQ counter flags in CM context that DQ can increment */
860 /* Enum of doorbell aggregative command selection */
861 enum db_agg_cmd_sel {
862 DB_AGG_CMD_NOP /* No operation */,
863 DB_AGG_CMD_SET /* Set the value */,
864 DB_AGG_CMD_ADD /* Add the value */,
865 DB_AGG_CMD_MAX /* Set max of current and new value */,
869 /* Enum of doorbell destination */
871 DB_DEST_XCM /* TX doorbell to XCM */,
872 DB_DEST_UCM /* RX doorbell to UCM */,
873 DB_DEST_TCM /* RX doorbell to TCM */,
880 * Enum of doorbell DPM types
883 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */,
884 DPM_ROCE /* RoCE DPM- to NIG */,
885 /* L2 DPM inline- to PBF, with packet data on doorbell */
887 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */,
892 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM
895 struct db_l2_dpm_data {
896 __le16 icid /* internal CID */;
897 __le16 bd_prod /* bd producer value to update */;
899 /* Size in QWORD-s of the DPM burst */
900 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F
901 #define DB_L2_DPM_DATA_SIZE_SHIFT 0
902 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type)
904 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3
905 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6
906 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */
907 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8
908 /* size of the packet to be transmitted in bytes */
909 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF
910 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16
911 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1
912 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
913 /* In DPM_L2_BD mode: the number of SGE-s */
914 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
915 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28
916 #define DB_L2_DPM_DATA_RESERVED1_MASK 0x1
917 #define DB_L2_DPM_DATA_RESERVED1_SHIFT 31
921 * Structure for SGE in a DPM doorbell of type DPM_L2_BD
923 struct db_l2_dpm_sge {
924 struct regpair addr /* Single continuous buffer */;
925 __le16 nbytes /* Number of bytes in this BD. */;
927 /* The TPH STAG index value */
928 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
929 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
930 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
931 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
932 /* Indicate if ST hint is requested or not */
933 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
934 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
935 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
936 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
940 /* Structure for doorbell address, in legacy mode */
941 struct db_legacy_addr {
943 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
944 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
945 /* doorbell extraction mode specifier- 0 if not used */
946 #define DB_LEGACY_ADDR_DEMS_MASK 0x7
947 #define DB_LEGACY_ADDR_DEMS_SHIFT 2
948 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */
949 #define DB_LEGACY_ADDR_ICID_SHIFT 5
953 * Structure for doorbell address, in PWM mode
957 #define DB_PWM_ADDR_RESERVED0_MASK 0x7
958 #define DB_PWM_ADDR_RESERVED0_SHIFT 0
959 /* Offset in PWM address space */
960 #define DB_PWM_ADDR_OFFSET_MASK 0x7F
961 #define DB_PWM_ADDR_OFFSET_SHIFT 3
962 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */
963 #define DB_PWM_ADDR_WID_SHIFT 10
964 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */
965 #define DB_PWM_ADDR_DPI_SHIFT 12
966 #define DB_PWM_ADDR_RESERVED1_MASK 0xF
967 #define DB_PWM_ADDR_RESERVED1_SHIFT 28
971 * Parameters to RoCE firmware, passed in EDPM doorbell
973 struct db_roce_dpm_params {
975 /* Size in QWORD-s of the DPM burst */
976 #define DB_ROCE_DPM_PARAMS_SIZE_MASK 0x3F
977 #define DB_ROCE_DPM_PARAMS_SIZE_SHIFT 0
978 /* Type of DPM transacation (DPM_ROCE) (use enum db_dpm_type) */
979 #define DB_ROCE_DPM_PARAMS_DPM_TYPE_MASK 0x3
980 #define DB_ROCE_DPM_PARAMS_DPM_TYPE_SHIFT 6
981 /* opcode for ROCE operation */
982 #define DB_ROCE_DPM_PARAMS_OPCODE_MASK 0xFF
983 #define DB_ROCE_DPM_PARAMS_OPCODE_SHIFT 8
984 /* the size of the WQE payload in bytes */
985 #define DB_ROCE_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
986 #define DB_ROCE_DPM_PARAMS_WQE_SIZE_SHIFT 16
987 #define DB_ROCE_DPM_PARAMS_RESERVED0_MASK 0x1
988 #define DB_ROCE_DPM_PARAMS_RESERVED0_SHIFT 27
989 /* RoCE completion flag */
990 #define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
991 #define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
992 #define DB_ROCE_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */
993 #define DB_ROCE_DPM_PARAMS_S_FLG_SHIFT 29
994 #define DB_ROCE_DPM_PARAMS_RESERVED1_MASK 0x3
995 #define DB_ROCE_DPM_PARAMS_RESERVED1_SHIFT 30
999 * Structure for doorbell data, in ROCE DPM mode, for the first doorbell in a
1002 struct db_roce_dpm_data {
1003 __le16 icid /* internal CID */;
1004 __le16 prod_val /* aggregated value to update */;
1005 /* parameters passed to RoCE firmware */
1006 struct db_roce_dpm_params params;
1009 /* Igu interrupt command */
1012 IGU_INT_DISABLE = 1,
1018 /* IGU producer or consumer update command */
1019 struct igu_prod_cons_update {
1020 __le32 sb_id_and_flags;
1021 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
1022 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
1023 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
1024 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
1025 /* interrupt enable/disable/nop (use enum igu_int_cmd) */
1026 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
1027 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
1028 /* (use enum igu_seg_access) */
1029 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
1030 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
1031 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
1032 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
1033 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
1034 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
1035 /* must always be set cleared (use enum command_type_bit) */
1036 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
1037 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
1041 /* Igu segments access for default status block only */
1042 enum igu_seg_access {
1043 IGU_SEG_ACCESS_REG = 0,
1044 IGU_SEG_ACCESS_ATTN = 1,
1050 * Enumeration for L3 type field of parsing_and_err_flags_union. L3Type:
1051 * 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according
1052 * to the last-ethertype)
1063 * Enumeration for l4Protocol field of parsing_and_err_flags_union. L4-protocol
1064 * 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the
1065 * first fragment, the protocol-type should be set to none.
1076 * Parsing and error flags field.
1078 struct parsing_and_err_flags {
1080 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled
1081 * according to the last-ethertype) (use enum l3_type)
1083 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
1084 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
1085 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and
1086 * its not the first fragment, the protocol-type should be set to none.
1087 * (use enum l4_protocol)
1089 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
1090 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
1091 /* Set if the packet is IPv4 fragment. */
1092 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
1093 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
1094 /* Set if VLAN tag exists. Invalid if tunnel type are IP GRE or IP GENEVE. */
1095 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
1096 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
1097 /* Set if L4 checksum was calculated. */
1098 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
1099 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
1100 /* Set for PTP packet. */
1101 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
1102 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
1103 /* Set if PTP timestamp recorded. */
1104 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
1105 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
1106 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6
1109 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
1110 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
1111 /* Set if L4 checksum validation failed. Valid only if L4 checksum was
1114 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
1115 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
1116 /* Set if GRE/VXLAN/GENEVE tunnel detected. */
1117 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
1118 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
1119 /* Set if VLAN tag exists in tunnel header. */
1120 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
1121 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
1122 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or
1123 * tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch
1125 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
1126 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
1127 /* Set if GRE or VXLAN/GENEVE UDP checksum was calculated. */
1128 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
1129 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
1130 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum
1133 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
1134 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
1145 /* Concrete Function ID. */
1146 struct pxp_concrete_fid {
1148 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */
1149 #define PXP_CONCRETE_FID_PFID_SHIFT 0
1150 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */
1151 #define PXP_CONCRETE_FID_PORT_SHIFT 4
1152 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */
1153 #define PXP_CONCRETE_FID_PATH_SHIFT 6
1154 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1
1155 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7
1156 #define PXP_CONCRETE_FID_VFID_MASK 0xFF
1157 #define PXP_CONCRETE_FID_VFID_SHIFT 8
1160 struct pxp_pretend_concrete_fid {
1162 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
1163 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
1164 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
1165 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
1166 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
1167 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
1168 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
1169 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
1172 union pxp_pretend_fid {
1173 struct pxp_pretend_concrete_fid concrete_fid;
1177 /* Pxp Pretend Command Register. */
1178 struct pxp_pretend_cmd {
1179 union pxp_pretend_fid fid;
1181 #define PXP_PRETEND_CMD_PATH_MASK 0x1
1182 #define PXP_PRETEND_CMD_PATH_SHIFT 0
1183 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
1184 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
1185 #define PXP_PRETEND_CMD_PORT_MASK 0x3
1186 #define PXP_PRETEND_CMD_PORT_SHIFT 2
1187 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
1188 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
1189 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
1190 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
1191 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
1192 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
1193 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
1194 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
1195 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
1196 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
1197 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
1198 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
1201 /* PTT Record in PXP Admin Window. */
1202 struct pxp_ptt_entry {
1204 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
1205 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0
1206 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
1207 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
1208 struct pxp_pretend_cmd pretend;
1213 * VF Zone A Permission Register.
1215 struct pxp_vf_zone_a_permission {
1217 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
1218 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
1219 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
1220 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
1221 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
1222 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
1223 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
1224 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
1231 struct rdif_task_context {
1232 __le32 initialRefTag;
1236 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
1237 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
1238 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
1239 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
1240 /* 0 = IP checksum, 1 = CRC */
1241 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
1242 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
1243 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
1244 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
1245 /* 1/2/3 - Protection Type */
1246 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
1247 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
1248 /* 0=0x0000, 1=0xffff */
1249 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1250 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1251 /* Keep reference tag constant */
1252 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
1253 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7
1254 u8 partialDifData[7];
1255 __le16 partialCrcValue;
1256 __le16 partialChecksumValue;
1259 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
1260 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
1261 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
1262 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
1263 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
1264 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
1265 #define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
1266 #define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
1267 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
1268 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
1269 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
1270 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
1271 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
1272 #define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
1273 #define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
1274 /* 0=None, 1=DIF, 2=DIX */
1275 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
1276 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
1277 /* DIF tag right at the beginning of DIF interval */
1278 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
1279 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
1280 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
1281 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
1283 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
1284 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
1285 /* Forward application tag with mask */
1286 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
1287 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14
1288 /* Forward reference tag with mask */
1289 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
1290 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15
1292 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF
1293 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0
1294 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF
1295 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4
1296 #define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1
1297 #define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8
1298 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
1299 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
1300 /* mask for refernce tag handling */
1301 #define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
1302 #define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10
1303 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
1304 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
1309 enum rss_hash_type {
1310 RSS_HASH_TYPE_DEFAULT = 0,
1311 RSS_HASH_TYPE_IPV4 = 1,
1312 RSS_HASH_TYPE_TCP_IPV4 = 2,
1313 RSS_HASH_TYPE_IPV6 = 3,
1314 RSS_HASH_TYPE_TCP_IPV6 = 4,
1315 RSS_HASH_TYPE_UDP_IPV4 = 5,
1316 RSS_HASH_TYPE_UDP_IPV6 = 6,
1320 /* status block structure */
1321 struct status_block {
1322 __le16 pi_array[PIS_PER_SB];
1324 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF
1325 #define STATUS_BLOCK_SB_NUM_SHIFT 0
1326 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
1327 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9
1328 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
1329 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16
1331 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
1332 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0
1333 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
1334 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
1339 #define PXP_VF_BAR0 0
1341 #define PXP_VF_BAR0_START_GRC 0x3E00
1342 #define PXP_VF_BAR0_GRC_LENGTH 0x200
1343 #define PXP_VF_BAR0_END_GRC \
1344 (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1)
1346 #define PXP_VF_BAR0_START_IGU 0
1347 #define PXP_VF_BAR0_IGU_LENGTH 0x3000
1348 #define PXP_VF_BAR0_END_IGU \
1349 (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1)
1351 #define PXP_VF_BAR0_START_DQ 0x3000
1352 #define PXP_VF_BAR0_DQ_LENGTH 0x200
1353 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
1354 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
1355 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
1356 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS \
1357 (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4)
1358 #define PXP_VF_BAR0_END_DQ \
1359 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1)
1361 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
1362 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
1363 #define PXP_VF_BAR0_END_TSDM_ZONE_B \
1364 (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1366 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
1367 #define PXP_VF_BAR0_END_MSDM_ZONE_B \
1368 (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1370 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
1371 #define PXP_VF_BAR0_END_USDM_ZONE_B \
1372 (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1374 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
1375 #define PXP_VF_BAR0_END_XSDM_ZONE_B \
1376 (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1378 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
1379 #define PXP_VF_BAR0_END_YSDM_ZONE_B \
1380 (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1382 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
1383 #define PXP_VF_BAR0_END_PSDM_ZONE_B \
1384 (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1386 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
1387 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
1389 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
1394 struct tdif_task_context {
1395 __le32 initialRefTag;
1398 __le16 partialCrcValueB;
1399 __le16 partialChecksumValueB;
1401 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF
1402 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0
1403 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF
1404 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4
1405 #define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1
1406 #define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8
1407 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
1408 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
1409 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
1410 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
1413 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
1414 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
1415 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
1416 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
1417 /* 0 = IP checksum, 1 = CRC */
1418 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
1419 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
1420 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
1421 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
1422 /* 1/2/3 - Protection Type */
1423 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
1424 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
1425 /* 0=0x0000, 1=0xffff */
1426 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1427 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1428 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
1429 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
1431 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
1432 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
1433 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
1434 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
1435 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
1436 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
1437 #define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
1438 #define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
1439 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
1440 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
1441 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
1442 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
1443 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
1444 #define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
1445 #define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
1446 /* 0=None, 1=DIF, 2=DIX */
1447 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
1448 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
1449 /* DIF tag right at the beginning of DIF interval */
1450 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
1451 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
1453 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
1454 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
1456 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
1457 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
1458 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF
1459 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14
1460 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF
1461 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18
1462 #define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1
1463 #define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22
1464 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1
1465 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23
1466 /* mask for refernce tag handling */
1467 #define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
1468 #define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24
1469 /* Forward application tag with mask */
1470 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
1471 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28
1472 /* Forward reference tag with mask */
1473 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
1474 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29
1475 /* Keep reference tag constant */
1476 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
1477 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30
1478 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
1479 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
1481 __le16 partialCrcValueA;
1482 __le16 partialChecksumValueA;
1484 u8 partialDifDataA[8];
1485 u8 partialDifDataB[8];
1492 struct timers_context {
1493 __le32 logical_client_0;
1494 /* Expiration time of logical client 0 */
1495 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF
1496 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
1497 /* Valid bit of logical client 0 */
1498 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
1499 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28
1500 /* Active bit of logical client 0 */
1501 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1
1502 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
1503 #define TIMERS_CONTEXT_RESERVED0_MASK 0x3
1504 #define TIMERS_CONTEXT_RESERVED0_SHIFT 30
1505 __le32 logical_client_1;
1506 /* Expiration time of logical client 1 */
1507 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF
1508 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
1509 /* Valid bit of logical client 1 */
1510 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
1511 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28
1512 /* Active bit of logical client 1 */
1513 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1
1514 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
1515 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3
1516 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30
1517 __le32 logical_client_2;
1518 /* Expiration time of logical client 2 */
1519 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF
1520 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
1521 /* Valid bit of logical client 2 */
1522 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
1523 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28
1524 /* Active bit of logical client 2 */
1525 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1
1526 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29
1527 #define TIMERS_CONTEXT_RESERVED2_MASK 0x3
1528 #define TIMERS_CONTEXT_RESERVED2_SHIFT 30
1529 __le32 host_expiration_fields;
1530 /* Expiration time on host (closest one) */
1531 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0xFFFFFFF
1532 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
1533 /* Valid bit of host expiration */
1534 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1
1535 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28
1536 #define TIMERS_CONTEXT_RESERVED3_MASK 0x7
1537 #define TIMERS_CONTEXT_RESERVED3_SHIFT 29
1542 * Enum for next_protocol field of tunnel_parsing_flags
1544 enum tunnel_next_protocol {
1549 MAX_TUNNEL_NEXT_PROTOCOL
1552 #endif /* __COMMON_HSI__ */