1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
9 /********************************/
10 /* PROTOCOL COMMON FW CONSTANTS */
11 /********************************/
13 /* Temporarily here should be added to HSI automatically by resource allocation
16 #define T_TEST_AGG_INT_TEMP 6
17 #define M_TEST_AGG_INT_TEMP 8
18 #define U_TEST_AGG_INT_TEMP 6
19 #define X_TEST_AGG_INT_TEMP 14
20 #define Y_TEST_AGG_INT_TEMP 4
21 #define P_TEST_AGG_INT_TEMP 4
23 #define X_FINAL_CLEANUP_AGG_INT 1
25 #define EVENT_RING_PAGE_SIZE_BYTES 4096
27 #define NUM_OF_GLOBAL_QUEUES 128
28 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
30 #define ISCSI_CDU_TASK_SEG_TYPE 0
31 #define FCOE_CDU_TASK_SEG_TYPE 0
32 #define RDMA_CDU_TASK_SEG_TYPE 1
34 #define FW_ASSERT_GENERAL_ATTN_IDX 32
36 #define MAX_PINNED_CCFC 32
38 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3
40 /* Queue Zone sizes in bytes */
41 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/
42 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX
43 *producer of VFs in backward compatibility
46 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/
47 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/
48 #define YSTORM_QZONE_SIZE 0
49 #define PSTORM_QZONE_SIZE 0
51 /*Log of mstorm default VF zone size.*/
52 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
53 /*Maximum number of RX queues that can be allocated to VF by default*/
54 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
55 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone
56 * size. Up to 96 VF supported in this mode
58 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
59 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size.
60 * Up to 48 VF supported in this mode
62 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
65 /********************************/
66 /* CORE (LIGHT L2) FW CONSTANTS */
67 /********************************/
69 #define CORE_LL2_MAX_RAMROD_PER_CON 8
70 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096
71 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096
72 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096
73 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1
75 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12
77 #define CORE_SPQE_PAGE_SIZE_BYTES 4096
80 * Usually LL2 queues are opened in pairs TX-RX.
81 * There is a hard restriction on number of RX queues (limited by Tstorm RAM)
82 * and TX counters (Pstorm RAM).
83 * Number of TX queues is almost unlimited.
84 * The constants are different so as to allow asymmetric LL2 connections
87 #define MAX_NUM_LL2_RX_QUEUES 48
88 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48
91 /****************************************************************************/
92 /* Include firmware version number only- do not add constants here to avoid */
93 /* redundunt compilations */
94 /****************************************************************************/
97 #define FW_MAJOR_VERSION 8
98 #define FW_MINOR_VERSION 37
99 #define FW_REVISION_VERSION 7
100 #define FW_ENGINEERING_VERSION 0
102 /***********************/
103 /* COMMON HW CONSTANTS */
104 /***********************/
107 #define MAX_NUM_PORTS_BB (2)
108 #define MAX_NUM_PORTS_K2 (4)
109 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
111 #define MAX_NUM_PFS_BB (8)
112 #define MAX_NUM_PFS_K2 (16)
113 #define MAX_NUM_PFS (MAX_NUM_PFS_K2)
114 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
116 #define MAX_NUM_VFS_BB (120)
117 #define MAX_NUM_VFS_K2 (192)
118 #define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_K2)
120 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
121 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)
123 /* in both BB and K2, the VF number starts from 16. so for arrays containing all
124 * possible PFs and VFs - we need a constant for this size
126 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)
127 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2)
128 #define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_K2)
130 #define MAX_NUM_VPORTS_K2 (208)
131 #define MAX_NUM_VPORTS_BB (160)
132 #define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2)
134 #define MAX_NUM_L2_QUEUES_BB (256)
135 #define MAX_NUM_L2_QUEUES_K2 (320)
137 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
138 #define NUM_PHYS_TCS_4PORT_K2 4
139 #define NUM_OF_PHYS_TCS 8
140 #define PURE_LB_TC NUM_OF_PHYS_TCS
141 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)
142 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
145 #define NUM_OF_CONNECTION_TYPES (8)
146 #define NUM_OF_TASK_TYPES (8)
147 #define NUM_OF_LCIDS (320)
148 #define NUM_OF_LTIDS (320)
150 /* Global PXP windows (GTT) */
151 #define NUM_OF_GTT 19
152 #define GTT_DWORD_SIZE_BITS 10
153 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2)
154 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS)
157 #define TOOLS_VERSION 10
162 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
163 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
165 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
166 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
168 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
169 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1)
170 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2)
171 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3)
172 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4)
173 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5)
181 #define DQ_DEMS_LEGACY 0
182 #define DQ_DEMS_TOE_MORE_TO_SEND 3
183 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4
184 #define DQ_DEMS_ROCE_CQ_CONS 7
186 /* XCM agg val selection (HW) */
187 #define DQ_XCM_AGG_VAL_SEL_WORD2 0
188 #define DQ_XCM_AGG_VAL_SEL_WORD3 1
189 #define DQ_XCM_AGG_VAL_SEL_WORD4 2
190 #define DQ_XCM_AGG_VAL_SEL_WORD5 3
191 #define DQ_XCM_AGG_VAL_SEL_REG3 4
192 #define DQ_XCM_AGG_VAL_SEL_REG4 5
193 #define DQ_XCM_AGG_VAL_SEL_REG5 6
194 #define DQ_XCM_AGG_VAL_SEL_REG6 7
196 /* XCM agg val selection (FW) */
197 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \
198 DQ_XCM_AGG_VAL_SEL_WORD2
199 #define DQ_XCM_ETH_TX_BD_CONS_CMD \
200 DQ_XCM_AGG_VAL_SEL_WORD3
201 #define DQ_XCM_CORE_TX_BD_CONS_CMD \
202 DQ_XCM_AGG_VAL_SEL_WORD3
203 #define DQ_XCM_ETH_TX_BD_PROD_CMD \
204 DQ_XCM_AGG_VAL_SEL_WORD4
205 #define DQ_XCM_CORE_TX_BD_PROD_CMD \
206 DQ_XCM_AGG_VAL_SEL_WORD4
207 #define DQ_XCM_CORE_SPQ_PROD_CMD \
208 DQ_XCM_AGG_VAL_SEL_WORD4
209 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
210 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
211 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
212 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
213 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
214 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
215 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
216 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
217 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
218 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
219 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
220 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
222 /* UCM agg val selection (HW) */
223 #define DQ_UCM_AGG_VAL_SEL_WORD0 0
224 #define DQ_UCM_AGG_VAL_SEL_WORD1 1
225 #define DQ_UCM_AGG_VAL_SEL_WORD2 2
226 #define DQ_UCM_AGG_VAL_SEL_WORD3 3
227 #define DQ_UCM_AGG_VAL_SEL_REG0 4
228 #define DQ_UCM_AGG_VAL_SEL_REG1 5
229 #define DQ_UCM_AGG_VAL_SEL_REG2 6
230 #define DQ_UCM_AGG_VAL_SEL_REG3 7
232 /* UCM agg val selection (FW) */
233 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2
234 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3
235 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0
236 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2
238 /* TCM agg val selection (HW) */
239 #define DQ_TCM_AGG_VAL_SEL_WORD0 0
240 #define DQ_TCM_AGG_VAL_SEL_WORD1 1
241 #define DQ_TCM_AGG_VAL_SEL_WORD2 2
242 #define DQ_TCM_AGG_VAL_SEL_WORD3 3
243 #define DQ_TCM_AGG_VAL_SEL_REG1 4
244 #define DQ_TCM_AGG_VAL_SEL_REG2 5
245 #define DQ_TCM_AGG_VAL_SEL_REG6 6
246 #define DQ_TCM_AGG_VAL_SEL_REG9 7
248 /* TCM agg val selection (FW) */
249 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1
250 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0
252 /* XCM agg counter flag selection (HW) */
253 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
254 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
255 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2
256 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3
257 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4
258 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5
259 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6
260 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7
262 /* XCM agg counter flag selection (FW) */
263 #define DQ_XCM_ETH_DQ_CF_CMD (1 << \
264 DQ_XCM_AGG_FLG_SHIFT_CF18)
265 #define DQ_XCM_CORE_DQ_CF_CMD (1 << \
266 DQ_XCM_AGG_FLG_SHIFT_CF18)
267 #define DQ_XCM_ETH_TERMINATE_CMD (1 << \
268 DQ_XCM_AGG_FLG_SHIFT_CF19)
269 #define DQ_XCM_CORE_TERMINATE_CMD (1 << \
270 DQ_XCM_AGG_FLG_SHIFT_CF19)
271 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << \
272 DQ_XCM_AGG_FLG_SHIFT_CF22)
273 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << \
274 DQ_XCM_AGG_FLG_SHIFT_CF22)
275 #define DQ_XCM_ETH_TPH_EN_CMD (1 << \
276 DQ_XCM_AGG_FLG_SHIFT_CF23)
277 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
278 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
279 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
280 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23)
281 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
282 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
284 /* UCM agg counter flag selection (HW) */
285 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0
286 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1
287 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2
288 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3
289 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4
290 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5
291 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6
292 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7
294 /* UCM agg counter flag selection (FW) */
295 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
296 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
297 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
298 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
299 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3)
300 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
301 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
303 /* TCM agg counter flag selection (HW) */
304 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0
305 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1
306 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2
307 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3
308 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4
309 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5
310 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6
311 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7
313 /* TCM agg counter flag selection (FW) */
314 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
315 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2)
316 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
317 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
318 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
319 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
320 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
321 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
323 /* PWM address mapping */
324 #define DQ_PWM_OFFSET_DPM_BASE 0x0
325 #define DQ_PWM_OFFSET_DPM_END 0x27
326 #define DQ_PWM_OFFSET_XCM16_BASE 0x40
327 #define DQ_PWM_OFFSET_XCM32_BASE 0x44
328 #define DQ_PWM_OFFSET_UCM16_BASE 0x48
329 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C
330 #define DQ_PWM_OFFSET_UCM16_4 0x50
331 #define DQ_PWM_OFFSET_TCM16_BASE 0x58
332 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C
333 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68
334 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69
335 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
337 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
338 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
339 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4)
340 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2)
341 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
342 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
343 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
345 #define DQ_REGION_SHIFT (12)
348 #define DQ_DPM_WQE_BUFF_SIZE (320)
350 /* Conn type ranges */
351 #define DQ_CONN_TYPE_RANGE_SHIFT (4)
357 /* number of TX queues in the QM */
358 #define MAX_QM_TX_QUEUES_K2 512
359 #define MAX_QM_TX_QUEUES_BB 448
360 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
362 /* number of Other queues in the QM */
363 #define MAX_QM_OTHER_QUEUES_BB 64
364 #define MAX_QM_OTHER_QUEUES_K2 128
365 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
367 /* number of queues in a PF queue group */
368 #define QM_PF_QUEUE_GROUP_SIZE 8
370 /* the size of a single queue element in bytes */
371 #define QM_PQ_ELEMENT_SIZE 4
373 /* base number of Tx PQs in the CM PQ representation.
374 * should be used when storing PQ IDs in CM PQ registers and context
376 #define CM_TX_PQ_BASE 0x200
378 /* number of global Vport/QCN rate limiters */
379 #define MAX_QM_GLOBAL_RLS 256
381 /* QM registers data */
382 #define QM_LINE_CRD_REG_WIDTH 16
383 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1))
384 #define QM_BYTE_CRD_REG_WIDTH 24
385 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1))
386 #define QM_WFQ_CRD_REG_WIDTH 32
387 #define QM_WFQ_CRD_REG_SIGN_BIT (1U << (QM_WFQ_CRD_REG_WIDTH - 1))
388 #define QM_RL_CRD_REG_WIDTH 32
389 #define QM_RL_CRD_REG_SIGN_BIT (1U << (QM_RL_CRD_REG_WIDTH - 1))
395 #define CAU_FSM_ETH_RX 0
396 #define CAU_FSM_ETH_TX 1
398 /* Number of Protocol Indices per Status Block */
399 #define PIS_PER_SB 12
400 #define MAX_PIS_PER_SB PIS_PER_SB
402 /* fsm is stopped or not valid for this sb */
403 #define CAU_HC_STOPPED_STATE 3
404 /* fsm is working without interrupt coalescing for this sb*/
405 #define CAU_HC_DISABLE_STATE 4
406 /* fsm is working with interrupt coalescing for this sb*/
407 #define CAU_HC_ENABLE_STATE 0
414 #define MAX_SB_PER_PATH_K2 (368)
415 #define MAX_SB_PER_PATH_BB (288)
416 #define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_K2
418 #define MAX_SB_PER_PF_MIMD 129
419 #define MAX_SB_PER_PF_SIMD 64
420 #define MAX_SB_PER_VF 64
422 /* Memory addresses on the BAR for the IGU Sub Block */
423 #define IGU_MEM_BASE 0x0000
425 #define IGU_MEM_MSIX_BASE 0x0000
426 #define IGU_MEM_MSIX_UPPER 0x0101
427 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
429 #define IGU_MEM_PBA_MSIX_BASE 0x0200
430 #define IGU_MEM_PBA_MSIX_UPPER 0x0202
431 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
433 #define IGU_CMD_INT_ACK_BASE 0x0400
434 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
435 MAX_TOT_SB_PER_PATH - \
437 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
439 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
440 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
441 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
443 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3
444 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4
445 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5
446 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
448 #define IGU_CMD_PROD_UPD_BASE 0x0600
449 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE + \
450 MAX_TOT_SB_PER_PATH - \
452 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
458 /* Bars for Blocks */
459 #define PXP_BAR_GRC 0
460 #define PXP_BAR_TSDM 0
461 #define PXP_BAR_USDM 0
462 #define PXP_BAR_XSDM 0
463 #define PXP_BAR_MSDM 0
464 #define PXP_BAR_YSDM 0
465 #define PXP_BAR_PSDM 0
466 #define PXP_BAR_IGU 0
470 #define PXP_PER_PF_ENTRY_SIZE 8
471 #define PXP_NUM_GLOBAL_WINDOWS 243
472 #define PXP_GLOBAL_ENTRY_SIZE 4
473 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4
474 #define PXP_PF_WINDOW_ADMIN_START 0
475 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000
476 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \
477 PXP_PF_WINDOW_ADMIN_LENGTH - 1)
478 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0
479 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \
480 PXP_PER_PF_ENTRY_SIZE)
481 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \
482 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
483 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200
484 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \
485 PXP_GLOBAL_ENTRY_SIZE)
486 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
487 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
488 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
489 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0
490 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4
491 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8
492 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc
494 #define PXP_NUM_PF_WINDOWS 12
496 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000
497 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS
498 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000
499 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
500 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
501 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
502 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \
503 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \
504 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
506 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
507 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
508 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS
509 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000
510 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
511 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
512 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
513 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
514 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
515 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
518 #define PXP_BAR0_START_GRC 0x0000
519 #define PXP_BAR0_GRC_LENGTH 0x1C00000
520 #define PXP_BAR0_END_GRC \
521 (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1)
523 #define PXP_BAR0_START_IGU 0x1C00000
524 #define PXP_BAR0_IGU_LENGTH 0x10000
525 #define PXP_BAR0_END_IGU \
526 (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1)
528 #define PXP_BAR0_START_TSDM 0x1C80000
529 #define PXP_BAR0_SDM_LENGTH 0x40000
530 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
531 #define PXP_BAR0_END_TSDM \
532 (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1)
534 #define PXP_BAR0_START_MSDM 0x1D00000
535 #define PXP_BAR0_END_MSDM \
536 (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1)
538 #define PXP_BAR0_START_USDM 0x1D80000
539 #define PXP_BAR0_END_USDM \
540 (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1)
542 #define PXP_BAR0_START_XSDM 0x1E00000
543 #define PXP_BAR0_END_XSDM \
544 (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1)
546 #define PXP_BAR0_START_YSDM 0x1E80000
547 #define PXP_BAR0_END_YSDM \
548 (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1)
550 #define PXP_BAR0_START_PSDM 0x1F00000
551 #define PXP_BAR0_END_PSDM \
552 (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1)
554 #define PXP_BAR0_FIRST_INVALID_ADDRESS \
555 (PXP_BAR0_END_PSDM + 1)
558 #define PXP_VF_BAR0 0
560 #define PXP_VF_BAR0_START_IGU 0
561 #define PXP_VF_BAR0_IGU_LENGTH 0x3000
562 #define PXP_VF_BAR0_END_IGU \
563 (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1)
565 #define PXP_VF_BAR0_START_DQ 0x3000
566 #define PXP_VF_BAR0_DQ_LENGTH 0x200
567 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
568 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
569 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
570 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS \
571 (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4)
572 #define PXP_VF_BAR0_END_DQ \
573 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1)
575 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
576 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
577 #define PXP_VF_BAR0_END_TSDM_ZONE_B \
578 (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
580 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
581 #define PXP_VF_BAR0_END_MSDM_ZONE_B \
582 (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
584 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
585 #define PXP_VF_BAR0_END_USDM_ZONE_B \
586 (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
588 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
589 #define PXP_VF_BAR0_END_XSDM_ZONE_B \
590 (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
592 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
593 #define PXP_VF_BAR0_END_YSDM_ZONE_B \
594 (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
596 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
597 #define PXP_VF_BAR0_END_PSDM_ZONE_B \
598 (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
600 #define PXP_VF_BAR0_START_GRC 0x3E00
601 #define PXP_VF_BAR0_GRC_LENGTH 0x200
602 #define PXP_VF_BAR0_END_GRC \
603 (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1)
605 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
606 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
608 #define PXP_VF_BAR0_START_IGU2 0x10000
609 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000
610 #define PXP_VF_BAR0_END_IGU2 \
611 (PXP_VF_BAR0_START_IGU2 + PXP_VF_BAR0_IGU2_LENGTH - 1)
613 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
615 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
616 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
619 #define PXP_NUM_ILT_RECORDS_BB 7600
620 #define PXP_NUM_ILT_RECORDS_K2 11000
621 #define MAX_NUM_ILT_RECORDS \
622 OSAL_MAX_T(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
625 #define PXP_QUEUES_ZONE_MAX_NUM 320
631 #define PRM_DMA_PAD_BYTES_NUM 2
637 #define SDM_OP_GEN_TRIG_NONE 0
638 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1
639 #define SDM_OP_GEN_TRIG_AGG_INT 2
640 #define SDM_OP_GEN_TRIG_LOADER 4
641 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
642 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9
644 /***********************************************************/
645 /* Completion types */
646 /***********************************************************/
648 #define SDM_COMP_TYPE_NONE 0
649 #define SDM_COMP_TYPE_WAKE_THREAD 1
650 #define SDM_COMP_TYPE_AGG_INT 2
651 /* Send direct message to local CM and/or remote CMs. Destinations are defined
652 * by vector in CompParams.
654 #define SDM_COMP_TYPE_CM 3
655 #define SDM_COMP_TYPE_LOADER 4
656 /* Send direct message to PXP (like "internal write" command) to write to remote
657 * Storm RAM via remote SDM
659 #define SDM_COMP_TYPE_PXP 5
660 /* Indicate error per thread */
661 #define SDM_COMP_TYPE_INDICATE_ERROR 6
662 #define SDM_COMP_TYPE_RELEASE_THREAD 7
663 /* Write to local RAM as a completion */
664 #define SDM_COMP_TYPE_RAM 8
665 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 /* Applicable only for E4 */
672 /* Number of PBF command queue lines. */
673 #define PBF_MAX_CMD_LINES 3328 /* Each line is 256b */
675 /* Number of BTB blocks. Each block is 256B. */
676 #define BTB_MAX_BLOCKS_BB 1440 /* 2880 blocks of 128B */
677 #define BTB_MAX_BLOCKS_K2 1840 /* 3680 blocks of 128B */
678 #define BTB_MAX_BLOCKS 1440
684 #define PRS_GFT_CAM_LINES_NO_MATCH 31
687 * Interrupt coalescing TimeSet
689 struct coalescing_timeset {
691 /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */
692 #define COALESCING_TIMESET_TIMESET_MASK 0x7F
693 #define COALESCING_TIMESET_TIMESET_SHIFT 0
694 /* Only if this flag is set, timeset will take effect */
695 #define COALESCING_TIMESET_VALID_MASK 0x1
696 #define COALESCING_TIMESET_VALID_SHIFT 7
699 struct common_queue_zone {
700 __le16 ring_drv_data_consumer;
705 * ETH Rx producers data
707 struct eth_rx_prod_data {
708 __le16 bd_prod /* BD producer. */;
709 __le16 cqe_prod /* CQE producer. */;
713 struct tcp_ulp_connect_done_params {
717 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1
718 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0
719 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F
720 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1
723 struct iscsi_connect_done_results {
724 __le16 icid /* Context ID of the connection */;
725 __le16 conn_id /* Driver connection ID */;
726 /* decided tcp params after connect done */
727 struct tcp_ulp_connect_done_params params;
731 struct iscsi_eqe_data {
732 __le16 icid /* Context ID of the connection */;
733 __le16 conn_id /* Driver connection ID */;
735 /* error code - relevant only if the opcode indicates its an error */
737 u8 error_pdu_opcode_reserved;
738 /* The processed PDUs opcode on which happened the error - updated for specific
739 * error codes, by default=0xFF
741 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
742 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0
743 /* Indication for driver is the error_pdu_opcode field has valid value */
744 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1
745 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6
746 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1
747 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
752 * Multi function mode
755 ERROR_MODE /* Unsupported mode */,
756 MF_OVLAN /* Multi function based on outer VLAN */,
757 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */,
761 /* Per-protocol connection types */
763 PROTOCOLID_ISCSI /* iSCSI */,
764 PROTOCOLID_FCOE /* FCoE */,
765 PROTOCOLID_ROCE /* RoCE */,
766 PROTOCOLID_CORE /* Core (light L2, slow path core) */,
767 PROTOCOLID_ETH /* Ethernet */,
768 PROTOCOLID_IWARP /* iWARP */,
769 PROTOCOLID_TOE /* TOE */,
770 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */,
771 PROTOCOLID_COMMON /* ProtocolCommon */,
772 PROTOCOLID_TCP /* TCP */,
778 __le32 lo /* low word for reg-pair */;
779 __le32 hi /* high word for reg-pair */;
787 struct ustorm_eth_queue_zone {
788 /* Rx interrupt coalescing TimeSet */
789 struct coalescing_timeset int_coalescing_timeset;
794 struct ustorm_queue_zone {
795 struct ustorm_eth_queue_zone eth;
796 struct common_queue_zone common;
799 /* status block structure */
800 struct cau_pi_entry {
802 /* A per protocol indexPROD value. */
803 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
804 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
805 /* This value determines the TimeSet that the PI is associated with */
806 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
807 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
808 /* Select the FSM within the SB */
809 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
810 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
811 /* Select the FSM within the SB */
812 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF
813 #define CAU_PI_ENTRY_RESERVED_SHIFT 24
816 /* status block structure */
817 struct cau_sb_entry {
819 /* The SB PROD index which is sent to the IGU. */
820 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
821 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0
822 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */
823 #define CAU_SB_ENTRY_STATE0_SHIFT 24
824 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */
825 #define CAU_SB_ENTRY_STATE1_SHIFT 28
827 /* Indicates the RX TimeSet that this SB is associated with. */
828 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
829 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
830 /* Indicates the TX TimeSet that this SB is associated with. */
831 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
832 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
833 /* This value will determine the RX FSM timer resolution in ticks */
834 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
835 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
836 /* This value will determine the TX FSM timer resolution in ticks */
837 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
838 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
839 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
840 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
841 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1
842 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26
843 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
844 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
845 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise
846 * the STAG will be equal to all ones.
848 #define CAU_SB_ENTRY_TPH_MASK 0x1
849 #define CAU_SB_ENTRY_TPH_SHIFT 31
854 * Igu cleanup bit values to distinguish between clean or producer consumer
857 enum command_type_bit {
858 IGU_COMMAND_TYPE_NOP = 0,
859 IGU_COMMAND_TYPE_SET = 1,
864 /* core doorbell data */
865 struct core_db_data {
867 /* destination of doorbell (use enum db_dest) */
868 #define CORE_DB_DATA_DEST_MASK 0x3
869 #define CORE_DB_DATA_DEST_SHIFT 0
870 /* aggregative command to CM (use enum db_agg_cmd_sel) */
871 #define CORE_DB_DATA_AGG_CMD_MASK 0x3
872 #define CORE_DB_DATA_AGG_CMD_SHIFT 2
873 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */
874 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4
875 #define CORE_DB_DATA_RESERVED_MASK 0x1
876 #define CORE_DB_DATA_RESERVED_SHIFT 5
877 /* aggregative value selection */
878 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
879 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
880 /* bit for every DQ counter flags in CM context that DQ can increment */
885 /* Enum of doorbell aggregative command selection */
886 enum db_agg_cmd_sel {
887 DB_AGG_CMD_NOP /* No operation */,
888 DB_AGG_CMD_SET /* Set the value */,
889 DB_AGG_CMD_ADD /* Add the value */,
890 DB_AGG_CMD_MAX /* Set max of current and new value */,
894 /* Enum of doorbell destination */
896 DB_DEST_XCM /* TX doorbell to XCM */,
897 DB_DEST_UCM /* RX doorbell to UCM */,
898 DB_DEST_TCM /* RX doorbell to TCM */,
905 * Enum of doorbell DPM types
908 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */,
909 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */,
910 /* L2 DPM inline- to PBF, with packet data on doorbell */
912 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */,
917 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM
920 struct db_l2_dpm_data {
921 __le16 icid /* internal CID */;
922 __le16 bd_prod /* bd producer value to update */;
924 /* Size in QWORD-s of the DPM burst */
925 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F
926 #define DB_L2_DPM_DATA_SIZE_SHIFT 0
927 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type)
929 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3
930 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6
931 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */
932 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8
933 /* size of the packet to be transmitted in bytes */
934 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF
935 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16
936 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1
937 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
938 /* In DPM_L2_BD mode: the number of SGE-s */
939 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
940 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28
941 /* Flag indicating whether to enable GFS search */
942 #define DB_L2_DPM_DATA_RESERVED1_MASK 0x1
943 #define DB_L2_DPM_DATA_RESERVED1_SHIFT 31
947 * Structure for SGE in a DPM doorbell of type DPM_L2_BD
949 struct db_l2_dpm_sge {
950 struct regpair addr /* Single continuous buffer */;
951 __le16 nbytes /* Number of bytes in this BD. */;
953 /* The TPH STAG index value */
954 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
955 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
956 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
957 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
958 /* Indicate if ST hint is requested or not */
959 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
960 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
961 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
962 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
966 /* Structure for doorbell address, in legacy mode */
967 struct db_legacy_addr {
969 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
970 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
971 /* doorbell extraction mode specifier- 0 if not used */
972 #define DB_LEGACY_ADDR_DEMS_MASK 0x7
973 #define DB_LEGACY_ADDR_DEMS_SHIFT 2
974 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */
975 #define DB_LEGACY_ADDR_ICID_SHIFT 5
979 * Structure for doorbell address, in PWM mode
983 #define DB_PWM_ADDR_RESERVED0_MASK 0x7
984 #define DB_PWM_ADDR_RESERVED0_SHIFT 0
985 /* Offset in PWM address space */
986 #define DB_PWM_ADDR_OFFSET_MASK 0x7F
987 #define DB_PWM_ADDR_OFFSET_SHIFT 3
988 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */
989 #define DB_PWM_ADDR_WID_SHIFT 10
990 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */
991 #define DB_PWM_ADDR_DPI_SHIFT 12
992 #define DB_PWM_ADDR_RESERVED1_MASK 0xF
993 #define DB_PWM_ADDR_RESERVED1_SHIFT 28
997 * Parameters to RDMA firmware, passed in EDPM doorbell
999 struct db_rdma_dpm_params {
1001 /* Size in QWORD-s of the DPM burst */
1002 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
1003 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
1004 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */
1005 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
1006 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6
1007 /* opcode for RDMA operation */
1008 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
1009 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8
1010 /* the size of the WQE payload in bytes */
1011 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
1012 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16
1013 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
1014 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27
1015 /* RoCE ack request (will be set 1) */
1016 #define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK 0x1
1017 #define DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT 28
1018 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */
1019 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
1020 /* RoCE completion flag for FW use */
1021 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
1022 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 30
1023 /* Connection type is iWARP */
1024 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
1025 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31
1029 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a
1032 struct db_rdma_dpm_data {
1033 __le16 icid /* internal CID */;
1034 __le16 prod_val /* aggregated value to update */;
1035 /* parameters passed to RDMA firmware */
1036 struct db_rdma_dpm_params params;
1039 /* Igu interrupt command */
1042 IGU_INT_DISABLE = 1,
1048 /* IGU producer or consumer update command */
1049 struct igu_prod_cons_update {
1050 __le32 sb_id_and_flags;
1051 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
1052 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
1053 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
1054 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
1055 /* interrupt enable/disable/nop (use enum igu_int_cmd) */
1056 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
1057 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
1058 /* (use enum igu_seg_access) */
1059 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
1060 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
1061 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
1062 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
1063 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
1064 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
1065 /* must always be set cleared (use enum command_type_bit) */
1066 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
1067 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
1071 /* Igu segments access for default status block only */
1072 enum igu_seg_access {
1073 IGU_SEG_ACCESS_REG = 0,
1074 IGU_SEG_ACCESS_ATTN = 1,
1080 * Enumeration for L3 type field of parsing_and_err_flags_union. L3Type:
1081 * 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according
1082 * to the last-ethertype)
1093 * Enumeration for l4Protocol field of parsing_and_err_flags_union. L4-protocol
1094 * 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the
1095 * first fragment, the protocol-type should be set to none.
1106 * Parsing and error flags field.
1108 struct parsing_and_err_flags {
1110 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled
1111 * according to the last-ethertype) (use enum l3_type)
1113 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
1114 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
1115 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and
1116 * its not the first fragment, the protocol-type should be set to none.
1117 * (use enum l4_protocol)
1119 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
1120 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
1121 /* Set if the packet is IPv4 fragment. */
1122 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
1123 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
1124 /* Set if VLAN tag exists. Invalid if tunnel type are IP GRE or IP GENEVE. */
1125 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
1126 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
1127 /* Set if L4 checksum was calculated. */
1128 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
1129 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
1130 /* Set for PTP packet. */
1131 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
1132 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
1133 /* Set if PTP timestamp recorded. */
1134 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
1135 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
1136 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6
1139 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
1140 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
1141 /* Set if L4 checksum validation failed. Valid only if L4 checksum was
1144 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
1145 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
1146 /* Set if GRE/VXLAN/GENEVE tunnel detected. */
1147 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
1148 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
1149 /* Set if VLAN tag exists in tunnel header. */
1150 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
1151 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
1152 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or
1153 * tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch
1155 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
1156 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
1157 /* Set if GRE or VXLAN/GENEVE UDP checksum was calculated. */
1158 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
1159 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
1160 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum
1163 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
1164 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
1169 * Parsing error flags bitmap.
1171 struct parsing_err_flags {
1173 /* MAC error indication */
1174 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
1175 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0
1176 /* truncation error indication */
1177 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1
1178 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1
1179 /* packet too small indication */
1180 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1
1181 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2
1182 /* Header Missing Tag */
1183 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1
1184 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3
1185 /* from frame cracker output */
1186 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1
1187 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4
1188 /* from frame cracker output */
1189 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1
1190 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5
1191 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len
1192 * indicates number that is bigger than real packet length 3. tunneling:
1193 * total-ip-length of the outer header points to offset that is smaller than
1194 * the one pointed to by the total-ip-len of the inner hdr.
1196 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1
1197 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6
1198 /* from frame cracker output */
1199 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1
1200 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7
1201 /* from frame cracker output. for either TCP or UDP */
1202 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1
1203 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8
1204 /* from frame cracker output */
1205 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1
1206 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9
1207 /* cksm calculated and value isn't 0xffff or L4-cksm-wasnt-calculated for any
1208 * reason, like: udp/ipv4 checksum is 0 etc.
1210 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1
1211 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10
1212 /* from frame cracker output */
1213 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1
1214 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11
1215 /* from frame cracker output */
1216 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1
1217 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12
1218 /* set if geneve option size was over 32 byte */
1219 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1
1220 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13
1221 /* from frame cracker output */
1222 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1
1223 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14
1224 /* from frame cracker output */
1225 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1
1226 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15
1237 /* Concrete Function ID. */
1238 struct pxp_concrete_fid {
1240 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */
1241 #define PXP_CONCRETE_FID_PFID_SHIFT 0
1242 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */
1243 #define PXP_CONCRETE_FID_PORT_SHIFT 4
1244 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */
1245 #define PXP_CONCRETE_FID_PATH_SHIFT 6
1246 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1
1247 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7
1248 #define PXP_CONCRETE_FID_VFID_MASK 0xFF
1249 #define PXP_CONCRETE_FID_VFID_SHIFT 8
1252 struct pxp_pretend_concrete_fid {
1254 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
1255 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
1256 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
1257 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
1258 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
1259 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
1260 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
1261 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
1264 union pxp_pretend_fid {
1265 struct pxp_pretend_concrete_fid concrete_fid;
1269 /* Pxp Pretend Command Register. */
1270 struct pxp_pretend_cmd {
1271 union pxp_pretend_fid fid;
1273 #define PXP_PRETEND_CMD_PATH_MASK 0x1
1274 #define PXP_PRETEND_CMD_PATH_SHIFT 0
1275 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
1276 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
1277 #define PXP_PRETEND_CMD_PORT_MASK 0x3
1278 #define PXP_PRETEND_CMD_PORT_SHIFT 2
1279 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
1280 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
1281 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
1282 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
1283 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
1284 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
1285 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
1286 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
1287 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
1288 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
1289 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
1290 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
1293 /* PTT Record in PXP Admin Window. */
1294 struct pxp_ptt_entry {
1296 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
1297 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0
1298 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
1299 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
1300 struct pxp_pretend_cmd pretend;
1305 * VF Zone A Permission Register.
1307 struct pxp_vf_zone_a_permission {
1309 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
1310 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
1311 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
1312 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
1313 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
1314 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
1315 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
1316 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
1323 struct rdif_task_context {
1324 __le32 initial_ref_tag;
1325 __le16 app_tag_value;
1326 __le16 app_tag_mask;
1328 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1329 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1330 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1331 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
1332 /* 0 = IP checksum, 1 = CRC */
1333 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1334 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
1335 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1336 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
1337 /* 1/2/3 - Protection Type */
1338 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1339 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
1340 /* 0=0x0000, 1=0xffff */
1341 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1342 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1343 /* Keep reference tag constant */
1344 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1345 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7
1346 u8 partial_dif_data[7];
1347 __le16 partial_crc_value;
1348 __le16 partial_checksum_value;
1349 __le32 offset_in_io;
1351 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1352 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1353 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1354 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
1355 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1356 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
1357 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1358 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
1359 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1360 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
1361 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1362 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
1363 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
1364 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1365 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
1366 /* 0=None, 1=DIF, 2=DIX */
1367 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1368 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
1369 /* DIF tag right at the beginning of DIF interval */
1370 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1371 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
1372 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
1373 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
1375 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1376 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
1377 /* Forward application tag with mask */
1378 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1379 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14
1380 /* Forward reference tag with mask */
1381 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1382 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15
1384 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
1385 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
1386 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
1387 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4
1388 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
1389 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8
1390 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
1391 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9
1392 /* mask for refernce tag handling */
1393 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1394 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10
1395 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
1396 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
1403 enum rss_hash_type {
1404 RSS_HASH_TYPE_DEFAULT = 0,
1405 RSS_HASH_TYPE_IPV4 = 1,
1406 RSS_HASH_TYPE_TCP_IPV4 = 2,
1407 RSS_HASH_TYPE_IPV6 = 3,
1408 RSS_HASH_TYPE_TCP_IPV6 = 4,
1409 RSS_HASH_TYPE_UDP_IPV4 = 5,
1410 RSS_HASH_TYPE_UDP_IPV6 = 6,
1415 * status block structure
1417 struct status_block {
1418 __le16 pi_array[PIS_PER_SB];
1420 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF
1421 #define STATUS_BLOCK_SB_NUM_SHIFT 0
1422 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
1423 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9
1424 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
1425 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16
1427 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
1428 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0
1429 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
1430 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
1437 struct tdif_task_context {
1438 __le32 initial_ref_tag;
1439 __le16 app_tag_value;
1440 __le16 app_tag_mask;
1441 __le16 partial_crc_value_b;
1442 __le16 partial_checksum_value_b;
1444 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
1445 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
1446 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
1447 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4
1448 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
1449 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8
1450 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
1451 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9
1452 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
1453 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
1456 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1457 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1458 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1459 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
1460 /* 0 = IP checksum, 1 = CRC */
1461 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1462 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
1463 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1464 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
1465 /* 1/2/3 - Protection Type */
1466 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1467 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
1468 /* 0=0x0000, 1=0xffff */
1469 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1470 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1471 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
1472 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
1474 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1475 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1476 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1477 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
1478 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1479 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
1480 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1481 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
1482 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1483 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
1484 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1485 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
1486 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
1487 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1488 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
1489 /* 0=None, 1=DIF, 2=DIX */
1490 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1491 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
1492 /* DIF tag right at the beginning of DIF interval */
1493 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1494 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
1495 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */
1496 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
1498 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1499 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
1500 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
1501 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14
1502 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
1503 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18
1504 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
1505 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22
1506 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
1507 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23
1508 /* mask for refernce tag handling */
1509 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1510 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24
1511 /* Forward application tag with mask */
1512 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1513 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28
1514 /* Forward reference tag with mask */
1515 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1516 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29
1517 /* Keep reference tag constant */
1518 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1519 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30
1520 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
1521 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
1522 __le32 offset_in_io_b;
1523 __le16 partial_crc_value_a;
1524 __le16 partial_checksum_value_a;
1525 __le32 offset_in_io_a;
1526 u8 partial_dif_data_a[8];
1527 u8 partial_dif_data_b[8];
1534 struct timers_context {
1535 __le32 logical_client_0;
1536 /* Expiration time of logical client 0 */
1537 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
1538 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
1539 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1
1540 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27
1541 /* Valid bit of logical client 0 */
1542 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
1543 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28
1544 /* Active bit of logical client 0 */
1545 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1
1546 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
1547 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3
1548 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30
1549 __le32 logical_client_1;
1550 /* Expiration time of logical client 1 */
1551 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF
1552 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
1553 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1
1554 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27
1555 /* Valid bit of logical client 1 */
1556 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
1557 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28
1558 /* Active bit of logical client 1 */
1559 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1
1560 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
1561 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3
1562 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30
1563 __le32 logical_client_2;
1564 /* Expiration time of logical client 2 */
1565 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF
1566 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
1567 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1
1568 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27
1569 /* Valid bit of logical client 2 */
1570 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
1571 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28
1572 /* Active bit of logical client 2 */
1573 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1
1574 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29
1575 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3
1576 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30
1577 __le32 host_expiration_fields;
1578 /* Expiration time on host (closest one) */
1579 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF
1580 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
1581 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1
1582 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27
1583 /* Valid bit of host expiration */
1584 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1
1585 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28
1586 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7
1587 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29
1592 * Enum for next_protocol field of tunnel_parsing_flags
1594 enum tunnel_next_protocol {
1599 MAX_TUNNEL_NEXT_PROTOCOL
1602 #endif /* __COMMON_HSI__ */