2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
10 #define __COMMON_HSI__
11 /********************************/
12 /* PROTOCOL COMMON FW CONSTANTS */
13 /********************************/
15 /* Temporarily here should be added to HSI automatically by resource allocation
18 #define T_TEST_AGG_INT_TEMP 6
19 #define M_TEST_AGG_INT_TEMP 8
20 #define U_TEST_AGG_INT_TEMP 6
21 #define X_TEST_AGG_INT_TEMP 14
22 #define Y_TEST_AGG_INT_TEMP 4
23 #define P_TEST_AGG_INT_TEMP 4
25 #define X_FINAL_CLEANUP_AGG_INT 1
27 #define EVENT_RING_PAGE_SIZE_BYTES 4096
29 #define NUM_OF_GLOBAL_QUEUES 128
30 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
32 #define ISCSI_CDU_TASK_SEG_TYPE 0
33 #define FCOE_CDU_TASK_SEG_TYPE 0
34 #define RDMA_CDU_TASK_SEG_TYPE 1
36 #define FW_ASSERT_GENERAL_ATTN_IDX 32
38 #define MAX_PINNED_CCFC 32
40 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3
42 /* Queue Zone sizes in bytes */
43 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/
44 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX
45 *producer of VFs in backward compatibility
48 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/
49 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/
50 #define YSTORM_QZONE_SIZE 0
51 #define PSTORM_QZONE_SIZE 0
53 /*Log of mstorm default VF zone size.*/
54 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
55 /*Maximum number of RX queues that can be allocated to VF by default*/
56 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
57 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone
58 * size. Up to 96 VF supported in this mode
60 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
61 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size.
62 * Up to 48 VF supported in this mode
64 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
67 /********************************/
68 /* CORE (LIGHT L2) FW CONSTANTS */
69 /********************************/
71 #define CORE_LL2_MAX_RAMROD_PER_CON 8
72 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096
73 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096
74 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096
75 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1
77 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12
79 #define CORE_SPQE_PAGE_SIZE_BYTES 4096
82 * Usually LL2 queues are opened in pairs TX-RX.
83 * There is a hard restriction on number of RX queues (limited by Tstorm RAM)
84 * and TX counters (Pstorm RAM).
85 * Number of TX queues is almost unlimited.
86 * The constants are different so as to allow asymmetric LL2 connections
89 #define MAX_NUM_LL2_RX_QUEUES 48
90 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48
93 /****************************************************************************/
94 /* Include firmware version number only- do not add constants here to avoid */
95 /* redundunt compilations */
96 /****************************************************************************/
99 #define FW_MAJOR_VERSION 8
100 #define FW_MINOR_VERSION 20
101 #define FW_REVISION_VERSION 0
102 #define FW_ENGINEERING_VERSION 0
104 /***********************/
105 /* COMMON HW CONSTANTS */
106 /***********************/
109 #define MAX_NUM_PORTS_K2 (4)
110 #define MAX_NUM_PORTS_BB (2)
111 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
113 #define MAX_NUM_PFS_K2 (16)
114 #define MAX_NUM_PFS_BB (8)
115 #define MAX_NUM_PFS (MAX_NUM_PFS_K2)
116 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
118 #define MAX_NUM_VFS_BB (120)
119 #define MAX_NUM_VFS_K2 (192)
120 #define E4_MAX_NUM_VFS (MAX_NUM_VFS_K2)
121 #define COMMON_MAX_NUM_VFS (240)
123 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
124 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)
125 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + E4_MAX_NUM_VFS)
127 /* in both BB and K2, the VF number starts from 16. so for arrays containing all
128 * possible PFs and VFs - we need a constant for this size
130 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)
131 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2)
132 #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + E4_MAX_NUM_VFS)
134 #define MAX_NUM_VPORTS_K2 (208)
135 #define MAX_NUM_VPORTS_BB (160)
136 #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2)
138 #define MAX_NUM_L2_QUEUES_K2 (320)
139 #define MAX_NUM_L2_QUEUES_BB (256)
140 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2)
142 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
144 #define NUM_PHYS_TCS_4PORT_K2 (4)
145 #define NUM_OF_PHYS_TCS (8)
147 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)
148 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
150 #define LB_TC (NUM_OF_PHYS_TCS)
152 /* Num of possible traffic priority values */
153 #define NUM_OF_PRIO (8)
155 #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
156 #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
157 #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
158 #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
161 #define E4_NUM_OF_CONNECTION_TYPES (8)
162 #define NUM_OF_TASK_TYPES (8)
163 #define NUM_OF_LCIDS (320)
164 #define NUM_OF_LTIDS (320)
167 #define MASTER_CLK_FREQ_E4 (375e6)
168 #define STORM_CLK_FREQ_E4 (1000e6)
169 #define CLK25M_CLK_FREQ_E4 (25e6)
171 /* Global PXP windows (GTT) */
172 #define NUM_OF_GTT 19
173 #define GTT_DWORD_SIZE_BITS 10
174 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2)
175 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS)
178 #define TOOLS_VERSION 10
183 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
184 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
186 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
187 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
189 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
190 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1)
191 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2)
192 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3)
193 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4)
194 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5)
202 #define DQ_DEMS_LEGACY 0
203 #define DQ_DEMS_TOE_MORE_TO_SEND 3
204 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4
205 #define DQ_DEMS_ROCE_CQ_CONS 7
207 /* XCM agg val selection (HW) */
208 #define DQ_XCM_AGG_VAL_SEL_WORD2 0
209 #define DQ_XCM_AGG_VAL_SEL_WORD3 1
210 #define DQ_XCM_AGG_VAL_SEL_WORD4 2
211 #define DQ_XCM_AGG_VAL_SEL_WORD5 3
212 #define DQ_XCM_AGG_VAL_SEL_REG3 4
213 #define DQ_XCM_AGG_VAL_SEL_REG4 5
214 #define DQ_XCM_AGG_VAL_SEL_REG5 6
215 #define DQ_XCM_AGG_VAL_SEL_REG6 7
217 /* XCM agg val selection (FW) */
218 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \
219 DQ_XCM_AGG_VAL_SEL_WORD2
220 #define DQ_XCM_ETH_TX_BD_CONS_CMD \
221 DQ_XCM_AGG_VAL_SEL_WORD3
222 #define DQ_XCM_CORE_TX_BD_CONS_CMD \
223 DQ_XCM_AGG_VAL_SEL_WORD3
224 #define DQ_XCM_ETH_TX_BD_PROD_CMD \
225 DQ_XCM_AGG_VAL_SEL_WORD4
226 #define DQ_XCM_CORE_TX_BD_PROD_CMD \
227 DQ_XCM_AGG_VAL_SEL_WORD4
228 #define DQ_XCM_CORE_SPQ_PROD_CMD \
229 DQ_XCM_AGG_VAL_SEL_WORD4
230 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
231 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
232 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
233 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
234 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
235 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
236 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
237 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
238 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
239 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
240 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
241 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
243 /* UCM agg val selection (HW) */
244 #define DQ_UCM_AGG_VAL_SEL_WORD0 0
245 #define DQ_UCM_AGG_VAL_SEL_WORD1 1
246 #define DQ_UCM_AGG_VAL_SEL_WORD2 2
247 #define DQ_UCM_AGG_VAL_SEL_WORD3 3
248 #define DQ_UCM_AGG_VAL_SEL_REG0 4
249 #define DQ_UCM_AGG_VAL_SEL_REG1 5
250 #define DQ_UCM_AGG_VAL_SEL_REG2 6
251 #define DQ_UCM_AGG_VAL_SEL_REG3 7
253 /* UCM agg val selection (FW) */
254 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2
255 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3
256 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0
257 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2
259 /* TCM agg val selection (HW) */
260 #define DQ_TCM_AGG_VAL_SEL_WORD0 0
261 #define DQ_TCM_AGG_VAL_SEL_WORD1 1
262 #define DQ_TCM_AGG_VAL_SEL_WORD2 2
263 #define DQ_TCM_AGG_VAL_SEL_WORD3 3
264 #define DQ_TCM_AGG_VAL_SEL_REG1 4
265 #define DQ_TCM_AGG_VAL_SEL_REG2 5
266 #define DQ_TCM_AGG_VAL_SEL_REG6 6
267 #define DQ_TCM_AGG_VAL_SEL_REG9 7
269 /* TCM agg val selection (FW) */
270 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1
271 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0
273 /* XCM agg counter flag selection (HW) */
274 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
275 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
276 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2
277 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3
278 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4
279 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5
280 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6
281 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7
283 /* XCM agg counter flag selection (FW) */
284 #define DQ_XCM_ETH_DQ_CF_CMD (1 << \
285 DQ_XCM_AGG_FLG_SHIFT_CF18)
286 #define DQ_XCM_CORE_DQ_CF_CMD (1 << \
287 DQ_XCM_AGG_FLG_SHIFT_CF18)
288 #define DQ_XCM_ETH_TERMINATE_CMD (1 << \
289 DQ_XCM_AGG_FLG_SHIFT_CF19)
290 #define DQ_XCM_CORE_TERMINATE_CMD (1 << \
291 DQ_XCM_AGG_FLG_SHIFT_CF19)
292 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << \
293 DQ_XCM_AGG_FLG_SHIFT_CF22)
294 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << \
295 DQ_XCM_AGG_FLG_SHIFT_CF22)
296 #define DQ_XCM_ETH_TPH_EN_CMD (1 << \
297 DQ_XCM_AGG_FLG_SHIFT_CF23)
298 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
299 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
300 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
301 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23)
302 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
303 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
305 /* UCM agg counter flag selection (HW) */
306 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0
307 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1
308 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2
309 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3
310 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4
311 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5
312 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6
313 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7
315 /* UCM agg counter flag selection (FW) */
316 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
317 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
318 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
319 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
320 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3)
321 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
322 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
324 /* TCM agg counter flag selection (HW) */
325 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0
326 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1
327 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2
328 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3
329 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4
330 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5
331 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6
332 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7
334 /* TCM agg counter flag selection (FW) */
335 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
336 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2)
337 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
338 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
339 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
340 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
341 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
342 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
344 /* PWM address mapping */
345 #define DQ_PWM_OFFSET_DPM_BASE 0x0
346 #define DQ_PWM_OFFSET_DPM_END 0x27
347 #define DQ_PWM_OFFSET_XCM16_BASE 0x40
348 #define DQ_PWM_OFFSET_XCM32_BASE 0x44
349 #define DQ_PWM_OFFSET_UCM16_BASE 0x48
350 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C
351 #define DQ_PWM_OFFSET_UCM16_4 0x50
352 #define DQ_PWM_OFFSET_TCM16_BASE 0x58
353 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C
354 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68
355 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69
356 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
358 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
359 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
360 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4)
361 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2)
362 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
363 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
364 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
366 #define DQ_REGION_SHIFT (12)
369 #define DQ_DPM_WQE_BUFF_SIZE (320)
371 /* Conn type ranges */
372 #define DQ_CONN_TYPE_RANGE_SHIFT (4)
378 /* number of TX queues in the QM */
379 #define MAX_QM_TX_QUEUES_K2 512
380 #define MAX_QM_TX_QUEUES_BB 448
381 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
383 /* number of Other queues in the QM */
384 #define MAX_QM_OTHER_QUEUES_BB 64
385 #define MAX_QM_OTHER_QUEUES_K2 128
386 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
388 /* number of queues in a PF queue group */
389 #define QM_PF_QUEUE_GROUP_SIZE 8
391 /* the size of a single queue element in bytes */
392 #define QM_PQ_ELEMENT_SIZE 4
394 /* base number of Tx PQs in the CM PQ representation.
395 * should be used when storing PQ IDs in CM PQ registers and context
397 #define CM_TX_PQ_BASE 0x200
399 /* number of global Vport/QCN rate limiters */
400 #define MAX_QM_GLOBAL_RLS 256
402 /* QM registers data */
403 #define QM_LINE_CRD_REG_WIDTH 16
404 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1))
405 #define QM_BYTE_CRD_REG_WIDTH 24
406 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1))
407 #define QM_WFQ_CRD_REG_WIDTH 32
408 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1))
409 #define QM_RL_CRD_REG_WIDTH 32
410 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1))
416 #define CAU_FSM_ETH_RX 0
417 #define CAU_FSM_ETH_TX 1
419 /* Number of Protocol Indices per Status Block */
420 #define PIS_PER_SB 12
422 /* fsm is stopped or not valid for this sb */
423 #define CAU_HC_STOPPED_STATE 3
424 /* fsm is working without interrupt coalescing for this sb*/
425 #define CAU_HC_DISABLE_STATE 4
426 /* fsm is working with interrupt coalescing for this sb*/
427 #define CAU_HC_ENABLE_STATE 0
434 #define MAX_SB_PER_PATH_K2 (368)
435 #define MAX_SB_PER_PATH_BB (288)
436 #define MAX_TOT_SB_PER_PATH \
439 #define MAX_SB_PER_PF_MIMD 129
440 #define MAX_SB_PER_PF_SIMD 64
441 #define MAX_SB_PER_VF 64
443 /* Memory addresses on the BAR for the IGU Sub Block */
444 #define IGU_MEM_BASE 0x0000
446 #define IGU_MEM_MSIX_BASE 0x0000
447 #define IGU_MEM_MSIX_UPPER 0x0101
448 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
450 #define IGU_MEM_PBA_MSIX_BASE 0x0200
451 #define IGU_MEM_PBA_MSIX_UPPER 0x0202
452 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
454 #define IGU_CMD_INT_ACK_BASE 0x0400
455 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
456 MAX_TOT_SB_PER_PATH - \
458 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
460 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
461 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
462 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
464 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3
465 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4
466 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5
467 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
469 #define IGU_CMD_PROD_UPD_BASE 0x0600
470 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
471 MAX_TOT_SB_PER_PATH - \
473 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
479 /* Bars for Blocks */
480 #define PXP_BAR_GRC 0
481 #define PXP_BAR_TSDM 0
482 #define PXP_BAR_USDM 0
483 #define PXP_BAR_XSDM 0
484 #define PXP_BAR_MSDM 0
485 #define PXP_BAR_YSDM 0
486 #define PXP_BAR_PSDM 0
487 #define PXP_BAR_IGU 0
491 #define PXP_PER_PF_ENTRY_SIZE 8
492 #define PXP_NUM_GLOBAL_WINDOWS 243
493 #define PXP_GLOBAL_ENTRY_SIZE 4
494 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4
495 #define PXP_PF_WINDOW_ADMIN_START 0
496 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000
497 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \
498 PXP_PF_WINDOW_ADMIN_LENGTH - 1)
499 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0
500 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \
501 PXP_PER_PF_ENTRY_SIZE)
502 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \
503 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
504 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200
505 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \
506 PXP_GLOBAL_ENTRY_SIZE)
507 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
508 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
509 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
510 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0
511 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4
512 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8
513 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc
515 #define PXP_NUM_PF_WINDOWS 12
517 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000
518 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS
519 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000
520 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
521 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
522 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
523 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \
524 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \
525 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
527 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
528 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
529 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS
530 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000
531 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
532 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
533 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
534 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
535 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
536 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
539 #define PXP_BAR0_START_GRC 0x0000
540 #define PXP_BAR0_GRC_LENGTH 0x1C00000
541 #define PXP_BAR0_END_GRC \
542 (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1)
544 #define PXP_BAR0_START_IGU 0x1C00000
545 #define PXP_BAR0_IGU_LENGTH 0x10000
546 #define PXP_BAR0_END_IGU \
547 (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1)
549 #define PXP_BAR0_START_TSDM 0x1C80000
550 #define PXP_BAR0_SDM_LENGTH 0x40000
551 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
552 #define PXP_BAR0_END_TSDM \
553 (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1)
555 #define PXP_BAR0_START_MSDM 0x1D00000
556 #define PXP_BAR0_END_MSDM \
557 (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1)
559 #define PXP_BAR0_START_USDM 0x1D80000
560 #define PXP_BAR0_END_USDM \
561 (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1)
563 #define PXP_BAR0_START_XSDM 0x1E00000
564 #define PXP_BAR0_END_XSDM \
565 (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1)
567 #define PXP_BAR0_START_YSDM 0x1E80000
568 #define PXP_BAR0_END_YSDM \
569 (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1)
571 #define PXP_BAR0_START_PSDM 0x1F00000
572 #define PXP_BAR0_END_PSDM \
573 (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1)
575 #define PXP_BAR0_FIRST_INVALID_ADDRESS \
576 (PXP_BAR0_END_PSDM + 1)
578 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
579 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
582 #define PXP_NUM_ILT_RECORDS_BB 7600
583 #define PXP_NUM_ILT_RECORDS_K2 11000
584 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
588 #define PXP_QUEUES_ZONE_MAX_NUM 320
596 #define PRM_DMA_PAD_BYTES_NUM 2
602 #define SDM_OP_GEN_TRIG_NONE 0
603 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1
604 #define SDM_OP_GEN_TRIG_AGG_INT 2
605 #define SDM_OP_GEN_TRIG_LOADER 4
606 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
607 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9
609 /***********************************************************/
610 /* Completion types */
611 /***********************************************************/
613 #define SDM_COMP_TYPE_NONE 0
614 #define SDM_COMP_TYPE_WAKE_THREAD 1
615 #define SDM_COMP_TYPE_AGG_INT 2
616 /* Send direct message to local CM and/or remote CMs. Destinations are defined
617 * by vector in CompParams.
619 #define SDM_COMP_TYPE_CM 3
620 #define SDM_COMP_TYPE_LOADER 4
621 /* Send direct message to PXP (like "internal write" command) to write to remote
622 * Storm RAM via remote SDM
624 #define SDM_COMP_TYPE_PXP 5
625 /* Indicate error per thread */
626 #define SDM_COMP_TYPE_INDICATE_ERROR 6
627 #define SDM_COMP_TYPE_RELEASE_THREAD 7
628 /* Write to local RAM as a completion */
629 #define SDM_COMP_TYPE_RAM 8
630 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 /* Applicable only for E4 */
637 /* Number of PBF command queue lines. Each line is 32B. */
638 #define PBF_MAX_CMD_LINES 3328
640 /* Number of BTB blocks. Each block is 256B. */
641 #define BTB_MAX_BLOCKS 1440
647 #define PRS_GFT_CAM_LINES_NO_MATCH 31
648 /* Async data KCQ CQE */
650 /* Context ID of the connection */
652 /* Task Id of the task (for error that happened on a a task) */
654 /* error code - relevant only if the opcode indicates its an error */
656 /* internal fw debug parameter */
661 * Interrupt coalescing TimeSet
663 struct coalescing_timeset {
665 /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */
666 #define COALESCING_TIMESET_TIMESET_MASK 0x7F
667 #define COALESCING_TIMESET_TIMESET_SHIFT 0
668 /* Only if this flag is set, timeset will take effect */
669 #define COALESCING_TIMESET_VALID_MASK 0x1
670 #define COALESCING_TIMESET_VALID_SHIFT 7
673 struct common_queue_zone {
674 __le16 ring_drv_data_consumer;
679 * ETH Rx producers data
681 struct eth_rx_prod_data {
682 __le16 bd_prod /* BD producer. */;
683 __le16 cqe_prod /* CQE producer. */;
687 __le32 lo /* low word for reg-pair */;
688 __le32 hi /* high word for reg-pair */;
692 * Event Ring VF-PF Channel data
694 struct vf_pf_channel_eqe_data {
695 struct regpair msg_addr /* VF-PF message address */;
698 struct iscsi_eqe_data {
699 __le32 cid /* Context ID of the connection */;
700 /* Task Id of the task (for error that happened on a a task) */;
702 /* error code - relevant only if the opcode indicates its an error */
704 u8 error_pdu_opcode_reserved;
705 /* The processed PDUs opcode on which happened the error - updated for specific
706 * error codes, by default=0xFF
708 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
709 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0
710 /* Indication for driver is the error_pdu_opcode field has valid value */
711 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1
712 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6
713 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1
714 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
718 * Event Ring malicious VF data
720 struct malicious_vf_eqe_data {
721 u8 vfId /* Malicious VF ID */;
722 u8 errId /* Malicious VF error */;
727 * Event Ring initial cleanup data
729 struct initial_cleanup_eqe_data {
737 union event_ring_data {
738 u8 bytes[8] /* Byte Array */;
739 struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */;
740 struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */;
741 struct regpair roceHandle /* Dedicated field for RDMA data */;
742 struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */;
743 struct initial_cleanup_eqe_data vf_init_cleanup
744 /* VF Initial Cleanup data */;
746 /* Event Ring Entry */
747 struct event_ring_entry {
748 u8 protocol_id /* Event Protocol ID */;
749 u8 opcode /* Event Opcode */;
750 __le16 reserved0 /* Reserved */;
751 __le16 echo /* Echo value from ramrod data on the host */;
752 u8 fw_return_code /* FW return code for SP ramrods */;
754 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */
755 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
756 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
757 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
758 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
759 union event_ring_data data;
762 /* Multi function mode */
764 ERROR_MODE /* Unsupported mode */,
765 MF_OVLAN /* Multi function based on outer VLAN */,
766 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */,
770 /* Per-protocol connection types */
772 PROTOCOLID_ISCSI /* iSCSI */,
773 PROTOCOLID_FCOE /* FCoE */,
774 PROTOCOLID_ROCE /* RoCE */,
775 PROTOCOLID_CORE /* Core (light L2, slow path core) */,
776 PROTOCOLID_ETH /* Ethernet */,
777 PROTOCOLID_IWARP /* iWARP */,
778 PROTOCOLID_TOE /* TOE */,
779 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */,
780 PROTOCOLID_COMMON /* ProtocolCommon */,
781 PROTOCOLID_TCP /* TCP */,
790 struct ustorm_eth_queue_zone {
791 /* Rx interrupt coalescing TimeSet */
792 struct coalescing_timeset int_coalescing_timeset;
797 struct ustorm_queue_zone {
798 struct ustorm_eth_queue_zone eth;
799 struct common_queue_zone common;
802 /* status block structure */
803 struct cau_pi_entry {
805 /* A per protocol indexPROD value. */
806 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
807 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
808 /* This value determines the TimeSet that the PI is associated with */
809 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
810 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
811 /* Select the FSM within the SB */
812 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
813 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
814 /* Select the FSM within the SB */
815 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF
816 #define CAU_PI_ENTRY_RESERVED_SHIFT 24
819 /* status block structure */
820 struct cau_sb_entry {
822 /* The SB PROD index which is sent to the IGU. */
823 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
824 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0
825 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */
826 #define CAU_SB_ENTRY_STATE0_SHIFT 24
827 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */
828 #define CAU_SB_ENTRY_STATE1_SHIFT 28
830 /* Indicates the RX TimeSet that this SB is associated with. */
831 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
832 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
833 /* Indicates the TX TimeSet that this SB is associated with. */
834 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
835 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
836 /* This value will determine the RX FSM timer resolution in ticks */
837 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
838 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
839 /* This value will determine the TX FSM timer resolution in ticks */
840 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
841 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
842 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
843 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
844 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1
845 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26
846 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
847 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
848 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise
849 * the STAG will be equal to all ones.
851 #define CAU_SB_ENTRY_TPH_MASK 0x1
852 #define CAU_SB_ENTRY_TPH_SHIFT 31
855 /* core doorbell data */
856 struct core_db_data {
858 /* destination of doorbell (use enum db_dest) */
859 #define CORE_DB_DATA_DEST_MASK 0x3
860 #define CORE_DB_DATA_DEST_SHIFT 0
861 /* aggregative command to CM (use enum db_agg_cmd_sel) */
862 #define CORE_DB_DATA_AGG_CMD_MASK 0x3
863 #define CORE_DB_DATA_AGG_CMD_SHIFT 2
864 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */
865 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4
866 #define CORE_DB_DATA_RESERVED_MASK 0x1
867 #define CORE_DB_DATA_RESERVED_SHIFT 5
868 /* aggregative value selection */
869 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
870 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
871 /* bit for every DQ counter flags in CM context that DQ can increment */
876 /* Enum of doorbell aggregative command selection */
877 enum db_agg_cmd_sel {
878 DB_AGG_CMD_NOP /* No operation */,
879 DB_AGG_CMD_SET /* Set the value */,
880 DB_AGG_CMD_ADD /* Add the value */,
881 DB_AGG_CMD_MAX /* Set max of current and new value */,
885 /* Enum of doorbell destination */
887 DB_DEST_XCM /* TX doorbell to XCM */,
888 DB_DEST_UCM /* RX doorbell to UCM */,
889 DB_DEST_TCM /* RX doorbell to TCM */,
896 * Enum of doorbell DPM types
899 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */,
900 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */,
901 /* L2 DPM inline- to PBF, with packet data on doorbell */
903 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */,
908 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM
911 struct db_l2_dpm_data {
912 __le16 icid /* internal CID */;
913 __le16 bd_prod /* bd producer value to update */;
915 /* Size in QWORD-s of the DPM burst */
916 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F
917 #define DB_L2_DPM_DATA_SIZE_SHIFT 0
918 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type)
920 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3
921 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6
922 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */
923 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8
924 /* size of the packet to be transmitted in bytes */
925 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF
926 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16
927 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1
928 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
929 /* In DPM_L2_BD mode: the number of SGE-s */
930 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
931 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28
932 /* Flag indicating whether to enable GFS search */
933 #define DB_L2_DPM_DATA_RESERVED1_MASK 0x1
934 #define DB_L2_DPM_DATA_RESERVED1_SHIFT 31
938 * Structure for SGE in a DPM doorbell of type DPM_L2_BD
940 struct db_l2_dpm_sge {
941 struct regpair addr /* Single continuous buffer */;
942 __le16 nbytes /* Number of bytes in this BD. */;
944 /* The TPH STAG index value */
945 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
946 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
947 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
948 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
949 /* Indicate if ST hint is requested or not */
950 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
951 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
952 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
953 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
957 /* Structure for doorbell address, in legacy mode */
958 struct db_legacy_addr {
960 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
961 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
962 /* doorbell extraction mode specifier- 0 if not used */
963 #define DB_LEGACY_ADDR_DEMS_MASK 0x7
964 #define DB_LEGACY_ADDR_DEMS_SHIFT 2
965 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */
966 #define DB_LEGACY_ADDR_ICID_SHIFT 5
970 * Structure for doorbell address, in PWM mode
974 #define DB_PWM_ADDR_RESERVED0_MASK 0x7
975 #define DB_PWM_ADDR_RESERVED0_SHIFT 0
976 /* Offset in PWM address space */
977 #define DB_PWM_ADDR_OFFSET_MASK 0x7F
978 #define DB_PWM_ADDR_OFFSET_SHIFT 3
979 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */
980 #define DB_PWM_ADDR_WID_SHIFT 10
981 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */
982 #define DB_PWM_ADDR_DPI_SHIFT 12
983 #define DB_PWM_ADDR_RESERVED1_MASK 0xF
984 #define DB_PWM_ADDR_RESERVED1_SHIFT 28
988 * Parameters to RDMA firmware, passed in EDPM doorbell
990 struct db_rdma_dpm_params {
992 /* Size in QWORD-s of the DPM burst */
993 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
994 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
995 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */
996 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
997 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6
998 /* opcode for RDMA operation */
999 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
1000 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8
1001 /* the size of the WQE payload in bytes */
1002 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
1003 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16
1004 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
1005 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27
1006 /* RoCE completion flag */
1007 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
1008 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
1009 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */
1010 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
1011 #define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x3
1012 #define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30
1013 /* Connection type is iWARP */
1014 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
1015 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31
1019 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a
1022 struct db_rdma_dpm_data {
1023 __le16 icid /* internal CID */;
1024 __le16 prod_val /* aggregated value to update */;
1025 /* parameters passed to RDMA firmware */
1026 struct db_rdma_dpm_params params;
1029 /* Igu interrupt command */
1032 IGU_INT_DISABLE = 1,
1038 /* IGU producer or consumer update command */
1039 struct igu_prod_cons_update {
1040 __le32 sb_id_and_flags;
1041 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
1042 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
1043 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
1044 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
1045 /* interrupt enable/disable/nop (use enum igu_int_cmd) */
1046 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
1047 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
1048 /* (use enum igu_seg_access) */
1049 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
1050 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
1051 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
1052 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
1053 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
1054 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
1055 /* must always be set cleared (use enum command_type_bit) */
1056 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
1057 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
1061 /* Igu segments access for default status block only */
1062 enum igu_seg_access {
1063 IGU_SEG_ACCESS_REG = 0,
1064 IGU_SEG_ACCESS_ATTN = 1,
1070 * Enumeration for L3 type field of parsing_and_err_flags_union. L3Type:
1071 * 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according
1072 * to the last-ethertype)
1083 * Enumeration for l4Protocol field of parsing_and_err_flags_union. L4-protocol
1084 * 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the
1085 * first fragment, the protocol-type should be set to none.
1096 * Parsing and error flags field.
1098 struct parsing_and_err_flags {
1100 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled
1101 * according to the last-ethertype) (use enum l3_type)
1103 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
1104 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
1105 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and
1106 * its not the first fragment, the protocol-type should be set to none.
1107 * (use enum l4_protocol)
1109 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
1110 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
1111 /* Set if the packet is IPv4 fragment. */
1112 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
1113 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
1114 /* Set if VLAN tag exists. Invalid if tunnel type are IP GRE or IP GENEVE. */
1115 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
1116 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
1117 /* Set if L4 checksum was calculated. */
1118 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
1119 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
1120 /* Set for PTP packet. */
1121 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
1122 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
1123 /* Set if PTP timestamp recorded. */
1124 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
1125 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
1126 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6
1129 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
1130 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
1131 /* Set if L4 checksum validation failed. Valid only if L4 checksum was
1134 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
1135 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
1136 /* Set if GRE/VXLAN/GENEVE tunnel detected. */
1137 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
1138 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
1139 /* Set if VLAN tag exists in tunnel header. */
1140 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
1141 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
1142 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or
1143 * tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch
1145 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
1146 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
1147 /* Set if GRE or VXLAN/GENEVE UDP checksum was calculated. */
1148 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
1149 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
1150 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum
1153 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
1154 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
1159 * Parsing error flags bitmap.
1161 struct parsing_err_flags {
1163 /* MAC error indication */
1164 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
1165 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0
1166 /* truncation error indication */
1167 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1
1168 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1
1169 /* packet too small indication */
1170 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1
1171 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2
1172 /* Header Missing Tag */
1173 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1
1174 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3
1175 /* from frame cracker output */
1176 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1
1177 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4
1178 /* from frame cracker output */
1179 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1
1180 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5
1181 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len
1182 * indicates number that is bigger than real packet length 3. tunneling:
1183 * total-ip-length of the outer header points to offset that is smaller than
1184 * the one pointed to by the total-ip-len of the inner hdr.
1186 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1
1187 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6
1188 /* from frame cracker output */
1189 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1
1190 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7
1191 /* from frame cracker output. for either TCP or UDP */
1192 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1
1193 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8
1194 /* from frame cracker output */
1195 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1
1196 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9
1197 /* cksm calculated and value isn't 0xffff or L4-cksm-wasnt-calculated for any
1198 * reason, like: udp/ipv4 checksum is 0 etc.
1200 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1
1201 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10
1202 /* from frame cracker output */
1203 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1
1204 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11
1205 /* from frame cracker output */
1206 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1
1207 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12
1208 /* set if geneve option size was over 32 byte */
1209 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1
1210 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13
1211 /* from frame cracker output */
1212 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1
1213 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14
1214 /* from frame cracker output */
1215 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1
1216 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15
1227 /* Concrete Function ID. */
1228 struct pxp_concrete_fid {
1230 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */
1231 #define PXP_CONCRETE_FID_PFID_SHIFT 0
1232 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */
1233 #define PXP_CONCRETE_FID_PORT_SHIFT 4
1234 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */
1235 #define PXP_CONCRETE_FID_PATH_SHIFT 6
1236 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1
1237 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7
1238 #define PXP_CONCRETE_FID_VFID_MASK 0xFF
1239 #define PXP_CONCRETE_FID_VFID_SHIFT 8
1242 struct pxp_pretend_concrete_fid {
1244 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
1245 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
1246 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
1247 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
1248 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
1249 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
1250 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
1251 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
1254 union pxp_pretend_fid {
1255 struct pxp_pretend_concrete_fid concrete_fid;
1259 /* Pxp Pretend Command Register. */
1260 struct pxp_pretend_cmd {
1261 union pxp_pretend_fid fid;
1263 #define PXP_PRETEND_CMD_PATH_MASK 0x1
1264 #define PXP_PRETEND_CMD_PATH_SHIFT 0
1265 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
1266 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
1267 #define PXP_PRETEND_CMD_PORT_MASK 0x3
1268 #define PXP_PRETEND_CMD_PORT_SHIFT 2
1269 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
1270 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
1271 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
1272 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
1273 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
1274 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
1275 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
1276 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
1277 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
1278 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
1279 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
1280 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
1283 /* PTT Record in PXP Admin Window. */
1284 struct pxp_ptt_entry {
1286 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
1287 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0
1288 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
1289 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
1290 struct pxp_pretend_cmd pretend;
1295 * VF Zone A Permission Register.
1297 struct pxp_vf_zone_a_permission {
1299 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
1300 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
1301 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
1302 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
1303 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
1304 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
1305 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
1306 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
1313 struct rdif_task_context {
1314 __le32 initialRefTag;
1318 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
1319 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
1320 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
1321 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
1322 /* 0 = IP checksum, 1 = CRC */
1323 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
1324 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
1325 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
1326 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
1327 /* 1/2/3 - Protection Type */
1328 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
1329 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
1330 /* 0=0x0000, 1=0xffff */
1331 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1332 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1333 /* Keep reference tag constant */
1334 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
1335 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7
1336 u8 partialDifData[7];
1337 __le16 partialCrcValue;
1338 __le16 partialChecksumValue;
1341 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
1342 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
1343 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
1344 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
1345 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
1346 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
1347 #define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
1348 #define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
1349 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
1350 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
1351 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
1352 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
1353 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
1354 #define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
1355 #define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
1356 /* 0=None, 1=DIF, 2=DIX */
1357 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
1358 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
1359 /* DIF tag right at the beginning of DIF interval */
1360 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
1361 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
1362 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
1363 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
1365 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
1366 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
1367 /* Forward application tag with mask */
1368 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
1369 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14
1370 /* Forward reference tag with mask */
1371 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
1372 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15
1374 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF
1375 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0
1376 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF
1377 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4
1378 #define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1
1379 #define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8
1380 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
1381 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
1382 /* mask for refernce tag handling */
1383 #define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
1384 #define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10
1385 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
1386 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
1391 enum rss_hash_type {
1392 RSS_HASH_TYPE_DEFAULT = 0,
1393 RSS_HASH_TYPE_IPV4 = 1,
1394 RSS_HASH_TYPE_TCP_IPV4 = 2,
1395 RSS_HASH_TYPE_IPV6 = 3,
1396 RSS_HASH_TYPE_TCP_IPV6 = 4,
1397 RSS_HASH_TYPE_UDP_IPV4 = 5,
1398 RSS_HASH_TYPE_UDP_IPV6 = 6,
1402 /* status block structure */
1403 struct status_block {
1404 __le16 pi_array[PIS_PER_SB];
1406 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF
1407 #define STATUS_BLOCK_SB_NUM_SHIFT 0
1408 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
1409 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9
1410 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
1411 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16
1413 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
1414 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0
1415 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
1416 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
1421 #define PXP_VF_BAR0 0
1423 #define PXP_VF_BAR0_START_GRC 0x3E00
1424 #define PXP_VF_BAR0_GRC_LENGTH 0x200
1425 #define PXP_VF_BAR0_END_GRC \
1426 (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1)
1428 #define PXP_VF_BAR0_START_IGU 0
1429 #define PXP_VF_BAR0_IGU_LENGTH 0x3000
1430 #define PXP_VF_BAR0_END_IGU \
1431 (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1)
1433 #define PXP_VF_BAR0_START_DQ 0x3000
1434 #define PXP_VF_BAR0_DQ_LENGTH 0x200
1435 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
1436 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
1437 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
1438 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS \
1439 (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4)
1440 #define PXP_VF_BAR0_END_DQ \
1441 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1)
1443 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
1444 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
1445 #define PXP_VF_BAR0_END_TSDM_ZONE_B \
1446 (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1448 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
1449 #define PXP_VF_BAR0_END_MSDM_ZONE_B \
1450 (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1452 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
1453 #define PXP_VF_BAR0_END_USDM_ZONE_B \
1454 (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1456 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
1457 #define PXP_VF_BAR0_END_XSDM_ZONE_B \
1458 (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1460 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
1461 #define PXP_VF_BAR0_END_YSDM_ZONE_B \
1462 (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1464 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
1465 #define PXP_VF_BAR0_END_PSDM_ZONE_B \
1466 (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
1468 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
1469 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
1471 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
1476 struct tdif_task_context {
1477 __le32 initialRefTag;
1480 __le16 partialCrcValueB;
1481 __le16 partialChecksumValueB;
1483 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF
1484 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0
1485 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF
1486 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4
1487 #define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1
1488 #define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8
1489 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
1490 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
1491 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
1492 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
1495 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
1496 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
1497 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
1498 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
1499 /* 0 = IP checksum, 1 = CRC */
1500 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
1501 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
1502 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
1503 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
1504 /* 1/2/3 - Protection Type */
1505 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
1506 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
1507 /* 0=0x0000, 1=0xffff */
1508 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1509 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1510 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
1511 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
1513 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
1514 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
1515 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
1516 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
1517 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
1518 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
1519 #define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
1520 #define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
1521 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
1522 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
1523 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
1524 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
1525 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
1526 #define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
1527 #define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
1528 /* 0=None, 1=DIF, 2=DIX */
1529 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
1530 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
1531 /* DIF tag right at the beginning of DIF interval */
1532 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
1533 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
1535 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
1536 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
1538 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
1539 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
1540 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF
1541 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14
1542 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF
1543 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18
1544 #define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1
1545 #define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22
1546 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1
1547 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23
1548 /* mask for refernce tag handling */
1549 #define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
1550 #define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24
1551 /* Forward application tag with mask */
1552 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
1553 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28
1554 /* Forward reference tag with mask */
1555 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
1556 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29
1557 /* Keep reference tag constant */
1558 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
1559 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30
1560 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
1561 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
1563 __le16 partialCrcValueA;
1564 __le16 partialChecksumValueA;
1566 u8 partialDifDataA[8];
1567 u8 partialDifDataB[8];
1574 struct timers_context {
1575 __le32 logical_client_0;
1576 /* Expiration time of logical client 0 */
1577 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
1578 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
1579 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1
1580 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27
1581 /* Valid bit of logical client 0 */
1582 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
1583 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28
1584 /* Active bit of logical client 0 */
1585 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1
1586 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
1587 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3
1588 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30
1589 __le32 logical_client_1;
1590 /* Expiration time of logical client 1 */
1591 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF
1592 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
1593 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1
1594 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27
1595 /* Valid bit of logical client 1 */
1596 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
1597 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28
1598 /* Active bit of logical client 1 */
1599 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1
1600 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
1601 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3
1602 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30
1603 __le32 logical_client_2;
1604 /* Expiration time of logical client 2 */
1605 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF
1606 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
1607 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1
1608 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27
1609 /* Valid bit of logical client 2 */
1610 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
1611 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28
1612 /* Active bit of logical client 2 */
1613 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1
1614 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29
1615 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3
1616 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30
1617 __le32 host_expiration_fields;
1618 /* Expiration time on host (closest one) */
1619 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF
1620 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
1621 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1
1622 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27
1623 /* Valid bit of host expiration */
1624 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1
1625 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28
1626 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7
1627 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29
1632 * Enum for next_protocol field of tunnel_parsing_flags
1634 enum tunnel_next_protocol {
1639 MAX_TUNNEL_NEXT_PROTOCOL
1642 #endif /* __COMMON_HSI__ */