2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_hsi_common.h"
13 #include "ecore_hsi_tools.h"
14 #include "ecore_proto_if.h"
15 #include "mcp_public.h"
17 #define MAX_HWFNS_PER_DEVICE (4)
18 #define NAME_SIZE 64 /* @DPDK */
20 /* @DPDK ARRAY_DECL */
21 #define ECORE_WFQ_UNIT 100
22 #include "../qede_logs.h" /* @DPDK */
25 #define ECORE_WID_SIZE (1024)
28 #define ECORE_PF_DEMS_SIZE (4)
31 enum ecore_coalescing_mode {
32 ECORE_COAL_MODE_DISABLE,
33 ECORE_COAL_MODE_ENABLE
37 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
38 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
39 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
40 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
41 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
42 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
43 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
44 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
45 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
46 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
47 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
51 #if !defined(CONFIG_ECORE_L2)
52 #define CONFIG_ECORE_L2
53 #define CONFIG_ECORE_SRIOV
58 #ifndef __EXTRACT__LINUX__
59 #define MASK_FIELD(_name, _value) \
60 ((_value) &= (_name##_MASK))
62 #define FIELD_VALUE(_name, _value) \
63 ((_value & _name##_MASK) << _name##_SHIFT)
65 #define SET_FIELD(value, name, flag) \
67 (value) &= ~(name##_MASK << name##_SHIFT); \
68 (value) |= (((u64)flag) << (name##_SHIFT)); \
71 #define GET_FIELD(value, name) \
72 (((value) >> (name##_SHIFT)) & name##_MASK)
75 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
77 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
78 (cid * ECORE_PF_DEMS_SIZE);
83 /* @DPDK: This is a backport from latest ecore for TSS fix */
84 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
86 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
87 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
92 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
93 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
94 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
97 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
101 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
104 #ifndef __EXTRACT__LINUX__
106 ECORE_LEVEL_VERBOSE = 0x0,
107 ECORE_LEVEL_INFO = 0x1,
108 ECORE_LEVEL_NOTICE = 0x2,
109 ECORE_LEVEL_ERR = 0x3,
112 #define ECORE_LOG_LEVEL_SHIFT (30)
113 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
114 #define ECORE_LOG_INFO_MASK (0x40000000)
115 #define ECORE_LOG_NOTICE_MASK (0x80000000)
119 ECORE_MSG_DRV = 0x0001,
120 ECORE_MSG_PROBE = 0x0002,
121 ECORE_MSG_LINK = 0x0004,
122 ECORE_MSG_TIMER = 0x0008,
123 ECORE_MSG_IFDOWN = 0x0010,
124 ECORE_MSG_IFUP = 0x0020,
125 ECORE_MSG_RX_ERR = 0x0040,
126 ECORE_MSG_TX_ERR = 0x0080,
127 ECORE_MSG_TX_QUEUED = 0x0100,
128 ECORE_MSG_INTR = 0x0200,
129 ECORE_MSG_TX_DONE = 0x0400,
130 ECORE_MSG_RX_STATUS = 0x0800,
131 ECORE_MSG_PKTDATA = 0x1000,
132 ECORE_MSG_HW = 0x2000,
133 ECORE_MSG_WOL = 0x4000,
135 ECORE_MSG_SPQ = 0x10000,
136 ECORE_MSG_STATS = 0x20000,
137 ECORE_MSG_DCB = 0x40000,
138 ECORE_MSG_IOV = 0x80000,
139 ECORE_MSG_SP = 0x100000,
140 ECORE_MSG_STORAGE = 0x200000,
141 ECORE_MSG_CXT = 0x800000,
142 ECORE_MSG_ILT = 0x2000000,
143 ECORE_MSG_DEBUG = 0x8000000,
144 /* to be added...up to 0x8000000 */
148 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
150 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
151 (val == (cond1) ? true1 : \
152 (val == (cond2) ? true2 : def))
155 struct ecore_ptt_pool;
157 struct ecore_sb_info;
158 struct ecore_sb_attn_info;
159 struct ecore_cxt_mngr;
160 struct ecore_dma_mem;
161 struct ecore_sb_sp_info;
162 struct ecore_igu_info;
163 struct ecore_mcp_info;
165 struct ecore_rt_data {
170 enum ecore_tunn_mode {
171 ECORE_MODE_L2GENEVE_TUNN,
172 ECORE_MODE_IPGENEVE_TUNN,
173 ECORE_MODE_L2GRE_TUNN,
174 ECORE_MODE_IPGRE_TUNN,
175 ECORE_MODE_VXLAN_TUNN,
178 enum ecore_tunn_clss {
179 ECORE_TUNN_CLSS_MAC_VLAN,
180 ECORE_TUNN_CLSS_MAC_VNI,
181 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
182 ECORE_TUNN_CLSS_INNER_MAC_VNI,
186 struct ecore_tunn_start_params {
187 unsigned long tunn_mode;
190 u8 update_vxlan_udp_port;
191 u8 update_geneve_udp_port;
193 u8 tunn_clss_l2geneve;
194 u8 tunn_clss_ipgeneve;
199 struct ecore_tunn_update_params {
200 unsigned long tunn_mode_update_mask;
201 unsigned long tunn_mode;
204 u8 update_rx_pf_clss;
205 u8 update_tx_pf_clss;
206 u8 update_vxlan_udp_port;
207 u8 update_geneve_udp_port;
209 u8 tunn_clss_l2geneve;
210 u8 tunn_clss_ipgeneve;
215 struct ecore_hw_sriov_info {
216 /* standard SRIOV capability fields, mostly for debugging */
217 int pos; /* capability position */
218 int nres; /* number of resources */
219 u32 cap; /* SR-IOV Capabilities */
220 u16 ctrl; /* SR-IOV Control */
221 u16 total_vfs; /* total VFs associated with the PF */
222 u16 num_vfs; /* number of vfs that have been started */
223 u64 active_vfs[3]; /* bitfield of active vfs */
224 #define ECORE_IS_VF_ACTIVE(_p_dev, _rel_vf_id) \
225 (!!(_p_dev->sriov_info.active_vfs[_rel_vf_id / 64] & \
226 (1ULL << (_rel_vf_id % 64))))
227 u16 initial_vfs; /* initial VFs associated with the PF */
228 u16 nr_virtfn; /* number of VFs available */
229 u16 offset; /* first VF Routing ID offset */
230 u16 stride; /* following VF stride */
231 u16 vf_device_id; /* VF device id */
232 u32 pgsz; /* page size for BAR alignment */
233 u8 link; /* Function Dependency Link */
235 bool b_hw_channel; /* Whether PF uses the HW-channel */
238 /* The PCI personality is not quite synonymous to protocol ID:
239 * 1. All personalities need CORE connections
240 * 2. The Ethernet personality may support also the RoCE protocol
242 enum ecore_pci_personality {
244 ECORE_PCI_DEFAULT /* default in shmem */
247 /* All VFs are symmetric, all counters are PF + all VFs */
248 struct ecore_qm_iids {
254 #define MAX_PF_PER_PORT 8
256 /*@@@TBD MK RESC: need to remove and use MCP interface instead */
257 /* HW / FW resources, output of features supported below, most information
258 * is received from MFW.
260 enum ECORE_RESOURCES {
274 /* Features that require resources, given as input to the resource management
275 * algorithm, the output are the resources above
286 enum ECORE_PORT_MODE {
287 ECORE_PORT_MODE_DE_2X40G,
288 ECORE_PORT_MODE_DE_2X50G,
289 ECORE_PORT_MODE_DE_1X100G,
290 ECORE_PORT_MODE_DE_4X10G_F,
291 ECORE_PORT_MODE_DE_4X10G_E,
292 ECORE_PORT_MODE_DE_4X20G,
293 ECORE_PORT_MODE_DE_1X40G,
294 ECORE_PORT_MODE_DE_2X25G,
295 ECORE_PORT_MODE_DE_1X25G
302 #ifndef __EXTRACT__LINUX__
303 enum ecore_hw_err_type {
304 ECORE_HW_ERR_FAN_FAIL,
305 ECORE_HW_ERR_MFW_RESP_FAIL,
306 ECORE_HW_ERR_HW_ATTN,
307 ECORE_HW_ERR_DMAE_FAIL,
308 ECORE_HW_ERR_RAMROD_FAIL,
309 ECORE_HW_ERR_FW_ASSERT,
313 struct ecore_hw_info {
314 /* PCI personality */
315 enum ecore_pci_personality personality;
317 /* Resource Allocation scheme results */
318 u32 resc_start[ECORE_MAX_RESC];
319 u32 resc_num[ECORE_MAX_RESC];
320 u32 feat_num[ECORE_MAX_FEATURES];
322 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
323 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
324 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
325 RESC_NUM(_p_hwfn, resc))
326 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
338 unsigned char hw_mac_addr[ETH_ALEN];
340 struct ecore_igu_info *p_igu_info;
343 u8 max_chains_per_vf;
347 unsigned long device_capabilities;
350 struct ecore_hw_cid_data {
352 bool b_cid_allocated;
353 u8 vfid; /* 1-based; 0 signals this is for a PF */
355 /* Additional identifiers */
360 /* maximun size of read/write commands (HW limit) */
361 #define DMAE_MAX_RW_SIZE 0x2000
363 struct ecore_dmae_info {
364 /* Mutex for synchronizing access to functions */
369 dma_addr_t completion_word_phys_addr;
371 /* The memory location where the DMAE writes the completion
372 * value when an operation is finished on this context.
374 u32 *p_completion_word;
376 dma_addr_t intermediate_buffer_phys_addr;
378 /* An intermediate buffer for DMAE operations that use virtual
379 * addresses - data is DMA'd to/from this buffer and then
380 * memcpy'd to/from the virtual address
382 u32 *p_intermediate_buffer;
384 dma_addr_t dmae_cmd_phys_addr;
385 struct dmae_cmd *p_dmae_cmd;
388 struct ecore_wfq_data {
389 u32 default_min_speed; /* When wfq feature is not configured */
390 u32 min_speed; /* when feature is configured for any 1 vport */
394 struct ecore_qm_info {
395 struct init_qm_pq_params *qm_pq_params;
396 struct init_qm_vport_params *qm_vport_params;
397 struct init_qm_port_params *qm_port_params;
408 u8 max_phys_tcs_per_port;
415 struct ecore_wfq_data *wfq_data;
423 #define CONFIG_ECORE_BINARY_FW
424 #define CONFIG_ECORE_ZIPPED_FW
426 struct ecore_fw_data {
427 #ifdef CONFIG_ECORE_BINARY_FW
428 struct fw_ver_info *fw_ver_info;
430 const u8 *modes_tree_buf;
431 union init_op *init_ops;
437 struct ecore_dev *p_dev;
438 u8 my_id; /* ID inside the PF */
439 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
440 u8 rel_pf_id; /* Relative to engine */
442 #define ECORE_PATH_ID(_p_hwfn) \
443 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
449 char name[NAME_SIZE];
452 bool first_on_engine;
455 u8 num_funcs_on_engine;
458 void OSAL_IOMEM *regview;
459 void OSAL_IOMEM *doorbells;
461 unsigned long db_size;
464 struct ecore_ptt_pool *p_ptt_pool;
467 struct ecore_hw_info hw_info;
469 /* rt_array (for init-tool) */
470 struct ecore_rt_data rt_data;
473 struct ecore_spq *p_spq;
476 struct ecore_eq *p_eq;
479 struct ecore_consq *p_consq;
481 /* Slow-Path definitions */
483 bool b_sp_dpc_enabled;
485 struct ecore_ptt *p_main_ptt;
486 struct ecore_ptt *p_dpc_ptt;
488 struct ecore_sb_sp_info *p_sp_sb;
489 struct ecore_sb_attn_info *p_sb_attn;
491 /* Protocol related */
492 struct ecore_ooo_info *p_ooo_info;
493 struct ecore_pf_params pf_params;
495 /* Array of sb_info of all status blocks */
496 struct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
499 struct ecore_cxt_mngr *p_cxt_mngr;
501 /* Flag indicating whether interrupts are enabled or not */
503 bool b_int_requested;
505 /* True if the driver requests for the link */
506 bool b_drv_link_init;
508 struct ecore_vf_iov *vf_iov_info;
509 struct ecore_pf_iov *pf_iov_info;
510 struct ecore_mcp_info *mcp_info;
512 struct ecore_hw_cid_data *p_tx_cids;
513 struct ecore_hw_cid_data *p_rx_cids;
515 struct ecore_dmae_info dmae_info;
518 struct ecore_qm_info qm_info;
520 /* Buffer for unzipping firmware data */
521 #ifdef CONFIG_ECORE_ZIPPED_FW
525 struct dbg_tools_data dbg_info;
527 struct z_stream_s *stream;
529 /* PWM region specific data */
532 u32 dpi_start_offset; /* this is used to
538 #ifndef __EXTRACT__LINUX__
549 char name[NAME_SIZE];
553 #define ECORE_DEV_TYPE_BB (0 << 0)
554 #define ECORE_DEV_TYPE_AH (1 << 0)
555 /* Translate type/revision combo into the proper conditions */
556 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
557 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && \
559 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && \
561 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
562 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
563 #define ECORE_GET_TYPE(dev) (ECORE_IS_BB_A0(dev) ? CHIP_BB_A0 : \
564 ECORE_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
570 #define CHIP_NUM_MASK 0xffff
571 #define CHIP_NUM_SHIFT 16
574 #define CHIP_REV_MASK 0xf
575 #define CHIP_REV_SHIFT 12
577 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
578 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
579 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
580 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
581 CHIP_REV_IS_EMUL_B0(_p_dev))
582 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
583 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
584 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
585 CHIP_REV_IS_FPGA_B0(_p_dev))
586 #define CHIP_REV_IS_SLOW(_p_dev) \
587 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
588 #define CHIP_REV_IS_A0(_p_dev) \
589 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
590 CHIP_REV_IS_FPGA_A0(_p_dev) || \
592 #define CHIP_REV_IS_B0(_p_dev) \
593 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
594 CHIP_REV_IS_FPGA_B0(_p_dev) || \
595 (_p_dev)->chip_rev == 1)
596 #define CHIP_REV_IS_ASIC(_p_dev) (!CHIP_REV_IS_SLOW(_p_dev))
598 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev)
599 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1)
603 #define CHIP_METAL_MASK 0xff
604 #define CHIP_METAL_SHIFT 4
607 #define CHIP_BOND_ID_MASK 0xf
608 #define CHIP_BOND_ID_SHIFT 0
611 u8 num_ports_in_engines;
612 u8 num_funcs_in_port;
615 enum ecore_mf_mode mf_mode;
616 #define IS_MF_DEFAULT(_p_hwfn) \
617 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
618 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
619 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
623 u8 ver_str[VER_SIZE];
624 /* Add MF related configuration */
631 enum ecore_coalescing_mode int_coalescing_mode;
632 u8 rx_coalesce_usecs;
633 u8 tx_coalesce_usecs;
635 /* Start Bar offset of first hwfn */
636 void OSAL_IOMEM *regview;
637 void OSAL_IOMEM *doorbells;
639 unsigned long db_size;
645 const struct iro *iro_arr;
646 #define IRO (p_hwfn->p_dev->iro_arr)
650 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
653 struct ecore_hw_sriov_info sriov_info;
654 unsigned long tunn_mode;
655 #define IS_ECORE_SRIOV(edev) (!!((edev)->sriov_info.total_vfs))
660 struct ecore_eth_stats *reset_stats;
661 struct ecore_fw_data *fw_data;
678 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
680 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
681 : MAX_NUM_L2_QUEUES_K2)
682 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
684 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
685 : MAX_SB_PER_PATH_K2)
686 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
689 #define ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn) ( \
690 (ECORE_IS_BB_A0(p_hwfn->p_dev)) && \
691 (ECORE_PATH_ID(p_hwfn) == 1) && \
692 ((p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X40G) || \
693 (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X50G) || \
694 (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X25G)))
697 * @brief ecore_concrete_to_sw_fid - get the sw function id from
698 * the concrete value.
700 * @param concrete_fid
702 * @return OSAL_INLINE u8
704 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
707 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
708 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
709 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
713 sw_fid = vfid + MAX_NUM_PFS;
723 static OSAL_INLINE u16 ecore_sriov_get_next_vf(struct ecore_hwfn *p_hwfn,
728 for (i = rel_vf_id; i < p_hwfn->p_dev->sriov_info.total_vfs; i++)
729 if (ECORE_IS_VF_ACTIVE(p_hwfn->p_dev, i))
732 return p_hwfn->p_dev->sriov_info.total_vfs;
735 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
736 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
739 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
740 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
741 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
742 int ecore_device_num_engines(struct ecore_dev *p_dev);
743 int ecore_device_num_ports(struct ecore_dev *p_dev);
745 #define ecore_for_each_vf(_p_hwfn, _i) \
746 for (_i = ecore_sriov_get_next_vf(_p_hwfn, 0); \
747 _i < _p_hwfn->p_dev->sriov_info.total_vfs; \
748 _i = ecore_sriov_get_next_vf(_p_hwfn, _i + 1))
750 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
752 #endif /* __ECORE_H */