2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_hsi_common.h"
13 #include "ecore_hsi_tools.h"
14 #include "ecore_proto_if.h"
15 #include "mcp_public.h"
17 #define MAX_HWFNS_PER_DEVICE (4)
18 #define NAME_SIZE 64 /* @DPDK */
20 /* @DPDK ARRAY_DECL */
21 #define ECORE_WFQ_UNIT 100
22 #include "../qede_logs.h" /* @DPDK */
25 #define ECORE_WID_SIZE (1024)
28 #define ECORE_PF_DEMS_SIZE (4)
31 enum ecore_coalescing_mode {
32 ECORE_COAL_MODE_DISABLE,
33 ECORE_COAL_MODE_ENABLE
37 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
38 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
39 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
40 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
41 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
42 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
43 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
44 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
45 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
46 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
47 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
51 #if !defined(CONFIG_ECORE_L2)
52 #define CONFIG_ECORE_L2
57 #ifndef __EXTRACT__LINUX__
58 #define MASK_FIELD(_name, _value) \
59 ((_value) &= (_name##_MASK))
61 #define FIELD_VALUE(_name, _value) \
62 ((_value & _name##_MASK) << _name##_SHIFT)
64 #define SET_FIELD(value, name, flag) \
66 (value) &= ~(name##_MASK << name##_SHIFT); \
67 (value) |= (((u64)flag) << (name##_SHIFT)); \
70 #define GET_FIELD(value, name) \
71 (((value) >> (name##_SHIFT)) & name##_MASK)
74 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
76 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
77 (cid * ECORE_PF_DEMS_SIZE);
82 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
83 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
84 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
87 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
91 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
94 #ifndef __EXTRACT__LINUX__
96 ECORE_LEVEL_VERBOSE = 0x0,
97 ECORE_LEVEL_INFO = 0x1,
98 ECORE_LEVEL_NOTICE = 0x2,
99 ECORE_LEVEL_ERR = 0x3,
102 #define ECORE_LOG_LEVEL_SHIFT (30)
103 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
104 #define ECORE_LOG_INFO_MASK (0x40000000)
105 #define ECORE_LOG_NOTICE_MASK (0x80000000)
109 ECORE_MSG_DRV = 0x0001,
110 ECORE_MSG_PROBE = 0x0002,
111 ECORE_MSG_LINK = 0x0004,
112 ECORE_MSG_TIMER = 0x0008,
113 ECORE_MSG_IFDOWN = 0x0010,
114 ECORE_MSG_IFUP = 0x0020,
115 ECORE_MSG_RX_ERR = 0x0040,
116 ECORE_MSG_TX_ERR = 0x0080,
117 ECORE_MSG_TX_QUEUED = 0x0100,
118 ECORE_MSG_INTR = 0x0200,
119 ECORE_MSG_TX_DONE = 0x0400,
120 ECORE_MSG_RX_STATUS = 0x0800,
121 ECORE_MSG_PKTDATA = 0x1000,
122 ECORE_MSG_HW = 0x2000,
123 ECORE_MSG_WOL = 0x4000,
125 ECORE_MSG_SPQ = 0x10000,
126 ECORE_MSG_STATS = 0x20000,
127 ECORE_MSG_DCB = 0x40000,
128 ECORE_MSG_IOV = 0x80000,
129 ECORE_MSG_SP = 0x100000,
130 ECORE_MSG_STORAGE = 0x200000,
131 ECORE_MSG_CXT = 0x800000,
132 ECORE_MSG_ILT = 0x2000000,
133 ECORE_MSG_DEBUG = 0x8000000,
134 /* to be added...up to 0x8000000 */
138 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
140 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
141 (val == (cond1) ? true1 : \
142 (val == (cond2) ? true2 : def))
145 struct ecore_ptt_pool;
147 struct ecore_sb_info;
148 struct ecore_sb_attn_info;
149 struct ecore_cxt_mngr;
150 struct ecore_dma_mem;
151 struct ecore_sb_sp_info;
152 struct ecore_igu_info;
153 struct ecore_mcp_info;
155 struct ecore_rt_data {
160 enum ecore_tunn_mode {
161 ECORE_MODE_L2GENEVE_TUNN,
162 ECORE_MODE_IPGENEVE_TUNN,
163 ECORE_MODE_L2GRE_TUNN,
164 ECORE_MODE_IPGRE_TUNN,
165 ECORE_MODE_VXLAN_TUNN,
168 enum ecore_tunn_clss {
169 ECORE_TUNN_CLSS_MAC_VLAN,
170 ECORE_TUNN_CLSS_MAC_VNI,
171 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
172 ECORE_TUNN_CLSS_INNER_MAC_VNI,
176 struct ecore_tunn_start_params {
177 unsigned long tunn_mode;
180 u8 update_vxlan_udp_port;
181 u8 update_geneve_udp_port;
183 u8 tunn_clss_l2geneve;
184 u8 tunn_clss_ipgeneve;
189 struct ecore_tunn_update_params {
190 unsigned long tunn_mode_update_mask;
191 unsigned long tunn_mode;
194 u8 update_rx_pf_clss;
195 u8 update_tx_pf_clss;
196 u8 update_vxlan_udp_port;
197 u8 update_geneve_udp_port;
199 u8 tunn_clss_l2geneve;
200 u8 tunn_clss_ipgeneve;
205 struct ecore_hw_sriov_info {
206 /* standard SRIOV capability fields, mostly for debugging */
207 int pos; /* capability position */
208 int nres; /* number of resources */
209 u32 cap; /* SR-IOV Capabilities */
210 u16 ctrl; /* SR-IOV Control */
211 u16 total_vfs; /* total VFs associated with the PF */
212 u16 num_vfs; /* number of vfs that have been started */
213 u64 active_vfs[3]; /* bitfield of active vfs */
214 #define ECORE_IS_VF_ACTIVE(_p_dev, _rel_vf_id) \
215 (!!(_p_dev->sriov_info.active_vfs[_rel_vf_id / 64] & \
216 (1ULL << (_rel_vf_id % 64))))
217 u16 initial_vfs; /* initial VFs associated with the PF */
218 u16 nr_virtfn; /* number of VFs available */
219 u16 offset; /* first VF Routing ID offset */
220 u16 stride; /* following VF stride */
221 u16 vf_device_id; /* VF device id */
222 u32 pgsz; /* page size for BAR alignment */
223 u8 link; /* Function Dependency Link */
225 bool b_hw_channel; /* Whether PF uses the HW-channel */
228 /* The PCI personality is not quite synonymous to protocol ID:
229 * 1. All personalities need CORE connections
230 * 2. The Ethernet personality may support also the RoCE protocol
232 enum ecore_pci_personality {
234 ECORE_PCI_DEFAULT /* default in shmem */
237 /* All VFs are symmetric, all counters are PF + all VFs */
238 struct ecore_qm_iids {
244 #define MAX_PF_PER_PORT 8
246 /*@@@TBD MK RESC: need to remove and use MCP interface instead */
247 /* HW / FW resources, output of features supported below, most information
248 * is received from MFW.
250 enum ECORE_RESOURCES {
264 /* Features that require resources, given as input to the resource management
265 * algorithm, the output are the resources above
276 enum ECORE_PORT_MODE {
277 ECORE_PORT_MODE_DE_2X40G,
278 ECORE_PORT_MODE_DE_2X50G,
279 ECORE_PORT_MODE_DE_1X100G,
280 ECORE_PORT_MODE_DE_4X10G_F,
281 ECORE_PORT_MODE_DE_4X10G_E,
282 ECORE_PORT_MODE_DE_4X20G,
283 ECORE_PORT_MODE_DE_1X40G,
284 ECORE_PORT_MODE_DE_2X25G,
285 ECORE_PORT_MODE_DE_1X25G
292 #ifndef __EXTRACT__LINUX__
293 enum ecore_hw_err_type {
294 ECORE_HW_ERR_FAN_FAIL,
295 ECORE_HW_ERR_MFW_RESP_FAIL,
296 ECORE_HW_ERR_HW_ATTN,
297 ECORE_HW_ERR_DMAE_FAIL,
298 ECORE_HW_ERR_RAMROD_FAIL,
299 ECORE_HW_ERR_FW_ASSERT,
303 struct ecore_hw_info {
304 /* PCI personality */
305 enum ecore_pci_personality personality;
307 /* Resource Allocation scheme results */
308 u32 resc_start[ECORE_MAX_RESC];
309 u32 resc_num[ECORE_MAX_RESC];
310 u32 feat_num[ECORE_MAX_FEATURES];
312 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
313 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
314 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
315 RESC_NUM(_p_hwfn, resc))
316 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
328 unsigned char hw_mac_addr[ETH_ALEN];
330 struct ecore_igu_info *p_igu_info;
333 u8 max_chains_per_vf;
337 unsigned long device_capabilities;
340 struct ecore_hw_cid_data {
342 bool b_cid_allocated;
343 u8 vfid; /* 1-based; 0 signals this is for a PF */
345 /* Additional identifiers */
350 /* maximun size of read/write commands (HW limit) */
351 #define DMAE_MAX_RW_SIZE 0x2000
353 struct ecore_dmae_info {
354 /* Mutex for synchronizing access to functions */
359 dma_addr_t completion_word_phys_addr;
361 /* The memory location where the DMAE writes the completion
362 * value when an operation is finished on this context.
364 u32 *p_completion_word;
366 dma_addr_t intermediate_buffer_phys_addr;
368 /* An intermediate buffer for DMAE operations that use virtual
369 * addresses - data is DMA'd to/from this buffer and then
370 * memcpy'd to/from the virtual address
372 u32 *p_intermediate_buffer;
374 dma_addr_t dmae_cmd_phys_addr;
375 struct dmae_cmd *p_dmae_cmd;
378 struct ecore_wfq_data {
379 u32 default_min_speed; /* When wfq feature is not configured */
380 u32 min_speed; /* when feature is configured for any 1 vport */
384 struct ecore_qm_info {
385 struct init_qm_pq_params *qm_pq_params;
386 struct init_qm_vport_params *qm_vport_params;
387 struct init_qm_port_params *qm_port_params;
398 u8 max_phys_tcs_per_port;
405 struct ecore_wfq_data *wfq_data;
413 #define CONFIG_ECORE_BINARY_FW
414 #define CONFIG_ECORE_ZIPPED_FW
416 struct ecore_fw_data {
417 #ifdef CONFIG_ECORE_BINARY_FW
418 struct fw_ver_info *fw_ver_info;
420 const u8 *modes_tree_buf;
421 union init_op *init_ops;
427 struct ecore_dev *p_dev;
428 u8 my_id; /* ID inside the PF */
429 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
430 u8 rel_pf_id; /* Relative to engine */
432 #define ECORE_PATH_ID(_p_hwfn) \
433 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
439 char name[NAME_SIZE];
442 bool first_on_engine;
445 u8 num_funcs_on_engine;
448 void OSAL_IOMEM *regview;
449 void OSAL_IOMEM *doorbells;
451 unsigned long db_size;
454 struct ecore_ptt_pool *p_ptt_pool;
457 struct ecore_hw_info hw_info;
459 /* rt_array (for init-tool) */
460 struct ecore_rt_data rt_data;
463 struct ecore_spq *p_spq;
466 struct ecore_eq *p_eq;
469 struct ecore_consq *p_consq;
471 /* Slow-Path definitions */
473 bool b_sp_dpc_enabled;
475 struct ecore_ptt *p_main_ptt;
476 struct ecore_ptt *p_dpc_ptt;
478 struct ecore_sb_sp_info *p_sp_sb;
479 struct ecore_sb_attn_info *p_sb_attn;
481 /* Protocol related */
482 struct ecore_ooo_info *p_ooo_info;
483 struct ecore_pf_params pf_params;
485 /* Array of sb_info of all status blocks */
486 struct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
489 struct ecore_cxt_mngr *p_cxt_mngr;
491 /* Flag indicating whether interrupts are enabled or not */
493 bool b_int_requested;
495 /* True if the driver requests for the link */
496 bool b_drv_link_init;
498 struct ecore_vf_iov *vf_iov_info;
499 struct ecore_pf_iov *pf_iov_info;
500 struct ecore_mcp_info *mcp_info;
502 struct ecore_hw_cid_data *p_tx_cids;
503 struct ecore_hw_cid_data *p_rx_cids;
505 struct ecore_dmae_info dmae_info;
508 struct ecore_qm_info qm_info;
510 /* Buffer for unzipping firmware data */
511 #ifdef CONFIG_ECORE_ZIPPED_FW
515 struct dbg_tools_data dbg_info;
517 struct z_stream_s *stream;
519 /* PWM region specific data */
522 u32 dpi_start_offset; /* this is used to
528 #ifndef __EXTRACT__LINUX__
539 char name[NAME_SIZE];
543 #define ECORE_DEV_TYPE_BB (0 << 0)
544 #define ECORE_DEV_TYPE_AH (1 << 0)
545 /* Translate type/revision combo into the proper conditions */
546 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
547 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && \
549 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && \
551 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
552 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
553 #define ECORE_GET_TYPE(dev) (ECORE_IS_BB_A0(dev) ? CHIP_BB_A0 : \
554 ECORE_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
560 #define CHIP_NUM_MASK 0xffff
561 #define CHIP_NUM_SHIFT 16
564 #define CHIP_REV_MASK 0xf
565 #define CHIP_REV_SHIFT 12
567 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
568 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
569 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
570 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
571 CHIP_REV_IS_EMUL_B0(_p_dev))
572 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
573 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
574 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
575 CHIP_REV_IS_FPGA_B0(_p_dev))
576 #define CHIP_REV_IS_SLOW(_p_dev) \
577 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
578 #define CHIP_REV_IS_A0(_p_dev) \
579 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
580 CHIP_REV_IS_FPGA_A0(_p_dev) || \
582 #define CHIP_REV_IS_B0(_p_dev) \
583 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
584 CHIP_REV_IS_FPGA_B0(_p_dev) || \
585 (_p_dev)->chip_rev == 1)
586 #define CHIP_REV_IS_ASIC(_p_dev) (!CHIP_REV_IS_SLOW(_p_dev))
588 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev)
589 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1)
593 #define CHIP_METAL_MASK 0xff
594 #define CHIP_METAL_SHIFT 4
597 #define CHIP_BOND_ID_MASK 0xf
598 #define CHIP_BOND_ID_SHIFT 0
601 u8 num_ports_in_engines;
602 u8 num_funcs_in_port;
605 enum ecore_mf_mode mf_mode;
606 #define IS_MF_DEFAULT(_p_hwfn) \
607 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
608 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
609 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
613 u8 ver_str[VER_SIZE];
614 /* Add MF related configuration */
621 enum ecore_coalescing_mode int_coalescing_mode;
622 u8 rx_coalesce_usecs;
623 u8 tx_coalesce_usecs;
625 /* Start Bar offset of first hwfn */
626 void OSAL_IOMEM *regview;
627 void OSAL_IOMEM *doorbells;
629 unsigned long db_size;
635 const struct iro *iro_arr;
636 #define IRO (p_hwfn->p_dev->iro_arr)
640 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
643 struct ecore_hw_sriov_info sriov_info;
644 unsigned long tunn_mode;
645 #define IS_ECORE_SRIOV(edev) (!!((edev)->sriov_info.total_vfs))
650 struct ecore_eth_stats *reset_stats;
651 struct ecore_fw_data *fw_data;
668 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
670 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
671 : MAX_NUM_L2_QUEUES_K2)
672 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
674 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
675 : MAX_SB_PER_PATH_K2)
676 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
679 #define ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn) ( \
680 (ECORE_IS_BB_A0(p_hwfn->p_dev)) && \
681 (ECORE_PATH_ID(p_hwfn) == 1) && \
682 ((p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X40G) || \
683 (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X50G) || \
684 (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X25G)))
687 * @brief ecore_concrete_to_sw_fid - get the sw function id from
688 * the concrete value.
690 * @param concrete_fid
692 * @return OSAL_INLINE u8
694 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
697 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
698 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
699 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
703 sw_fid = vfid + MAX_NUM_PFS;
713 static OSAL_INLINE u16 ecore_sriov_get_next_vf(struct ecore_hwfn *p_hwfn,
718 for (i = rel_vf_id; i < p_hwfn->p_dev->sriov_info.total_vfs; i++)
719 if (ECORE_IS_VF_ACTIVE(p_hwfn->p_dev, i))
722 return p_hwfn->p_dev->sriov_info.total_vfs;
725 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
726 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
729 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
730 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
731 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
732 int ecore_device_num_engines(struct ecore_dev *p_dev);
733 int ecore_device_num_ports(struct ecore_dev *p_dev);
735 #define ecore_for_each_vf(_p_hwfn, _i) \
736 for (_i = ecore_sriov_get_next_vf(_p_hwfn, 0); \
737 _i < _p_hwfn->p_dev->sriov_info.total_vfs; \
738 _i = ecore_sriov_get_next_vf(_p_hwfn, _i + 1))
740 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
742 #endif /* __ECORE_H */