2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
17 #define CONFIG_ECORE_BINARY_FW
18 #undef CONFIG_ECORE_ZIPPED_FW
20 #ifdef CONFIG_ECORE_ZIPPED_FW
24 #include "ecore_hsi_common.h"
25 #include "ecore_hsi_debug_tools.h"
26 #include "ecore_hsi_init_func.h"
27 #include "ecore_hsi_init_tool.h"
28 #include "ecore_proto_if.h"
29 #include "mcp_public.h"
31 #define ECORE_MAJOR_VERSION 8
32 #define ECORE_MINOR_VERSION 18
33 #define ECORE_REVISION_VERSION 7
34 #define ECORE_ENGINEERING_VERSION 1
36 #define ECORE_VERSION \
37 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \
38 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
40 #define STORM_FW_VERSION \
41 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
42 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
44 #define MAX_HWFNS_PER_DEVICE 2
45 #define NAME_SIZE 128 /* @DPDK */
46 #define ECORE_WFQ_UNIT 100
47 #include "../qede_logs.h" /* @DPDK */
49 #define ISCSI_BDQ_ID(_port_id) (_port_id)
50 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
52 #define ECORE_WID_SIZE (1024)
53 #define ECORE_MIN_WIDS (4)
56 #define ECORE_PF_DEMS_SIZE (4)
59 enum ecore_coalescing_mode {
60 ECORE_COAL_MODE_DISABLE,
61 ECORE_COAL_MODE_ENABLE
65 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
66 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
67 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
68 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
69 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
70 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
71 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
72 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
73 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
74 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
75 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
76 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
80 #if !defined(CONFIG_ECORE_L2)
81 #define CONFIG_ECORE_L2
82 #define CONFIG_ECORE_SRIOV
87 #ifndef __EXTRACT__LINUX__
88 #define MASK_FIELD(_name, _value) \
89 ((_value) &= (_name##_MASK))
91 #define FIELD_VALUE(_name, _value) \
92 ((_value & _name##_MASK) << _name##_SHIFT)
94 #define SET_FIELD(value, name, flag) \
96 (value) &= ~(name##_MASK << name##_SHIFT); \
97 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
100 #define GET_FIELD(value, name) \
101 (((value) >> (name##_SHIFT)) & name##_MASK)
103 #define GET_MFW_FIELD(name, field) \
104 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
106 #define SET_MFW_FIELD(name, field, value) \
108 (name) &= ~((field ## _MASK)); \
109 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
113 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
115 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
116 (cid * ECORE_PF_DEMS_SIZE);
121 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
123 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
124 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
129 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
130 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
131 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
135 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
139 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
143 #ifndef __EXTRACT__LINUX__
145 ECORE_LEVEL_VERBOSE = 0x0,
146 ECORE_LEVEL_INFO = 0x1,
147 ECORE_LEVEL_NOTICE = 0x2,
148 ECORE_LEVEL_ERR = 0x3,
151 #define ECORE_LOG_LEVEL_SHIFT (30)
152 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
153 #define ECORE_LOG_INFO_MASK (0x40000000)
154 #define ECORE_LOG_NOTICE_MASK (0x80000000)
158 ECORE_MSG_DRV = 0x0001,
159 ECORE_MSG_PROBE = 0x0002,
160 ECORE_MSG_LINK = 0x0004,
161 ECORE_MSG_TIMER = 0x0008,
162 ECORE_MSG_IFDOWN = 0x0010,
163 ECORE_MSG_IFUP = 0x0020,
164 ECORE_MSG_RX_ERR = 0x0040,
165 ECORE_MSG_TX_ERR = 0x0080,
166 ECORE_MSG_TX_QUEUED = 0x0100,
167 ECORE_MSG_INTR = 0x0200,
168 ECORE_MSG_TX_DONE = 0x0400,
169 ECORE_MSG_RX_STATUS = 0x0800,
170 ECORE_MSG_PKTDATA = 0x1000,
171 ECORE_MSG_HW = 0x2000,
172 ECORE_MSG_WOL = 0x4000,
174 ECORE_MSG_SPQ = 0x10000,
175 ECORE_MSG_STATS = 0x20000,
176 ECORE_MSG_DCB = 0x40000,
177 ECORE_MSG_IOV = 0x80000,
178 ECORE_MSG_SP = 0x100000,
179 ECORE_MSG_STORAGE = 0x200000,
180 ECORE_MSG_OOO = 0x200000,
181 ECORE_MSG_CXT = 0x800000,
182 ECORE_MSG_LL2 = 0x1000000,
183 ECORE_MSG_ILT = 0x2000000,
184 ECORE_MSG_RDMA = 0x4000000,
185 ECORE_MSG_DEBUG = 0x8000000,
186 /* to be added...up to 0x8000000 */
190 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
192 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
193 (val == (cond1) ? true1 : \
194 (val == (cond2) ? true2 : def))
197 struct ecore_ptt_pool;
199 struct ecore_sb_info;
200 struct ecore_sb_attn_info;
201 struct ecore_cxt_mngr;
202 struct ecore_dma_mem;
203 struct ecore_sb_sp_info;
204 struct ecore_ll2_info;
205 struct ecore_l2_info;
206 struct ecore_igu_info;
207 struct ecore_mcp_info;
208 struct ecore_dcbx_info;
210 struct ecore_rt_data {
215 enum ecore_tunn_mode {
216 ECORE_MODE_L2GENEVE_TUNN,
217 ECORE_MODE_IPGENEVE_TUNN,
218 ECORE_MODE_L2GRE_TUNN,
219 ECORE_MODE_IPGRE_TUNN,
220 ECORE_MODE_VXLAN_TUNN,
223 enum ecore_tunn_clss {
224 ECORE_TUNN_CLSS_MAC_VLAN,
225 ECORE_TUNN_CLSS_MAC_VNI,
226 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
227 ECORE_TUNN_CLSS_INNER_MAC_VNI,
228 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
232 struct ecore_tunn_update_type {
235 enum ecore_tunn_clss tun_cls;
238 struct ecore_tunn_update_udp_port {
243 struct ecore_tunnel_info {
244 struct ecore_tunn_update_type vxlan;
245 struct ecore_tunn_update_type l2_geneve;
246 struct ecore_tunn_update_type ip_geneve;
247 struct ecore_tunn_update_type l2_gre;
248 struct ecore_tunn_update_type ip_gre;
250 struct ecore_tunn_update_udp_port vxlan_port;
251 struct ecore_tunn_update_udp_port geneve_port;
253 bool b_update_rx_cls;
254 bool b_update_tx_cls;
257 /* The PCI personality is not quite synonymous to protocol ID:
258 * 1. All personalities need CORE connections
259 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
261 enum ecore_pci_personality {
268 ECORE_PCI_DEFAULT /* default in shmem */
271 /* All VFs are symmetric, all counters are PF + all VFs */
272 struct ecore_qm_iids {
278 #define MAX_PF_PER_PORT 8
280 /* HW / FW resources, output of features supported below, most information
281 * is received from MFW.
283 enum ecore_resources {
295 ECORE_RDMA_STATS_QUEUE,
298 /* This is needed only internally for matching against the IGU.
299 * In case of legacy MFW, would be set to `0'.
306 /* Features that require resources, given as input to the resource management
307 * algorithm, the output are the resources above
322 enum ecore_port_mode {
323 ECORE_PORT_MODE_DE_2X40G,
324 ECORE_PORT_MODE_DE_2X50G,
325 ECORE_PORT_MODE_DE_1X100G,
326 ECORE_PORT_MODE_DE_4X10G_F,
327 ECORE_PORT_MODE_DE_4X10G_E,
328 ECORE_PORT_MODE_DE_4X20G,
329 ECORE_PORT_MODE_DE_1X40G,
330 ECORE_PORT_MODE_DE_2X25G,
331 ECORE_PORT_MODE_DE_1X25G,
332 ECORE_PORT_MODE_DE_4X25G,
333 ECORE_PORT_MODE_DE_2X10G,
344 #ifndef __EXTRACT__LINUX__
345 enum ecore_hw_err_type {
346 ECORE_HW_ERR_FAN_FAIL,
347 ECORE_HW_ERR_MFW_RESP_FAIL,
348 ECORE_HW_ERR_HW_ATTN,
349 ECORE_HW_ERR_DMAE_FAIL,
350 ECORE_HW_ERR_RAMROD_FAIL,
351 ECORE_HW_ERR_FW_ASSERT,
355 enum ecore_db_rec_exec {
361 struct ecore_hw_info {
362 /* PCI personality */
363 enum ecore_pci_personality personality;
364 #define ECORE_IS_RDMA_PERSONALITY(dev) \
365 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
366 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
367 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
368 #define ECORE_IS_ROCE_PERSONALITY(dev) \
369 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
370 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
371 #define ECORE_IS_IWARP_PERSONALITY(dev) \
372 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
373 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
374 #define ECORE_IS_L2_PERSONALITY(dev) \
375 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
376 ECORE_IS_RDMA_PERSONALITY(dev))
378 /* Resource Allocation scheme results */
379 u32 resc_start[ECORE_MAX_RESC];
380 u32 resc_num[ECORE_MAX_RESC];
381 u32 feat_num[ECORE_MAX_FEATURES];
383 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
384 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
385 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
386 RESC_NUM(_p_hwfn, resc))
387 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
389 /* Amount of traffic classes HW supports */
392 /* Amount of TCs which should be active according to DCBx or upper layer driver
398 /* The traffic class used by PF for it's offloaded protocol */
406 unsigned char hw_mac_addr[ETH_ALEN];
407 u64 node_wwn; /* For FCoE only */
408 u64 port_wwn; /* For FCoE only */
413 struct ecore_igu_info *p_igu_info;
415 u8 max_chains_per_vf;
419 unsigned long device_capabilities;
421 /* Default DCBX mode */
427 /* maximun size of read/write commands (HW limit) */
428 #define DMAE_MAX_RW_SIZE 0x2000
430 struct ecore_dmae_info {
431 /* Mutex for synchronizing access to functions */
436 dma_addr_t completion_word_phys_addr;
438 /* The memory location where the DMAE writes the completion
439 * value when an operation is finished on this context.
441 u32 *p_completion_word;
443 dma_addr_t intermediate_buffer_phys_addr;
445 /* An intermediate buffer for DMAE operations that use virtual
446 * addresses - data is DMA'd to/from this buffer and then
447 * memcpy'd to/from the virtual address
449 u32 *p_intermediate_buffer;
451 dma_addr_t dmae_cmd_phys_addr;
452 struct dmae_cmd *p_dmae_cmd;
455 struct ecore_wfq_data {
456 u32 default_min_speed; /* When wfq feature is not configured */
457 u32 min_speed; /* when feature is configured for any 1 vport */
461 struct ecore_qm_info {
462 struct init_qm_pq_params *qm_pq_params;
463 struct init_qm_vport_params *qm_vport_params;
464 struct init_qm_port_params *qm_port_params;
477 u8 max_phys_tcs_per_port;
485 struct ecore_wfq_data *wfq_data;
489 struct ecore_db_recovery_info {
491 osal_spinlock_t lock;
492 u32 db_recovery_counter;
500 struct ecore_fw_data {
501 #ifdef CONFIG_ECORE_BINARY_FW
502 struct fw_ver_info *fw_ver_info;
504 const u8 *modes_tree_buf;
505 union init_op *init_ops;
511 struct ecore_dev *p_dev;
512 u8 my_id; /* ID inside the PF */
513 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
514 u8 rel_pf_id; /* Relative to engine*/
516 #define ECORE_PATH_ID(_p_hwfn) \
517 (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
523 char name[NAME_SIZE];
526 bool first_on_engine;
529 u8 num_funcs_on_engine;
533 void OSAL_IOMEM *regview;
534 void OSAL_IOMEM *doorbells;
536 unsigned long db_size;
539 struct ecore_ptt_pool *p_ptt_pool;
542 struct ecore_hw_info hw_info;
544 /* rt_array (for init-tool) */
545 struct ecore_rt_data rt_data;
548 struct ecore_spq *p_spq;
551 struct ecore_eq *p_eq;
554 struct ecore_consq *p_consq;
556 /* Slow-Path definitions */
558 bool b_sp_dpc_enabled;
560 struct ecore_ptt *p_main_ptt;
561 struct ecore_ptt *p_dpc_ptt;
563 struct ecore_sb_sp_info *p_sp_sb;
564 struct ecore_sb_attn_info *p_sb_attn;
566 /* Protocol related */
568 struct ecore_ll2_info *p_ll2_info;
569 struct ecore_ooo_info *p_ooo_info;
570 struct ecore_iscsi_info *p_iscsi_info;
571 struct ecore_fcoe_info *p_fcoe_info;
572 struct ecore_rdma_info *p_rdma_info;
573 struct ecore_pf_params pf_params;
575 bool b_rdma_enabled_in_prs;
576 u32 rdma_prs_search_reg;
578 struct ecore_cxt_mngr *p_cxt_mngr;
580 /* Flag indicating whether interrupts are enabled or not*/
582 bool b_int_requested;
584 /* True if the driver requests for the link */
585 bool b_drv_link_init;
587 struct ecore_vf_iov *vf_iov_info;
588 struct ecore_pf_iov *pf_iov_info;
589 struct ecore_mcp_info *mcp_info;
590 struct ecore_dcbx_info *p_dcbx_info;
592 struct ecore_dmae_info dmae_info;
595 struct ecore_qm_info qm_info;
597 #ifdef CONFIG_ECORE_ZIPPED_FW
598 /* Buffer for unzipping firmware data */
602 struct dbg_tools_data dbg_info;
604 struct z_stream_s *stream;
606 /* PWM region specific data */
609 u32 dpi_start_offset; /* this is used to
614 /* If one of the following is set then EDPM shouldn't be used */
619 struct ecore_l2_info *p_l2_info;
621 /* Mechanism for recovering from doorbell drop */
622 struct ecore_db_recovery_info db_recovery_info;
625 struct ecore_ptt *p_arfs_ptt;
628 #ifndef __EXTRACT__LINUX__
637 struct ecore_dbg_feature {
643 enum qed_dbg_features {
646 DBG_FEATURE_IDLE_CHK,
647 DBG_FEATURE_MCP_TRACE,
648 DBG_FEATURE_REG_FIFO,
649 DBG_FEATURE_PROTECTION_OVERRIDE,
653 enum ecore_dev_type {
661 char name[NAME_SIZE];
664 enum ecore_dev_type type;
665 /* Translate type/revision combo into the proper conditions */
666 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
667 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
669 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
670 (CHIP_REV_IS_TEDIBEAR(dev)))
672 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
674 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
675 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
679 #define ECORE_DEV_ID_MASK 0xff00
680 #define ECORE_DEV_ID_MASK_BB 0x1600
681 #define ECORE_DEV_ID_MASK_AH 0x8000
684 #define CHIP_NUM_MASK 0xffff
685 #define CHIP_NUM_SHIFT 0
688 #define CHIP_REV_MASK 0xf
689 #define CHIP_REV_SHIFT 0
691 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
692 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
693 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
694 #define CHIP_REV_IS_EMUL(_p_dev) \
695 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
696 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
697 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
698 #define CHIP_REV_IS_FPGA(_p_dev) \
699 (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
700 #define CHIP_REV_IS_SLOW(_p_dev) \
701 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
702 #define CHIP_REV_IS_A0(_p_dev) \
703 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
704 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
705 #define CHIP_REV_IS_B0(_p_dev) \
706 (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
707 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
708 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
710 #define CHIP_REV_IS_A0(_p_dev) \
711 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
712 #define CHIP_REV_IS_B0(_p_dev) \
713 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
717 #define CHIP_METAL_MASK 0xff
718 #define CHIP_METAL_SHIFT 0
721 #define CHIP_BOND_ID_MASK 0xff
722 #define CHIP_BOND_ID_SHIFT 0
726 u8 num_ports_in_engine;
727 u8 num_funcs_in_port;
730 enum ecore_mf_mode mf_mode;
731 #define IS_MF_DEFAULT(_p_hwfn) \
732 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
733 #define IS_MF_SI(_p_hwfn) \
734 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
735 #define IS_MF_SD(_p_hwfn) \
736 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
741 /* Add MF related configuration */
748 enum ecore_coalescing_mode int_coalescing_mode;
749 u16 rx_coalesce_usecs;
750 u16 tx_coalesce_usecs;
752 /* Start Bar offset of first hwfn */
753 void OSAL_IOMEM *regview;
754 void OSAL_IOMEM *doorbells;
756 unsigned long db_size;
762 const struct iro *iro_arr;
763 #define IRO (p_hwfn->p_dev->iro_arr)
767 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
768 #define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1)
771 struct ecore_hw_sriov_info *p_iov_info;
772 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
773 struct ecore_tunnel_info tunnel;
775 bool b_dont_override_vf_msix;
781 u32 rdma_max_srq_sge;
783 struct ecore_eth_stats *reset_stats;
784 struct ecore_fw_data *fw_data;
791 /* Indicates whether should prevent attentions from being reasserted */
795 /* Indicates whether allowing the MFW to collect a crash dump */
798 /* Indicates if the reg_fifo is checked after any register access */
805 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
811 struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
815 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
817 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
818 : MAX_NUM_L2_QUEUES_K2)
819 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
821 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
822 : MAX_SB_PER_PATH_K2)
823 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
827 * @brief ecore_concrete_to_sw_fid - get the sw function id from
828 * the concrete value.
830 * @param concrete_fid
832 * @return OSAL_INLINE u8
834 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
836 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
837 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
838 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
842 sw_fid = vfid + MAX_NUM_PFS;
852 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
853 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
854 struct ecore_ptt *p_ptt,
857 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
858 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
859 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
860 int ecore_device_num_engines(struct ecore_dev *p_dev);
861 int ecore_device_num_ports(struct ecore_dev *p_dev);
862 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
865 /* Flags for indication of required queues */
866 #define PQ_FLAGS_RLS (1 << 0)
867 #define PQ_FLAGS_MCOS (1 << 1)
868 #define PQ_FLAGS_LB (1 << 2)
869 #define PQ_FLAGS_OOO (1 << 3)
870 #define PQ_FLAGS_ACK (1 << 4)
871 #define PQ_FLAGS_OFLD (1 << 5)
872 #define PQ_FLAGS_VFS (1 << 6)
874 /* physical queue index for cm context intialization */
875 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
876 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
877 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
878 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
880 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
882 /* doorbell recovery mechanism */
883 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
884 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
885 enum ecore_db_rec_exec);
887 /* amount of resources used in qm init */
888 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
889 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
890 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
891 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
892 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
894 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
896 #endif /* __ECORE_H */