drivers/net/qede/base/ecore.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_H
  10 #define __ECORE_H
  11
  12 /* @DPDK */
  13 #include <sys/stat.h>
  14 #include <fcntl.h>
  15 #include <unistd.h>
  16
  17 #define CONFIG_ECORE_BINARY_FW
  18 #undef CONFIG_ECORE_ZIPPED_FW
  19
  20 #ifdef CONFIG_ECORE_ZIPPED_FW
  21 #include <zlib.h>
  22 #endif
  23
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_hsi_debug_tools.h"
  26 #include "ecore_hsi_init_func.h"
  27 #include "ecore_hsi_init_tool.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define MAX_HWFNS_PER_DEVICE    2
  32 #define NAME_SIZE 128 /* @DPDK */
  33 #define VER_SIZE 16
  34 #define ECORE_WFQ_UNIT  100
  35 #include "../qede_logs.h" /* @DPDK */
  36
  37 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  38 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  39 /* Constants */
  40 #define ECORE_WID_SIZE          (1024)
  41
  42 /* Configurable */
  43 #define ECORE_PF_DEMS_SIZE      (4)
  44
  45 /* cau states */
  46 enum ecore_coalescing_mode {
  47         ECORE_COAL_MODE_DISABLE,
  48         ECORE_COAL_MODE_ENABLE
  49 };
  50
  51 enum ecore_nvm_cmd {
  52         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  53         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  54         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  55         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  56         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  57         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  58         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  59         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  60         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  61         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  62         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  63 };
  64
  65 #ifndef LINUX_REMOVE
  66 #if !defined(CONFIG_ECORE_L2)
  67 #define CONFIG_ECORE_L2
  68 #define CONFIG_ECORE_SRIOV
  69 #endif
  70 #endif
  71
  72 /* helpers */
  73 #ifndef __EXTRACT__LINUX__
  74 #define MASK_FIELD(_name, _value)                                       \
  75                 ((_value) &= (_name##_MASK))
  76
  77 #define FIELD_VALUE(_name, _value)                                      \
  78                 ((_value & _name##_MASK) << _name##_SHIFT)
  79
  80 #define SET_FIELD(value, name, flag)                                    \
  81 do {                                                                    \
  82         (value) &= ~(name##_MASK << name##_SHIFT);                      \
  83         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
  84 } while (0)
  85
  86 #define GET_FIELD(value, name)                                          \
  87         (((value) >> (name##_SHIFT)) & name##_MASK)
  88 #endif
  89
  90 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
  91 {
  92         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
  93                       (cid * ECORE_PF_DEMS_SIZE);
  94
  95         return db_addr;
  96 }
  97
  98 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
  99 {
 100         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 101                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 102
 103         return db_addr;
 104 }
 105
 106 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 107         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 108          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 109
 110 #ifndef LINUX_REMOVE
 111 #ifndef U64_HI
 112 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 113 #endif
 114
 115 #ifndef U64_LO
 116 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 117 #endif
 118 #endif
 119
 120 #ifndef __EXTRACT__LINUX__
 121 enum DP_LEVEL {
 122         ECORE_LEVEL_VERBOSE     = 0x0,
 123         ECORE_LEVEL_INFO        = 0x1,
 124         ECORE_LEVEL_NOTICE      = 0x2,
 125         ECORE_LEVEL_ERR         = 0x3,
 126 };
 127
 128 #define ECORE_LOG_LEVEL_SHIFT   (30)
 129 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 130 #define ECORE_LOG_INFO_MASK     (0x40000000)
 131 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 132
 133 enum DP_MODULE {
 134 #ifndef LINUX_REMOVE
 135         ECORE_MSG_DRV           = 0x0001,
 136         ECORE_MSG_PROBE         = 0x0002,
 137         ECORE_MSG_LINK          = 0x0004,
 138         ECORE_MSG_TIMER         = 0x0008,
 139         ECORE_MSG_IFDOWN        = 0x0010,
 140         ECORE_MSG_IFUP          = 0x0020,
 141         ECORE_MSG_RX_ERR        = 0x0040,
 142         ECORE_MSG_TX_ERR        = 0x0080,
 143         ECORE_MSG_TX_QUEUED     = 0x0100,
 144         ECORE_MSG_INTR          = 0x0200,
 145         ECORE_MSG_TX_DONE       = 0x0400,
 146         ECORE_MSG_RX_STATUS     = 0x0800,
 147         ECORE_MSG_PKTDATA       = 0x1000,
 148         ECORE_MSG_HW            = 0x2000,
 149         ECORE_MSG_WOL           = 0x4000,
 150 #endif
 151         ECORE_MSG_SPQ           = 0x10000,
 152         ECORE_MSG_STATS         = 0x20000,
 153         ECORE_MSG_DCB           = 0x40000,
 154         ECORE_MSG_IOV           = 0x80000,
 155         ECORE_MSG_SP            = 0x100000,
 156         ECORE_MSG_STORAGE       = 0x200000,
 157         ECORE_MSG_OOO           = 0x200000,
 158         ECORE_MSG_CXT           = 0x800000,
 159         ECORE_MSG_LL2           = 0x1000000,
 160         ECORE_MSG_ILT           = 0x2000000,
 161         ECORE_MSG_RDMA          = 0x4000000,
 162         ECORE_MSG_DEBUG         = 0x8000000,
 163         /* to be added...up to 0x8000000 */
 164 };
 165 #endif
 166
 167 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 168
 169 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 170         (val == (cond1) ? true1 : \
 171          (val == (cond2) ? true2 : def))
 172
 173 /* forward */
 174 struct ecore_ptt_pool;
 175 struct ecore_spq;
 176 struct ecore_sb_info;
 177 struct ecore_sb_attn_info;
 178 struct ecore_cxt_mngr;
 179 struct ecore_dma_mem;
 180 struct ecore_sb_sp_info;
 181 struct ecore_ll2_info;
 182 struct ecore_igu_info;
 183 struct ecore_mcp_info;
 184 struct ecore_dcbx_info;
 185
 186 struct ecore_rt_data {
 187         u32     *init_val;
 188         bool    *b_valid;
 189 };
 190
 191 enum ecore_tunn_mode {
 192         ECORE_MODE_L2GENEVE_TUNN,
 193         ECORE_MODE_IPGENEVE_TUNN,
 194         ECORE_MODE_L2GRE_TUNN,
 195         ECORE_MODE_IPGRE_TUNN,
 196         ECORE_MODE_VXLAN_TUNN,
 197 };
 198
 199 enum ecore_tunn_clss {
 200         ECORE_TUNN_CLSS_MAC_VLAN,
 201         ECORE_TUNN_CLSS_MAC_VNI,
 202         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 203         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 204         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 205         MAX_ECORE_TUNN_CLSS,
 206 };
 207
 208 struct ecore_tunn_start_params {
 209         unsigned long tunn_mode;
 210         u16     vxlan_udp_port;
 211         u16     geneve_udp_port;
 212         u8      update_vxlan_udp_port;
 213         u8      update_geneve_udp_port;
 214         u8      tunn_clss_vxlan;
 215         u8      tunn_clss_l2geneve;
 216         u8      tunn_clss_ipgeneve;
 217         u8      tunn_clss_l2gre;
 218         u8      tunn_clss_ipgre;
 219 };
 220
 221 struct ecore_tunn_update_params {
 222         unsigned long tunn_mode_update_mask;
 223         unsigned long tunn_mode;
 224         u16     vxlan_udp_port;
 225         u16     geneve_udp_port;
 226         u8      update_rx_pf_clss;
 227         u8      update_tx_pf_clss;
 228         u8      update_vxlan_udp_port;
 229         u8      update_geneve_udp_port;
 230         u8      tunn_clss_vxlan;
 231         u8      tunn_clss_l2geneve;
 232         u8      tunn_clss_ipgeneve;
 233         u8      tunn_clss_l2gre;
 234         u8      tunn_clss_ipgre;
 235 };
 236
 237 /* The PCI personality is not quite synonymous to protocol ID:
 238  * 1. All personalities need CORE connections
 239  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 240  */
 241 enum ecore_pci_personality {
 242         ECORE_PCI_ETH,
 243         ECORE_PCI_FCOE,
 244         ECORE_PCI_ISCSI,
 245         ECORE_PCI_ETH_ROCE,
 246         ECORE_PCI_ETH_IWARP,
 247         ECORE_PCI_ETH_RDMA,
 248         ECORE_PCI_DEFAULT /* default in shmem */
 249 };
 250
 251 /* All VFs are symmetric, all counters are PF + all VFs */
 252 struct ecore_qm_iids {
 253         u32 cids;
 254         u32 vf_cids;
 255         u32 tids;
 256 };
 257
 258 #define MAX_PF_PER_PORT 8
 259
 260 /* HW / FW resources, output of features supported below, most information
 261  * is received from MFW.
 262  */
 263 enum ecore_resources {
 264         ECORE_SB,
 265         ECORE_L2_QUEUE,
 266         ECORE_VPORT,
 267         ECORE_RSS_ENG,
 268         ECORE_PQ,
 269         ECORE_RL,
 270         ECORE_MAC,
 271         ECORE_VLAN,
 272         ECORE_RDMA_CNQ_RAM,
 273         ECORE_ILT,
 274         ECORE_LL2_QUEUE,
 275         ECORE_CMDQS_CQS,
 276         ECORE_RDMA_STATS_QUEUE,
 277         ECORE_MAX_RESC,                 /* must be last */
 278 };
 279
 280 /* Features that require resources, given as input to the resource management
 281  * algorithm, the output are the resources above
 282  */
 283 enum ecore_feature {
 284         ECORE_PF_L2_QUE,
 285         ECORE_PF_TC,
 286         ECORE_VF,
 287         ECORE_EXTRA_VF_QUE,
 288         ECORE_VMQ,
 289         ECORE_RDMA_CNQ,
 290         ECORE_ISCSI_CQ,
 291         ECORE_FCOE_CQ,
 292         ECORE_VF_L2_QUE,
 293         ECORE_MAX_FEATURES,
 294 };
 295
 296 enum ecore_port_mode {
 297         ECORE_PORT_MODE_DE_2X40G,
 298         ECORE_PORT_MODE_DE_2X50G,
 299         ECORE_PORT_MODE_DE_1X100G,
 300         ECORE_PORT_MODE_DE_4X10G_F,
 301         ECORE_PORT_MODE_DE_4X10G_E,
 302         ECORE_PORT_MODE_DE_4X20G,
 303         ECORE_PORT_MODE_DE_1X40G,
 304         ECORE_PORT_MODE_DE_2X25G,
 305         ECORE_PORT_MODE_DE_1X25G,
 306         ECORE_PORT_MODE_DE_4X25G,
 307         ECORE_PORT_MODE_DE_2X10G,
 308 };
 309
 310 enum ecore_dev_cap {
 311         ECORE_DEV_CAP_ETH,
 312         ECORE_DEV_CAP_FCOE,
 313         ECORE_DEV_CAP_ISCSI,
 314         ECORE_DEV_CAP_ROCE,
 315         ECORE_DEV_CAP_IWARP
 316 };
 317
 318 #ifndef __EXTRACT__LINUX__
 319 enum ecore_hw_err_type {
 320         ECORE_HW_ERR_FAN_FAIL,
 321         ECORE_HW_ERR_MFW_RESP_FAIL,
 322         ECORE_HW_ERR_HW_ATTN,
 323         ECORE_HW_ERR_DMAE_FAIL,
 324         ECORE_HW_ERR_RAMROD_FAIL,
 325         ECORE_HW_ERR_FW_ASSERT,
 326 };
 327 #endif
 328
 329 struct ecore_hw_info {
 330         /* PCI personality */
 331         enum ecore_pci_personality personality;
 332 #define ECORE_IS_RDMA_PERSONALITY(dev)                      \
 333         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE ||  \
 334          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 335          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 336 #define ECORE_IS_ROCE_PERSONALITY(dev)                     \
 337         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 338          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 339 #define ECORE_IS_IWARP_PERSONALITY(dev)                     \
 340         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 341          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 342 #define ECORE_IS_L2_PERSONALITY(dev)                  \
 343         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 344          ECORE_IS_RDMA_PERSONALITY(dev))
 345
 346         /* Resource Allocation scheme results */
 347         u32 resc_start[ECORE_MAX_RESC];
 348         u32 resc_num[ECORE_MAX_RESC];
 349         u32 feat_num[ECORE_MAX_FEATURES];
 350
 351         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 352         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 353         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 354                                          RESC_NUM(_p_hwfn, resc))
 355         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 356
 357         /* Amount of traffic classes HW supports */
 358         u8 num_hw_tc;
 359
 360 /* Amount of TCs which should be active according to DCBx or upper layer driver
 361  * configuration
 362  */
 363
 364         u8 num_active_tc;
 365
 366         /* Traffic class used for tcp out of order traffic */
 367         u8 ooo_tc;
 368
 369         /* The traffic class used by PF for it's offloaded protocol */
 370         u8 offload_tc;
 371
 372         u32 concrete_fid;
 373         u16 opaque_fid;
 374         u16 ovlan;
 375         u32 part_num[4];
 376
 377         unsigned char hw_mac_addr[ETH_ALEN];
 378         u64 node_wwn; /* For FCoE only */
 379         u64 port_wwn; /* For FCoE only */
 380
 381         u16 num_iscsi_conns;
 382         u16 num_fcoe_conns;
 383
 384         struct ecore_igu_info *p_igu_info;
 385         /* Sriov */
 386         u8 max_chains_per_vf;
 387
 388         u32 port_mode;
 389         u32     hw_mode;
 390         unsigned long device_capabilities;
 391
 392         /* Default DCBX mode */
 393         u8 dcbx_mode;
 394
 395         u16 mtu;
 396 };
 397
 398 struct ecore_hw_cid_data {
 399         u32     cid;
 400         bool    b_cid_allocated;
 401         u8      vfid; /* 1-based; 0 signals this is for a PF */
 402
 403         /* Additional identifiers */
 404         u16     opaque_fid;
 405         u8      vport_id;
 406 };
 407
 408 /* maximun size of read/write commands (HW limit) */
 409 #define DMAE_MAX_RW_SIZE        0x2000
 410
 411 struct ecore_dmae_info {
 412         /* Mutex for synchronizing access to functions */
 413         osal_mutex_t    mutex;
 414
 415         u8 channel;
 416
 417         dma_addr_t completion_word_phys_addr;
 418
 419         /* The memory location where the DMAE writes the completion
 420          * value when an operation is finished on this context.
 421          */
 422         u32 *p_completion_word;
 423
 424         dma_addr_t intermediate_buffer_phys_addr;
 425
 426         /* An intermediate buffer for DMAE operations that use virtual
 427          * addresses - data is DMA'd to/from this buffer and then
 428          * memcpy'd to/from the virtual address
 429          */
 430         u32 *p_intermediate_buffer;
 431
 432         dma_addr_t dmae_cmd_phys_addr;
 433         struct dmae_cmd *p_dmae_cmd;
 434 };
 435
 436 struct ecore_wfq_data {
 437         u32 default_min_speed; /* When wfq feature is not configured */
 438         u32 min_speed; /* when feature is configured for any 1 vport */
 439         bool configured;
 440 };
 441
 442 struct ecore_qm_info {
 443         struct init_qm_pq_params    *qm_pq_params;
 444         struct init_qm_vport_params *qm_vport_params;
 445         struct init_qm_port_params  *qm_port_params;
 446         u16                     start_pq;
 447         u8                      start_vport;
 448         u16                     pure_lb_pq;
 449         u16                     offload_pq;
 450         u16                     pure_ack_pq;
 451         u16                     ooo_pq;
 452         u16                     first_vf_pq;
 453         u16                     first_mcos_pq;
 454         u16                     first_rl_pq;
 455         u16                     num_pqs;
 456         u16                     num_vf_pqs;
 457         u8                      num_vports;
 458         u8                      max_phys_tcs_per_port;
 459         bool                    pf_rl_en;
 460         bool                    pf_wfq_en;
 461         bool                    vport_rl_en;
 462         bool                    vport_wfq_en;
 463         u8                      pf_wfq;
 464         u32                     pf_rl;
 465         struct ecore_wfq_data   *wfq_data;
 466         u8                      num_pf_rls;
 467 };
 468
 469 struct storm_stats {
 470         u32 address;
 471         u32 len;
 472 };
 473
 474 struct ecore_fw_data {
 475 #ifdef CONFIG_ECORE_BINARY_FW
 476         struct fw_ver_info *fw_ver_info;
 477 #endif
 478         const u8 *modes_tree_buf;
 479         union init_op *init_ops;
 480         const u32 *arr_data;
 481         u32 init_ops_size;
 482 };
 483
 484 struct ecore_hwfn {
 485         struct ecore_dev                *p_dev;
 486         u8                              my_id;          /* ID inside the PF */
 487 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 488         u8                              rel_pf_id;      /* Relative to engine*/
 489         u8                              abs_pf_id;
 490         #define ECORE_PATH_ID(_p_hwfn) \
 491                 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 492         u8                              port_id;
 493         bool                            b_active;
 494
 495         u32                             dp_module;
 496         u8                              dp_level;
 497         char                            name[NAME_SIZE];
 498         void                            *dp_ctx;
 499
 500         bool                            first_on_engine;
 501         bool                            hw_init_done;
 502
 503         u8                              num_funcs_on_engine;
 504         u8                              enabled_func_idx;
 505
 506         /* BAR access */
 507         void OSAL_IOMEM                 *regview;
 508         void OSAL_IOMEM                 *doorbells;
 509         u64                             db_phys_addr;
 510         unsigned long                   db_size;
 511
 512         /* PTT pool */
 513         struct ecore_ptt_pool           *p_ptt_pool;
 514
 515         /* HW info */
 516         struct ecore_hw_info            hw_info;
 517
 518         /* rt_array (for init-tool) */
 519         struct ecore_rt_data            rt_data;
 520
 521         /* SPQ */
 522         struct ecore_spq                *p_spq;
 523
 524         /* EQ */
 525         struct ecore_eq                 *p_eq;
 526
 527         /* Consolidate Q*/
 528         struct ecore_consq              *p_consq;
 529
 530         /* Slow-Path definitions */
 531         osal_dpc_t                      sp_dpc;
 532         bool                            b_sp_dpc_enabled;
 533
 534         struct ecore_ptt                *p_main_ptt;
 535         struct ecore_ptt                *p_dpc_ptt;
 536
 537         struct ecore_sb_sp_info         *p_sp_sb;
 538         struct ecore_sb_attn_info       *p_sb_attn;
 539
 540         /* Protocol related */
 541         bool                            using_ll2;
 542         struct ecore_ll2_info           *p_ll2_info;
 543         struct ecore_ooo_info           *p_ooo_info;
 544         struct ecore_iscsi_info         *p_iscsi_info;
 545         struct ecore_fcoe_info          *p_fcoe_info;
 546         struct ecore_rdma_info          *p_rdma_info;
 547         struct ecore_pf_params          pf_params;
 548
 549         bool                            b_rdma_enabled_in_prs;
 550         u32                             rdma_prs_search_reg;
 551
 552         /* Array of sb_info of all status blocks */
 553         struct ecore_sb_info            *sbs_info[MAX_SB_PER_PF_MIMD];
 554         u16                             num_sbs;
 555
 556         struct ecore_cxt_mngr           *p_cxt_mngr;
 557
 558         /* Flag indicating whether interrupts are enabled or not*/
 559         bool                            b_int_enabled;
 560         bool                            b_int_requested;
 561
 562         /* True if the driver requests for the link */
 563         bool                            b_drv_link_init;
 564
 565         struct ecore_vf_iov             *vf_iov_info;
 566         struct ecore_pf_iov             *pf_iov_info;
 567         struct ecore_mcp_info           *mcp_info;
 568         struct ecore_dcbx_info          *p_dcbx_info;
 569
 570         struct ecore_hw_cid_data        *p_tx_cids;
 571         struct ecore_hw_cid_data        *p_rx_cids;
 572
 573         struct ecore_dmae_info          dmae_info;
 574
 575         /* QM init */
 576         struct ecore_qm_info            qm_info;
 577
 578 #ifdef CONFIG_ECORE_ZIPPED_FW
 579         /* Buffer for unzipping firmware data */
 580         void *unzip_buf;
 581 #endif
 582
 583         struct dbg_tools_data           dbg_info;
 584
 585         struct z_stream_s               *stream;
 586
 587         /* PWM region specific data */
 588         u32                             dpi_size;
 589         u32                             dpi_count;
 590         u32                             dpi_start_offset; /* this is used to
 591                                                            * calculate th
 592                                                            * doorbell address
 593                                                            */
 594
 595         /* If one of the following is set then EDPM shouldn't be used */
 596         u8                              dcbx_no_edpm;
 597         u8                              db_bar_no_edpm;
 598 };
 599
 600 #ifndef __EXTRACT__LINUX__
 601 enum ecore_mf_mode {
 602         ECORE_MF_DEFAULT,
 603         ECORE_MF_OVLAN,
 604         ECORE_MF_NPAR,
 605 };
 606 #endif
 607
 608 /* @DPDK */
 609 struct ecore_dbg_feature {
 610         u8                              *dump_buf;
 611         u32                             buf_size;
 612         u32                             dumped_dwords;
 613 };
 614
 615 enum qed_dbg_features {
 616         DBG_FEATURE_BUS,
 617         DBG_FEATURE_GRC,
 618         DBG_FEATURE_IDLE_CHK,
 619         DBG_FEATURE_MCP_TRACE,
 620         DBG_FEATURE_REG_FIFO,
 621         DBG_FEATURE_PROTECTION_OVERRIDE,
 622         DBG_FEATURE_NUM
 623 };
 624
 625 struct ecore_dev {
 626         u32                             dp_module;
 627         u8                              dp_level;
 628         char                            name[NAME_SIZE];
 629         void                            *dp_ctx;
 630
 631         u8                              type;
 632 #define ECORE_DEV_TYPE_BB       (0 << 0)
 633 #define ECORE_DEV_TYPE_AH       (1 << 0)
 634 /* Translate type/revision combo into the proper conditions */
 635 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 636 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 637 #ifndef ASIC_ONLY
 638 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 639                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 640 #else
 641 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 642 #endif
 643 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 644 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 645
 646 #define ECORE_DEV_ID_MASK       0xff00
 647 #define ECORE_DEV_ID_MASK_BB    0x1600
 648 #define ECORE_DEV_ID_MASK_AH    0x8000
 649
 650         u16 vendor_id;
 651         u16 device_id;
 652
 653         u16                             chip_num;
 654         #define CHIP_NUM_MASK                   0xffff
 655         #define CHIP_NUM_SHIFT                  16
 656
 657         u16                             chip_rev;
 658         #define CHIP_REV_MASK                   0xf
 659         #define CHIP_REV_SHIFT                  12
 660 #ifndef ASIC_ONLY
 661         #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
 662         #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
 663         #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
 664         #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 665                                           CHIP_REV_IS_EMUL_B0(_p_dev))
 666         #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
 667         #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
 668         #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
 669                                           CHIP_REV_IS_FPGA_B0(_p_dev))
 670         #define CHIP_REV_IS_SLOW(_p_dev) \
 671                 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 672         #define CHIP_REV_IS_A0(_p_dev) \
 673                 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 674                  CHIP_REV_IS_FPGA_A0(_p_dev) || \
 675                  !(_p_dev)->chip_rev)
 676         #define CHIP_REV_IS_B0(_p_dev) \
 677                 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
 678                  CHIP_REV_IS_FPGA_B0(_p_dev) || \
 679                  (_p_dev)->chip_rev == 1)
 680         #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
 681 #else
 682         #define CHIP_REV_IS_A0(_p_dev)  (!(_p_dev)->chip_rev)
 683         #define CHIP_REV_IS_B0(_p_dev)  ((_p_dev)->chip_rev == 1)
 684 #endif
 685
 686         u16                             chip_metal;
 687         #define CHIP_METAL_MASK                 0xff
 688         #define CHIP_METAL_SHIFT                4
 689
 690         u16                             chip_bond_id;
 691         #define CHIP_BOND_ID_MASK               0xf
 692         #define CHIP_BOND_ID_SHIFT              0
 693
 694         u8                              num_engines;
 695         u8                              num_ports_in_engines;
 696         u8                              num_funcs_in_port;
 697
 698         u8                              path_id;
 699         enum ecore_mf_mode              mf_mode;
 700         #define IS_MF_DEFAULT(_p_hwfn)  \
 701                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 702         #define IS_MF_SI(_p_hwfn)       \
 703                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 704         #define IS_MF_SD(_p_hwfn)       \
 705                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 706
 707         int                             pcie_width;
 708         int                             pcie_speed;
 709         u8                              ver_str[NAME_SIZE]; /* @DPDK */
 710         /* Add MF related configuration */
 711         u8                              mcp_rev;
 712         u8                              boot_mode;
 713
 714         u8                              wol;
 715
 716         u32                             int_mode;
 717         enum ecore_coalescing_mode      int_coalescing_mode;
 718         u16                             rx_coalesce_usecs;
 719         u16                             tx_coalesce_usecs;
 720
 721         /* Start Bar offset of first hwfn */
 722         void OSAL_IOMEM                 *regview;
 723         void OSAL_IOMEM                 *doorbells;
 724         u64                             db_phys_addr;
 725         unsigned long                   db_size;
 726
 727         /* PCI */
 728         u8                              cache_shift;
 729
 730         /* Init */
 731         const struct iro                *iro_arr;
 732         #define IRO (p_hwfn->p_dev->iro_arr)
 733
 734         /* HW functions */
 735         u8                              num_hwfns;
 736         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 737
 738         /* SRIOV */
 739         struct ecore_hw_sriov_info      *p_iov_info;
 740 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 741         unsigned long                   tunn_mode;
 742
 743         bool                            b_is_vf;
 744
 745         u32                             drv_type;
 746
 747         u32                             rdma_max_sge;
 748         u32                             rdma_max_inline;
 749         u32                             rdma_max_srq_sge;
 750
 751         struct ecore_eth_stats          *reset_stats;
 752         struct ecore_fw_data            *fw_data;
 753
 754         u32                             mcp_nvm_resp;
 755
 756         /* Recovery */
 757         bool                            recov_in_prog;
 758
 759 /* Indicates whether should prevent attentions from being reasserted */
 760
 761         bool                            attn_clr_en;
 762
 763         /* Indicates whether allowing the MFW to collect a crash dump */
 764         bool                            mdump_en;
 765
 766         /* Indicates if the reg_fifo is checked after any register access */
 767         bool                            chk_reg_fifo;
 768
 769 #ifndef ASIC_ONLY
 770         bool                            b_is_emul_full;
 771 #endif
 772
 773 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 774         void                            *firmware;
 775         u64                             fw_len;
 776 #endif
 777
 778         /* @DPDK */
 779         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 780         u8                              engine_for_debug;
 781 };
 782
 783 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 784                                                   : MAX_NUM_VFS_K2)
 785 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 786                                                   : MAX_NUM_L2_QUEUES_K2)
 787 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 788                                                   : MAX_NUM_PORTS_K2)
 789 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 790                                                   : MAX_SB_PER_PATH_K2)
 791 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 792                                                   : MAX_NUM_PFS_K2)
 793
 794 /**
 795  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 796  *        the concrete value.
 797  *
 798  * @param concrete_fid
 799  *
 800  * @return OSAL_INLINE u8
 801  */
 802 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
 803                                           u32 concrete_fid)
 804 {
 805         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 806         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 807         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 808         u8 sw_fid;
 809
 810         if (vf_valid)
 811                 sw_fid = vfid + MAX_NUM_PFS;
 812         else
 813                 sw_fid = pfid;
 814
 815         return sw_fid;
 816 }
 817
 818 #define PURE_LB_TC 8
 819 #define PKT_LB_TC 9
 820
 821 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 822 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 823                                            u32 min_pf_rate);
 824
 825 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 826 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 827 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 828 int ecore_device_num_engines(struct ecore_dev *p_dev);
 829 int ecore_device_num_ports(struct ecore_dev *p_dev);
 830 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 831                            u8 *mac);
 832
 833 /* Flags for indication of required queues */
 834 #define PQ_FLAGS_RLS    (1 << 0)
 835 #define PQ_FLAGS_MCOS   (1 << 1)
 836 #define PQ_FLAGS_LB     (1 << 2)
 837 #define PQ_FLAGS_OOO    (1 << 3)
 838 #define PQ_FLAGS_ACK    (1 << 4)
 839 #define PQ_FLAGS_OFLD   (1 << 5)
 840 #define PQ_FLAGS_VFS    (1 << 6)
 841
 842 /* physical queue index for cm context intialization */
 843 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 844 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 845 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 846 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
 847
 848 /* amount of resources used in qm init */
 849 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 850 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 851 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 852 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 853 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 854
 855 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 856
 857 #endif /* __ECORE_H */