drivers/net/qede/base/ecore.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #ifndef __ECORE_H
   8 #define __ECORE_H
   9
  10 /* @DPDK */
  11 #include <sys/stat.h>
  12 #include <fcntl.h>
  13 #include <unistd.h>
  14
  15 #define CONFIG_ECORE_BINARY_FW
  16 #undef CONFIG_ECORE_ZIPPED_FW
  17
  18 #ifdef CONFIG_ECORE_ZIPPED_FW
  19 #include <zlib.h>
  20 #endif
  21
  22 #include "ecore_status.h"
  23 #include "ecore_hsi_common.h"
  24 #include "ecore_hsi_debug_tools.h"
  25 #include "ecore_hsi_init_func.h"
  26 #include "ecore_hsi_init_tool.h"
  27 #include "ecore_hsi_func_common.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define ECORE_MAJOR_VERSION             8
  32 #define ECORE_MINOR_VERSION             40
  33 #define ECORE_REVISION_VERSION          26
  34 #define ECORE_ENGINEERING_VERSION       0
  35
  36 #define ECORE_VERSION                                                   \
  37         ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) |    \
  38          (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
  39
  40 #define STORM_FW_VERSION                                                \
  41         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |  \
  42          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  43
  44 #define IS_ECORE_PACING(p_hwfn) \
  45         (!!(p_hwfn->b_en_pacing))
  46
  47 #define MAX_HWFNS_PER_DEVICE    2
  48 #define NAME_SIZE 128 /* @DPDK */
  49 #define ECORE_WFQ_UNIT  100
  50 #include "../qede_logs.h" /* @DPDK */
  51
  52 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  53 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  54 /* Constants */
  55 #define ECORE_WID_SIZE          (1024)
  56 #define ECORE_MIN_WIDS          (4)
  57
  58 /* Configurable */
  59 #define ECORE_PF_DEMS_SIZE      (4)
  60
  61 /* cau states */
  62 enum ecore_coalescing_mode {
  63         ECORE_COAL_MODE_DISABLE,
  64         ECORE_COAL_MODE_ENABLE
  65 };
  66
  67 enum ecore_nvm_cmd {
  68         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  69         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  70         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  71         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  72         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  73         ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
  74         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  75         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  76         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  77         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  78         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  79         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  80 };
  81
  82 #ifndef LINUX_REMOVE
  83 #if !defined(CONFIG_ECORE_L2)
  84 #define CONFIG_ECORE_L2
  85 #define CONFIG_ECORE_SRIOV
  86 #endif
  87 #endif
  88
  89 /* helpers */
  90 #ifndef __EXTRACT__LINUX__
  91 #define MASK_FIELD(_name, _value)                                       \
  92                 ((_value) &= (_name##_MASK))
  93
  94 #define FIELD_VALUE(_name, _value)                                      \
  95                 ((_value & _name##_MASK) << _name##_SHIFT)
  96
  97 #define SET_FIELD(value, name, flag)                                    \
  98 do {                                                                    \
  99         (value) &= ~(name##_MASK << name##_SHIFT);                      \
 100         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
 101 } while (0)
 102
 103 #define GET_FIELD(value, name)                                          \
 104         (((value) >> (name##_SHIFT)) & name##_MASK)
 105
 106 #define GET_MFW_FIELD(name, field)                              \
 107         (((name) & (field ## _MASK)) >> (field ## _OFFSET))
 108
 109 #define SET_MFW_FIELD(name, field, value)                               \
 110 do {                                                                    \
 111         (name) &= ~((field ## _MASK));          \
 112         (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
 113 } while (0)
 114 #endif
 115
 116 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
 117 {
 118         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 119                       (cid * ECORE_PF_DEMS_SIZE);
 120
 121         return db_addr;
 122 }
 123
 124 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 125 {
 126         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 127                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 128
 129         return db_addr;
 130 }
 131
 132 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 133         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 134          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 135
 136 #ifndef LINUX_REMOVE
 137 #ifndef U64_HI
 138 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 139 #endif
 140
 141 #ifndef U64_LO
 142 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 143 #endif
 144 #endif
 145
 146 #ifndef __EXTRACT__LINUX__
 147 enum DP_LEVEL {
 148         ECORE_LEVEL_VERBOSE     = 0x0,
 149         ECORE_LEVEL_INFO        = 0x1,
 150         ECORE_LEVEL_NOTICE      = 0x2,
 151         ECORE_LEVEL_ERR         = 0x3,
 152 };
 153
 154 #define ECORE_LOG_LEVEL_SHIFT   (30)
 155 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 156 #define ECORE_LOG_INFO_MASK     (0x40000000)
 157 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 158
 159 enum DP_MODULE {
 160 #ifndef LINUX_REMOVE
 161         ECORE_MSG_DRV           = 0x0001,
 162         ECORE_MSG_PROBE         = 0x0002,
 163         ECORE_MSG_LINK          = 0x0004,
 164         ECORE_MSG_TIMER         = 0x0008,
 165         ECORE_MSG_IFDOWN        = 0x0010,
 166         ECORE_MSG_IFUP          = 0x0020,
 167         ECORE_MSG_RX_ERR        = 0x0040,
 168         ECORE_MSG_TX_ERR        = 0x0080,
 169         ECORE_MSG_TX_QUEUED     = 0x0100,
 170         ECORE_MSG_INTR          = 0x0200,
 171         ECORE_MSG_TX_DONE       = 0x0400,
 172         ECORE_MSG_RX_STATUS     = 0x0800,
 173         ECORE_MSG_PKTDATA       = 0x1000,
 174         ECORE_MSG_HW            = 0x2000,
 175         ECORE_MSG_WOL           = 0x4000,
 176 #endif
 177         ECORE_MSG_SPQ           = 0x10000,
 178         ECORE_MSG_STATS         = 0x20000,
 179         ECORE_MSG_DCB           = 0x40000,
 180         ECORE_MSG_IOV           = 0x80000,
 181         ECORE_MSG_SP            = 0x100000,
 182         ECORE_MSG_STORAGE       = 0x200000,
 183         ECORE_MSG_OOO           = 0x200000,
 184         ECORE_MSG_CXT           = 0x800000,
 185         ECORE_MSG_LL2           = 0x1000000,
 186         ECORE_MSG_ILT           = 0x2000000,
 187         ECORE_MSG_RDMA          = 0x4000000,
 188         ECORE_MSG_DEBUG         = 0x8000000,
 189         /* to be added...up to 0x8000000 */
 190 };
 191 #endif
 192
 193 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 194
 195 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 196         (val == (cond1) ? true1 : \
 197          (val == (cond2) ? true2 : def))
 198
 199 /* forward */
 200 struct ecore_ptt_pool;
 201 struct ecore_spq;
 202 struct ecore_sb_info;
 203 struct ecore_sb_attn_info;
 204 struct ecore_cxt_mngr;
 205 struct ecore_dma_mem;
 206 struct ecore_sb_sp_info;
 207 struct ecore_ll2_info;
 208 struct ecore_l2_info;
 209 struct ecore_igu_info;
 210 struct ecore_mcp_info;
 211 struct ecore_dcbx_info;
 212 struct ecore_llh_info;
 213
 214 struct ecore_rt_data {
 215         u32     *init_val;
 216         bool    *b_valid;
 217 };
 218
 219 enum ecore_tunn_mode {
 220         ECORE_MODE_L2GENEVE_TUNN,
 221         ECORE_MODE_IPGENEVE_TUNN,
 222         ECORE_MODE_L2GRE_TUNN,
 223         ECORE_MODE_IPGRE_TUNN,
 224         ECORE_MODE_VXLAN_TUNN,
 225 };
 226
 227 enum ecore_tunn_clss {
 228         ECORE_TUNN_CLSS_MAC_VLAN,
 229         ECORE_TUNN_CLSS_MAC_VNI,
 230         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 231         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 232         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 233         MAX_ECORE_TUNN_CLSS,
 234 };
 235
 236 struct ecore_tunn_update_type {
 237         bool b_update_mode;
 238         bool b_mode_enabled;
 239         enum ecore_tunn_clss tun_cls;
 240 };
 241
 242 struct ecore_tunn_update_udp_port {
 243         bool b_update_port;
 244         u16 port;
 245 };
 246
 247 struct ecore_tunnel_info {
 248         struct ecore_tunn_update_type vxlan;
 249         struct ecore_tunn_update_type l2_geneve;
 250         struct ecore_tunn_update_type ip_geneve;
 251         struct ecore_tunn_update_type l2_gre;
 252         struct ecore_tunn_update_type ip_gre;
 253
 254         struct ecore_tunn_update_udp_port vxlan_port;
 255         struct ecore_tunn_update_udp_port geneve_port;
 256
 257         bool b_update_rx_cls;
 258         bool b_update_tx_cls;
 259 };
 260
 261 /* The PCI personality is not quite synonymous to protocol ID:
 262  * 1. All personalities need CORE connections
 263  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 264  */
 265 enum ecore_pci_personality {
 266         ECORE_PCI_ETH,
 267         ECORE_PCI_FCOE,
 268         ECORE_PCI_ISCSI,
 269         ECORE_PCI_ETH_ROCE,
 270         ECORE_PCI_ETH_IWARP,
 271         ECORE_PCI_ETH_RDMA,
 272         ECORE_PCI_DEFAULT /* default in shmem */
 273 };
 274
 275 /* All VFs are symmetric, all counters are PF + all VFs */
 276 struct ecore_qm_iids {
 277         u32 cids;
 278         u32 vf_cids;
 279         u32 tids;
 280 };
 281
 282 #define MAX_PF_PER_PORT 8
 283
 284 /* HW / FW resources, output of features supported below, most information
 285  * is received from MFW.
 286  */
 287 enum ecore_resources {
 288         ECORE_L2_QUEUE,
 289         ECORE_VPORT,
 290         ECORE_RSS_ENG,
 291         ECORE_PQ,
 292         ECORE_RL,
 293         ECORE_MAC,
 294         ECORE_VLAN,
 295         ECORE_RDMA_CNQ_RAM,
 296         ECORE_ILT,
 297         ECORE_LL2_QUEUE,
 298         ECORE_CMDQS_CQS,
 299         ECORE_RDMA_STATS_QUEUE,
 300         ECORE_BDQ,
 301
 302         /* This is needed only internally for matching against the IGU.
 303          * In case of legacy MFW, would be set to `0'.
 304          */
 305         ECORE_SB,
 306
 307         ECORE_MAX_RESC,
 308 };
 309
 310 /* Features that require resources, given as input to the resource management
 311  * algorithm, the output are the resources above
 312  */
 313 enum ecore_feature {
 314         ECORE_PF_L2_QUE,
 315         ECORE_PF_TC,
 316         ECORE_VF,
 317         ECORE_EXTRA_VF_QUE,
 318         ECORE_VMQ,
 319         ECORE_RDMA_CNQ,
 320         ECORE_ISCSI_CQ,
 321         ECORE_FCOE_CQ,
 322         ECORE_VF_L2_QUE,
 323         ECORE_MAX_FEATURES,
 324 };
 325
 326 enum ecore_port_mode {
 327         ECORE_PORT_MODE_DE_2X40G,
 328         ECORE_PORT_MODE_DE_2X50G,
 329         ECORE_PORT_MODE_DE_1X100G,
 330         ECORE_PORT_MODE_DE_4X10G_F,
 331         ECORE_PORT_MODE_DE_4X10G_E,
 332         ECORE_PORT_MODE_DE_4X20G,
 333         ECORE_PORT_MODE_DE_1X40G,
 334         ECORE_PORT_MODE_DE_2X25G,
 335         ECORE_PORT_MODE_DE_1X25G,
 336         ECORE_PORT_MODE_DE_4X25G,
 337         ECORE_PORT_MODE_DE_2X10G,
 338 };
 339
 340 enum ecore_dev_cap {
 341         ECORE_DEV_CAP_ETH,
 342         ECORE_DEV_CAP_FCOE,
 343         ECORE_DEV_CAP_ISCSI,
 344         ECORE_DEV_CAP_ROCE,
 345         ECORE_DEV_CAP_IWARP
 346 };
 347
 348 #ifndef __EXTRACT__LINUX__
 349 enum ecore_hw_err_type {
 350         ECORE_HW_ERR_FAN_FAIL,
 351         ECORE_HW_ERR_MFW_RESP_FAIL,
 352         ECORE_HW_ERR_HW_ATTN,
 353         ECORE_HW_ERR_DMAE_FAIL,
 354         ECORE_HW_ERR_RAMROD_FAIL,
 355         ECORE_HW_ERR_FW_ASSERT,
 356 };
 357 #endif
 358
 359 enum ecore_db_rec_exec {
 360         DB_REC_DRY_RUN,
 361         DB_REC_REAL_DEAL,
 362         DB_REC_ONCE,
 363 };
 364
 365 struct ecore_hw_info {
 366         /* PCI personality */
 367         enum ecore_pci_personality personality;
 368 #define ECORE_IS_RDMA_PERSONALITY(dev) \
 369         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 370          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 371          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 372 #define ECORE_IS_ROCE_PERSONALITY(dev) \
 373         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 374          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 375 #define ECORE_IS_IWARP_PERSONALITY(dev) \
 376         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 377          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 378 #define ECORE_IS_L2_PERSONALITY(dev) \
 379         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 380          ECORE_IS_RDMA_PERSONALITY(dev))
 381 #define ECORE_IS_FCOE_PERSONALITY(dev) \
 382         ((dev)->hw_info.personality == ECORE_PCI_FCOE)
 383 #define ECORE_IS_ISCSI_PERSONALITY(dev) \
 384         ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
 385
 386         /* Resource Allocation scheme results */
 387         u32 resc_start[ECORE_MAX_RESC];
 388         u32 resc_num[ECORE_MAX_RESC];
 389         u32 feat_num[ECORE_MAX_FEATURES];
 390
 391         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 392         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 393         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 394                                          RESC_NUM(_p_hwfn, resc))
 395         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 396
 397         /* Amount of traffic classes HW supports */
 398         u8 num_hw_tc;
 399
 400 /* Amount of TCs which should be active according to DCBx or upper layer driver
 401  * configuration
 402  */
 403
 404         u8 num_active_tc;
 405
 406         /* The traffic class used by PF for it's offloaded protocol */
 407         u8 offload_tc;
 408
 409         u32 concrete_fid;
 410         u16 opaque_fid;
 411         u16 ovlan;
 412         u32 part_num[4];
 413
 414         unsigned char hw_mac_addr[ETH_ALEN];
 415         u64 node_wwn; /* For FCoE only */
 416         u64 port_wwn; /* For FCoE only */
 417
 418         u16 num_iscsi_conns;
 419         u16 num_fcoe_conns;
 420
 421         struct ecore_igu_info *p_igu_info;
 422         /* Sriov */
 423         u8 max_chains_per_vf;
 424
 425         u32 port_mode;
 426         u32 hw_mode;
 427         u32 device_capabilities;
 428
 429         /* Default DCBX mode */
 430         u8 dcbx_mode;
 431
 432         u16 mtu;
 433 };
 434
 435 /* maximun size of read/write commands (HW limit) */
 436 #define DMAE_MAX_RW_SIZE        0x2000
 437
 438 struct ecore_dmae_info {
 439         /* Spinlock for synchronizing access to functions */
 440         osal_spinlock_t lock;
 441
 442         bool b_mem_ready;
 443
 444         u8 channel;
 445
 446         dma_addr_t completion_word_phys_addr;
 447
 448         /* The memory location where the DMAE writes the completion
 449          * value when an operation is finished on this context.
 450          */
 451         u32 *p_completion_word;
 452
 453         dma_addr_t intermediate_buffer_phys_addr;
 454
 455         /* An intermediate buffer for DMAE operations that use virtual
 456          * addresses - data is DMA'd to/from this buffer and then
 457          * memcpy'd to/from the virtual address
 458          */
 459         u32 *p_intermediate_buffer;
 460
 461         dma_addr_t dmae_cmd_phys_addr;
 462         struct dmae_cmd *p_dmae_cmd;
 463 };
 464
 465 struct ecore_wfq_data {
 466         u32 default_min_speed; /* When wfq feature is not configured */
 467         u32 min_speed; /* when feature is configured for any 1 vport */
 468         bool configured;
 469 };
 470
 471 #define OFLD_GRP_SIZE 4
 472
 473 struct ecore_qm_info {
 474         struct init_qm_pq_params    *qm_pq_params;
 475         struct init_qm_vport_params *qm_vport_params;
 476         struct init_qm_port_params  *qm_port_params;
 477         u16                     start_pq;
 478         u8                      start_vport;
 479         u16                     pure_lb_pq;
 480         u16                     offload_pq;
 481         u16                     pure_ack_pq;
 482         u16                     ooo_pq;
 483         u16                     first_vf_pq;
 484         u16                     first_mcos_pq;
 485         u16                     first_rl_pq;
 486         u16                     num_pqs;
 487         u16                     num_vf_pqs;
 488         u8                      num_vports;
 489         u8                      max_phys_tcs_per_port;
 490         u8                      ooo_tc;
 491         bool                    pf_rl_en;
 492         bool                    pf_wfq_en;
 493         bool                    vport_rl_en;
 494         bool                    vport_wfq_en;
 495         u8                      pf_wfq;
 496         u32                     pf_rl;
 497         struct ecore_wfq_data   *wfq_data;
 498         u8                      num_pf_rls;
 499 };
 500
 501 struct ecore_db_recovery_info {
 502         osal_list_t list;
 503         osal_spinlock_t lock;
 504         u32 db_recovery_counter;
 505 };
 506
 507 struct storm_stats {
 508         u32 address;
 509         u32 len;
 510 };
 511
 512 struct ecore_fw_data {
 513 #ifdef CONFIG_ECORE_BINARY_FW
 514         struct fw_ver_info *fw_ver_info;
 515 #endif
 516         const u8 *modes_tree_buf;
 517         union init_op *init_ops;
 518         const u32 *arr_data;
 519         const u32 *fw_overlays;
 520         u32 fw_overlays_len;
 521         u32 init_ops_size;
 522 };
 523
 524 enum ecore_mf_mode_bit {
 525         /* Supports PF-classification based on tag */
 526         ECORE_MF_OVLAN_CLSS,
 527
 528         /* Supports PF-classification based on MAC */
 529         ECORE_MF_LLH_MAC_CLSS,
 530
 531         /* Supports PF-classification based on protocol type */
 532         ECORE_MF_LLH_PROTO_CLSS,
 533
 534         /* Requires a default PF to be set */
 535         ECORE_MF_NEED_DEF_PF,
 536
 537         /* Allow LL2 to multicast/broadcast */
 538         ECORE_MF_LL2_NON_UNICAST,
 539
 540         /* Allow Cross-PF [& child VFs] Tx-switching */
 541         ECORE_MF_INTER_PF_SWITCH,
 542
 543         /* TODO - if we ever re-utilize any of this logic, we can rename */
 544         ECORE_MF_UFP_SPECIFIC,
 545
 546         ECORE_MF_DISABLE_ARFS,
 547
 548         /* Use vlan for steering */
 549         ECORE_MF_8021Q_TAGGING,
 550
 551         /* Use stag for steering */
 552         ECORE_MF_8021AD_TAGGING,
 553
 554         /* Allow FIP discovery fallback */
 555         ECORE_MF_FIP_SPECIAL,
 556 };
 557
 558 enum ecore_ufp_mode {
 559         ECORE_UFP_MODE_ETS,
 560         ECORE_UFP_MODE_VNIC_BW,
 561 };
 562
 563 enum ecore_ufp_pri_type {
 564         ECORE_UFP_PRI_OS,
 565         ECORE_UFP_PRI_VNIC
 566 };
 567
 568 struct ecore_ufp_info {
 569         enum ecore_ufp_pri_type pri_type;
 570         enum ecore_ufp_mode mode;
 571         u8 tc;
 572 };
 573
 574 enum BAR_ID {
 575         BAR_ID_0,       /* used for GRC */
 576         BAR_ID_1        /* Used for doorbells */
 577 };
 578
 579 struct ecore_nvm_image_info {
 580         u32                             num_images;
 581         struct bist_nvm_image_att       *image_att;
 582         bool                            valid;
 583 };
 584
 585 struct ecore_hwfn {
 586         struct ecore_dev                *p_dev;
 587         u8                              my_id;          /* ID inside the PF */
 588 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 589         u8                              rel_pf_id;      /* Relative to engine*/
 590         u8                              abs_pf_id;
 591 #define ECORE_PATH_ID(_p_hwfn) \
 592         (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
 593         u8                              port_id;
 594         bool                            b_active;
 595
 596         u32                             dp_module;
 597         u8                              dp_level;
 598         char                            name[NAME_SIZE];
 599         void                            *dp_ctx;
 600
 601         bool                            first_on_engine;
 602         bool                            hw_init_done;
 603
 604         u8                              num_funcs_on_engine;
 605         u8                              enabled_func_idx;
 606         u8                              num_funcs_on_port;
 607
 608         /* BAR access */
 609         void OSAL_IOMEM                 *regview;
 610         void OSAL_IOMEM                 *doorbells;
 611         u64                             db_phys_addr;
 612         unsigned long                   db_size;
 613
 614         /* PTT pool */
 615         struct ecore_ptt_pool           *p_ptt_pool;
 616
 617         /* HW info */
 618         struct ecore_hw_info            hw_info;
 619
 620         /* rt_array (for init-tool) */
 621         struct ecore_rt_data            rt_data;
 622
 623         /* SPQ */
 624         struct ecore_spq                *p_spq;
 625
 626         /* EQ */
 627         struct ecore_eq                 *p_eq;
 628
 629         /* Consolidate Q*/
 630         struct ecore_consq              *p_consq;
 631
 632         /* Slow-Path definitions */
 633         osal_dpc_t                      sp_dpc;
 634         bool                            b_sp_dpc_enabled;
 635
 636         struct ecore_ptt                *p_main_ptt;
 637         struct ecore_ptt                *p_dpc_ptt;
 638
 639         struct ecore_sb_sp_info         *p_sp_sb;
 640         struct ecore_sb_attn_info       *p_sb_attn;
 641
 642         /* Protocol related */
 643         bool                            using_ll2;
 644         struct ecore_ll2_info           *p_ll2_info;
 645         struct ecore_ooo_info           *p_ooo_info;
 646         struct ecore_iscsi_info         *p_iscsi_info;
 647         struct ecore_fcoe_info          *p_fcoe_info;
 648         struct ecore_rdma_info          *p_rdma_info;
 649         struct ecore_pf_params          pf_params;
 650
 651         bool                            b_rdma_enabled_in_prs;
 652         u32                             rdma_prs_search_reg;
 653
 654         struct ecore_cxt_mngr           *p_cxt_mngr;
 655
 656         /* Flag indicating whether interrupts are enabled or not*/
 657         bool                            b_int_enabled;
 658         bool                            b_int_requested;
 659
 660         /* True if the driver requests for the link */
 661         bool                            b_drv_link_init;
 662
 663         struct ecore_vf_iov             *vf_iov_info;
 664         struct ecore_pf_iov             *pf_iov_info;
 665         struct ecore_mcp_info           *mcp_info;
 666         struct ecore_dcbx_info          *p_dcbx_info;
 667         struct ecore_ufp_info           ufp_info;
 668
 669         struct ecore_dmae_info          dmae_info;
 670
 671         /* QM init */
 672         struct ecore_qm_info            qm_info;
 673
 674 #ifdef CONFIG_ECORE_ZIPPED_FW
 675         /* Buffer for unzipping firmware data */
 676         void *unzip_buf;
 677 #endif
 678
 679         struct dbg_tools_data           dbg_info;
 680         void                            *dbg_user_info;
 681         struct virt_mem_desc            dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];
 682
 683         struct z_stream_s               *stream;
 684
 685         /* PWM region specific data */
 686         u32                             dpi_size;
 687         u32                             dpi_count;
 688         u32                             dpi_start_offset; /* this is used to
 689                                                            * calculate th
 690                                                            * doorbell address
 691                                                            */
 692
 693         /* If one of the following is set then EDPM shouldn't be used */
 694         u8                              dcbx_no_edpm;
 695         u8                              db_bar_no_edpm;
 696
 697         /* L2-related */
 698         struct ecore_l2_info            *p_l2_info;
 699
 700         /* Mechanism for recovering from doorbell drop */
 701         struct ecore_db_recovery_info   db_recovery_info;
 702
 703         /* Enable/disable pacing, if request to enable then
 704          * IOV and mcos configuration will be skipped.
 705          * this actually reflects the value requested in
 706          * struct ecore_hw_prepare_params by ecore client.
 707          */
 708         bool b_en_pacing;
 709
 710         /* Nvm images number and attributes */
 711         struct ecore_nvm_image_info     nvm_info;
 712
 713         struct phys_mem_desc            *fw_overlay_mem;
 714
 715         /* @DPDK */
 716         struct ecore_ptt                *p_arfs_ptt;
 717
 718         /* DPDK specific, not the part of vanilla ecore */
 719         osal_spinlock_t spq_lock;
 720         u32 iov_task_flags;
 721 };
 722
 723 enum ecore_mf_mode {
 724         ECORE_MF_DEFAULT,
 725         ECORE_MF_OVLAN,
 726         ECORE_MF_NPAR,
 727         ECORE_MF_UFP,
 728 };
 729
 730 enum ecore_dev_type {
 731         ECORE_DEV_TYPE_BB,
 732         ECORE_DEV_TYPE_AH,
 733 };
 734
 735 /* @DPDK */
 736 enum ecore_dbg_features {
 737         DBG_FEATURE_GRC,
 738         DBG_FEATURE_IDLE_CHK,
 739         DBG_FEATURE_MCP_TRACE,
 740         DBG_FEATURE_REG_FIFO,
 741         DBG_FEATURE_IGU_FIFO,
 742         DBG_FEATURE_PROTECTION_OVERRIDE,
 743         DBG_FEATURE_FW_ASSERTS,
 744         DBG_FEATURE_ILT,
 745         DBG_FEATURE_NUM
 746 };
 747
 748 struct ecore_dbg_feature {
 749         u8                              *dump_buf;
 750         u32                             buf_size;
 751         u32                             dumped_dwords;
 752 };
 753
 754 struct ecore_dbg_params {
 755         struct ecore_dbg_feature features[DBG_FEATURE_NUM];
 756         u8 engine_for_debug;
 757         bool print_data;
 758 };
 759
 760 struct ecore_dev {
 761         u32                             dp_module;
 762         u8                              dp_level;
 763         char                            name[NAME_SIZE];
 764         void                            *dp_ctx;
 765
 766         enum ecore_dev_type             type;
 767 /* Translate type/revision combo into the proper conditions */
 768 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 769 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 770 #ifndef ASIC_ONLY
 771 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 772                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 773 #else
 774 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 775 #endif
 776 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 777 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 778
 779         u16 vendor_id;
 780         u16 device_id;
 781 #define ECORE_DEV_ID_MASK       0xff00
 782 #define ECORE_DEV_ID_MASK_BB    0x1600
 783 #define ECORE_DEV_ID_MASK_AH    0x8000
 784
 785         u16                             chip_num;
 786 #define CHIP_NUM_MASK                   0xffff
 787 #define CHIP_NUM_SHIFT                  0
 788
 789         u8                              chip_rev;
 790 #define CHIP_REV_MASK                   0xf
 791 #define CHIP_REV_SHIFT                  0
 792 #ifndef ASIC_ONLY
 793 #define CHIP_REV_IS_TEDIBEAR(_p_dev)    ((_p_dev)->chip_rev == 0x5)
 794 #define CHIP_REV_IS_EMUL_A0(_p_dev)     ((_p_dev)->chip_rev == 0xe)
 795 #define CHIP_REV_IS_EMUL_B0(_p_dev)     ((_p_dev)->chip_rev == 0xc)
 796 #define CHIP_REV_IS_EMUL(_p_dev) \
 797         (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
 798 #define CHIP_REV_IS_FPGA_A0(_p_dev)     ((_p_dev)->chip_rev == 0xf)
 799 #define CHIP_REV_IS_FPGA_B0(_p_dev)     ((_p_dev)->chip_rev == 0xd)
 800 #define CHIP_REV_IS_FPGA(_p_dev) \
 801         (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
 802 #define CHIP_REV_IS_SLOW(_p_dev) \
 803         (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 804 #define CHIP_REV_IS_A0(_p_dev) \
 805         (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
 806          (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
 807 #define CHIP_REV_IS_B0(_p_dev) \
 808         (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
 809          ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
 810 #define CHIP_REV_IS_ASIC(_p_dev)        !CHIP_REV_IS_SLOW(_p_dev)
 811 #else
 812 #define CHIP_REV_IS_A0(_p_dev) \
 813         (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
 814 #define CHIP_REV_IS_B0(_p_dev) \
 815         ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
 816 #endif
 817
 818         u8                              chip_metal;
 819 #define CHIP_METAL_MASK                 0xff
 820 #define CHIP_METAL_SHIFT                0
 821
 822         u8                              chip_bond_id;
 823 #define CHIP_BOND_ID_MASK               0xff
 824 #define CHIP_BOND_ID_SHIFT              0
 825
 826         u8                              num_engines;
 827         u8                              num_ports;
 828         u8                              num_ports_in_engine;
 829         u8                              num_funcs_in_port;
 830
 831         u8                              path_id;
 832
 833         u32                             mf_bits;
 834         enum ecore_mf_mode              mf_mode;
 835 #define IS_MF_DEFAULT(_p_hwfn)  \
 836         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 837 #define IS_MF_SI(_p_hwfn)       \
 838         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 839 #define IS_MF_SD(_p_hwfn)       \
 840         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 841
 842         int                             pcie_width;
 843         int                             pcie_speed;
 844
 845         /* Add MF related configuration */
 846         u8                              mcp_rev;
 847         u8                              boot_mode;
 848
 849         u8                              wol;
 850
 851         u32                             int_mode;
 852         enum ecore_coalescing_mode      int_coalescing_mode;
 853         u16                             rx_coalesce_usecs;
 854         u16                             tx_coalesce_usecs;
 855
 856         /* Start Bar offset of first hwfn */
 857         void OSAL_IOMEM                 *regview;
 858         void OSAL_IOMEM                 *doorbells;
 859         u64                             db_phys_addr;
 860         unsigned long                   db_size;
 861
 862         /* PCI */
 863         u8                              cache_shift;
 864
 865         /* Init */
 866         const u32                       *iro_arr;
 867 #define IRO     ((const struct iro *)p_hwfn->p_dev->iro_arr)
 868
 869         /* HW functions */
 870         u8                              num_hwfns;
 871         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 872 #define ECORE_LEADING_HWFN(dev)         (&dev->hwfns[0])
 873 #define ECORE_IS_CMT(dev)               ((dev)->num_hwfns > 1)
 874
 875         /* Engine affinity */
 876         u8                              l2_affin_hint;
 877         u8                              fir_affin;
 878         u8                              iwarp_affin;
 879         /* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */
 880 #define ECORE_FIR_AFFIN_HWFN(dev)       (&dev->hwfns[dev->fir_affin])
 881         /* Macro for getting the engine-affinitized hwfn for iWARP */
 882 #define ECORE_IWARP_AFFIN_HWFN(dev)     (&dev->hwfns[dev->iwarp_affin])
 883         /* Generic macro for getting the engine-affinitized hwfn */
 884 #define ECORE_AFFIN_HWFN(dev) \
 885         (ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \
 886          ECORE_IWARP_AFFIN_HWFN(dev) : \
 887          ECORE_FIR_AFFIN_HWFN(dev))
 888         /* Macro for getting the index (0/1) of the engine-affinitized hwfn */
 889 #define ECORE_AFFIN_HWFN_IDX(dev) \
 890         (IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1)
 891
 892         /* SRIOV */
 893         struct ecore_hw_sriov_info      *p_iov_info;
 894 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 895         struct ecore_tunnel_info        tunnel;
 896         bool                            b_is_vf;
 897         bool                            b_dont_override_vf_msix;
 898
 899         u32                             drv_type;
 900
 901         u32                             rdma_max_sge;
 902         u32                             rdma_max_inline;
 903         u32                             rdma_max_srq_sge;
 904
 905         struct ecore_eth_stats          *reset_stats;
 906         struct ecore_fw_data            *fw_data;
 907
 908         u32                             mcp_nvm_resp;
 909
 910         /* Recovery */
 911         bool                            recov_in_prog;
 912
 913 /* Indicates whether should prevent attentions from being reasserted */
 914
 915         bool                            attn_clr_en;
 916
 917         /* Indicates whether allowing the MFW to collect a crash dump */
 918         bool                            allow_mdump;
 919
 920         /* Indicates if the reg_fifo is checked after any register access */
 921         bool                            chk_reg_fifo;
 922
 923 #ifndef ASIC_ONLY
 924         bool                            b_is_emul_full;
 925         bool                            b_is_emul_mac;
 926 #endif
 927         /* LLH info */
 928         u8                              ppfid_bitmap;
 929         struct ecore_llh_info           *p_llh_info;
 930
 931         /* Indicates whether this PF serves a storage target */
 932         bool                            b_is_target;
 933
 934 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 935         void                            *firmware;
 936         u64                             fw_len;
 937 #endif
 938         bool                            disable_ilt_dump;
 939
 940         /* @DPDK */
 941         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 942         struct ecore_dbg_params         dbg_params;
 943         osal_mutex_t                    dbg_lock;
 944
 945         /* DPDK specific ecore field */
 946         struct rte_pci_device           *pci_dev;
 947 };
 948
 949 enum ecore_hsi_def_type {
 950         ECORE_HSI_DEF_MAX_NUM_VFS,
 951         ECORE_HSI_DEF_MAX_NUM_L2_QUEUES,
 952         ECORE_HSI_DEF_MAX_NUM_PORTS,
 953         ECORE_HSI_DEF_MAX_SB_PER_PATH,
 954         ECORE_HSI_DEF_MAX_NUM_PFS,
 955         ECORE_HSI_DEF_MAX_NUM_VPORTS,
 956         ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE,
 957         ECORE_HSI_DEF_MAX_QM_TX_QUEUES,
 958         ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS,
 959         ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
 960         ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS,
 961         ECORE_HSI_DEF_MAX_PBF_CMD_LINES,
 962         ECORE_HSI_DEF_MAX_BTB_BLOCKS,
 963         ECORE_NUM_HSI_DEFS
 964 };
 965
 966 u32 ecore_get_hsi_def_val(struct ecore_dev *p_dev,
 967                           enum ecore_hsi_def_type type);
 968
 969 #define NUM_OF_VFS(dev) \
 970         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VFS)
 971 #define NUM_OF_L2_QUEUES(dev) \
 972         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_L2_QUEUES)
 973 #define NUM_OF_PORTS(dev) \
 974         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PORTS)
 975 #define NUM_OF_SBS(dev) \
 976         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_SB_PER_PATH)
 977 #define NUM_OF_ENG_PFS(dev) \
 978         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PFS)
 979 #define NUM_OF_VPORTS(dev) \
 980         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VPORTS)
 981 #define NUM_OF_RSS_ENGINES(dev) \
 982         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE)
 983 #define NUM_OF_QM_TX_QUEUES(dev) \
 984         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_TX_QUEUES)
 985 #define NUM_OF_PXP_ILT_RECORDS(dev) \
 986         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS)
 987 #define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
 988         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
 989 #define NUM_OF_QM_GLOBAL_RLS(dev) \
 990         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS)
 991 #define NUM_OF_PBF_CMD_LINES(dev) \
 992         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_PBF_CMD_LINES)
 993 #define NUM_OF_BTB_BLOCKS(dev) \
 994         ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_BTB_BLOCKS)
 995
 996 #define CRC8_TABLE_SIZE 256
 997
 998 /**
 999  * @brief ecore_concrete_to_sw_fid - get the sw function id from
1000  *        the concrete value.
1001  *
1002  * @param concrete_fid
1003  *
1004  * @return OSAL_INLINE u8
1005  */
1006 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
1007 {
1008         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
1009         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
1010         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
1011         u8 sw_fid;
1012
1013         if (vf_valid)
1014                 sw_fid = vfid + MAX_NUM_PFS;
1015         else
1016                 sw_fid = pfid;
1017
1018         return sw_fid;
1019 }
1020
1021 #define PKT_LB_TC 9
1022
1023 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
1024 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
1025                                            struct ecore_ptt *p_ptt,
1026                                            u32 min_pf_rate);
1027
1028 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
1029 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
1030 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
1031 int ecore_device_num_engines(struct ecore_dev *p_dev);
1032 int ecore_device_num_ports(struct ecore_dev *p_dev);
1033 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
1034                            u8 *mac);
1035
1036 /* Flags for indication of required queues */
1037 #define PQ_FLAGS_RLS    (1 << 0)
1038 #define PQ_FLAGS_MCOS   (1 << 1)
1039 #define PQ_FLAGS_LB     (1 << 2)
1040 #define PQ_FLAGS_OOO    (1 << 3)
1041 #define PQ_FLAGS_ACK    (1 << 4)
1042 #define PQ_FLAGS_OFLD   (1 << 5)
1043 #define PQ_FLAGS_VFS    (1 << 6)
1044 #define PQ_FLAGS_LLT    (1 << 7)
1045
1046 /* physical queue index for cm context intialization */
1047 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
1048 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
1049 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
1050 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
1051
1052 /* qm vport for rate limit configuration */
1053 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
1054
1055 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
1056
1057 /* doorbell recovery mechanism */
1058 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
1059 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
1060                                enum ecore_db_rec_exec);
1061
1062 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn);
1063
1064 /* amount of resources used in qm init */
1065 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
1066 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
1067 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
1068 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
1069 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
1070
1071 #define MFW_PORT(_p_hwfn)       ((_p_hwfn)->abs_pf_id % \
1072                                  ecore_device_num_ports((_p_hwfn)->p_dev))
1073
1074 /* The PFID<->PPFID calculation is based on the relative index of a PF on its
1075  * port. In BB there is a bug in the LLH in which the PPFID is actually engine
1076  * based, and thus it equals the PFID.
1077  */
1078 #define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \
1079         (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
1080          (abs_ppfid) : \
1081          (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \
1082          MFW_PORT(_p_hwfn))
1083 #define ECORE_PPFID_BY_PFID(_p_hwfn) \
1084         (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
1085          (_p_hwfn)->rel_pf_id : \
1086          (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine)
1087
1088 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1089                                          struct ecore_ptt *p_ptt, u32 addr,
1090                                          u32 val);
1091
1092 /* Utility functions for dumping the content of the NIG LLH filters */
1093 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);
1094 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);
1095
1096 /**
1097  * @brief ecore_set_platform_str - Set the debug dump platform string.
1098  * Write the ecore version and device's string to the given buffer.
1099  *
1100  * @param p_hwfn
1101  * @param buf_str
1102  * @param buf_size
1103  */
1104 void ecore_set_platform_str(struct ecore_hwfn *p_hwfn,
1105                             char *buf_str, u32 buf_size);
1106
1107 #define TSTORM_QZONE_START      PXP_VF_BAR0_START_SDM_ZONE_A
1108
1109 #define MSTORM_QZONE_START(dev) \
1110         (TSTORM_QZONE_START + (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
1111
1112 #endif /* __ECORE_H */