drivers/net/qede/base/ecore.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_H
  10 #define __ECORE_H
  11
  12 /* @DPDK */
  13 #include <sys/stat.h>
  14 #include <fcntl.h>
  15 #include <unistd.h>
  16
  17 #define CONFIG_ECORE_BINARY_FW
  18 #undef CONFIG_ECORE_ZIPPED_FW
  19
  20 #ifdef CONFIG_ECORE_ZIPPED_FW
  21 #include <zlib.h>
  22 #endif
  23
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_hsi_debug_tools.h"
  26 #include "ecore_hsi_init_func.h"
  27 #include "ecore_hsi_init_tool.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define ECORE_MAJOR_VERSION             8
  32 #define ECORE_MINOR_VERSION             18
  33 #define ECORE_REVISION_VERSION          7
  34 #define ECORE_ENGINEERING_VERSION       0
  35
  36 #define ECORE_VERSION                                                   \
  37         ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) |    \
  38          (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
  39
  40 #define STORM_FW_VERSION                                                \
  41         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |  \
  42          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  43
  44 #define MAX_HWFNS_PER_DEVICE    2
  45 #define NAME_SIZE 128 /* @DPDK */
  46 #define ECORE_WFQ_UNIT  100
  47 #include "../qede_logs.h" /* @DPDK */
  48
  49 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  50 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  51 /* Constants */
  52 #define ECORE_WID_SIZE          (1024)
  53
  54 /* Configurable */
  55 #define ECORE_PF_DEMS_SIZE      (4)
  56
  57 /* cau states */
  58 enum ecore_coalescing_mode {
  59         ECORE_COAL_MODE_DISABLE,
  60         ECORE_COAL_MODE_ENABLE
  61 };
  62
  63 enum ecore_nvm_cmd {
  64         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  65         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  66         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  67         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  68         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  69         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  70         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  71         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  72         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  73         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  74         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  75 };
  76
  77 #ifndef LINUX_REMOVE
  78 #if !defined(CONFIG_ECORE_L2)
  79 #define CONFIG_ECORE_L2
  80 #define CONFIG_ECORE_SRIOV
  81 #endif
  82 #endif
  83
  84 /* helpers */
  85 #ifndef __EXTRACT__LINUX__
  86 #define MASK_FIELD(_name, _value)                                       \
  87                 ((_value) &= (_name##_MASK))
  88
  89 #define FIELD_VALUE(_name, _value)                                      \
  90                 ((_value & _name##_MASK) << _name##_SHIFT)
  91
  92 #define SET_FIELD(value, name, flag)                                    \
  93 do {                                                                    \
  94         (value) &= ~(name##_MASK << name##_SHIFT);                      \
  95         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
  96 } while (0)
  97
  98 #define GET_FIELD(value, name)                                          \
  99         (((value) >> (name##_SHIFT)) & name##_MASK)
 100 #endif
 101
 102 #define ECORE_MFW_GET_FIELD(name, field)                                \
 103         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
 104
 105 #define ECORE_MFW_SET_FIELD(name, field, value)                         \
 106 do {                                                                    \
 107         (name) &= ~((field ## _MASK) << (field ## _SHIFT));             \
 108         (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));  \
 109 } while (0)
 110
 111 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
 112 {
 113         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 114                       (cid * ECORE_PF_DEMS_SIZE);
 115
 116         return db_addr;
 117 }
 118
 119 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 120 {
 121         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 122                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 123
 124         return db_addr;
 125 }
 126
 127 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 128         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 129          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 130
 131 #ifndef LINUX_REMOVE
 132 #ifndef U64_HI
 133 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 134 #endif
 135
 136 #ifndef U64_LO
 137 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 138 #endif
 139 #endif
 140
 141 #ifndef __EXTRACT__LINUX__
 142 enum DP_LEVEL {
 143         ECORE_LEVEL_VERBOSE     = 0x0,
 144         ECORE_LEVEL_INFO        = 0x1,
 145         ECORE_LEVEL_NOTICE      = 0x2,
 146         ECORE_LEVEL_ERR         = 0x3,
 147 };
 148
 149 #define ECORE_LOG_LEVEL_SHIFT   (30)
 150 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 151 #define ECORE_LOG_INFO_MASK     (0x40000000)
 152 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 153
 154 enum DP_MODULE {
 155 #ifndef LINUX_REMOVE
 156         ECORE_MSG_DRV           = 0x0001,
 157         ECORE_MSG_PROBE         = 0x0002,
 158         ECORE_MSG_LINK          = 0x0004,
 159         ECORE_MSG_TIMER         = 0x0008,
 160         ECORE_MSG_IFDOWN        = 0x0010,
 161         ECORE_MSG_IFUP          = 0x0020,
 162         ECORE_MSG_RX_ERR        = 0x0040,
 163         ECORE_MSG_TX_ERR        = 0x0080,
 164         ECORE_MSG_TX_QUEUED     = 0x0100,
 165         ECORE_MSG_INTR          = 0x0200,
 166         ECORE_MSG_TX_DONE       = 0x0400,
 167         ECORE_MSG_RX_STATUS     = 0x0800,
 168         ECORE_MSG_PKTDATA       = 0x1000,
 169         ECORE_MSG_HW            = 0x2000,
 170         ECORE_MSG_WOL           = 0x4000,
 171 #endif
 172         ECORE_MSG_SPQ           = 0x10000,
 173         ECORE_MSG_STATS         = 0x20000,
 174         ECORE_MSG_DCB           = 0x40000,
 175         ECORE_MSG_IOV           = 0x80000,
 176         ECORE_MSG_SP            = 0x100000,
 177         ECORE_MSG_STORAGE       = 0x200000,
 178         ECORE_MSG_OOO           = 0x200000,
 179         ECORE_MSG_CXT           = 0x800000,
 180         ECORE_MSG_LL2           = 0x1000000,
 181         ECORE_MSG_ILT           = 0x2000000,
 182         ECORE_MSG_RDMA          = 0x4000000,
 183         ECORE_MSG_DEBUG         = 0x8000000,
 184         /* to be added...up to 0x8000000 */
 185 };
 186 #endif
 187
 188 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 189
 190 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 191         (val == (cond1) ? true1 : \
 192          (val == (cond2) ? true2 : def))
 193
 194 /* forward */
 195 struct ecore_ptt_pool;
 196 struct ecore_spq;
 197 struct ecore_sb_info;
 198 struct ecore_sb_attn_info;
 199 struct ecore_cxt_mngr;
 200 struct ecore_dma_mem;
 201 struct ecore_sb_sp_info;
 202 struct ecore_ll2_info;
 203 struct ecore_igu_info;
 204 struct ecore_mcp_info;
 205 struct ecore_dcbx_info;
 206
 207 struct ecore_rt_data {
 208         u32     *init_val;
 209         bool    *b_valid;
 210 };
 211
 212 enum ecore_tunn_mode {
 213         ECORE_MODE_L2GENEVE_TUNN,
 214         ECORE_MODE_IPGENEVE_TUNN,
 215         ECORE_MODE_L2GRE_TUNN,
 216         ECORE_MODE_IPGRE_TUNN,
 217         ECORE_MODE_VXLAN_TUNN,
 218 };
 219
 220 enum ecore_tunn_clss {
 221         ECORE_TUNN_CLSS_MAC_VLAN,
 222         ECORE_TUNN_CLSS_MAC_VNI,
 223         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 224         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 225         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 226         MAX_ECORE_TUNN_CLSS,
 227 };
 228
 229 struct ecore_tunn_update_type {
 230         bool b_update_mode;
 231         bool b_mode_enabled;
 232         enum ecore_tunn_clss tun_cls;
 233 };
 234
 235 struct ecore_tunn_update_udp_port {
 236         bool b_update_port;
 237         u16 port;
 238 };
 239
 240 struct ecore_tunnel_info {
 241         struct ecore_tunn_update_type vxlan;
 242         struct ecore_tunn_update_type l2_geneve;
 243         struct ecore_tunn_update_type ip_geneve;
 244         struct ecore_tunn_update_type l2_gre;
 245         struct ecore_tunn_update_type ip_gre;
 246
 247         struct ecore_tunn_update_udp_port vxlan_port;
 248         struct ecore_tunn_update_udp_port geneve_port;
 249
 250         bool b_update_rx_cls;
 251         bool b_update_tx_cls;
 252 };
 253
 254 /* The PCI personality is not quite synonymous to protocol ID:
 255  * 1. All personalities need CORE connections
 256  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 257  */
 258 enum ecore_pci_personality {
 259         ECORE_PCI_ETH,
 260         ECORE_PCI_FCOE,
 261         ECORE_PCI_ISCSI,
 262         ECORE_PCI_ETH_ROCE,
 263         ECORE_PCI_ETH_IWARP,
 264         ECORE_PCI_ETH_RDMA,
 265         ECORE_PCI_DEFAULT /* default in shmem */
 266 };
 267
 268 /* All VFs are symmetric, all counters are PF + all VFs */
 269 struct ecore_qm_iids {
 270         u32 cids;
 271         u32 vf_cids;
 272         u32 tids;
 273 };
 274
 275 #define MAX_PF_PER_PORT 8
 276
 277 /* HW / FW resources, output of features supported below, most information
 278  * is received from MFW.
 279  */
 280 enum ecore_resources {
 281         ECORE_SB,
 282         ECORE_L2_QUEUE,
 283         ECORE_VPORT,
 284         ECORE_RSS_ENG,
 285         ECORE_PQ,
 286         ECORE_RL,
 287         ECORE_MAC,
 288         ECORE_VLAN,
 289         ECORE_RDMA_CNQ_RAM,
 290         ECORE_ILT,
 291         ECORE_LL2_QUEUE,
 292         ECORE_CMDQS_CQS,
 293         ECORE_RDMA_STATS_QUEUE,
 294         ECORE_BDQ,
 295         ECORE_MAX_RESC,                 /* must be last */
 296 };
 297
 298 /* Features that require resources, given as input to the resource management
 299  * algorithm, the output are the resources above
 300  */
 301 enum ecore_feature {
 302         ECORE_PF_L2_QUE,
 303         ECORE_PF_TC,
 304         ECORE_VF,
 305         ECORE_EXTRA_VF_QUE,
 306         ECORE_VMQ,
 307         ECORE_RDMA_CNQ,
 308         ECORE_ISCSI_CQ,
 309         ECORE_FCOE_CQ,
 310         ECORE_VF_L2_QUE,
 311         ECORE_MAX_FEATURES,
 312 };
 313
 314 enum ecore_port_mode {
 315         ECORE_PORT_MODE_DE_2X40G,
 316         ECORE_PORT_MODE_DE_2X50G,
 317         ECORE_PORT_MODE_DE_1X100G,
 318         ECORE_PORT_MODE_DE_4X10G_F,
 319         ECORE_PORT_MODE_DE_4X10G_E,
 320         ECORE_PORT_MODE_DE_4X20G,
 321         ECORE_PORT_MODE_DE_1X40G,
 322         ECORE_PORT_MODE_DE_2X25G,
 323         ECORE_PORT_MODE_DE_1X25G,
 324         ECORE_PORT_MODE_DE_4X25G,
 325         ECORE_PORT_MODE_DE_2X10G,
 326 };
 327
 328 enum ecore_dev_cap {
 329         ECORE_DEV_CAP_ETH,
 330         ECORE_DEV_CAP_FCOE,
 331         ECORE_DEV_CAP_ISCSI,
 332         ECORE_DEV_CAP_ROCE,
 333         ECORE_DEV_CAP_IWARP
 334 };
 335
 336 #ifndef __EXTRACT__LINUX__
 337 enum ecore_hw_err_type {
 338         ECORE_HW_ERR_FAN_FAIL,
 339         ECORE_HW_ERR_MFW_RESP_FAIL,
 340         ECORE_HW_ERR_HW_ATTN,
 341         ECORE_HW_ERR_DMAE_FAIL,
 342         ECORE_HW_ERR_RAMROD_FAIL,
 343         ECORE_HW_ERR_FW_ASSERT,
 344 };
 345 #endif
 346
 347 struct ecore_hw_info {
 348         /* PCI personality */
 349         enum ecore_pci_personality personality;
 350 #define ECORE_IS_RDMA_PERSONALITY(dev)                      \
 351         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE ||  \
 352          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 353          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 354 #define ECORE_IS_ROCE_PERSONALITY(dev)                     \
 355         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 356          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 357 #define ECORE_IS_IWARP_PERSONALITY(dev)                     \
 358         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 359          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 360 #define ECORE_IS_L2_PERSONALITY(dev)                  \
 361         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 362          ECORE_IS_RDMA_PERSONALITY(dev))
 363
 364         /* Resource Allocation scheme results */
 365         u32 resc_start[ECORE_MAX_RESC];
 366         u32 resc_num[ECORE_MAX_RESC];
 367         u32 feat_num[ECORE_MAX_FEATURES];
 368
 369         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 370         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 371         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 372                                          RESC_NUM(_p_hwfn, resc))
 373         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 374
 375         /* Amount of traffic classes HW supports */
 376         u8 num_hw_tc;
 377
 378 /* Amount of TCs which should be active according to DCBx or upper layer driver
 379  * configuration
 380  */
 381
 382         u8 num_active_tc;
 383
 384         /* The traffic class used by PF for it's offloaded protocol */
 385         u8 offload_tc;
 386
 387         u32 concrete_fid;
 388         u16 opaque_fid;
 389         u16 ovlan;
 390         u32 part_num[4];
 391
 392         unsigned char hw_mac_addr[ETH_ALEN];
 393         u64 node_wwn; /* For FCoE only */
 394         u64 port_wwn; /* For FCoE only */
 395
 396         u16 num_iscsi_conns;
 397         u16 num_fcoe_conns;
 398
 399         struct ecore_igu_info *p_igu_info;
 400         /* Sriov */
 401         u8 max_chains_per_vf;
 402
 403         u32 port_mode;
 404         u32     hw_mode;
 405         unsigned long device_capabilities;
 406
 407         /* Default DCBX mode */
 408         u8 dcbx_mode;
 409
 410         u16 mtu;
 411 };
 412
 413 /* maximun size of read/write commands (HW limit) */
 414 #define DMAE_MAX_RW_SIZE        0x2000
 415
 416 struct ecore_dmae_info {
 417         /* Mutex for synchronizing access to functions */
 418         osal_mutex_t    mutex;
 419
 420         u8 channel;
 421
 422         dma_addr_t completion_word_phys_addr;
 423
 424         /* The memory location where the DMAE writes the completion
 425          * value when an operation is finished on this context.
 426          */
 427         u32 *p_completion_word;
 428
 429         dma_addr_t intermediate_buffer_phys_addr;
 430
 431         /* An intermediate buffer for DMAE operations that use virtual
 432          * addresses - data is DMA'd to/from this buffer and then
 433          * memcpy'd to/from the virtual address
 434          */
 435         u32 *p_intermediate_buffer;
 436
 437         dma_addr_t dmae_cmd_phys_addr;
 438         struct dmae_cmd *p_dmae_cmd;
 439 };
 440
 441 struct ecore_wfq_data {
 442         u32 default_min_speed; /* When wfq feature is not configured */
 443         u32 min_speed; /* when feature is configured for any 1 vport */
 444         bool configured;
 445 };
 446
 447 struct ecore_qm_info {
 448         struct init_qm_pq_params    *qm_pq_params;
 449         struct init_qm_vport_params *qm_vport_params;
 450         struct init_qm_port_params  *qm_port_params;
 451         u16                     start_pq;
 452         u8                      start_vport;
 453         u16                     pure_lb_pq;
 454         u16                     offload_pq;
 455         u16                     pure_ack_pq;
 456         u16                     ooo_pq;
 457         u16                     first_vf_pq;
 458         u16                     first_mcos_pq;
 459         u16                     first_rl_pq;
 460         u16                     num_pqs;
 461         u16                     num_vf_pqs;
 462         u8                      num_vports;
 463         u8                      max_phys_tcs_per_port;
 464         u8                      ooo_tc;
 465         bool                    pf_rl_en;
 466         bool                    pf_wfq_en;
 467         bool                    vport_rl_en;
 468         bool                    vport_wfq_en;
 469         u8                      pf_wfq;
 470         u32                     pf_rl;
 471         struct ecore_wfq_data   *wfq_data;
 472         u8                      num_pf_rls;
 473 };
 474
 475 struct storm_stats {
 476         u32 address;
 477         u32 len;
 478 };
 479
 480 struct ecore_fw_data {
 481 #ifdef CONFIG_ECORE_BINARY_FW
 482         struct fw_ver_info *fw_ver_info;
 483 #endif
 484         const u8 *modes_tree_buf;
 485         union init_op *init_ops;
 486         const u32 *arr_data;
 487         u32 init_ops_size;
 488 };
 489
 490 struct ecore_hwfn {
 491         struct ecore_dev                *p_dev;
 492         u8                              my_id;          /* ID inside the PF */
 493 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 494         u8                              rel_pf_id;      /* Relative to engine*/
 495         u8                              abs_pf_id;
 496         #define ECORE_PATH_ID(_p_hwfn) \
 497                 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 498         u8                              port_id;
 499         bool                            b_active;
 500
 501         u32                             dp_module;
 502         u8                              dp_level;
 503         char                            name[NAME_SIZE];
 504         void                            *dp_ctx;
 505
 506         bool                            first_on_engine;
 507         bool                            hw_init_done;
 508
 509         u8                              num_funcs_on_engine;
 510         u8                              enabled_func_idx;
 511
 512         /* BAR access */
 513         void OSAL_IOMEM                 *regview;
 514         void OSAL_IOMEM                 *doorbells;
 515         u64                             db_phys_addr;
 516         unsigned long                   db_size;
 517
 518         /* PTT pool */
 519         struct ecore_ptt_pool           *p_ptt_pool;
 520
 521         /* HW info */
 522         struct ecore_hw_info            hw_info;
 523
 524         /* rt_array (for init-tool) */
 525         struct ecore_rt_data            rt_data;
 526
 527         /* SPQ */
 528         struct ecore_spq                *p_spq;
 529
 530         /* EQ */
 531         struct ecore_eq                 *p_eq;
 532
 533         /* Consolidate Q*/
 534         struct ecore_consq              *p_consq;
 535
 536         /* Slow-Path definitions */
 537         osal_dpc_t                      sp_dpc;
 538         bool                            b_sp_dpc_enabled;
 539
 540         struct ecore_ptt                *p_main_ptt;
 541         struct ecore_ptt                *p_dpc_ptt;
 542
 543         struct ecore_sb_sp_info         *p_sp_sb;
 544         struct ecore_sb_attn_info       *p_sb_attn;
 545
 546         /* Protocol related */
 547         bool                            using_ll2;
 548         struct ecore_ll2_info           *p_ll2_info;
 549         struct ecore_ooo_info           *p_ooo_info;
 550         struct ecore_iscsi_info         *p_iscsi_info;
 551         struct ecore_fcoe_info          *p_fcoe_info;
 552         struct ecore_rdma_info          *p_rdma_info;
 553         struct ecore_pf_params          pf_params;
 554
 555         bool                            b_rdma_enabled_in_prs;
 556         u32                             rdma_prs_search_reg;
 557
 558         /* Array of sb_info of all status blocks */
 559         struct ecore_sb_info            *sbs_info[MAX_SB_PER_PF_MIMD];
 560         u16                             num_sbs;
 561
 562         struct ecore_cxt_mngr           *p_cxt_mngr;
 563
 564         /* Flag indicating whether interrupts are enabled or not*/
 565         bool                            b_int_enabled;
 566         bool                            b_int_requested;
 567
 568         /* True if the driver requests for the link */
 569         bool                            b_drv_link_init;
 570
 571         struct ecore_vf_iov             *vf_iov_info;
 572         struct ecore_pf_iov             *pf_iov_info;
 573         struct ecore_mcp_info           *mcp_info;
 574         struct ecore_dcbx_info          *p_dcbx_info;
 575
 576         struct ecore_dmae_info          dmae_info;
 577
 578         /* QM init */
 579         struct ecore_qm_info            qm_info;
 580
 581 #ifdef CONFIG_ECORE_ZIPPED_FW
 582         /* Buffer for unzipping firmware data */
 583         void *unzip_buf;
 584 #endif
 585
 586         struct dbg_tools_data           dbg_info;
 587
 588         struct z_stream_s               *stream;
 589
 590         /* PWM region specific data */
 591         u32                             dpi_size;
 592         u32                             dpi_count;
 593         u32                             dpi_start_offset; /* this is used to
 594                                                            * calculate th
 595                                                            * doorbell address
 596                                                            */
 597
 598         /* If one of the following is set then EDPM shouldn't be used */
 599         u8                              dcbx_no_edpm;
 600         u8                              db_bar_no_edpm;
 601 };
 602
 603 #ifndef __EXTRACT__LINUX__
 604 enum ecore_mf_mode {
 605         ECORE_MF_DEFAULT,
 606         ECORE_MF_OVLAN,
 607         ECORE_MF_NPAR,
 608 };
 609 #endif
 610
 611 /* @DPDK */
 612 struct ecore_dbg_feature {
 613         u8                              *dump_buf;
 614         u32                             buf_size;
 615         u32                             dumped_dwords;
 616 };
 617
 618 enum qed_dbg_features {
 619         DBG_FEATURE_BUS,
 620         DBG_FEATURE_GRC,
 621         DBG_FEATURE_IDLE_CHK,
 622         DBG_FEATURE_MCP_TRACE,
 623         DBG_FEATURE_REG_FIFO,
 624         DBG_FEATURE_PROTECTION_OVERRIDE,
 625         DBG_FEATURE_NUM
 626 };
 627
 628 struct ecore_dev {
 629         u32                             dp_module;
 630         u8                              dp_level;
 631         char                            name[NAME_SIZE];
 632         void                            *dp_ctx;
 633
 634         u8                              type;
 635 #define ECORE_DEV_TYPE_BB       (0 << 0)
 636 #define ECORE_DEV_TYPE_AH       (1 << 0)
 637 /* Translate type/revision combo into the proper conditions */
 638 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 639 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 640 #ifndef ASIC_ONLY
 641 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 642                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 643 #else
 644 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 645 #endif
 646 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 647 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 648
 649 #define ECORE_DEV_ID_MASK       0xff00
 650 #define ECORE_DEV_ID_MASK_BB    0x1600
 651 #define ECORE_DEV_ID_MASK_AH    0x8000
 652
 653         u16 vendor_id;
 654         u16 device_id;
 655
 656         u16                             chip_num;
 657         #define CHIP_NUM_MASK                   0xffff
 658         #define CHIP_NUM_SHIFT                  16
 659
 660         u16                             chip_rev;
 661         #define CHIP_REV_MASK                   0xf
 662         #define CHIP_REV_SHIFT                  12
 663 #ifndef ASIC_ONLY
 664         #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
 665         #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
 666         #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
 667         #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 668                                           CHIP_REV_IS_EMUL_B0(_p_dev))
 669         #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
 670         #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
 671         #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
 672                                           CHIP_REV_IS_FPGA_B0(_p_dev))
 673         #define CHIP_REV_IS_SLOW(_p_dev) \
 674                 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 675         #define CHIP_REV_IS_A0(_p_dev) \
 676                 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 677                  CHIP_REV_IS_FPGA_A0(_p_dev) || \
 678                  !(_p_dev)->chip_rev)
 679         #define CHIP_REV_IS_B0(_p_dev) \
 680                 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
 681                  CHIP_REV_IS_FPGA_B0(_p_dev) || \
 682                  (_p_dev)->chip_rev == 1)
 683         #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
 684 #else
 685         #define CHIP_REV_IS_A0(_p_dev)  (!(_p_dev)->chip_rev)
 686         #define CHIP_REV_IS_B0(_p_dev)  ((_p_dev)->chip_rev == 1)
 687 #endif
 688
 689         u16                             chip_metal;
 690         #define CHIP_METAL_MASK                 0xff
 691         #define CHIP_METAL_SHIFT                4
 692
 693         u16                             chip_bond_id;
 694         #define CHIP_BOND_ID_MASK               0xf
 695         #define CHIP_BOND_ID_SHIFT              0
 696
 697         u8                              num_engines;
 698         u8                              num_ports_in_engines;
 699         u8                              num_funcs_in_port;
 700
 701         u8                              path_id;
 702         enum ecore_mf_mode              mf_mode;
 703         #define IS_MF_DEFAULT(_p_hwfn)  \
 704                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 705         #define IS_MF_SI(_p_hwfn)       \
 706                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 707         #define IS_MF_SD(_p_hwfn)       \
 708                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 709
 710         int                             pcie_width;
 711         int                             pcie_speed;
 712
 713         /* Add MF related configuration */
 714         u8                              mcp_rev;
 715         u8                              boot_mode;
 716
 717         u8                              wol;
 718
 719         u32                             int_mode;
 720         enum ecore_coalescing_mode      int_coalescing_mode;
 721         u16                             rx_coalesce_usecs;
 722         u16                             tx_coalesce_usecs;
 723
 724         /* Start Bar offset of first hwfn */
 725         void OSAL_IOMEM                 *regview;
 726         void OSAL_IOMEM                 *doorbells;
 727         u64                             db_phys_addr;
 728         unsigned long                   db_size;
 729
 730         /* PCI */
 731         u8                              cache_shift;
 732
 733         /* Init */
 734         const struct iro                *iro_arr;
 735         #define IRO (p_hwfn->p_dev->iro_arr)
 736
 737         /* HW functions */
 738         u8                              num_hwfns;
 739         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 740
 741         /* SRIOV */
 742         struct ecore_hw_sriov_info      *p_iov_info;
 743 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 744         struct ecore_tunnel_info        tunnel;
 745         bool                            b_is_vf;
 746
 747         u32                             drv_type;
 748
 749         u32                             rdma_max_sge;
 750         u32                             rdma_max_inline;
 751         u32                             rdma_max_srq_sge;
 752
 753         struct ecore_eth_stats          *reset_stats;
 754         struct ecore_fw_data            *fw_data;
 755
 756         u32                             mcp_nvm_resp;
 757
 758         /* Recovery */
 759         bool                            recov_in_prog;
 760
 761 /* Indicates whether should prevent attentions from being reasserted */
 762
 763         bool                            attn_clr_en;
 764
 765         /* Indicates whether allowing the MFW to collect a crash dump */
 766         bool                            mdump_en;
 767
 768         /* Indicates if the reg_fifo is checked after any register access */
 769         bool                            chk_reg_fifo;
 770
 771 #ifndef ASIC_ONLY
 772         bool                            b_is_emul_full;
 773 #endif
 774
 775 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 776         void                            *firmware;
 777         u64                             fw_len;
 778 #endif
 779
 780         /* @DPDK */
 781         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 782         u8                              engine_for_debug;
 783 };
 784
 785 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 786                                                   : MAX_NUM_VFS_K2)
 787 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 788                                                   : MAX_NUM_L2_QUEUES_K2)
 789 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 790                                                   : MAX_NUM_PORTS_K2)
 791 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 792                                                   : MAX_SB_PER_PATH_K2)
 793 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 794                                                   : MAX_NUM_PFS_K2)
 795
 796 /**
 797  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 798  *        the concrete value.
 799  *
 800  * @param concrete_fid
 801  *
 802  * @return OSAL_INLINE u8
 803  */
 804 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
 805                                           u32 concrete_fid)
 806 {
 807         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 808         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 809         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 810         u8 sw_fid;
 811
 812         if (vf_valid)
 813                 sw_fid = vfid + MAX_NUM_PFS;
 814         else
 815                 sw_fid = pfid;
 816
 817         return sw_fid;
 818 }
 819
 820 #define PURE_LB_TC 8
 821 #define PKT_LB_TC 9
 822
 823 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 824 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 825                                            u32 min_pf_rate);
 826
 827 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 828 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 829 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 830 int ecore_device_num_engines(struct ecore_dev *p_dev);
 831 int ecore_device_num_ports(struct ecore_dev *p_dev);
 832 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 833                            u8 *mac);
 834
 835 /* Flags for indication of required queues */
 836 #define PQ_FLAGS_RLS    (1 << 0)
 837 #define PQ_FLAGS_MCOS   (1 << 1)
 838 #define PQ_FLAGS_LB     (1 << 2)
 839 #define PQ_FLAGS_OOO    (1 << 3)
 840 #define PQ_FLAGS_ACK    (1 << 4)
 841 #define PQ_FLAGS_OFLD   (1 << 5)
 842 #define PQ_FLAGS_VFS    (1 << 6)
 843
 844 /* physical queue index for cm context intialization */
 845 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 846 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 847 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 848 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
 849
 850 /* amount of resources used in qm init */
 851 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 852 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 853 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 854 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 855 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 856
 857 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 858
 859 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
 860
 861 #endif /* __ECORE_H */