1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
15 #define CONFIG_ECORE_BINARY_FW
16 #undef CONFIG_ECORE_ZIPPED_FW
18 #ifdef CONFIG_ECORE_ZIPPED_FW
22 #include "ecore_hsi_common.h"
23 #include "ecore_hsi_debug_tools.h"
24 #include "ecore_hsi_init_func.h"
25 #include "ecore_hsi_init_tool.h"
26 #include "ecore_proto_if.h"
27 #include "mcp_public.h"
29 #define ECORE_MAJOR_VERSION 8
30 #define ECORE_MINOR_VERSION 37
31 #define ECORE_REVISION_VERSION 20
32 #define ECORE_ENGINEERING_VERSION 0
34 #define ECORE_VERSION \
35 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \
36 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
38 #define STORM_FW_VERSION \
39 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
40 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
42 #define IS_ECORE_PACING(p_hwfn) \
43 (!!(p_hwfn->b_en_pacing))
45 #define MAX_HWFNS_PER_DEVICE 2
46 #define NAME_SIZE 128 /* @DPDK */
47 #define ECORE_WFQ_UNIT 100
48 #include "../qede_logs.h" /* @DPDK */
50 #define ISCSI_BDQ_ID(_port_id) (_port_id)
51 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
53 #define ECORE_WID_SIZE (1024)
54 #define ECORE_MIN_WIDS (4)
57 #define ECORE_PF_DEMS_SIZE (4)
60 enum ecore_coalescing_mode {
61 ECORE_COAL_MODE_DISABLE,
62 ECORE_COAL_MODE_ENABLE
66 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
67 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
68 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
69 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
70 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
71 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
72 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
73 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
74 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
75 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
76 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
77 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
81 #if !defined(CONFIG_ECORE_L2)
82 #define CONFIG_ECORE_L2
83 #define CONFIG_ECORE_SRIOV
88 #ifndef __EXTRACT__LINUX__
89 #define MASK_FIELD(_name, _value) \
90 ((_value) &= (_name##_MASK))
92 #define FIELD_VALUE(_name, _value) \
93 ((_value & _name##_MASK) << _name##_SHIFT)
95 #define SET_FIELD(value, name, flag) \
97 (value) &= ~(name##_MASK << name##_SHIFT); \
98 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
101 #define GET_FIELD(value, name) \
102 (((value) >> (name##_SHIFT)) & name##_MASK)
104 #define GET_MFW_FIELD(name, field) \
105 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
107 #define SET_MFW_FIELD(name, field, value) \
109 (name) &= ~((field ## _MASK)); \
110 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
114 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
116 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
117 (cid * ECORE_PF_DEMS_SIZE);
122 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
124 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
125 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
130 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
131 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
132 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
136 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
140 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
144 #ifndef __EXTRACT__LINUX__
146 ECORE_LEVEL_VERBOSE = 0x0,
147 ECORE_LEVEL_INFO = 0x1,
148 ECORE_LEVEL_NOTICE = 0x2,
149 ECORE_LEVEL_ERR = 0x3,
152 #define ECORE_LOG_LEVEL_SHIFT (30)
153 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
154 #define ECORE_LOG_INFO_MASK (0x40000000)
155 #define ECORE_LOG_NOTICE_MASK (0x80000000)
159 ECORE_MSG_DRV = 0x0001,
160 ECORE_MSG_PROBE = 0x0002,
161 ECORE_MSG_LINK = 0x0004,
162 ECORE_MSG_TIMER = 0x0008,
163 ECORE_MSG_IFDOWN = 0x0010,
164 ECORE_MSG_IFUP = 0x0020,
165 ECORE_MSG_RX_ERR = 0x0040,
166 ECORE_MSG_TX_ERR = 0x0080,
167 ECORE_MSG_TX_QUEUED = 0x0100,
168 ECORE_MSG_INTR = 0x0200,
169 ECORE_MSG_TX_DONE = 0x0400,
170 ECORE_MSG_RX_STATUS = 0x0800,
171 ECORE_MSG_PKTDATA = 0x1000,
172 ECORE_MSG_HW = 0x2000,
173 ECORE_MSG_WOL = 0x4000,
175 ECORE_MSG_SPQ = 0x10000,
176 ECORE_MSG_STATS = 0x20000,
177 ECORE_MSG_DCB = 0x40000,
178 ECORE_MSG_IOV = 0x80000,
179 ECORE_MSG_SP = 0x100000,
180 ECORE_MSG_STORAGE = 0x200000,
181 ECORE_MSG_OOO = 0x200000,
182 ECORE_MSG_CXT = 0x800000,
183 ECORE_MSG_LL2 = 0x1000000,
184 ECORE_MSG_ILT = 0x2000000,
185 ECORE_MSG_RDMA = 0x4000000,
186 ECORE_MSG_DEBUG = 0x8000000,
187 /* to be added...up to 0x8000000 */
191 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
193 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
194 (val == (cond1) ? true1 : \
195 (val == (cond2) ? true2 : def))
198 struct ecore_ptt_pool;
200 struct ecore_sb_info;
201 struct ecore_sb_attn_info;
202 struct ecore_cxt_mngr;
203 struct ecore_dma_mem;
204 struct ecore_sb_sp_info;
205 struct ecore_ll2_info;
206 struct ecore_l2_info;
207 struct ecore_igu_info;
208 struct ecore_mcp_info;
209 struct ecore_dcbx_info;
211 struct ecore_rt_data {
216 enum ecore_tunn_mode {
217 ECORE_MODE_L2GENEVE_TUNN,
218 ECORE_MODE_IPGENEVE_TUNN,
219 ECORE_MODE_L2GRE_TUNN,
220 ECORE_MODE_IPGRE_TUNN,
221 ECORE_MODE_VXLAN_TUNN,
224 enum ecore_tunn_clss {
225 ECORE_TUNN_CLSS_MAC_VLAN,
226 ECORE_TUNN_CLSS_MAC_VNI,
227 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
228 ECORE_TUNN_CLSS_INNER_MAC_VNI,
229 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
233 struct ecore_tunn_update_type {
236 enum ecore_tunn_clss tun_cls;
239 struct ecore_tunn_update_udp_port {
244 struct ecore_tunnel_info {
245 struct ecore_tunn_update_type vxlan;
246 struct ecore_tunn_update_type l2_geneve;
247 struct ecore_tunn_update_type ip_geneve;
248 struct ecore_tunn_update_type l2_gre;
249 struct ecore_tunn_update_type ip_gre;
251 struct ecore_tunn_update_udp_port vxlan_port;
252 struct ecore_tunn_update_udp_port geneve_port;
254 bool b_update_rx_cls;
255 bool b_update_tx_cls;
258 /* The PCI personality is not quite synonymous to protocol ID:
259 * 1. All personalities need CORE connections
260 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
262 enum ecore_pci_personality {
269 ECORE_PCI_DEFAULT /* default in shmem */
272 /* All VFs are symmetric, all counters are PF + all VFs */
273 struct ecore_qm_iids {
279 #define MAX_PF_PER_PORT 8
281 /* HW / FW resources, output of features supported below, most information
282 * is received from MFW.
284 enum ecore_resources {
296 ECORE_RDMA_STATS_QUEUE,
299 /* This is needed only internally for matching against the IGU.
300 * In case of legacy MFW, would be set to `0'.
307 /* Features that require resources, given as input to the resource management
308 * algorithm, the output are the resources above
323 enum ecore_port_mode {
324 ECORE_PORT_MODE_DE_2X40G,
325 ECORE_PORT_MODE_DE_2X50G,
326 ECORE_PORT_MODE_DE_1X100G,
327 ECORE_PORT_MODE_DE_4X10G_F,
328 ECORE_PORT_MODE_DE_4X10G_E,
329 ECORE_PORT_MODE_DE_4X20G,
330 ECORE_PORT_MODE_DE_1X40G,
331 ECORE_PORT_MODE_DE_2X25G,
332 ECORE_PORT_MODE_DE_1X25G,
333 ECORE_PORT_MODE_DE_4X25G,
334 ECORE_PORT_MODE_DE_2X10G,
345 #ifndef __EXTRACT__LINUX__
346 enum ecore_hw_err_type {
347 ECORE_HW_ERR_FAN_FAIL,
348 ECORE_HW_ERR_MFW_RESP_FAIL,
349 ECORE_HW_ERR_HW_ATTN,
350 ECORE_HW_ERR_DMAE_FAIL,
351 ECORE_HW_ERR_RAMROD_FAIL,
352 ECORE_HW_ERR_FW_ASSERT,
356 enum ecore_db_rec_exec {
362 struct ecore_hw_info {
363 /* PCI personality */
364 enum ecore_pci_personality personality;
365 #define ECORE_IS_RDMA_PERSONALITY(dev) \
366 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
367 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
368 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
369 #define ECORE_IS_ROCE_PERSONALITY(dev) \
370 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
371 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
372 #define ECORE_IS_IWARP_PERSONALITY(dev) \
373 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
374 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
375 #define ECORE_IS_L2_PERSONALITY(dev) \
376 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
377 ECORE_IS_RDMA_PERSONALITY(dev))
378 #define ECORE_IS_FCOE_PERSONALITY(dev) \
379 ((dev)->hw_info.personality == ECORE_PCI_FCOE)
380 #define ECORE_IS_ISCSI_PERSONALITY(dev) \
381 ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
383 /* Resource Allocation scheme results */
384 u32 resc_start[ECORE_MAX_RESC];
385 u32 resc_num[ECORE_MAX_RESC];
386 u32 feat_num[ECORE_MAX_FEATURES];
388 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
389 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
390 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
391 RESC_NUM(_p_hwfn, resc))
392 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
394 /* Amount of traffic classes HW supports */
397 /* Amount of TCs which should be active according to DCBx or upper layer driver
403 /* The traffic class used by PF for it's offloaded protocol */
411 unsigned char hw_mac_addr[ETH_ALEN];
412 u64 node_wwn; /* For FCoE only */
413 u64 port_wwn; /* For FCoE only */
418 struct ecore_igu_info *p_igu_info;
420 u8 max_chains_per_vf;
424 unsigned long device_capabilities;
426 /* Default DCBX mode */
432 /* maximun size of read/write commands (HW limit) */
433 #define DMAE_MAX_RW_SIZE 0x2000
435 struct ecore_dmae_info {
436 /* Spinlock for synchronizing access to functions */
437 osal_spinlock_t lock;
443 dma_addr_t completion_word_phys_addr;
445 /* The memory location where the DMAE writes the completion
446 * value when an operation is finished on this context.
448 u32 *p_completion_word;
450 dma_addr_t intermediate_buffer_phys_addr;
452 /* An intermediate buffer for DMAE operations that use virtual
453 * addresses - data is DMA'd to/from this buffer and then
454 * memcpy'd to/from the virtual address
456 u32 *p_intermediate_buffer;
458 dma_addr_t dmae_cmd_phys_addr;
459 struct dmae_cmd *p_dmae_cmd;
462 struct ecore_wfq_data {
463 u32 default_min_speed; /* When wfq feature is not configured */
464 u32 min_speed; /* when feature is configured for any 1 vport */
468 struct ecore_qm_info {
469 struct init_qm_pq_params *qm_pq_params;
470 struct init_qm_vport_params *qm_vport_params;
471 struct init_qm_port_params *qm_port_params;
484 u8 max_phys_tcs_per_port;
492 struct ecore_wfq_data *wfq_data;
496 struct ecore_db_recovery_info {
498 osal_spinlock_t lock;
499 u32 db_recovery_counter;
507 struct ecore_fw_data {
508 #ifdef CONFIG_ECORE_BINARY_FW
509 struct fw_ver_info *fw_ver_info;
511 const u8 *modes_tree_buf;
512 union init_op *init_ops;
517 enum ecore_mf_mode_bit {
518 /* Supports PF-classification based on tag */
521 /* Supports PF-classification based on MAC */
522 ECORE_MF_LLH_MAC_CLSS,
524 /* Supports PF-classification based on protocol type */
525 ECORE_MF_LLH_PROTO_CLSS,
527 /* Requires a default PF to be set */
528 ECORE_MF_NEED_DEF_PF,
530 /* Allow LL2 to multicast/broadcast */
531 ECORE_MF_LL2_NON_UNICAST,
533 /* Allow Cross-PF [& child VFs] Tx-switching */
534 ECORE_MF_INTER_PF_SWITCH,
536 /* TODO - if we ever re-utilize any of this logic, we can rename */
537 ECORE_MF_UFP_SPECIFIC,
539 ECORE_MF_DISABLE_ARFS,
541 /* Use vlan for steering */
542 ECORE_MF_8021Q_TAGGING,
544 /* Use stag for steering */
545 ECORE_MF_8021AD_TAGGING,
548 enum ecore_ufp_mode {
550 ECORE_UFP_MODE_VNIC_BW,
553 enum ecore_ufp_pri_type {
558 struct ecore_ufp_info {
559 enum ecore_ufp_pri_type pri_type;
560 enum ecore_ufp_mode mode;
565 BAR_ID_0, /* used for GRC */
566 BAR_ID_1 /* Used for doorbells */
570 struct ecore_dev *p_dev;
571 u8 my_id; /* ID inside the PF */
572 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
573 u8 rel_pf_id; /* Relative to engine*/
575 #define ECORE_PATH_ID(_p_hwfn) \
576 (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
582 char name[NAME_SIZE];
585 bool first_on_engine;
588 u8 num_funcs_on_engine;
592 void OSAL_IOMEM *regview;
593 void OSAL_IOMEM *doorbells;
595 unsigned long db_size;
598 struct ecore_ptt_pool *p_ptt_pool;
601 struct ecore_hw_info hw_info;
603 /* rt_array (for init-tool) */
604 struct ecore_rt_data rt_data;
607 struct ecore_spq *p_spq;
610 struct ecore_eq *p_eq;
613 struct ecore_consq *p_consq;
615 /* Slow-Path definitions */
617 bool b_sp_dpc_enabled;
619 struct ecore_ptt *p_main_ptt;
620 struct ecore_ptt *p_dpc_ptt;
622 struct ecore_sb_sp_info *p_sp_sb;
623 struct ecore_sb_attn_info *p_sb_attn;
625 /* Protocol related */
627 struct ecore_ll2_info *p_ll2_info;
628 struct ecore_ooo_info *p_ooo_info;
629 struct ecore_iscsi_info *p_iscsi_info;
630 struct ecore_fcoe_info *p_fcoe_info;
631 struct ecore_rdma_info *p_rdma_info;
632 struct ecore_pf_params pf_params;
634 bool b_rdma_enabled_in_prs;
635 u32 rdma_prs_search_reg;
637 struct ecore_cxt_mngr *p_cxt_mngr;
639 /* Flag indicating whether interrupts are enabled or not*/
641 bool b_int_requested;
643 /* True if the driver requests for the link */
644 bool b_drv_link_init;
646 struct ecore_vf_iov *vf_iov_info;
647 struct ecore_pf_iov *pf_iov_info;
648 struct ecore_mcp_info *mcp_info;
649 struct ecore_dcbx_info *p_dcbx_info;
650 struct ecore_ufp_info ufp_info;
652 struct ecore_dmae_info dmae_info;
655 struct ecore_qm_info qm_info;
657 #ifdef CONFIG_ECORE_ZIPPED_FW
658 /* Buffer for unzipping firmware data */
662 struct dbg_tools_data dbg_info;
665 struct z_stream_s *stream;
667 /* PWM region specific data */
670 u32 dpi_start_offset; /* this is used to
675 /* If one of the following is set then EDPM shouldn't be used */
680 struct ecore_l2_info *p_l2_info;
682 /* Mechanism for recovering from doorbell drop */
683 struct ecore_db_recovery_info db_recovery_info;
685 /* Enable/disable pacing, if request to enable then
686 * IOV and mcos configuration will be skipped.
687 * this actually reflects the value requested in
688 * struct ecore_hw_prepare_params by ecore client.
693 struct ecore_ptt *p_arfs_ptt;
704 struct ecore_dbg_feature {
710 enum qed_dbg_features {
713 DBG_FEATURE_IDLE_CHK,
714 DBG_FEATURE_MCP_TRACE,
715 DBG_FEATURE_REG_FIFO,
716 DBG_FEATURE_PROTECTION_OVERRIDE,
720 enum ecore_dev_type {
728 char name[NAME_SIZE];
731 enum ecore_dev_type type;
732 /* Translate type/revision combo into the proper conditions */
733 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
734 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
736 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
737 (CHIP_REV_IS_TEDIBEAR(dev)))
739 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
741 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
742 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
746 #define ECORE_DEV_ID_MASK 0xff00
747 #define ECORE_DEV_ID_MASK_BB 0x1600
748 #define ECORE_DEV_ID_MASK_AH 0x8000
751 #define CHIP_NUM_MASK 0xffff
752 #define CHIP_NUM_SHIFT 0
755 #define CHIP_REV_MASK 0xf
756 #define CHIP_REV_SHIFT 0
758 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
759 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
760 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
761 #define CHIP_REV_IS_EMUL(_p_dev) \
762 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
763 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
764 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
765 #define CHIP_REV_IS_FPGA(_p_dev) \
766 (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
767 #define CHIP_REV_IS_SLOW(_p_dev) \
768 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
769 #define CHIP_REV_IS_A0(_p_dev) \
770 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
771 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
772 #define CHIP_REV_IS_B0(_p_dev) \
773 (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
774 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
775 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
777 #define CHIP_REV_IS_A0(_p_dev) \
778 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
779 #define CHIP_REV_IS_B0(_p_dev) \
780 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
784 #define CHIP_METAL_MASK 0xff
785 #define CHIP_METAL_SHIFT 0
788 #define CHIP_BOND_ID_MASK 0xff
789 #define CHIP_BOND_ID_SHIFT 0
793 u8 num_ports_in_engine;
794 u8 num_funcs_in_port;
798 unsigned long mf_bits;
799 enum ecore_mf_mode mf_mode;
800 #define IS_MF_DEFAULT(_p_hwfn) \
801 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
802 #define IS_MF_SI(_p_hwfn) \
803 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
804 #define IS_MF_SD(_p_hwfn) \
805 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
810 /* Add MF related configuration */
817 enum ecore_coalescing_mode int_coalescing_mode;
818 u16 rx_coalesce_usecs;
819 u16 tx_coalesce_usecs;
821 /* Start Bar offset of first hwfn */
822 void OSAL_IOMEM *regview;
823 void OSAL_IOMEM *doorbells;
825 unsigned long db_size;
831 const struct iro *iro_arr;
832 #define IRO (p_hwfn->p_dev->iro_arr)
836 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
837 #define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1)
840 struct ecore_hw_sriov_info *p_iov_info;
841 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
842 struct ecore_tunnel_info tunnel;
844 bool b_dont_override_vf_msix;
850 u32 rdma_max_srq_sge;
852 struct ecore_eth_stats *reset_stats;
853 struct ecore_fw_data *fw_data;
860 /* Indicates whether should prevent attentions from being reasserted */
864 /* Indicates whether allowing the MFW to collect a crash dump */
867 /* Indicates if the reg_fifo is checked after any register access */
874 /* Indicates whether this PF serves a storage target */
877 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
883 struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
887 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
889 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
890 : MAX_NUM_L2_QUEUES_K2)
891 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
893 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
894 : MAX_SB_PER_PATH_K2)
895 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
898 #define CRC8_TABLE_SIZE 256
901 * @brief ecore_concrete_to_sw_fid - get the sw function id from
902 * the concrete value.
904 * @param concrete_fid
906 * @return OSAL_INLINE u8
908 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
910 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
911 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
912 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
916 sw_fid = vfid + MAX_NUM_PFS;
924 #define MAX_NUM_VOQS_E4 20
926 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
927 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
928 struct ecore_ptt *p_ptt,
931 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
932 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
933 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
934 int ecore_device_num_engines(struct ecore_dev *p_dev);
935 int ecore_device_num_ports(struct ecore_dev *p_dev);
936 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
939 /* Flags for indication of required queues */
940 #define PQ_FLAGS_RLS (1 << 0)
941 #define PQ_FLAGS_MCOS (1 << 1)
942 #define PQ_FLAGS_LB (1 << 2)
943 #define PQ_FLAGS_OOO (1 << 3)
944 #define PQ_FLAGS_ACK (1 << 4)
945 #define PQ_FLAGS_OFLD (1 << 5)
946 #define PQ_FLAGS_VFS (1 << 6)
947 #define PQ_FLAGS_LLT (1 << 7)
949 /* physical queue index for cm context intialization */
950 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
951 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
952 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
953 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
955 /* qm vport for rate limit configuration */
956 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
958 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
960 /* doorbell recovery mechanism */
961 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
962 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
963 enum ecore_db_rec_exec);
965 /* amount of resources used in qm init */
966 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
967 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
968 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
969 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
970 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
972 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
974 #endif /* __ECORE_H */