2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
17 #define CONFIG_ECORE_BINARY_FW
18 #define CONFIG_ECORE_ZIPPED_FW
20 #ifdef CONFIG_ECORE_ZIPPED_FW
24 #include "ecore_hsi_common.h"
25 #include "ecore_hsi_debug_tools.h"
26 #include "ecore_hsi_init_func.h"
27 #include "ecore_hsi_init_tool.h"
28 #include "ecore_proto_if.h"
29 #include "mcp_public.h"
31 #define MAX_HWFNS_PER_DEVICE (4)
32 #define NAME_SIZE 64 /* @DPDK */
34 /* @DPDK ARRAY_DECL */
35 #define ECORE_WFQ_UNIT 100
36 #include "../qede_logs.h" /* @DPDK */
39 #define ECORE_WID_SIZE (1024)
42 #define ECORE_PF_DEMS_SIZE (4)
45 enum ecore_coalescing_mode {
46 ECORE_COAL_MODE_DISABLE,
47 ECORE_COAL_MODE_ENABLE
51 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
52 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
53 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
54 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
55 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
56 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
57 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
58 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
59 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
60 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
61 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
65 #if !defined(CONFIG_ECORE_L2)
66 #define CONFIG_ECORE_L2
67 #define CONFIG_ECORE_SRIOV
72 #ifndef __EXTRACT__LINUX__
73 #define MASK_FIELD(_name, _value) \
74 ((_value) &= (_name##_MASK))
76 #define FIELD_VALUE(_name, _value) \
77 ((_value & _name##_MASK) << _name##_SHIFT)
79 #define SET_FIELD(value, name, flag) \
81 (value) &= ~(name##_MASK << name##_SHIFT); \
82 (value) |= (((u64)flag) << (name##_SHIFT)); \
85 #define GET_FIELD(value, name) \
86 (((value) >> (name##_SHIFT)) & name##_MASK)
89 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
91 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
92 (cid * ECORE_PF_DEMS_SIZE);
97 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
99 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
100 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
105 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
106 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
107 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
111 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
115 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
119 #ifndef __EXTRACT__LINUX__
121 ECORE_LEVEL_VERBOSE = 0x0,
122 ECORE_LEVEL_INFO = 0x1,
123 ECORE_LEVEL_NOTICE = 0x2,
124 ECORE_LEVEL_ERR = 0x3,
127 #define ECORE_LOG_LEVEL_SHIFT (30)
128 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
129 #define ECORE_LOG_INFO_MASK (0x40000000)
130 #define ECORE_LOG_NOTICE_MASK (0x80000000)
134 ECORE_MSG_DRV = 0x0001,
135 ECORE_MSG_PROBE = 0x0002,
136 ECORE_MSG_LINK = 0x0004,
137 ECORE_MSG_TIMER = 0x0008,
138 ECORE_MSG_IFDOWN = 0x0010,
139 ECORE_MSG_IFUP = 0x0020,
140 ECORE_MSG_RX_ERR = 0x0040,
141 ECORE_MSG_TX_ERR = 0x0080,
142 ECORE_MSG_TX_QUEUED = 0x0100,
143 ECORE_MSG_INTR = 0x0200,
144 ECORE_MSG_TX_DONE = 0x0400,
145 ECORE_MSG_RX_STATUS = 0x0800,
146 ECORE_MSG_PKTDATA = 0x1000,
147 ECORE_MSG_HW = 0x2000,
148 ECORE_MSG_WOL = 0x4000,
150 ECORE_MSG_SPQ = 0x10000,
151 ECORE_MSG_STATS = 0x20000,
152 ECORE_MSG_DCB = 0x40000,
153 ECORE_MSG_IOV = 0x80000,
154 ECORE_MSG_SP = 0x100000,
155 ECORE_MSG_STORAGE = 0x200000,
156 ECORE_MSG_CXT = 0x800000,
157 ECORE_MSG_ILT = 0x2000000,
158 ECORE_MSG_DEBUG = 0x8000000,
159 /* to be added...up to 0x8000000 */
163 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
165 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
166 (val == (cond1) ? true1 : \
167 (val == (cond2) ? true2 : def))
170 struct ecore_ptt_pool;
172 struct ecore_sb_info;
173 struct ecore_sb_attn_info;
174 struct ecore_cxt_mngr;
175 struct ecore_dma_mem;
176 struct ecore_sb_sp_info;
177 struct ecore_igu_info;
178 struct ecore_mcp_info;
179 struct ecore_dcbx_info;
181 struct ecore_rt_data {
186 enum ecore_tunn_mode {
187 ECORE_MODE_L2GENEVE_TUNN,
188 ECORE_MODE_IPGENEVE_TUNN,
189 ECORE_MODE_L2GRE_TUNN,
190 ECORE_MODE_IPGRE_TUNN,
191 ECORE_MODE_VXLAN_TUNN,
194 enum ecore_tunn_clss {
195 ECORE_TUNN_CLSS_MAC_VLAN,
196 ECORE_TUNN_CLSS_MAC_VNI,
197 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
198 ECORE_TUNN_CLSS_INNER_MAC_VNI,
202 struct ecore_tunn_start_params {
203 unsigned long tunn_mode;
206 u8 update_vxlan_udp_port;
207 u8 update_geneve_udp_port;
209 u8 tunn_clss_l2geneve;
210 u8 tunn_clss_ipgeneve;
215 struct ecore_tunn_update_params {
216 unsigned long tunn_mode_update_mask;
217 unsigned long tunn_mode;
220 u8 update_rx_pf_clss;
221 u8 update_tx_pf_clss;
222 u8 update_vxlan_udp_port;
223 u8 update_geneve_udp_port;
225 u8 tunn_clss_l2geneve;
226 u8 tunn_clss_ipgeneve;
231 struct ecore_hw_sriov_info {
232 /* standard SRIOV capability fields, mostly for debugging */
233 int pos; /* capability position */
234 int nres; /* number of resources */
235 u32 cap; /* SR-IOV Capabilities */
236 u16 ctrl; /* SR-IOV Control */
237 u16 total_vfs; /* total VFs associated with the PF */
238 u16 num_vfs; /* number of vfs that have been started */
239 u64 active_vfs[3]; /* bitfield of active vfs */
240 #define ECORE_IS_VF_ACTIVE(_p_dev, _rel_vf_id) \
241 (!!(_p_dev->sriov_info.active_vfs[_rel_vf_id / 64] & \
242 (1ULL << (_rel_vf_id % 64))))
243 u16 initial_vfs; /* initial VFs associated with the PF */
244 u16 nr_virtfn; /* number of VFs available */
245 u16 offset; /* first VF Routing ID offset */
246 u16 stride; /* following VF stride */
247 u16 vf_device_id; /* VF device id */
248 u32 pgsz; /* page size for BAR alignment */
249 u8 link; /* Function Dependency Link */
251 bool b_hw_channel; /* Whether PF uses the HW-channel */
254 /* The PCI personality is not quite synonymous to protocol ID:
255 * 1. All personalities need CORE connections
256 * 2. The Ethernet personality may support also the RoCE protocol
258 enum ecore_pci_personality {
260 ECORE_PCI_DEFAULT /* default in shmem */
263 /* All VFs are symmetric, all counters are PF + all VFs */
264 struct ecore_qm_iids {
270 #define MAX_PF_PER_PORT 8
272 /*@@@TBD MK RESC: need to remove and use MCP interface instead */
273 /* HW / FW resources, output of features supported below, most information
274 * is received from MFW.
276 enum ECORE_RESOURCES {
290 /* Features that require resources, given as input to the resource management
291 * algorithm, the output are the resources above
302 enum ECORE_PORT_MODE {
303 ECORE_PORT_MODE_DE_2X40G,
304 ECORE_PORT_MODE_DE_2X50G,
305 ECORE_PORT_MODE_DE_1X100G,
306 ECORE_PORT_MODE_DE_4X10G_F,
307 ECORE_PORT_MODE_DE_4X10G_E,
308 ECORE_PORT_MODE_DE_4X20G,
309 ECORE_PORT_MODE_DE_1X40G,
310 ECORE_PORT_MODE_DE_2X25G,
311 ECORE_PORT_MODE_DE_1X25G
318 #ifndef __EXTRACT__LINUX__
319 enum ecore_hw_err_type {
320 ECORE_HW_ERR_FAN_FAIL,
321 ECORE_HW_ERR_MFW_RESP_FAIL,
322 ECORE_HW_ERR_HW_ATTN,
323 ECORE_HW_ERR_DMAE_FAIL,
324 ECORE_HW_ERR_RAMROD_FAIL,
325 ECORE_HW_ERR_FW_ASSERT,
329 struct ecore_hw_info {
330 /* PCI personality */
331 enum ecore_pci_personality personality;
333 /* Resource Allocation scheme results */
334 u32 resc_start[ECORE_MAX_RESC];
335 u32 resc_num[ECORE_MAX_RESC];
336 u32 feat_num[ECORE_MAX_FEATURES];
338 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
339 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
340 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
341 RESC_NUM(_p_hwfn, resc))
342 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
354 unsigned char hw_mac_addr[ETH_ALEN];
356 struct ecore_igu_info *p_igu_info;
359 u8 max_chains_per_vf;
363 unsigned long device_capabilities;
366 struct ecore_hw_cid_data {
368 bool b_cid_allocated;
369 u8 vfid; /* 1-based; 0 signals this is for a PF */
371 /* Additional identifiers */
376 /* maximun size of read/write commands (HW limit) */
377 #define DMAE_MAX_RW_SIZE 0x2000
379 struct ecore_dmae_info {
380 /* Mutex for synchronizing access to functions */
385 dma_addr_t completion_word_phys_addr;
387 /* The memory location where the DMAE writes the completion
388 * value when an operation is finished on this context.
390 u32 *p_completion_word;
392 dma_addr_t intermediate_buffer_phys_addr;
394 /* An intermediate buffer for DMAE operations that use virtual
395 * addresses - data is DMA'd to/from this buffer and then
396 * memcpy'd to/from the virtual address
398 u32 *p_intermediate_buffer;
400 dma_addr_t dmae_cmd_phys_addr;
401 struct dmae_cmd *p_dmae_cmd;
404 struct ecore_wfq_data {
405 u32 default_min_speed; /* When wfq feature is not configured */
406 u32 min_speed; /* when feature is configured for any 1 vport */
410 struct ecore_qm_info {
411 struct init_qm_pq_params *qm_pq_params;
412 struct init_qm_vport_params *qm_vport_params;
413 struct init_qm_port_params *qm_port_params;
424 u8 max_phys_tcs_per_port;
431 struct ecore_wfq_data *wfq_data;
439 struct ecore_fw_data {
440 #ifdef CONFIG_ECORE_BINARY_FW
441 struct fw_ver_info *fw_ver_info;
443 const u8 *modes_tree_buf;
444 union init_op *init_ops;
450 struct ecore_dev *p_dev;
451 u8 my_id; /* ID inside the PF */
452 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
453 u8 rel_pf_id; /* Relative to engine*/
455 #define ECORE_PATH_ID(_p_hwfn) \
456 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
462 char name[NAME_SIZE];
465 bool first_on_engine;
468 u8 num_funcs_on_engine;
471 void OSAL_IOMEM *regview;
472 void OSAL_IOMEM *doorbells;
474 unsigned long db_size;
477 struct ecore_ptt_pool *p_ptt_pool;
480 struct ecore_hw_info hw_info;
482 /* rt_array (for init-tool) */
483 struct ecore_rt_data rt_data;
486 struct ecore_spq *p_spq;
489 struct ecore_eq *p_eq;
492 struct ecore_consq *p_consq;
494 /* Slow-Path definitions */
496 bool b_sp_dpc_enabled;
498 struct ecore_ptt *p_main_ptt;
499 struct ecore_ptt *p_dpc_ptt;
501 struct ecore_sb_sp_info *p_sp_sb;
502 struct ecore_sb_attn_info *p_sb_attn;
504 /* Protocol related */
505 struct ecore_ooo_info *p_ooo_info;
506 struct ecore_pf_params pf_params;
508 /* Array of sb_info of all status blocks */
509 struct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
512 struct ecore_cxt_mngr *p_cxt_mngr;
514 /* Flag indicating whether interrupts are enabled or not*/
516 bool b_int_requested;
518 /* True if the driver requests for the link */
519 bool b_drv_link_init;
521 struct ecore_vf_iov *vf_iov_info;
522 struct ecore_pf_iov *pf_iov_info;
523 struct ecore_mcp_info *mcp_info;
524 struct ecore_dcbx_info *p_dcbx_info;
526 struct ecore_hw_cid_data *p_tx_cids;
527 struct ecore_hw_cid_data *p_rx_cids;
529 struct ecore_dmae_info dmae_info;
532 struct ecore_qm_info qm_info;
534 #ifdef CONFIG_ECORE_ZIPPED_FW
535 /* Buffer for unzipping firmware data */
539 struct dbg_tools_data dbg_info;
541 struct z_stream_s *stream;
543 /* PWM region specific data */
546 u32 dpi_start_offset; /* this is used to
552 #ifndef __EXTRACT__LINUX__
563 char name[NAME_SIZE];
567 #define ECORE_DEV_TYPE_BB (0 << 0)
568 #define ECORE_DEV_TYPE_AH (1 << 0)
569 /* Translate type/revision combo into the proper conditions */
570 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
571 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
573 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
574 (CHIP_REV_IS_TEDIBEAR(dev)))
576 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
578 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
579 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
585 #define CHIP_NUM_MASK 0xffff
586 #define CHIP_NUM_SHIFT 16
589 #define CHIP_REV_MASK 0xf
590 #define CHIP_REV_SHIFT 12
592 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
593 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
594 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
595 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
596 CHIP_REV_IS_EMUL_B0(_p_dev))
597 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
598 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
599 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
600 CHIP_REV_IS_FPGA_B0(_p_dev))
601 #define CHIP_REV_IS_SLOW(_p_dev) \
602 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
603 #define CHIP_REV_IS_A0(_p_dev) \
604 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
605 CHIP_REV_IS_FPGA_A0(_p_dev) || \
607 #define CHIP_REV_IS_B0(_p_dev) \
608 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
609 CHIP_REV_IS_FPGA_B0(_p_dev) || \
610 (_p_dev)->chip_rev == 1)
611 #define CHIP_REV_IS_ASIC(_p_dev) (!CHIP_REV_IS_SLOW(_p_dev))
613 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev)
614 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1)
618 #define CHIP_METAL_MASK 0xff
619 #define CHIP_METAL_SHIFT 4
622 #define CHIP_BOND_ID_MASK 0xf
623 #define CHIP_BOND_ID_SHIFT 0
626 u8 num_ports_in_engines;
627 u8 num_funcs_in_port;
630 enum ecore_mf_mode mf_mode;
631 #define IS_MF_DEFAULT(_p_hwfn) \
632 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
633 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
634 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
638 u8 ver_str[VER_SIZE];
639 /* Add MF related configuration */
646 enum ecore_coalescing_mode int_coalescing_mode;
647 u8 rx_coalesce_usecs;
648 u8 tx_coalesce_usecs;
650 /* Start Bar offset of first hwfn */
651 void OSAL_IOMEM *regview;
652 void OSAL_IOMEM *doorbells;
654 unsigned long db_size;
660 const struct iro *iro_arr;
661 #define IRO (p_hwfn->p_dev->iro_arr)
665 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
668 struct ecore_hw_sriov_info sriov_info;
669 unsigned long tunn_mode;
670 #define IS_ECORE_SRIOV(edev) (!!((edev)->sriov_info.total_vfs))
675 struct ecore_eth_stats *reset_stats;
676 struct ecore_fw_data *fw_data;
687 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
694 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
696 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
697 : MAX_NUM_L2_QUEUES_K2)
698 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
700 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
701 : MAX_SB_PER_PATH_K2)
702 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
705 #define ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn) ( \
706 (ECORE_IS_BB_A0(p_hwfn->p_dev)) && \
707 (ECORE_PATH_ID(p_hwfn) == 1) && \
708 ((p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X40G) || \
709 (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X50G) || \
710 (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X25G)))
713 * @brief ecore_concrete_to_sw_fid - get the sw function id from
714 * the concrete value.
716 * @param concrete_fid
718 * @return OSAL_INLINE u8
720 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
723 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
724 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
725 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
729 sw_fid = vfid + MAX_NUM_PFS;
739 static OSAL_INLINE u16 ecore_sriov_get_next_vf(struct ecore_hwfn *p_hwfn,
744 for (i = rel_vf_id; i < p_hwfn->p_dev->sriov_info.total_vfs; i++)
745 if (ECORE_IS_VF_ACTIVE(p_hwfn->p_dev, i))
748 return p_hwfn->p_dev->sriov_info.total_vfs;
751 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
752 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
755 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
756 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
757 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
758 int ecore_device_num_engines(struct ecore_dev *p_dev);
759 int ecore_device_num_ports(struct ecore_dev *p_dev);
761 #define ecore_for_each_vf(_p_hwfn, _i) \
762 for (_i = ecore_sriov_get_next_vf(_p_hwfn, 0); \
763 _i < _p_hwfn->p_dev->sriov_info.total_vfs; \
764 _i = ecore_sriov_get_next_vf(_p_hwfn, _i + 1))
766 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
768 #endif /* __ECORE_H */