2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
17 #define CONFIG_ECORE_BINARY_FW
18 #undef CONFIG_ECORE_ZIPPED_FW
20 #ifdef CONFIG_ECORE_ZIPPED_FW
24 #include "ecore_hsi_common.h"
25 #include "ecore_hsi_debug_tools.h"
26 #include "ecore_hsi_init_func.h"
27 #include "ecore_hsi_init_tool.h"
28 #include "ecore_proto_if.h"
29 #include "mcp_public.h"
31 #define ECORE_MAJOR_VERSION 8
32 #define ECORE_MINOR_VERSION 18
33 #define ECORE_REVISION_VERSION 7
34 #define ECORE_ENGINEERING_VERSION 1
36 #define ECORE_VERSION \
37 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \
38 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
40 #define STORM_FW_VERSION \
41 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
42 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
44 #define MAX_HWFNS_PER_DEVICE 2
45 #define NAME_SIZE 128 /* @DPDK */
46 #define ECORE_WFQ_UNIT 100
47 #include "../qede_logs.h" /* @DPDK */
49 #define ISCSI_BDQ_ID(_port_id) (_port_id)
50 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
52 #define ECORE_WID_SIZE (1024)
55 #define ECORE_PF_DEMS_SIZE (4)
58 enum ecore_coalescing_mode {
59 ECORE_COAL_MODE_DISABLE,
60 ECORE_COAL_MODE_ENABLE
64 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
65 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
66 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
67 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
68 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
69 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
70 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
71 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
72 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
73 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
74 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
75 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
79 #if !defined(CONFIG_ECORE_L2)
80 #define CONFIG_ECORE_L2
81 #define CONFIG_ECORE_SRIOV
86 #ifndef __EXTRACT__LINUX__
87 #define MASK_FIELD(_name, _value) \
88 ((_value) &= (_name##_MASK))
90 #define FIELD_VALUE(_name, _value) \
91 ((_value & _name##_MASK) << _name##_SHIFT)
93 #define SET_FIELD(value, name, flag) \
95 (value) &= ~(name##_MASK << name##_SHIFT); \
96 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
99 #define GET_FIELD(value, name) \
100 (((value) >> (name##_SHIFT)) & name##_MASK)
102 #define GET_MFW_FIELD(name, field) \
103 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
105 #define SET_MFW_FIELD(name, field, value) \
107 (name) &= ~((field ## _MASK)); \
108 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
112 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
114 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
115 (cid * ECORE_PF_DEMS_SIZE);
120 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
122 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
123 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
128 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
129 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
130 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
134 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
138 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
142 #ifndef __EXTRACT__LINUX__
144 ECORE_LEVEL_VERBOSE = 0x0,
145 ECORE_LEVEL_INFO = 0x1,
146 ECORE_LEVEL_NOTICE = 0x2,
147 ECORE_LEVEL_ERR = 0x3,
150 #define ECORE_LOG_LEVEL_SHIFT (30)
151 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
152 #define ECORE_LOG_INFO_MASK (0x40000000)
153 #define ECORE_LOG_NOTICE_MASK (0x80000000)
157 ECORE_MSG_DRV = 0x0001,
158 ECORE_MSG_PROBE = 0x0002,
159 ECORE_MSG_LINK = 0x0004,
160 ECORE_MSG_TIMER = 0x0008,
161 ECORE_MSG_IFDOWN = 0x0010,
162 ECORE_MSG_IFUP = 0x0020,
163 ECORE_MSG_RX_ERR = 0x0040,
164 ECORE_MSG_TX_ERR = 0x0080,
165 ECORE_MSG_TX_QUEUED = 0x0100,
166 ECORE_MSG_INTR = 0x0200,
167 ECORE_MSG_TX_DONE = 0x0400,
168 ECORE_MSG_RX_STATUS = 0x0800,
169 ECORE_MSG_PKTDATA = 0x1000,
170 ECORE_MSG_HW = 0x2000,
171 ECORE_MSG_WOL = 0x4000,
173 ECORE_MSG_SPQ = 0x10000,
174 ECORE_MSG_STATS = 0x20000,
175 ECORE_MSG_DCB = 0x40000,
176 ECORE_MSG_IOV = 0x80000,
177 ECORE_MSG_SP = 0x100000,
178 ECORE_MSG_STORAGE = 0x200000,
179 ECORE_MSG_OOO = 0x200000,
180 ECORE_MSG_CXT = 0x800000,
181 ECORE_MSG_LL2 = 0x1000000,
182 ECORE_MSG_ILT = 0x2000000,
183 ECORE_MSG_RDMA = 0x4000000,
184 ECORE_MSG_DEBUG = 0x8000000,
185 /* to be added...up to 0x8000000 */
189 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
191 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
192 (val == (cond1) ? true1 : \
193 (val == (cond2) ? true2 : def))
196 struct ecore_ptt_pool;
198 struct ecore_sb_info;
199 struct ecore_sb_attn_info;
200 struct ecore_cxt_mngr;
201 struct ecore_dma_mem;
202 struct ecore_sb_sp_info;
203 struct ecore_ll2_info;
204 struct ecore_l2_info;
205 struct ecore_igu_info;
206 struct ecore_mcp_info;
207 struct ecore_dcbx_info;
209 struct ecore_rt_data {
214 enum ecore_tunn_mode {
215 ECORE_MODE_L2GENEVE_TUNN,
216 ECORE_MODE_IPGENEVE_TUNN,
217 ECORE_MODE_L2GRE_TUNN,
218 ECORE_MODE_IPGRE_TUNN,
219 ECORE_MODE_VXLAN_TUNN,
222 enum ecore_tunn_clss {
223 ECORE_TUNN_CLSS_MAC_VLAN,
224 ECORE_TUNN_CLSS_MAC_VNI,
225 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
226 ECORE_TUNN_CLSS_INNER_MAC_VNI,
227 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
231 struct ecore_tunn_update_type {
234 enum ecore_tunn_clss tun_cls;
237 struct ecore_tunn_update_udp_port {
242 struct ecore_tunnel_info {
243 struct ecore_tunn_update_type vxlan;
244 struct ecore_tunn_update_type l2_geneve;
245 struct ecore_tunn_update_type ip_geneve;
246 struct ecore_tunn_update_type l2_gre;
247 struct ecore_tunn_update_type ip_gre;
249 struct ecore_tunn_update_udp_port vxlan_port;
250 struct ecore_tunn_update_udp_port geneve_port;
252 bool b_update_rx_cls;
253 bool b_update_tx_cls;
256 /* The PCI personality is not quite synonymous to protocol ID:
257 * 1. All personalities need CORE connections
258 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
260 enum ecore_pci_personality {
267 ECORE_PCI_DEFAULT /* default in shmem */
270 /* All VFs are symmetric, all counters are PF + all VFs */
271 struct ecore_qm_iids {
277 #define MAX_PF_PER_PORT 8
279 /* HW / FW resources, output of features supported below, most information
280 * is received from MFW.
282 enum ecore_resources {
294 ECORE_RDMA_STATS_QUEUE,
297 /* This is needed only internally for matching against the IGU.
298 * In case of legacy MFW, would be set to `0'.
305 /* Features that require resources, given as input to the resource management
306 * algorithm, the output are the resources above
321 enum ecore_port_mode {
322 ECORE_PORT_MODE_DE_2X40G,
323 ECORE_PORT_MODE_DE_2X50G,
324 ECORE_PORT_MODE_DE_1X100G,
325 ECORE_PORT_MODE_DE_4X10G_F,
326 ECORE_PORT_MODE_DE_4X10G_E,
327 ECORE_PORT_MODE_DE_4X20G,
328 ECORE_PORT_MODE_DE_1X40G,
329 ECORE_PORT_MODE_DE_2X25G,
330 ECORE_PORT_MODE_DE_1X25G,
331 ECORE_PORT_MODE_DE_4X25G,
332 ECORE_PORT_MODE_DE_2X10G,
343 #ifndef __EXTRACT__LINUX__
344 enum ecore_hw_err_type {
345 ECORE_HW_ERR_FAN_FAIL,
346 ECORE_HW_ERR_MFW_RESP_FAIL,
347 ECORE_HW_ERR_HW_ATTN,
348 ECORE_HW_ERR_DMAE_FAIL,
349 ECORE_HW_ERR_RAMROD_FAIL,
350 ECORE_HW_ERR_FW_ASSERT,
354 enum ecore_db_rec_exec {
360 struct ecore_hw_info {
361 /* PCI personality */
362 enum ecore_pci_personality personality;
363 #define ECORE_IS_RDMA_PERSONALITY(dev) \
364 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
365 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
366 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
367 #define ECORE_IS_ROCE_PERSONALITY(dev) \
368 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
369 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
370 #define ECORE_IS_IWARP_PERSONALITY(dev) \
371 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
372 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
373 #define ECORE_IS_L2_PERSONALITY(dev) \
374 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
375 ECORE_IS_RDMA_PERSONALITY(dev))
377 /* Resource Allocation scheme results */
378 u32 resc_start[ECORE_MAX_RESC];
379 u32 resc_num[ECORE_MAX_RESC];
380 u32 feat_num[ECORE_MAX_FEATURES];
382 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
383 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
384 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
385 RESC_NUM(_p_hwfn, resc))
386 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
388 /* Amount of traffic classes HW supports */
391 /* Amount of TCs which should be active according to DCBx or upper layer driver
397 /* The traffic class used by PF for it's offloaded protocol */
405 unsigned char hw_mac_addr[ETH_ALEN];
406 u64 node_wwn; /* For FCoE only */
407 u64 port_wwn; /* For FCoE only */
412 struct ecore_igu_info *p_igu_info;
414 u8 max_chains_per_vf;
418 unsigned long device_capabilities;
420 /* Default DCBX mode */
426 /* maximun size of read/write commands (HW limit) */
427 #define DMAE_MAX_RW_SIZE 0x2000
429 struct ecore_dmae_info {
430 /* Mutex for synchronizing access to functions */
435 dma_addr_t completion_word_phys_addr;
437 /* The memory location where the DMAE writes the completion
438 * value when an operation is finished on this context.
440 u32 *p_completion_word;
442 dma_addr_t intermediate_buffer_phys_addr;
444 /* An intermediate buffer for DMAE operations that use virtual
445 * addresses - data is DMA'd to/from this buffer and then
446 * memcpy'd to/from the virtual address
448 u32 *p_intermediate_buffer;
450 dma_addr_t dmae_cmd_phys_addr;
451 struct dmae_cmd *p_dmae_cmd;
454 struct ecore_wfq_data {
455 u32 default_min_speed; /* When wfq feature is not configured */
456 u32 min_speed; /* when feature is configured for any 1 vport */
460 struct ecore_qm_info {
461 struct init_qm_pq_params *qm_pq_params;
462 struct init_qm_vport_params *qm_vport_params;
463 struct init_qm_port_params *qm_port_params;
476 u8 max_phys_tcs_per_port;
484 struct ecore_wfq_data *wfq_data;
488 struct ecore_db_recovery_info {
490 osal_spinlock_t lock;
491 u32 db_recovery_counter;
499 struct ecore_fw_data {
500 #ifdef CONFIG_ECORE_BINARY_FW
501 struct fw_ver_info *fw_ver_info;
503 const u8 *modes_tree_buf;
504 union init_op *init_ops;
510 struct ecore_dev *p_dev;
511 u8 my_id; /* ID inside the PF */
512 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
513 u8 rel_pf_id; /* Relative to engine*/
515 #define ECORE_PATH_ID(_p_hwfn) \
516 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
522 char name[NAME_SIZE];
525 bool first_on_engine;
528 u8 num_funcs_on_engine;
532 void OSAL_IOMEM *regview;
533 void OSAL_IOMEM *doorbells;
535 unsigned long db_size;
538 struct ecore_ptt_pool *p_ptt_pool;
541 struct ecore_hw_info hw_info;
543 /* rt_array (for init-tool) */
544 struct ecore_rt_data rt_data;
547 struct ecore_spq *p_spq;
550 struct ecore_eq *p_eq;
553 struct ecore_consq *p_consq;
555 /* Slow-Path definitions */
557 bool b_sp_dpc_enabled;
559 struct ecore_ptt *p_main_ptt;
560 struct ecore_ptt *p_dpc_ptt;
562 struct ecore_sb_sp_info *p_sp_sb;
563 struct ecore_sb_attn_info *p_sb_attn;
565 /* Protocol related */
567 struct ecore_ll2_info *p_ll2_info;
568 struct ecore_ooo_info *p_ooo_info;
569 struct ecore_iscsi_info *p_iscsi_info;
570 struct ecore_fcoe_info *p_fcoe_info;
571 struct ecore_rdma_info *p_rdma_info;
572 struct ecore_pf_params pf_params;
574 bool b_rdma_enabled_in_prs;
575 u32 rdma_prs_search_reg;
577 struct ecore_cxt_mngr *p_cxt_mngr;
579 /* Flag indicating whether interrupts are enabled or not*/
581 bool b_int_requested;
583 /* True if the driver requests for the link */
584 bool b_drv_link_init;
586 struct ecore_vf_iov *vf_iov_info;
587 struct ecore_pf_iov *pf_iov_info;
588 struct ecore_mcp_info *mcp_info;
589 struct ecore_dcbx_info *p_dcbx_info;
591 struct ecore_dmae_info dmae_info;
594 struct ecore_qm_info qm_info;
596 #ifdef CONFIG_ECORE_ZIPPED_FW
597 /* Buffer for unzipping firmware data */
601 struct dbg_tools_data dbg_info;
603 struct z_stream_s *stream;
605 /* PWM region specific data */
608 u32 dpi_start_offset; /* this is used to
613 /* If one of the following is set then EDPM shouldn't be used */
618 struct ecore_l2_info *p_l2_info;
620 /* Mechanism for recovering from doorbell drop */
621 struct ecore_db_recovery_info db_recovery_info;
624 struct ecore_ptt *p_arfs_ptt;
627 #ifndef __EXTRACT__LINUX__
636 struct ecore_dbg_feature {
642 enum qed_dbg_features {
645 DBG_FEATURE_IDLE_CHK,
646 DBG_FEATURE_MCP_TRACE,
647 DBG_FEATURE_REG_FIFO,
648 DBG_FEATURE_PROTECTION_OVERRIDE,
652 enum ecore_dev_type {
660 char name[NAME_SIZE];
663 enum ecore_dev_type type;
664 /* Translate type/revision combo into the proper conditions */
665 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
666 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
668 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
669 (CHIP_REV_IS_TEDIBEAR(dev)))
671 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
673 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
674 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
678 #define ECORE_DEV_ID_MASK 0xff00
679 #define ECORE_DEV_ID_MASK_BB 0x1600
680 #define ECORE_DEV_ID_MASK_AH 0x8000
683 #define CHIP_NUM_MASK 0xffff
684 #define CHIP_NUM_SHIFT 0
687 #define CHIP_REV_MASK 0xf
688 #define CHIP_REV_SHIFT 0
690 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
691 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
692 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
693 #define CHIP_REV_IS_EMUL(_p_dev) \
694 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
695 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
696 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
697 #define CHIP_REV_IS_FPGA(_p_dev) \
698 (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
699 #define CHIP_REV_IS_SLOW(_p_dev) \
700 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
701 #define CHIP_REV_IS_A0(_p_dev) \
702 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
703 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
704 #define CHIP_REV_IS_B0(_p_dev) \
705 (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
706 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
707 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
709 #define CHIP_REV_IS_A0(_p_dev) \
710 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
711 #define CHIP_REV_IS_B0(_p_dev) \
712 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
716 #define CHIP_METAL_MASK 0xff
717 #define CHIP_METAL_SHIFT 0
720 #define CHIP_BOND_ID_MASK 0xff
721 #define CHIP_BOND_ID_SHIFT 0
725 u8 num_ports_in_engine;
726 u8 num_funcs_in_port;
729 enum ecore_mf_mode mf_mode;
730 #define IS_MF_DEFAULT(_p_hwfn) \
731 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
732 #define IS_MF_SI(_p_hwfn) \
733 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
734 #define IS_MF_SD(_p_hwfn) \
735 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
740 /* Add MF related configuration */
747 enum ecore_coalescing_mode int_coalescing_mode;
748 u16 rx_coalesce_usecs;
749 u16 tx_coalesce_usecs;
751 /* Start Bar offset of first hwfn */
752 void OSAL_IOMEM *regview;
753 void OSAL_IOMEM *doorbells;
755 unsigned long db_size;
761 const struct iro *iro_arr;
762 #define IRO (p_hwfn->p_dev->iro_arr)
766 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
769 struct ecore_hw_sriov_info *p_iov_info;
770 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
771 struct ecore_tunnel_info tunnel;
773 bool b_dont_override_vf_msix;
779 u32 rdma_max_srq_sge;
781 struct ecore_eth_stats *reset_stats;
782 struct ecore_fw_data *fw_data;
789 /* Indicates whether should prevent attentions from being reasserted */
793 /* Indicates whether allowing the MFW to collect a crash dump */
796 /* Indicates if the reg_fifo is checked after any register access */
803 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
809 struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
813 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
815 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
816 : MAX_NUM_L2_QUEUES_K2)
817 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
819 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
820 : MAX_SB_PER_PATH_K2)
821 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
825 * @brief ecore_concrete_to_sw_fid - get the sw function id from
826 * the concrete value.
828 * @param concrete_fid
830 * @return OSAL_INLINE u8
832 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
834 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
835 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
836 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
840 sw_fid = vfid + MAX_NUM_PFS;
850 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
851 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
852 struct ecore_ptt *p_ptt,
855 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
856 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
857 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
858 int ecore_device_num_engines(struct ecore_dev *p_dev);
859 int ecore_device_num_ports(struct ecore_dev *p_dev);
860 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
863 /* Flags for indication of required queues */
864 #define PQ_FLAGS_RLS (1 << 0)
865 #define PQ_FLAGS_MCOS (1 << 1)
866 #define PQ_FLAGS_LB (1 << 2)
867 #define PQ_FLAGS_OOO (1 << 3)
868 #define PQ_FLAGS_ACK (1 << 4)
869 #define PQ_FLAGS_OFLD (1 << 5)
870 #define PQ_FLAGS_VFS (1 << 6)
872 /* physical queue index for cm context intialization */
873 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
874 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
875 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
876 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
878 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
880 /* doorbell recovery mechanism */
881 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
882 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
883 enum ecore_db_rec_exec);
885 /* amount of resources used in qm init */
886 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
887 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
888 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
889 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
890 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
892 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
894 #endif /* __ECORE_H */