2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
17 #define CONFIG_ECORE_BINARY_FW
18 #undef CONFIG_ECORE_ZIPPED_FW
20 #ifdef CONFIG_ECORE_ZIPPED_FW
24 #include "ecore_hsi_common.h"
25 #include "ecore_hsi_debug_tools.h"
26 #include "ecore_hsi_init_func.h"
27 #include "ecore_hsi_init_tool.h"
28 #include "ecore_proto_if.h"
29 #include "mcp_public.h"
31 #define MAX_HWFNS_PER_DEVICE 2
32 #define NAME_SIZE 128 /* @DPDK */
33 #define ECORE_WFQ_UNIT 100
34 #include "../qede_logs.h" /* @DPDK */
36 #define ISCSI_BDQ_ID(_port_id) (_port_id)
37 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
39 #define ECORE_WID_SIZE (1024)
42 #define ECORE_PF_DEMS_SIZE (4)
45 enum ecore_coalescing_mode {
46 ECORE_COAL_MODE_DISABLE,
47 ECORE_COAL_MODE_ENABLE
51 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
52 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
53 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
54 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
55 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
56 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
57 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
58 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
59 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
60 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
61 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
65 #if !defined(CONFIG_ECORE_L2)
66 #define CONFIG_ECORE_L2
67 #define CONFIG_ECORE_SRIOV
72 #ifndef __EXTRACT__LINUX__
73 #define MASK_FIELD(_name, _value) \
74 ((_value) &= (_name##_MASK))
76 #define FIELD_VALUE(_name, _value) \
77 ((_value & _name##_MASK) << _name##_SHIFT)
79 #define SET_FIELD(value, name, flag) \
81 (value) &= ~(name##_MASK << name##_SHIFT); \
82 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
85 #define GET_FIELD(value, name) \
86 (((value) >> (name##_SHIFT)) & name##_MASK)
89 #define ECORE_MFW_GET_FIELD(name, field) \
90 (((name) & (field ## _MASK)) >> (field ## _SHIFT))
92 #define ECORE_MFW_SET_FIELD(name, field, value) \
94 (name) &= ~((field ## _MASK) << (field ## _SHIFT)); \
95 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK)); \
98 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
100 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
101 (cid * ECORE_PF_DEMS_SIZE);
106 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
108 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
109 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
114 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
115 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
116 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
120 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
124 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
128 #ifndef __EXTRACT__LINUX__
130 ECORE_LEVEL_VERBOSE = 0x0,
131 ECORE_LEVEL_INFO = 0x1,
132 ECORE_LEVEL_NOTICE = 0x2,
133 ECORE_LEVEL_ERR = 0x3,
136 #define ECORE_LOG_LEVEL_SHIFT (30)
137 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
138 #define ECORE_LOG_INFO_MASK (0x40000000)
139 #define ECORE_LOG_NOTICE_MASK (0x80000000)
143 ECORE_MSG_DRV = 0x0001,
144 ECORE_MSG_PROBE = 0x0002,
145 ECORE_MSG_LINK = 0x0004,
146 ECORE_MSG_TIMER = 0x0008,
147 ECORE_MSG_IFDOWN = 0x0010,
148 ECORE_MSG_IFUP = 0x0020,
149 ECORE_MSG_RX_ERR = 0x0040,
150 ECORE_MSG_TX_ERR = 0x0080,
151 ECORE_MSG_TX_QUEUED = 0x0100,
152 ECORE_MSG_INTR = 0x0200,
153 ECORE_MSG_TX_DONE = 0x0400,
154 ECORE_MSG_RX_STATUS = 0x0800,
155 ECORE_MSG_PKTDATA = 0x1000,
156 ECORE_MSG_HW = 0x2000,
157 ECORE_MSG_WOL = 0x4000,
159 ECORE_MSG_SPQ = 0x10000,
160 ECORE_MSG_STATS = 0x20000,
161 ECORE_MSG_DCB = 0x40000,
162 ECORE_MSG_IOV = 0x80000,
163 ECORE_MSG_SP = 0x100000,
164 ECORE_MSG_STORAGE = 0x200000,
165 ECORE_MSG_OOO = 0x200000,
166 ECORE_MSG_CXT = 0x800000,
167 ECORE_MSG_LL2 = 0x1000000,
168 ECORE_MSG_ILT = 0x2000000,
169 ECORE_MSG_RDMA = 0x4000000,
170 ECORE_MSG_DEBUG = 0x8000000,
171 /* to be added...up to 0x8000000 */
175 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
177 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
178 (val == (cond1) ? true1 : \
179 (val == (cond2) ? true2 : def))
182 struct ecore_ptt_pool;
184 struct ecore_sb_info;
185 struct ecore_sb_attn_info;
186 struct ecore_cxt_mngr;
187 struct ecore_dma_mem;
188 struct ecore_sb_sp_info;
189 struct ecore_ll2_info;
190 struct ecore_igu_info;
191 struct ecore_mcp_info;
192 struct ecore_dcbx_info;
194 struct ecore_rt_data {
199 enum ecore_tunn_mode {
200 ECORE_MODE_L2GENEVE_TUNN,
201 ECORE_MODE_IPGENEVE_TUNN,
202 ECORE_MODE_L2GRE_TUNN,
203 ECORE_MODE_IPGRE_TUNN,
204 ECORE_MODE_VXLAN_TUNN,
207 enum ecore_tunn_clss {
208 ECORE_TUNN_CLSS_MAC_VLAN,
209 ECORE_TUNN_CLSS_MAC_VNI,
210 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
211 ECORE_TUNN_CLSS_INNER_MAC_VNI,
212 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
216 struct ecore_tunn_update_type {
219 enum ecore_tunn_clss tun_cls;
222 struct ecore_tunn_update_udp_port {
227 struct ecore_tunnel_info {
228 struct ecore_tunn_update_type vxlan;
229 struct ecore_tunn_update_type l2_geneve;
230 struct ecore_tunn_update_type ip_geneve;
231 struct ecore_tunn_update_type l2_gre;
232 struct ecore_tunn_update_type ip_gre;
234 struct ecore_tunn_update_udp_port vxlan_port;
235 struct ecore_tunn_update_udp_port geneve_port;
237 bool b_update_rx_cls;
238 bool b_update_tx_cls;
241 /* The PCI personality is not quite synonymous to protocol ID:
242 * 1. All personalities need CORE connections
243 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
245 enum ecore_pci_personality {
252 ECORE_PCI_DEFAULT /* default in shmem */
255 /* All VFs are symmetric, all counters are PF + all VFs */
256 struct ecore_qm_iids {
262 #define MAX_PF_PER_PORT 8
264 /* HW / FW resources, output of features supported below, most information
265 * is received from MFW.
267 enum ecore_resources {
280 ECORE_RDMA_STATS_QUEUE,
281 ECORE_MAX_RESC, /* must be last */
284 /* Features that require resources, given as input to the resource management
285 * algorithm, the output are the resources above
300 enum ecore_port_mode {
301 ECORE_PORT_MODE_DE_2X40G,
302 ECORE_PORT_MODE_DE_2X50G,
303 ECORE_PORT_MODE_DE_1X100G,
304 ECORE_PORT_MODE_DE_4X10G_F,
305 ECORE_PORT_MODE_DE_4X10G_E,
306 ECORE_PORT_MODE_DE_4X20G,
307 ECORE_PORT_MODE_DE_1X40G,
308 ECORE_PORT_MODE_DE_2X25G,
309 ECORE_PORT_MODE_DE_1X25G,
310 ECORE_PORT_MODE_DE_4X25G,
311 ECORE_PORT_MODE_DE_2X10G,
322 #ifndef __EXTRACT__LINUX__
323 enum ecore_hw_err_type {
324 ECORE_HW_ERR_FAN_FAIL,
325 ECORE_HW_ERR_MFW_RESP_FAIL,
326 ECORE_HW_ERR_HW_ATTN,
327 ECORE_HW_ERR_DMAE_FAIL,
328 ECORE_HW_ERR_RAMROD_FAIL,
329 ECORE_HW_ERR_FW_ASSERT,
333 struct ecore_hw_info {
334 /* PCI personality */
335 enum ecore_pci_personality personality;
336 #define ECORE_IS_RDMA_PERSONALITY(dev) \
337 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
338 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
339 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
340 #define ECORE_IS_ROCE_PERSONALITY(dev) \
341 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
342 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
343 #define ECORE_IS_IWARP_PERSONALITY(dev) \
344 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
345 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
346 #define ECORE_IS_L2_PERSONALITY(dev) \
347 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
348 ECORE_IS_RDMA_PERSONALITY(dev))
350 /* Resource Allocation scheme results */
351 u32 resc_start[ECORE_MAX_RESC];
352 u32 resc_num[ECORE_MAX_RESC];
353 u32 feat_num[ECORE_MAX_FEATURES];
355 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
356 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
357 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
358 RESC_NUM(_p_hwfn, resc))
359 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
361 /* Amount of traffic classes HW supports */
364 /* Amount of TCs which should be active according to DCBx or upper layer driver
370 /* The traffic class used by PF for it's offloaded protocol */
378 unsigned char hw_mac_addr[ETH_ALEN];
379 u64 node_wwn; /* For FCoE only */
380 u64 port_wwn; /* For FCoE only */
385 struct ecore_igu_info *p_igu_info;
387 u8 max_chains_per_vf;
391 unsigned long device_capabilities;
393 /* Default DCBX mode */
399 /* maximun size of read/write commands (HW limit) */
400 #define DMAE_MAX_RW_SIZE 0x2000
402 struct ecore_dmae_info {
403 /* Mutex for synchronizing access to functions */
408 dma_addr_t completion_word_phys_addr;
410 /* The memory location where the DMAE writes the completion
411 * value when an operation is finished on this context.
413 u32 *p_completion_word;
415 dma_addr_t intermediate_buffer_phys_addr;
417 /* An intermediate buffer for DMAE operations that use virtual
418 * addresses - data is DMA'd to/from this buffer and then
419 * memcpy'd to/from the virtual address
421 u32 *p_intermediate_buffer;
423 dma_addr_t dmae_cmd_phys_addr;
424 struct dmae_cmd *p_dmae_cmd;
427 struct ecore_wfq_data {
428 u32 default_min_speed; /* When wfq feature is not configured */
429 u32 min_speed; /* when feature is configured for any 1 vport */
433 struct ecore_qm_info {
434 struct init_qm_pq_params *qm_pq_params;
435 struct init_qm_vport_params *qm_vport_params;
436 struct init_qm_port_params *qm_port_params;
449 u8 max_phys_tcs_per_port;
457 struct ecore_wfq_data *wfq_data;
466 struct ecore_fw_data {
467 #ifdef CONFIG_ECORE_BINARY_FW
468 struct fw_ver_info *fw_ver_info;
470 const u8 *modes_tree_buf;
471 union init_op *init_ops;
477 struct ecore_dev *p_dev;
478 u8 my_id; /* ID inside the PF */
479 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
480 u8 rel_pf_id; /* Relative to engine*/
482 #define ECORE_PATH_ID(_p_hwfn) \
483 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
489 char name[NAME_SIZE];
492 bool first_on_engine;
495 u8 num_funcs_on_engine;
499 void OSAL_IOMEM *regview;
500 void OSAL_IOMEM *doorbells;
502 unsigned long db_size;
505 struct ecore_ptt_pool *p_ptt_pool;
508 struct ecore_hw_info hw_info;
510 /* rt_array (for init-tool) */
511 struct ecore_rt_data rt_data;
514 struct ecore_spq *p_spq;
517 struct ecore_eq *p_eq;
520 struct ecore_consq *p_consq;
522 /* Slow-Path definitions */
524 bool b_sp_dpc_enabled;
526 struct ecore_ptt *p_main_ptt;
527 struct ecore_ptt *p_dpc_ptt;
529 struct ecore_sb_sp_info *p_sp_sb;
530 struct ecore_sb_attn_info *p_sb_attn;
532 /* Protocol related */
534 struct ecore_ll2_info *p_ll2_info;
535 struct ecore_ooo_info *p_ooo_info;
536 struct ecore_iscsi_info *p_iscsi_info;
537 struct ecore_fcoe_info *p_fcoe_info;
538 struct ecore_rdma_info *p_rdma_info;
539 struct ecore_pf_params pf_params;
541 bool b_rdma_enabled_in_prs;
542 u32 rdma_prs_search_reg;
544 /* Array of sb_info of all status blocks */
545 struct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
548 struct ecore_cxt_mngr *p_cxt_mngr;
550 /* Flag indicating whether interrupts are enabled or not*/
552 bool b_int_requested;
554 /* True if the driver requests for the link */
555 bool b_drv_link_init;
557 struct ecore_vf_iov *vf_iov_info;
558 struct ecore_pf_iov *pf_iov_info;
559 struct ecore_mcp_info *mcp_info;
560 struct ecore_dcbx_info *p_dcbx_info;
562 struct ecore_dmae_info dmae_info;
565 struct ecore_qm_info qm_info;
567 #ifdef CONFIG_ECORE_ZIPPED_FW
568 /* Buffer for unzipping firmware data */
572 struct dbg_tools_data dbg_info;
574 struct z_stream_s *stream;
576 /* PWM region specific data */
579 u32 dpi_start_offset; /* this is used to
584 /* If one of the following is set then EDPM shouldn't be used */
589 #ifndef __EXTRACT__LINUX__
598 struct ecore_dbg_feature {
604 enum qed_dbg_features {
607 DBG_FEATURE_IDLE_CHK,
608 DBG_FEATURE_MCP_TRACE,
609 DBG_FEATURE_REG_FIFO,
610 DBG_FEATURE_PROTECTION_OVERRIDE,
617 char name[NAME_SIZE];
621 #define ECORE_DEV_TYPE_BB (0 << 0)
622 #define ECORE_DEV_TYPE_AH (1 << 0)
623 /* Translate type/revision combo into the proper conditions */
624 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
625 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
627 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
628 (CHIP_REV_IS_TEDIBEAR(dev)))
630 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
632 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
633 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
635 #define ECORE_DEV_ID_MASK 0xff00
636 #define ECORE_DEV_ID_MASK_BB 0x1600
637 #define ECORE_DEV_ID_MASK_AH 0x8000
643 #define CHIP_NUM_MASK 0xffff
644 #define CHIP_NUM_SHIFT 16
647 #define CHIP_REV_MASK 0xf
648 #define CHIP_REV_SHIFT 12
650 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
651 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
652 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
653 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
654 CHIP_REV_IS_EMUL_B0(_p_dev))
655 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
656 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
657 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
658 CHIP_REV_IS_FPGA_B0(_p_dev))
659 #define CHIP_REV_IS_SLOW(_p_dev) \
660 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
661 #define CHIP_REV_IS_A0(_p_dev) \
662 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
663 CHIP_REV_IS_FPGA_A0(_p_dev) || \
665 #define CHIP_REV_IS_B0(_p_dev) \
666 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
667 CHIP_REV_IS_FPGA_B0(_p_dev) || \
668 (_p_dev)->chip_rev == 1)
669 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
671 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev)
672 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1)
676 #define CHIP_METAL_MASK 0xff
677 #define CHIP_METAL_SHIFT 4
680 #define CHIP_BOND_ID_MASK 0xf
681 #define CHIP_BOND_ID_SHIFT 0
684 u8 num_ports_in_engines;
685 u8 num_funcs_in_port;
688 enum ecore_mf_mode mf_mode;
689 #define IS_MF_DEFAULT(_p_hwfn) \
690 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
691 #define IS_MF_SI(_p_hwfn) \
692 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
693 #define IS_MF_SD(_p_hwfn) \
694 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
699 /* Add MF related configuration */
706 enum ecore_coalescing_mode int_coalescing_mode;
707 u16 rx_coalesce_usecs;
708 u16 tx_coalesce_usecs;
710 /* Start Bar offset of first hwfn */
711 void OSAL_IOMEM *regview;
712 void OSAL_IOMEM *doorbells;
714 unsigned long db_size;
720 const struct iro *iro_arr;
721 #define IRO (p_hwfn->p_dev->iro_arr)
725 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
728 struct ecore_hw_sriov_info *p_iov_info;
729 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
730 struct ecore_tunnel_info tunnel;
737 u32 rdma_max_srq_sge;
739 struct ecore_eth_stats *reset_stats;
740 struct ecore_fw_data *fw_data;
747 /* Indicates whether should prevent attentions from being reasserted */
751 /* Indicates whether allowing the MFW to collect a crash dump */
754 /* Indicates if the reg_fifo is checked after any register access */
761 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
767 struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
771 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
773 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
774 : MAX_NUM_L2_QUEUES_K2)
775 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
777 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
778 : MAX_SB_PER_PATH_K2)
779 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
783 * @brief ecore_concrete_to_sw_fid - get the sw function id from
784 * the concrete value.
786 * @param concrete_fid
788 * @return OSAL_INLINE u8
790 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
793 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
794 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
795 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
799 sw_fid = vfid + MAX_NUM_PFS;
809 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
810 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
813 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
814 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
815 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
816 int ecore_device_num_engines(struct ecore_dev *p_dev);
817 int ecore_device_num_ports(struct ecore_dev *p_dev);
818 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
821 /* Flags for indication of required queues */
822 #define PQ_FLAGS_RLS (1 << 0)
823 #define PQ_FLAGS_MCOS (1 << 1)
824 #define PQ_FLAGS_LB (1 << 2)
825 #define PQ_FLAGS_OOO (1 << 3)
826 #define PQ_FLAGS_ACK (1 << 4)
827 #define PQ_FLAGS_OFLD (1 << 5)
828 #define PQ_FLAGS_VFS (1 << 6)
830 /* physical queue index for cm context intialization */
831 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
832 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
833 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
834 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
836 /* amount of resources used in qm init */
837 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
838 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
839 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
840 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
841 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
843 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
845 #endif /* __ECORE_H */