2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
17 #define CONFIG_ECORE_BINARY_FW
18 #undef CONFIG_ECORE_ZIPPED_FW
20 #ifdef CONFIG_ECORE_ZIPPED_FW
24 #include "ecore_hsi_common.h"
25 #include "ecore_hsi_debug_tools.h"
26 #include "ecore_hsi_init_func.h"
27 #include "ecore_hsi_init_tool.h"
28 #include "ecore_proto_if.h"
29 #include "mcp_public.h"
31 #define MAX_HWFNS_PER_DEVICE (4)
32 #define NAME_SIZE 128 /* @DPDK */
34 #define ECORE_WFQ_UNIT 100
35 #include "../qede_logs.h" /* @DPDK */
37 #define ISCSI_BDQ_ID(_port_id) (_port_id)
38 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
40 #define ECORE_WID_SIZE (1024)
43 #define ECORE_PF_DEMS_SIZE (4)
46 enum ecore_coalescing_mode {
47 ECORE_COAL_MODE_DISABLE,
48 ECORE_COAL_MODE_ENABLE
52 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
53 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
54 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
55 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
56 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
57 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
58 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
59 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
60 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
61 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
62 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
66 #if !defined(CONFIG_ECORE_L2)
67 #define CONFIG_ECORE_L2
68 #define CONFIG_ECORE_SRIOV
73 #ifndef __EXTRACT__LINUX__
74 #define MASK_FIELD(_name, _value) \
75 ((_value) &= (_name##_MASK))
77 #define FIELD_VALUE(_name, _value) \
78 ((_value & _name##_MASK) << _name##_SHIFT)
80 #define SET_FIELD(value, name, flag) \
82 (value) &= ~(name##_MASK << name##_SHIFT); \
83 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
86 #define GET_FIELD(value, name) \
87 (((value) >> (name##_SHIFT)) & name##_MASK)
90 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
92 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
93 (cid * ECORE_PF_DEMS_SIZE);
98 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
100 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
101 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
106 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
107 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
108 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
112 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
116 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
120 #ifndef __EXTRACT__LINUX__
122 ECORE_LEVEL_VERBOSE = 0x0,
123 ECORE_LEVEL_INFO = 0x1,
124 ECORE_LEVEL_NOTICE = 0x2,
125 ECORE_LEVEL_ERR = 0x3,
128 #define ECORE_LOG_LEVEL_SHIFT (30)
129 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
130 #define ECORE_LOG_INFO_MASK (0x40000000)
131 #define ECORE_LOG_NOTICE_MASK (0x80000000)
135 ECORE_MSG_DRV = 0x0001,
136 ECORE_MSG_PROBE = 0x0002,
137 ECORE_MSG_LINK = 0x0004,
138 ECORE_MSG_TIMER = 0x0008,
139 ECORE_MSG_IFDOWN = 0x0010,
140 ECORE_MSG_IFUP = 0x0020,
141 ECORE_MSG_RX_ERR = 0x0040,
142 ECORE_MSG_TX_ERR = 0x0080,
143 ECORE_MSG_TX_QUEUED = 0x0100,
144 ECORE_MSG_INTR = 0x0200,
145 ECORE_MSG_TX_DONE = 0x0400,
146 ECORE_MSG_RX_STATUS = 0x0800,
147 ECORE_MSG_PKTDATA = 0x1000,
148 ECORE_MSG_HW = 0x2000,
149 ECORE_MSG_WOL = 0x4000,
151 ECORE_MSG_SPQ = 0x10000,
152 ECORE_MSG_STATS = 0x20000,
153 ECORE_MSG_DCB = 0x40000,
154 ECORE_MSG_IOV = 0x80000,
155 ECORE_MSG_SP = 0x100000,
156 ECORE_MSG_STORAGE = 0x200000,
157 ECORE_MSG_OOO = 0x200000,
158 ECORE_MSG_CXT = 0x800000,
159 ECORE_MSG_LL2 = 0x1000000,
160 ECORE_MSG_ILT = 0x2000000,
161 ECORE_MSG_RDMA = 0x4000000,
162 ECORE_MSG_DEBUG = 0x8000000,
163 /* to be added...up to 0x8000000 */
167 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
169 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
170 (val == (cond1) ? true1 : \
171 (val == (cond2) ? true2 : def))
174 struct ecore_ptt_pool;
176 struct ecore_sb_info;
177 struct ecore_sb_attn_info;
178 struct ecore_cxt_mngr;
179 struct ecore_dma_mem;
180 struct ecore_sb_sp_info;
181 struct ecore_ll2_info;
182 struct ecore_igu_info;
183 struct ecore_mcp_info;
184 struct ecore_dcbx_info;
186 struct ecore_rt_data {
191 enum ecore_tunn_mode {
192 ECORE_MODE_L2GENEVE_TUNN,
193 ECORE_MODE_IPGENEVE_TUNN,
194 ECORE_MODE_L2GRE_TUNN,
195 ECORE_MODE_IPGRE_TUNN,
196 ECORE_MODE_VXLAN_TUNN,
199 enum ecore_tunn_clss {
200 ECORE_TUNN_CLSS_MAC_VLAN,
201 ECORE_TUNN_CLSS_MAC_VNI,
202 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
203 ECORE_TUNN_CLSS_INNER_MAC_VNI,
204 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
208 struct ecore_tunn_start_params {
209 unsigned long tunn_mode;
212 u8 update_vxlan_udp_port;
213 u8 update_geneve_udp_port;
215 u8 tunn_clss_l2geneve;
216 u8 tunn_clss_ipgeneve;
221 struct ecore_tunn_update_params {
222 unsigned long tunn_mode_update_mask;
223 unsigned long tunn_mode;
226 u8 update_rx_pf_clss;
227 u8 update_tx_pf_clss;
228 u8 update_vxlan_udp_port;
229 u8 update_geneve_udp_port;
231 u8 tunn_clss_l2geneve;
232 u8 tunn_clss_ipgeneve;
237 /* The PCI personality is not quite synonymous to protocol ID:
238 * 1. All personalities need CORE connections
239 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
241 enum ecore_pci_personality {
247 ECORE_PCI_DEFAULT /* default in shmem */
250 /* All VFs are symmetric, all counters are PF + all VFs */
251 struct ecore_qm_iids {
257 #define MAX_PF_PER_PORT 8
259 /* HW / FW resources, output of features supported below, most information
260 * is received from MFW.
262 enum ecore_resources {
275 ECORE_RDMA_STATS_QUEUE,
276 ECORE_MAX_RESC, /* must be last */
279 /* Features that require resources, given as input to the resource management
280 * algorithm, the output are the resources above
294 enum ecore_port_mode {
295 ECORE_PORT_MODE_DE_2X40G,
296 ECORE_PORT_MODE_DE_2X50G,
297 ECORE_PORT_MODE_DE_1X100G,
298 ECORE_PORT_MODE_DE_4X10G_F,
299 ECORE_PORT_MODE_DE_4X10G_E,
300 ECORE_PORT_MODE_DE_4X20G,
301 ECORE_PORT_MODE_DE_1X40G,
302 ECORE_PORT_MODE_DE_2X25G,
303 ECORE_PORT_MODE_DE_1X25G,
304 ECORE_PORT_MODE_DE_4X25G,
305 ECORE_PORT_MODE_DE_2X10G,
316 #ifndef __EXTRACT__LINUX__
317 enum ecore_hw_err_type {
318 ECORE_HW_ERR_FAN_FAIL,
319 ECORE_HW_ERR_MFW_RESP_FAIL,
320 ECORE_HW_ERR_HW_ATTN,
321 ECORE_HW_ERR_DMAE_FAIL,
322 ECORE_HW_ERR_RAMROD_FAIL,
323 ECORE_HW_ERR_FW_ASSERT,
327 struct ecore_hw_info {
328 /* PCI personality */
329 enum ecore_pci_personality personality;
331 /* Resource Allocation scheme results */
332 u32 resc_start[ECORE_MAX_RESC];
333 u32 resc_num[ECORE_MAX_RESC];
334 u32 feat_num[ECORE_MAX_FEATURES];
336 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
337 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
338 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
339 RESC_NUM(_p_hwfn, resc))
340 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
342 /* Amount of traffic classes HW supports */
345 /* Amount of TCs which should be active according to DCBx or upper layer driver
351 /* Traffic class used for tcp out of order traffic */
354 /* The traffic class used by PF for it's offloaded protocol */
362 unsigned char hw_mac_addr[ETH_ALEN];
363 u64 node_wwn; /* For FCoE only */
364 u64 port_wwn; /* For FCoE only */
369 struct ecore_igu_info *p_igu_info;
371 u8 max_chains_per_vf;
375 unsigned long device_capabilities;
378 struct ecore_hw_cid_data {
380 bool b_cid_allocated;
381 u8 vfid; /* 1-based; 0 signals this is for a PF */
383 /* Additional identifiers */
388 /* maximun size of read/write commands (HW limit) */
389 #define DMAE_MAX_RW_SIZE 0x2000
391 struct ecore_dmae_info {
392 /* Mutex for synchronizing access to functions */
397 dma_addr_t completion_word_phys_addr;
399 /* The memory location where the DMAE writes the completion
400 * value when an operation is finished on this context.
402 u32 *p_completion_word;
404 dma_addr_t intermediate_buffer_phys_addr;
406 /* An intermediate buffer for DMAE operations that use virtual
407 * addresses - data is DMA'd to/from this buffer and then
408 * memcpy'd to/from the virtual address
410 u32 *p_intermediate_buffer;
412 dma_addr_t dmae_cmd_phys_addr;
413 struct dmae_cmd *p_dmae_cmd;
416 struct ecore_wfq_data {
417 u32 default_min_speed; /* When wfq feature is not configured */
418 u32 min_speed; /* when feature is configured for any 1 vport */
422 struct ecore_qm_info {
423 struct init_qm_pq_params *qm_pq_params;
424 struct init_qm_vport_params *qm_vport_params;
425 struct init_qm_port_params *qm_port_params;
436 u8 max_phys_tcs_per_port;
443 struct ecore_wfq_data *wfq_data;
452 struct ecore_fw_data {
453 #ifdef CONFIG_ECORE_BINARY_FW
454 struct fw_ver_info *fw_ver_info;
456 const u8 *modes_tree_buf;
457 union init_op *init_ops;
463 struct ecore_dev *p_dev;
464 u8 my_id; /* ID inside the PF */
465 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
466 u8 rel_pf_id; /* Relative to engine*/
468 #define ECORE_PATH_ID(_p_hwfn) \
469 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
475 char name[NAME_SIZE];
478 bool first_on_engine;
481 u8 num_funcs_on_engine;
485 void OSAL_IOMEM *regview;
486 void OSAL_IOMEM *doorbells;
488 unsigned long db_size;
491 struct ecore_ptt_pool *p_ptt_pool;
494 struct ecore_hw_info hw_info;
496 /* rt_array (for init-tool) */
497 struct ecore_rt_data rt_data;
500 struct ecore_spq *p_spq;
503 struct ecore_eq *p_eq;
506 struct ecore_consq *p_consq;
508 /* Slow-Path definitions */
510 bool b_sp_dpc_enabled;
512 struct ecore_ptt *p_main_ptt;
513 struct ecore_ptt *p_dpc_ptt;
515 struct ecore_sb_sp_info *p_sp_sb;
516 struct ecore_sb_attn_info *p_sb_attn;
518 /* Protocol related */
520 struct ecore_ll2_info *p_ll2_info;
521 struct ecore_ooo_info *p_ooo_info;
522 struct ecore_iscsi_info *p_iscsi_info;
523 struct ecore_fcoe_info *p_fcoe_info;
524 struct ecore_rdma_info *p_rdma_info;
525 struct ecore_pf_params pf_params;
527 bool b_rdma_enabled_in_prs;
528 u32 rdma_prs_search_reg;
530 /* Array of sb_info of all status blocks */
531 struct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
534 struct ecore_cxt_mngr *p_cxt_mngr;
536 /* Flag indicating whether interrupts are enabled or not*/
538 bool b_int_requested;
540 /* True if the driver requests for the link */
541 bool b_drv_link_init;
543 struct ecore_vf_iov *vf_iov_info;
544 struct ecore_pf_iov *pf_iov_info;
545 struct ecore_mcp_info *mcp_info;
546 struct ecore_dcbx_info *p_dcbx_info;
548 struct ecore_hw_cid_data *p_tx_cids;
549 struct ecore_hw_cid_data *p_rx_cids;
551 struct ecore_dmae_info dmae_info;
554 struct ecore_qm_info qm_info;
556 #ifdef CONFIG_ECORE_ZIPPED_FW
557 /* Buffer for unzipping firmware data */
561 struct dbg_tools_data dbg_info;
563 struct z_stream_s *stream;
565 /* PWM region specific data */
568 u32 dpi_start_offset; /* this is used to
573 /* If one of the following is set then EDPM shouldn't be used */
578 #ifndef __EXTRACT__LINUX__
587 struct ecore_dbg_feature {
593 enum qed_dbg_features {
596 DBG_FEATURE_IDLE_CHK,
597 DBG_FEATURE_MCP_TRACE,
598 DBG_FEATURE_REG_FIFO,
599 DBG_FEATURE_PROTECTION_OVERRIDE,
606 char name[NAME_SIZE];
610 #define ECORE_DEV_TYPE_BB (0 << 0)
611 #define ECORE_DEV_TYPE_AH (1 << 0)
612 /* Translate type/revision combo into the proper conditions */
613 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
614 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
616 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
617 (CHIP_REV_IS_TEDIBEAR(dev)))
619 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
621 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
622 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
628 #define CHIP_NUM_MASK 0xffff
629 #define CHIP_NUM_SHIFT 16
632 #define CHIP_REV_MASK 0xf
633 #define CHIP_REV_SHIFT 12
635 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
636 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
637 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
638 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
639 CHIP_REV_IS_EMUL_B0(_p_dev))
640 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
641 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
642 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
643 CHIP_REV_IS_FPGA_B0(_p_dev))
644 #define CHIP_REV_IS_SLOW(_p_dev) \
645 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
646 #define CHIP_REV_IS_A0(_p_dev) \
647 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
648 CHIP_REV_IS_FPGA_A0(_p_dev) || \
650 #define CHIP_REV_IS_B0(_p_dev) \
651 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
652 CHIP_REV_IS_FPGA_B0(_p_dev) || \
653 (_p_dev)->chip_rev == 1)
654 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
656 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev)
657 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1)
661 #define CHIP_METAL_MASK 0xff
662 #define CHIP_METAL_SHIFT 4
665 #define CHIP_BOND_ID_MASK 0xf
666 #define CHIP_BOND_ID_SHIFT 0
669 u8 num_ports_in_engines;
670 u8 num_funcs_in_port;
673 enum ecore_mf_mode mf_mode;
674 #define IS_MF_DEFAULT(_p_hwfn) \
675 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
676 #define IS_MF_SI(_p_hwfn) \
677 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
678 #define IS_MF_SD(_p_hwfn) \
679 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
683 u8 ver_str[NAME_SIZE]; /* @DPDK */
684 /* Add MF related configuration */
691 enum ecore_coalescing_mode int_coalescing_mode;
692 u16 rx_coalesce_usecs;
693 u16 tx_coalesce_usecs;
695 /* Start Bar offset of first hwfn */
696 void OSAL_IOMEM *regview;
697 void OSAL_IOMEM *doorbells;
699 unsigned long db_size;
705 const struct iro *iro_arr;
706 #define IRO (p_hwfn->p_dev->iro_arr)
710 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
713 struct ecore_hw_sriov_info *p_iov_info;
714 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
715 unsigned long tunn_mode;
723 u32 rdma_max_srq_sge;
725 struct ecore_eth_stats *reset_stats;
726 struct ecore_fw_data *fw_data;
733 /* Indicates whether should prevent attentions from being reasserted */
737 /* Indicates whether allowing the MFW to collect a crash dump */
740 /* Indicates if the reg_fifo is checked after any register access */
747 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
753 struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
757 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
759 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
760 : MAX_NUM_L2_QUEUES_K2)
761 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
763 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
764 : MAX_SB_PER_PATH_K2)
765 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
769 * @brief ecore_concrete_to_sw_fid - get the sw function id from
770 * the concrete value.
772 * @param concrete_fid
774 * @return OSAL_INLINE u8
776 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
779 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
780 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
781 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
785 sw_fid = vfid + MAX_NUM_PFS;
795 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
796 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
799 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
800 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
801 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
802 int ecore_device_num_engines(struct ecore_dev *p_dev);
803 int ecore_device_num_ports(struct ecore_dev *p_dev);
804 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
807 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
809 #endif /* __ECORE_H */