drivers/net/qede/base/ecore.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_H
  10 #define __ECORE_H
  11
  12 /* @DPDK */
  13 #include <sys/stat.h>
  14 #include <fcntl.h>
  15 #include <unistd.h>
  16
  17 #define CONFIG_ECORE_BINARY_FW
  18 #undef CONFIG_ECORE_ZIPPED_FW
  19
  20 #ifdef CONFIG_ECORE_ZIPPED_FW
  21 #include <zlib.h>
  22 #endif
  23
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_hsi_debug_tools.h"
  26 #include "ecore_hsi_init_func.h"
  27 #include "ecore_hsi_init_tool.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define MAX_HWFNS_PER_DEVICE    2
  32 #define NAME_SIZE 128 /* @DPDK */
  33 #define ECORE_WFQ_UNIT  100
  34 #include "../qede_logs.h" /* @DPDK */
  35
  36 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  37 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  38 /* Constants */
  39 #define ECORE_WID_SIZE          (1024)
  40
  41 /* Configurable */
  42 #define ECORE_PF_DEMS_SIZE      (4)
  43
  44 /* cau states */
  45 enum ecore_coalescing_mode {
  46         ECORE_COAL_MODE_DISABLE,
  47         ECORE_COAL_MODE_ENABLE
  48 };
  49
  50 enum ecore_nvm_cmd {
  51         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  52         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  53         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  54         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  55         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  56         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  57         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  58         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  59         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  60         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  61         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  62 };
  63
  64 #ifndef LINUX_REMOVE
  65 #if !defined(CONFIG_ECORE_L2)
  66 #define CONFIG_ECORE_L2
  67 #define CONFIG_ECORE_SRIOV
  68 #endif
  69 #endif
  70
  71 /* helpers */
  72 #ifndef __EXTRACT__LINUX__
  73 #define MASK_FIELD(_name, _value)                                       \
  74                 ((_value) &= (_name##_MASK))
  75
  76 #define FIELD_VALUE(_name, _value)                                      \
  77                 ((_value & _name##_MASK) << _name##_SHIFT)
  78
  79 #define SET_FIELD(value, name, flag)                                    \
  80 do {                                                                    \
  81         (value) &= ~(name##_MASK << name##_SHIFT);                      \
  82         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
  83 } while (0)
  84
  85 #define GET_FIELD(value, name)                                          \
  86         (((value) >> (name##_SHIFT)) & name##_MASK)
  87 #endif
  88
  89 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
  90 {
  91         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
  92                       (cid * ECORE_PF_DEMS_SIZE);
  93
  94         return db_addr;
  95 }
  96
  97 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
  98 {
  99         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 100                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 101
 102         return db_addr;
 103 }
 104
 105 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 106         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 107          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 108
 109 #ifndef LINUX_REMOVE
 110 #ifndef U64_HI
 111 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 112 #endif
 113
 114 #ifndef U64_LO
 115 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 116 #endif
 117 #endif
 118
 119 #ifndef __EXTRACT__LINUX__
 120 enum DP_LEVEL {
 121         ECORE_LEVEL_VERBOSE     = 0x0,
 122         ECORE_LEVEL_INFO        = 0x1,
 123         ECORE_LEVEL_NOTICE      = 0x2,
 124         ECORE_LEVEL_ERR         = 0x3,
 125 };
 126
 127 #define ECORE_LOG_LEVEL_SHIFT   (30)
 128 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 129 #define ECORE_LOG_INFO_MASK     (0x40000000)
 130 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 131
 132 enum DP_MODULE {
 133 #ifndef LINUX_REMOVE
 134         ECORE_MSG_DRV           = 0x0001,
 135         ECORE_MSG_PROBE         = 0x0002,
 136         ECORE_MSG_LINK          = 0x0004,
 137         ECORE_MSG_TIMER         = 0x0008,
 138         ECORE_MSG_IFDOWN        = 0x0010,
 139         ECORE_MSG_IFUP          = 0x0020,
 140         ECORE_MSG_RX_ERR        = 0x0040,
 141         ECORE_MSG_TX_ERR        = 0x0080,
 142         ECORE_MSG_TX_QUEUED     = 0x0100,
 143         ECORE_MSG_INTR          = 0x0200,
 144         ECORE_MSG_TX_DONE       = 0x0400,
 145         ECORE_MSG_RX_STATUS     = 0x0800,
 146         ECORE_MSG_PKTDATA       = 0x1000,
 147         ECORE_MSG_HW            = 0x2000,
 148         ECORE_MSG_WOL           = 0x4000,
 149 #endif
 150         ECORE_MSG_SPQ           = 0x10000,
 151         ECORE_MSG_STATS         = 0x20000,
 152         ECORE_MSG_DCB           = 0x40000,
 153         ECORE_MSG_IOV           = 0x80000,
 154         ECORE_MSG_SP            = 0x100000,
 155         ECORE_MSG_STORAGE       = 0x200000,
 156         ECORE_MSG_OOO           = 0x200000,
 157         ECORE_MSG_CXT           = 0x800000,
 158         ECORE_MSG_LL2           = 0x1000000,
 159         ECORE_MSG_ILT           = 0x2000000,
 160         ECORE_MSG_RDMA          = 0x4000000,
 161         ECORE_MSG_DEBUG         = 0x8000000,
 162         /* to be added...up to 0x8000000 */
 163 };
 164 #endif
 165
 166 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 167
 168 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 169         (val == (cond1) ? true1 : \
 170          (val == (cond2) ? true2 : def))
 171
 172 /* forward */
 173 struct ecore_ptt_pool;
 174 struct ecore_spq;
 175 struct ecore_sb_info;
 176 struct ecore_sb_attn_info;
 177 struct ecore_cxt_mngr;
 178 struct ecore_dma_mem;
 179 struct ecore_sb_sp_info;
 180 struct ecore_ll2_info;
 181 struct ecore_igu_info;
 182 struct ecore_mcp_info;
 183 struct ecore_dcbx_info;
 184
 185 struct ecore_rt_data {
 186         u32     *init_val;
 187         bool    *b_valid;
 188 };
 189
 190 enum ecore_tunn_mode {
 191         ECORE_MODE_L2GENEVE_TUNN,
 192         ECORE_MODE_IPGENEVE_TUNN,
 193         ECORE_MODE_L2GRE_TUNN,
 194         ECORE_MODE_IPGRE_TUNN,
 195         ECORE_MODE_VXLAN_TUNN,
 196 };
 197
 198 enum ecore_tunn_clss {
 199         ECORE_TUNN_CLSS_MAC_VLAN,
 200         ECORE_TUNN_CLSS_MAC_VNI,
 201         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 202         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 203         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 204         MAX_ECORE_TUNN_CLSS,
 205 };
 206
 207 struct ecore_tunn_start_params {
 208         unsigned long tunn_mode;
 209         u16     vxlan_udp_port;
 210         u16     geneve_udp_port;
 211         u8      update_vxlan_udp_port;
 212         u8      update_geneve_udp_port;
 213         u8      tunn_clss_vxlan;
 214         u8      tunn_clss_l2geneve;
 215         u8      tunn_clss_ipgeneve;
 216         u8      tunn_clss_l2gre;
 217         u8      tunn_clss_ipgre;
 218 };
 219
 220 struct ecore_tunn_update_params {
 221         unsigned long tunn_mode_update_mask;
 222         unsigned long tunn_mode;
 223         u16     vxlan_udp_port;
 224         u16     geneve_udp_port;
 225         u8      update_rx_pf_clss;
 226         u8      update_tx_pf_clss;
 227         u8      update_vxlan_udp_port;
 228         u8      update_geneve_udp_port;
 229         u8      tunn_clss_vxlan;
 230         u8      tunn_clss_l2geneve;
 231         u8      tunn_clss_ipgeneve;
 232         u8      tunn_clss_l2gre;
 233         u8      tunn_clss_ipgre;
 234 };
 235
 236 /* The PCI personality is not quite synonymous to protocol ID:
 237  * 1. All personalities need CORE connections
 238  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 239  */
 240 enum ecore_pci_personality {
 241         ECORE_PCI_ETH,
 242         ECORE_PCI_FCOE,
 243         ECORE_PCI_ISCSI,
 244         ECORE_PCI_ETH_ROCE,
 245         ECORE_PCI_ETH_IWARP,
 246         ECORE_PCI_ETH_RDMA,
 247         ECORE_PCI_DEFAULT /* default in shmem */
 248 };
 249
 250 /* All VFs are symmetric, all counters are PF + all VFs */
 251 struct ecore_qm_iids {
 252         u32 cids;
 253         u32 vf_cids;
 254         u32 tids;
 255 };
 256
 257 #define MAX_PF_PER_PORT 8
 258
 259 /* HW / FW resources, output of features supported below, most information
 260  * is received from MFW.
 261  */
 262 enum ecore_resources {
 263         ECORE_SB,
 264         ECORE_L2_QUEUE,
 265         ECORE_VPORT,
 266         ECORE_RSS_ENG,
 267         ECORE_PQ,
 268         ECORE_RL,
 269         ECORE_MAC,
 270         ECORE_VLAN,
 271         ECORE_RDMA_CNQ_RAM,
 272         ECORE_ILT,
 273         ECORE_LL2_QUEUE,
 274         ECORE_CMDQS_CQS,
 275         ECORE_RDMA_STATS_QUEUE,
 276         ECORE_MAX_RESC,                 /* must be last */
 277 };
 278
 279 /* Features that require resources, given as input to the resource management
 280  * algorithm, the output are the resources above
 281  */
 282 enum ecore_feature {
 283         ECORE_PF_L2_QUE,
 284         ECORE_PF_TC,
 285         ECORE_VF,
 286         ECORE_EXTRA_VF_QUE,
 287         ECORE_VMQ,
 288         ECORE_RDMA_CNQ,
 289         ECORE_ISCSI_CQ,
 290         ECORE_FCOE_CQ,
 291         ECORE_VF_L2_QUE,
 292         ECORE_MAX_FEATURES,
 293 };
 294
 295 enum ecore_port_mode {
 296         ECORE_PORT_MODE_DE_2X40G,
 297         ECORE_PORT_MODE_DE_2X50G,
 298         ECORE_PORT_MODE_DE_1X100G,
 299         ECORE_PORT_MODE_DE_4X10G_F,
 300         ECORE_PORT_MODE_DE_4X10G_E,
 301         ECORE_PORT_MODE_DE_4X20G,
 302         ECORE_PORT_MODE_DE_1X40G,
 303         ECORE_PORT_MODE_DE_2X25G,
 304         ECORE_PORT_MODE_DE_1X25G,
 305         ECORE_PORT_MODE_DE_4X25G,
 306         ECORE_PORT_MODE_DE_2X10G,
 307 };
 308
 309 enum ecore_dev_cap {
 310         ECORE_DEV_CAP_ETH,
 311         ECORE_DEV_CAP_FCOE,
 312         ECORE_DEV_CAP_ISCSI,
 313         ECORE_DEV_CAP_ROCE,
 314         ECORE_DEV_CAP_IWARP
 315 };
 316
 317 #ifndef __EXTRACT__LINUX__
 318 enum ecore_hw_err_type {
 319         ECORE_HW_ERR_FAN_FAIL,
 320         ECORE_HW_ERR_MFW_RESP_FAIL,
 321         ECORE_HW_ERR_HW_ATTN,
 322         ECORE_HW_ERR_DMAE_FAIL,
 323         ECORE_HW_ERR_RAMROD_FAIL,
 324         ECORE_HW_ERR_FW_ASSERT,
 325 };
 326 #endif
 327
 328 struct ecore_hw_info {
 329         /* PCI personality */
 330         enum ecore_pci_personality personality;
 331 #define ECORE_IS_RDMA_PERSONALITY(dev)                      \
 332         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE ||  \
 333          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 334          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 335 #define ECORE_IS_ROCE_PERSONALITY(dev)                     \
 336         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 337          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 338 #define ECORE_IS_IWARP_PERSONALITY(dev)                     \
 339         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 340          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 341 #define ECORE_IS_L2_PERSONALITY(dev)                  \
 342         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 343          ECORE_IS_RDMA_PERSONALITY(dev))
 344
 345         /* Resource Allocation scheme results */
 346         u32 resc_start[ECORE_MAX_RESC];
 347         u32 resc_num[ECORE_MAX_RESC];
 348         u32 feat_num[ECORE_MAX_FEATURES];
 349
 350         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 351         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 352         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 353                                          RESC_NUM(_p_hwfn, resc))
 354         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 355
 356         /* Amount of traffic classes HW supports */
 357         u8 num_hw_tc;
 358
 359 /* Amount of TCs which should be active according to DCBx or upper layer driver
 360  * configuration
 361  */
 362
 363         u8 num_active_tc;
 364
 365         /* Traffic class used for tcp out of order traffic */
 366         u8 ooo_tc;
 367
 368         /* The traffic class used by PF for it's offloaded protocol */
 369         u8 offload_tc;
 370
 371         u32 concrete_fid;
 372         u16 opaque_fid;
 373         u16 ovlan;
 374         u32 part_num[4];
 375
 376         unsigned char hw_mac_addr[ETH_ALEN];
 377         u64 node_wwn; /* For FCoE only */
 378         u64 port_wwn; /* For FCoE only */
 379
 380         u16 num_iscsi_conns;
 381         u16 num_fcoe_conns;
 382
 383         struct ecore_igu_info *p_igu_info;
 384         /* Sriov */
 385         u8 max_chains_per_vf;
 386
 387         u32 port_mode;
 388         u32     hw_mode;
 389         unsigned long device_capabilities;
 390
 391         /* Default DCBX mode */
 392         u8 dcbx_mode;
 393
 394         u16 mtu;
 395 };
 396
 397 struct ecore_hw_cid_data {
 398         u32     cid;
 399         bool    b_cid_allocated;
 400         u8      vfid; /* 1-based; 0 signals this is for a PF */
 401
 402         /* Additional identifiers */
 403         u16     opaque_fid;
 404         u8      vport_id;
 405 };
 406
 407 /* maximun size of read/write commands (HW limit) */
 408 #define DMAE_MAX_RW_SIZE        0x2000
 409
 410 struct ecore_dmae_info {
 411         /* Mutex for synchronizing access to functions */
 412         osal_mutex_t    mutex;
 413
 414         u8 channel;
 415
 416         dma_addr_t completion_word_phys_addr;
 417
 418         /* The memory location where the DMAE writes the completion
 419          * value when an operation is finished on this context.
 420          */
 421         u32 *p_completion_word;
 422
 423         dma_addr_t intermediate_buffer_phys_addr;
 424
 425         /* An intermediate buffer for DMAE operations that use virtual
 426          * addresses - data is DMA'd to/from this buffer and then
 427          * memcpy'd to/from the virtual address
 428          */
 429         u32 *p_intermediate_buffer;
 430
 431         dma_addr_t dmae_cmd_phys_addr;
 432         struct dmae_cmd *p_dmae_cmd;
 433 };
 434
 435 struct ecore_wfq_data {
 436         u32 default_min_speed; /* When wfq feature is not configured */
 437         u32 min_speed; /* when feature is configured for any 1 vport */
 438         bool configured;
 439 };
 440
 441 struct ecore_qm_info {
 442         struct init_qm_pq_params    *qm_pq_params;
 443         struct init_qm_vport_params *qm_vport_params;
 444         struct init_qm_port_params  *qm_port_params;
 445         u16                     start_pq;
 446         u8                      start_vport;
 447         u16                     pure_lb_pq;
 448         u16                     offload_pq;
 449         u16                     pure_ack_pq;
 450         u16                     ooo_pq;
 451         u16                     first_vf_pq;
 452         u16                     first_mcos_pq;
 453         u16                     first_rl_pq;
 454         u16                     num_pqs;
 455         u16                     num_vf_pqs;
 456         u8                      num_vports;
 457         u8                      max_phys_tcs_per_port;
 458         bool                    pf_rl_en;
 459         bool                    pf_wfq_en;
 460         bool                    vport_rl_en;
 461         bool                    vport_wfq_en;
 462         u8                      pf_wfq;
 463         u32                     pf_rl;
 464         struct ecore_wfq_data   *wfq_data;
 465         u8                      num_pf_rls;
 466 };
 467
 468 struct storm_stats {
 469         u32 address;
 470         u32 len;
 471 };
 472
 473 struct ecore_fw_data {
 474 #ifdef CONFIG_ECORE_BINARY_FW
 475         struct fw_ver_info *fw_ver_info;
 476 #endif
 477         const u8 *modes_tree_buf;
 478         union init_op *init_ops;
 479         const u32 *arr_data;
 480         u32 init_ops_size;
 481 };
 482
 483 struct ecore_hwfn {
 484         struct ecore_dev                *p_dev;
 485         u8                              my_id;          /* ID inside the PF */
 486 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 487         u8                              rel_pf_id;      /* Relative to engine*/
 488         u8                              abs_pf_id;
 489         #define ECORE_PATH_ID(_p_hwfn) \
 490                 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 491         u8                              port_id;
 492         bool                            b_active;
 493
 494         u32                             dp_module;
 495         u8                              dp_level;
 496         char                            name[NAME_SIZE];
 497         void                            *dp_ctx;
 498
 499         bool                            first_on_engine;
 500         bool                            hw_init_done;
 501
 502         u8                              num_funcs_on_engine;
 503         u8                              enabled_func_idx;
 504
 505         /* BAR access */
 506         void OSAL_IOMEM                 *regview;
 507         void OSAL_IOMEM                 *doorbells;
 508         u64                             db_phys_addr;
 509         unsigned long                   db_size;
 510
 511         /* PTT pool */
 512         struct ecore_ptt_pool           *p_ptt_pool;
 513
 514         /* HW info */
 515         struct ecore_hw_info            hw_info;
 516
 517         /* rt_array (for init-tool) */
 518         struct ecore_rt_data            rt_data;
 519
 520         /* SPQ */
 521         struct ecore_spq                *p_spq;
 522
 523         /* EQ */
 524         struct ecore_eq                 *p_eq;
 525
 526         /* Consolidate Q*/
 527         struct ecore_consq              *p_consq;
 528
 529         /* Slow-Path definitions */
 530         osal_dpc_t                      sp_dpc;
 531         bool                            b_sp_dpc_enabled;
 532
 533         struct ecore_ptt                *p_main_ptt;
 534         struct ecore_ptt                *p_dpc_ptt;
 535
 536         struct ecore_sb_sp_info         *p_sp_sb;
 537         struct ecore_sb_attn_info       *p_sb_attn;
 538
 539         /* Protocol related */
 540         bool                            using_ll2;
 541         struct ecore_ll2_info           *p_ll2_info;
 542         struct ecore_ooo_info           *p_ooo_info;
 543         struct ecore_iscsi_info         *p_iscsi_info;
 544         struct ecore_fcoe_info          *p_fcoe_info;
 545         struct ecore_rdma_info          *p_rdma_info;
 546         struct ecore_pf_params          pf_params;
 547
 548         bool                            b_rdma_enabled_in_prs;
 549         u32                             rdma_prs_search_reg;
 550
 551         /* Array of sb_info of all status blocks */
 552         struct ecore_sb_info            *sbs_info[MAX_SB_PER_PF_MIMD];
 553         u16                             num_sbs;
 554
 555         struct ecore_cxt_mngr           *p_cxt_mngr;
 556
 557         /* Flag indicating whether interrupts are enabled or not*/
 558         bool                            b_int_enabled;
 559         bool                            b_int_requested;
 560
 561         /* True if the driver requests for the link */
 562         bool                            b_drv_link_init;
 563
 564         struct ecore_vf_iov             *vf_iov_info;
 565         struct ecore_pf_iov             *pf_iov_info;
 566         struct ecore_mcp_info           *mcp_info;
 567         struct ecore_dcbx_info          *p_dcbx_info;
 568
 569         struct ecore_hw_cid_data        *p_tx_cids;
 570         struct ecore_hw_cid_data        *p_rx_cids;
 571
 572         struct ecore_dmae_info          dmae_info;
 573
 574         /* QM init */
 575         struct ecore_qm_info            qm_info;
 576
 577 #ifdef CONFIG_ECORE_ZIPPED_FW
 578         /* Buffer for unzipping firmware data */
 579         void *unzip_buf;
 580 #endif
 581
 582         struct dbg_tools_data           dbg_info;
 583
 584         struct z_stream_s               *stream;
 585
 586         /* PWM region specific data */
 587         u32                             dpi_size;
 588         u32                             dpi_count;
 589         u32                             dpi_start_offset; /* this is used to
 590                                                            * calculate th
 591                                                            * doorbell address
 592                                                            */
 593
 594         /* If one of the following is set then EDPM shouldn't be used */
 595         u8                              dcbx_no_edpm;
 596         u8                              db_bar_no_edpm;
 597 };
 598
 599 #ifndef __EXTRACT__LINUX__
 600 enum ecore_mf_mode {
 601         ECORE_MF_DEFAULT,
 602         ECORE_MF_OVLAN,
 603         ECORE_MF_NPAR,
 604 };
 605 #endif
 606
 607 /* @DPDK */
 608 struct ecore_dbg_feature {
 609         u8                              *dump_buf;
 610         u32                             buf_size;
 611         u32                             dumped_dwords;
 612 };
 613
 614 enum qed_dbg_features {
 615         DBG_FEATURE_BUS,
 616         DBG_FEATURE_GRC,
 617         DBG_FEATURE_IDLE_CHK,
 618         DBG_FEATURE_MCP_TRACE,
 619         DBG_FEATURE_REG_FIFO,
 620         DBG_FEATURE_PROTECTION_OVERRIDE,
 621         DBG_FEATURE_NUM
 622 };
 623
 624 struct ecore_dev {
 625         u32                             dp_module;
 626         u8                              dp_level;
 627         char                            name[NAME_SIZE];
 628         void                            *dp_ctx;
 629
 630         u8                              type;
 631 #define ECORE_DEV_TYPE_BB       (0 << 0)
 632 #define ECORE_DEV_TYPE_AH       (1 << 0)
 633 /* Translate type/revision combo into the proper conditions */
 634 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 635 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 636 #ifndef ASIC_ONLY
 637 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 638                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 639 #else
 640 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 641 #endif
 642 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 643 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 644
 645 #define ECORE_DEV_ID_MASK       0xff00
 646 #define ECORE_DEV_ID_MASK_BB    0x1600
 647 #define ECORE_DEV_ID_MASK_AH    0x8000
 648
 649         u16 vendor_id;
 650         u16 device_id;
 651
 652         u16                             chip_num;
 653         #define CHIP_NUM_MASK                   0xffff
 654         #define CHIP_NUM_SHIFT                  16
 655
 656         u16                             chip_rev;
 657         #define CHIP_REV_MASK                   0xf
 658         #define CHIP_REV_SHIFT                  12
 659 #ifndef ASIC_ONLY
 660         #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
 661         #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
 662         #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
 663         #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 664                                           CHIP_REV_IS_EMUL_B0(_p_dev))
 665         #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
 666         #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
 667         #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
 668                                           CHIP_REV_IS_FPGA_B0(_p_dev))
 669         #define CHIP_REV_IS_SLOW(_p_dev) \
 670                 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 671         #define CHIP_REV_IS_A0(_p_dev) \
 672                 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 673                  CHIP_REV_IS_FPGA_A0(_p_dev) || \
 674                  !(_p_dev)->chip_rev)
 675         #define CHIP_REV_IS_B0(_p_dev) \
 676                 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
 677                  CHIP_REV_IS_FPGA_B0(_p_dev) || \
 678                  (_p_dev)->chip_rev == 1)
 679         #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
 680 #else
 681         #define CHIP_REV_IS_A0(_p_dev)  (!(_p_dev)->chip_rev)
 682         #define CHIP_REV_IS_B0(_p_dev)  ((_p_dev)->chip_rev == 1)
 683 #endif
 684
 685         u16                             chip_metal;
 686         #define CHIP_METAL_MASK                 0xff
 687         #define CHIP_METAL_SHIFT                4
 688
 689         u16                             chip_bond_id;
 690         #define CHIP_BOND_ID_MASK               0xf
 691         #define CHIP_BOND_ID_SHIFT              0
 692
 693         u8                              num_engines;
 694         u8                              num_ports_in_engines;
 695         u8                              num_funcs_in_port;
 696
 697         u8                              path_id;
 698         enum ecore_mf_mode              mf_mode;
 699         #define IS_MF_DEFAULT(_p_hwfn)  \
 700                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 701         #define IS_MF_SI(_p_hwfn)       \
 702                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 703         #define IS_MF_SD(_p_hwfn)       \
 704                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 705
 706         int                             pcie_width;
 707         int                             pcie_speed;
 708
 709         /* Add MF related configuration */
 710         u8                              mcp_rev;
 711         u8                              boot_mode;
 712
 713         u8                              wol;
 714
 715         u32                             int_mode;
 716         enum ecore_coalescing_mode      int_coalescing_mode;
 717         u16                             rx_coalesce_usecs;
 718         u16                             tx_coalesce_usecs;
 719
 720         /* Start Bar offset of first hwfn */
 721         void OSAL_IOMEM                 *regview;
 722         void OSAL_IOMEM                 *doorbells;
 723         u64                             db_phys_addr;
 724         unsigned long                   db_size;
 725
 726         /* PCI */
 727         u8                              cache_shift;
 728
 729         /* Init */
 730         const struct iro                *iro_arr;
 731         #define IRO (p_hwfn->p_dev->iro_arr)
 732
 733         /* HW functions */
 734         u8                              num_hwfns;
 735         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 736
 737         /* SRIOV */
 738         struct ecore_hw_sriov_info      *p_iov_info;
 739 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 740         unsigned long                   tunn_mode;
 741
 742         bool                            b_is_vf;
 743
 744         u32                             drv_type;
 745
 746         u32                             rdma_max_sge;
 747         u32                             rdma_max_inline;
 748         u32                             rdma_max_srq_sge;
 749
 750         struct ecore_eth_stats          *reset_stats;
 751         struct ecore_fw_data            *fw_data;
 752
 753         u32                             mcp_nvm_resp;
 754
 755         /* Recovery */
 756         bool                            recov_in_prog;
 757
 758 /* Indicates whether should prevent attentions from being reasserted */
 759
 760         bool                            attn_clr_en;
 761
 762         /* Indicates whether allowing the MFW to collect a crash dump */
 763         bool                            mdump_en;
 764
 765         /* Indicates if the reg_fifo is checked after any register access */
 766         bool                            chk_reg_fifo;
 767
 768 #ifndef ASIC_ONLY
 769         bool                            b_is_emul_full;
 770 #endif
 771
 772 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 773         void                            *firmware;
 774         u64                             fw_len;
 775 #endif
 776
 777         /* @DPDK */
 778         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 779         u8                              engine_for_debug;
 780 };
 781
 782 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 783                                                   : MAX_NUM_VFS_K2)
 784 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 785                                                   : MAX_NUM_L2_QUEUES_K2)
 786 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 787                                                   : MAX_NUM_PORTS_K2)
 788 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 789                                                   : MAX_SB_PER_PATH_K2)
 790 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 791                                                   : MAX_NUM_PFS_K2)
 792
 793 /**
 794  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 795  *        the concrete value.
 796  *
 797  * @param concrete_fid
 798  *
 799  * @return OSAL_INLINE u8
 800  */
 801 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
 802                                           u32 concrete_fid)
 803 {
 804         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 805         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 806         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 807         u8 sw_fid;
 808
 809         if (vf_valid)
 810                 sw_fid = vfid + MAX_NUM_PFS;
 811         else
 812                 sw_fid = pfid;
 813
 814         return sw_fid;
 815 }
 816
 817 #define PURE_LB_TC 8
 818 #define PKT_LB_TC 9
 819
 820 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 821 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 822                                            u32 min_pf_rate);
 823
 824 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 825 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 826 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 827 int ecore_device_num_engines(struct ecore_dev *p_dev);
 828 int ecore_device_num_ports(struct ecore_dev *p_dev);
 829 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 830                            u8 *mac);
 831
 832 /* Flags for indication of required queues */
 833 #define PQ_FLAGS_RLS    (1 << 0)
 834 #define PQ_FLAGS_MCOS   (1 << 1)
 835 #define PQ_FLAGS_LB     (1 << 2)
 836 #define PQ_FLAGS_OOO    (1 << 3)
 837 #define PQ_FLAGS_ACK    (1 << 4)
 838 #define PQ_FLAGS_OFLD   (1 << 5)
 839 #define PQ_FLAGS_VFS    (1 << 6)
 840
 841 /* physical queue index for cm context intialization */
 842 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 843 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 844 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 845 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
 846
 847 /* amount of resources used in qm init */
 848 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 849 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 850 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 851 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 852 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 853
 854 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 855
 856 #endif /* __ECORE_H */