drivers/net/qede/base/ecore.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_H
  10 #define __ECORE_H
  11
  12 /* @DPDK */
  13 #include <sys/stat.h>
  14 #include <fcntl.h>
  15 #include <unistd.h>
  16
  17 #define CONFIG_ECORE_BINARY_FW
  18 #define CONFIG_ECORE_ZIPPED_FW
  19
  20 #ifdef CONFIG_ECORE_ZIPPED_FW
  21 #include <zlib.h>
  22 #endif
  23
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_hsi_debug_tools.h"
  26 #include "ecore_hsi_init_func.h"
  27 #include "ecore_hsi_init_tool.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define MAX_HWFNS_PER_DEVICE    (4)
  32 #define NAME_SIZE 64            /* @DPDK */
  33 #define VER_SIZE 16
  34 /* @DPDK ARRAY_DECL */
  35 #define ECORE_WFQ_UNIT  100
  36 #include "../qede_logs.h" /* @DPDK */
  37
  38 /* Constants */
  39 #define ECORE_WID_SIZE          (1024)
  40
  41 /* Configurable */
  42 #define ECORE_PF_DEMS_SIZE      (4)
  43
  44 /* cau states */
  45 enum ecore_coalescing_mode {
  46         ECORE_COAL_MODE_DISABLE,
  47         ECORE_COAL_MODE_ENABLE
  48 };
  49
  50 enum ecore_nvm_cmd {
  51         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  52         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  53         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  54         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  55         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  56         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  57         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  58         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  59         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  60         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  61         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  62 };
  63
  64 #ifndef LINUX_REMOVE
  65 #if !defined(CONFIG_ECORE_L2)
  66 #define CONFIG_ECORE_L2
  67 #define CONFIG_ECORE_SRIOV
  68 #endif
  69 #endif
  70
  71 /* helpers */
  72 #ifndef __EXTRACT__LINUX__
  73 #define MASK_FIELD(_name, _value)                                       \
  74                 ((_value) &= (_name##_MASK))
  75
  76 #define FIELD_VALUE(_name, _value)                                      \
  77                 ((_value & _name##_MASK) << _name##_SHIFT)
  78
  79 #define SET_FIELD(value, name, flag)                                    \
  80 do {                                                                    \
  81         (value) &= ~(name##_MASK << name##_SHIFT);                      \
  82         (value) |= (((u64)flag) << (name##_SHIFT));                     \
  83 } while (0)
  84
  85 #define GET_FIELD(value, name)                                          \
  86         (((value) >> (name##_SHIFT)) & name##_MASK)
  87 #endif
  88
  89 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
  90 {
  91         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
  92                       (cid * ECORE_PF_DEMS_SIZE);
  93
  94         return db_addr;
  95 }
  96
  97 /* @DPDK: This is a backport from latest ecore for TSS fix */
  98 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
  99 {
 100         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 101                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 102
 103         return db_addr;
 104 }
 105
 106 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 107         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 108          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 109
 110 #ifndef U64_HI
 111 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 112 #endif
 113
 114 #ifndef U64_LO
 115 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 116 #endif
 117
 118 #ifndef __EXTRACT__LINUX__
 119 enum DP_LEVEL {
 120         ECORE_LEVEL_VERBOSE     = 0x0,
 121         ECORE_LEVEL_INFO        = 0x1,
 122         ECORE_LEVEL_NOTICE      = 0x2,
 123         ECORE_LEVEL_ERR         = 0x3,
 124 };
 125
 126 #define ECORE_LOG_LEVEL_SHIFT   (30)
 127 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 128 #define ECORE_LOG_INFO_MASK     (0x40000000)
 129 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 130
 131 enum DP_MODULE {
 132 #ifndef LINUX_REMOVE
 133         ECORE_MSG_DRV           = 0x0001,
 134         ECORE_MSG_PROBE         = 0x0002,
 135         ECORE_MSG_LINK          = 0x0004,
 136         ECORE_MSG_TIMER         = 0x0008,
 137         ECORE_MSG_IFDOWN        = 0x0010,
 138         ECORE_MSG_IFUP          = 0x0020,
 139         ECORE_MSG_RX_ERR        = 0x0040,
 140         ECORE_MSG_TX_ERR        = 0x0080,
 141         ECORE_MSG_TX_QUEUED     = 0x0100,
 142         ECORE_MSG_INTR          = 0x0200,
 143         ECORE_MSG_TX_DONE       = 0x0400,
 144         ECORE_MSG_RX_STATUS     = 0x0800,
 145         ECORE_MSG_PKTDATA       = 0x1000,
 146         ECORE_MSG_HW            = 0x2000,
 147         ECORE_MSG_WOL           = 0x4000,
 148 #endif
 149         ECORE_MSG_SPQ           = 0x10000,
 150         ECORE_MSG_STATS         = 0x20000,
 151         ECORE_MSG_DCB           = 0x40000,
 152         ECORE_MSG_IOV           = 0x80000,
 153         ECORE_MSG_SP            = 0x100000,
 154         ECORE_MSG_STORAGE       = 0x200000,
 155         ECORE_MSG_CXT           = 0x800000,
 156         ECORE_MSG_ILT           = 0x2000000,
 157         ECORE_MSG_DEBUG         = 0x8000000,
 158         /* to be added...up to 0x8000000 */
 159 };
 160 #endif
 161
 162 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 163
 164 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 165         (val == (cond1) ? true1 : \
 166          (val == (cond2) ? true2 : def))
 167
 168 /* forward */
 169 struct ecore_ptt_pool;
 170 struct ecore_spq;
 171 struct ecore_sb_info;
 172 struct ecore_sb_attn_info;
 173 struct ecore_cxt_mngr;
 174 struct ecore_dma_mem;
 175 struct ecore_sb_sp_info;
 176 struct ecore_igu_info;
 177 struct ecore_mcp_info;
 178 struct ecore_dcbx_info;
 179
 180 struct ecore_rt_data {
 181         u32     *init_val;
 182         bool    *b_valid;
 183 };
 184
 185 enum ecore_tunn_mode {
 186         ECORE_MODE_L2GENEVE_TUNN,
 187         ECORE_MODE_IPGENEVE_TUNN,
 188         ECORE_MODE_L2GRE_TUNN,
 189         ECORE_MODE_IPGRE_TUNN,
 190         ECORE_MODE_VXLAN_TUNN,
 191 };
 192
 193 enum ecore_tunn_clss {
 194         ECORE_TUNN_CLSS_MAC_VLAN,
 195         ECORE_TUNN_CLSS_MAC_VNI,
 196         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 197         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 198         MAX_ECORE_TUNN_CLSS,
 199 };
 200
 201 struct ecore_tunn_start_params {
 202         unsigned long tunn_mode;
 203         u16     vxlan_udp_port;
 204         u16     geneve_udp_port;
 205         u8      update_vxlan_udp_port;
 206         u8      update_geneve_udp_port;
 207         u8      tunn_clss_vxlan;
 208         u8      tunn_clss_l2geneve;
 209         u8      tunn_clss_ipgeneve;
 210         u8      tunn_clss_l2gre;
 211         u8      tunn_clss_ipgre;
 212 };
 213
 214 struct ecore_tunn_update_params {
 215         unsigned long tunn_mode_update_mask;
 216         unsigned long tunn_mode;
 217         u16     vxlan_udp_port;
 218         u16     geneve_udp_port;
 219         u8      update_rx_pf_clss;
 220         u8      update_tx_pf_clss;
 221         u8      update_vxlan_udp_port;
 222         u8      update_geneve_udp_port;
 223         u8      tunn_clss_vxlan;
 224         u8      tunn_clss_l2geneve;
 225         u8      tunn_clss_ipgeneve;
 226         u8      tunn_clss_l2gre;
 227         u8      tunn_clss_ipgre;
 228 };
 229
 230 struct ecore_hw_sriov_info {
 231         /* standard SRIOV capability fields, mostly for debugging */
 232         int pos;                /* capability position */
 233         int nres;               /* number of resources */
 234         u32 cap;                /* SR-IOV Capabilities */
 235         u16 ctrl;               /* SR-IOV Control */
 236         u16 total_vfs;          /* total VFs associated with the PF */
 237         u16 num_vfs;            /* number of vfs that have been started */
 238         u64 active_vfs[3];      /* bitfield of active vfs */
 239 #define ECORE_IS_VF_ACTIVE(_p_dev, _rel_vf_id)  \
 240                 (!!(_p_dev->sriov_info.active_vfs[_rel_vf_id / 64] & \
 241                     (1ULL << (_rel_vf_id % 64))))
 242         u16 initial_vfs;        /* initial VFs associated with the PF */
 243         u16 nr_virtfn;          /* number of VFs available */
 244         u16 offset;             /* first VF Routing ID offset */
 245         u16 stride;             /* following VF stride */
 246         u16 vf_device_id;       /* VF device id */
 247         u32 pgsz;               /* page size for BAR alignment */
 248         u8 link;                /* Function Dependency Link */
 249
 250         bool b_hw_channel;      /* Whether PF uses the HW-channel */
 251 };
 252
 253 /* The PCI personality is not quite synonymous to protocol ID:
 254  * 1. All personalities need CORE connections
 255  * 2. The Ethernet personality may support also the RoCE protocol
 256  */
 257 enum ecore_pci_personality {
 258         ECORE_PCI_ETH,
 259         ECORE_PCI_DEFAULT /* default in shmem */
 260 };
 261
 262 /* All VFs are symmetric, all counters are PF + all VFs */
 263 struct ecore_qm_iids {
 264         u32 cids;
 265         u32 vf_cids;
 266         u32 tids;
 267 };
 268
 269 #define MAX_PF_PER_PORT 8
 270
 271 /*@@@TBD MK RESC: need to remove and use MCP interface instead */
 272 /* HW / FW resources, output of features supported below, most information
 273  * is received from MFW.
 274  */
 275 enum ECORE_RESOURCES {
 276         ECORE_SB,
 277         ECORE_L2_QUEUE,
 278         ECORE_VPORT,
 279         ECORE_RSS_ENG,
 280         ECORE_PQ,
 281         ECORE_RL,
 282         ECORE_MAC,
 283         ECORE_VLAN,
 284         ECORE_ILT,
 285         ECORE_CMDQS_CQS,
 286         ECORE_MAX_RESC,
 287 };
 288
 289 /* Features that require resources, given as input to the resource management
 290  * algorithm, the output are the resources above
 291  */
 292 enum ECORE_FEATURE {
 293         ECORE_PF_L2_QUE,
 294         ECORE_PF_TC,
 295         ECORE_VF,
 296         ECORE_EXTRA_VF_QUE,
 297         ECORE_VMQ,
 298         ECORE_MAX_FEATURES,
 299 };
 300
 301 enum ECORE_PORT_MODE {
 302         ECORE_PORT_MODE_DE_2X40G,
 303         ECORE_PORT_MODE_DE_2X50G,
 304         ECORE_PORT_MODE_DE_1X100G,
 305         ECORE_PORT_MODE_DE_4X10G_F,
 306         ECORE_PORT_MODE_DE_4X10G_E,
 307         ECORE_PORT_MODE_DE_4X20G,
 308         ECORE_PORT_MODE_DE_1X40G,
 309         ECORE_PORT_MODE_DE_2X25G,
 310         ECORE_PORT_MODE_DE_1X25G
 311 };
 312
 313 enum ecore_dev_cap {
 314         ECORE_DEV_CAP_ETH,
 315 };
 316
 317 #ifndef __EXTRACT__LINUX__
 318 enum ecore_hw_err_type {
 319         ECORE_HW_ERR_FAN_FAIL,
 320         ECORE_HW_ERR_MFW_RESP_FAIL,
 321         ECORE_HW_ERR_HW_ATTN,
 322         ECORE_HW_ERR_DMAE_FAIL,
 323         ECORE_HW_ERR_RAMROD_FAIL,
 324         ECORE_HW_ERR_FW_ASSERT,
 325 };
 326 #endif
 327
 328 struct ecore_hw_info {
 329         /* PCI personality */
 330         enum ecore_pci_personality personality;
 331
 332         /* Resource Allocation scheme results */
 333         u32 resc_start[ECORE_MAX_RESC];
 334         u32 resc_num[ECORE_MAX_RESC];
 335         u32 feat_num[ECORE_MAX_FEATURES];
 336
 337         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 338         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 339         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 340                                          RESC_NUM(_p_hwfn, resc))
 341         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 342
 343         u8 num_tc;
 344         u8 ooo_tc;
 345         u8 offload_tc;
 346         u8 non_offload_tc;
 347
 348         u32 concrete_fid;
 349         u16 opaque_fid;
 350         u16 ovlan;
 351         u32 part_num[4];
 352
 353         unsigned char hw_mac_addr[ETH_ALEN];
 354
 355         struct ecore_igu_info *p_igu_info;
 356         /* Sriov */
 357         u32 first_vf_in_pf;
 358         u8 max_chains_per_vf;
 359
 360         u32 port_mode;
 361         u32     hw_mode;
 362         unsigned long device_capabilities;
 363 };
 364
 365 struct ecore_hw_cid_data {
 366         u32     cid;
 367         bool    b_cid_allocated;
 368         u8      vfid; /* 1-based; 0 signals this is for a PF */
 369
 370         /* Additional identifiers */
 371         u16     opaque_fid;
 372         u8      vport_id;
 373 };
 374
 375 /* maximun size of read/write commands (HW limit) */
 376 #define DMAE_MAX_RW_SIZE        0x2000
 377
 378 struct ecore_dmae_info {
 379         /* Mutex for synchronizing access to functions */
 380         osal_mutex_t    mutex;
 381
 382         u8 channel;
 383
 384         dma_addr_t completion_word_phys_addr;
 385
 386         /* The memory location where the DMAE writes the completion
 387          * value when an operation is finished on this context.
 388          */
 389         u32 *p_completion_word;
 390
 391         dma_addr_t intermediate_buffer_phys_addr;
 392
 393         /* An intermediate buffer for DMAE operations that use virtual
 394          * addresses - data is DMA'd to/from this buffer and then
 395          * memcpy'd to/from the virtual address
 396          */
 397         u32 *p_intermediate_buffer;
 398
 399         dma_addr_t dmae_cmd_phys_addr;
 400         struct dmae_cmd *p_dmae_cmd;
 401 };
 402
 403 struct ecore_wfq_data {
 404         u32 default_min_speed; /* When wfq feature is not configured */
 405         u32 min_speed; /* when feature is configured for any 1 vport */
 406         bool configured;
 407 };
 408
 409 struct ecore_qm_info {
 410         struct init_qm_pq_params    *qm_pq_params;
 411         struct init_qm_vport_params *qm_vport_params;
 412         struct init_qm_port_params  *qm_port_params;
 413         u16                     start_pq;
 414         u8                      start_vport;
 415         u8                      pure_lb_pq;
 416         u8                      offload_pq;
 417         u8                      pure_ack_pq;
 418         u8                      ooo_pq;
 419         u8                      vf_queues_offset;
 420         u16                     num_pqs;
 421         u16                     num_vf_pqs;
 422         u8                      num_vports;
 423         u8                      max_phys_tcs_per_port;
 424         bool                    pf_rl_en;
 425         bool                    pf_wfq_en;
 426         bool                    vport_rl_en;
 427         bool                    vport_wfq_en;
 428         u8                      pf_wfq;
 429         u32                     pf_rl;
 430         struct ecore_wfq_data   *wfq_data;
 431 };
 432
 433 struct storm_stats {
 434         u32 address;
 435         u32 len;
 436 };
 437
 438 struct ecore_fw_data {
 439 #ifdef CONFIG_ECORE_BINARY_FW
 440         struct fw_ver_info *fw_ver_info;
 441 #endif
 442         const u8 *modes_tree_buf;
 443         union init_op *init_ops;
 444         const u32 *arr_data;
 445         u32 init_ops_size;
 446 };
 447
 448 struct ecore_hwfn {
 449         struct ecore_dev                *p_dev;
 450         u8                              my_id;          /* ID inside the PF */
 451 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 452         u8                              rel_pf_id;      /* Relative to engine*/
 453         u8                              abs_pf_id;
 454         #define ECORE_PATH_ID(_p_hwfn) \
 455                 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 456         u8                              port_id;
 457         bool                            b_active;
 458
 459         u32                             dp_module;
 460         u8                              dp_level;
 461         char                            name[NAME_SIZE];
 462         void                            *dp_ctx;
 463
 464         bool                            first_on_engine;
 465         bool                            hw_init_done;
 466
 467         u8                              num_funcs_on_engine;
 468
 469         /* BAR access */
 470         void OSAL_IOMEM                 *regview;
 471         void OSAL_IOMEM                 *doorbells;
 472         u64                             db_phys_addr;
 473         unsigned long                   db_size;
 474
 475         /* PTT pool */
 476         struct ecore_ptt_pool           *p_ptt_pool;
 477
 478         /* HW info */
 479         struct ecore_hw_info            hw_info;
 480
 481         /* rt_array (for init-tool) */
 482         struct ecore_rt_data            rt_data;
 483
 484         /* SPQ */
 485         struct ecore_spq                *p_spq;
 486
 487         /* EQ */
 488         struct ecore_eq                 *p_eq;
 489
 490         /* Consolidate Q*/
 491         struct ecore_consq              *p_consq;
 492
 493         /* Slow-Path definitions */
 494         osal_dpc_t                      sp_dpc;
 495         bool                            b_sp_dpc_enabled;
 496
 497         struct ecore_ptt                *p_main_ptt;
 498         struct ecore_ptt                *p_dpc_ptt;
 499
 500         struct ecore_sb_sp_info         *p_sp_sb;
 501         struct ecore_sb_attn_info       *p_sb_attn;
 502
 503         /* Protocol related */
 504         struct ecore_ooo_info           *p_ooo_info;
 505         struct ecore_pf_params          pf_params;
 506
 507         /* Array of sb_info of all status blocks */
 508         struct ecore_sb_info            *sbs_info[MAX_SB_PER_PF_MIMD];
 509         u16                             num_sbs;
 510
 511         struct ecore_cxt_mngr           *p_cxt_mngr;
 512
 513         /* Flag indicating whether interrupts are enabled or not*/
 514         bool                            b_int_enabled;
 515         bool                            b_int_requested;
 516
 517         /* True if the driver requests for the link */
 518         bool                            b_drv_link_init;
 519
 520         struct ecore_vf_iov             *vf_iov_info;
 521         struct ecore_pf_iov             *pf_iov_info;
 522         struct ecore_mcp_info           *mcp_info;
 523         struct ecore_dcbx_info          *p_dcbx_info;
 524
 525         struct ecore_hw_cid_data        *p_tx_cids;
 526         struct ecore_hw_cid_data        *p_rx_cids;
 527
 528         struct ecore_dmae_info          dmae_info;
 529
 530         /* QM init */
 531         struct ecore_qm_info            qm_info;
 532
 533 #ifdef CONFIG_ECORE_ZIPPED_FW
 534         /* Buffer for unzipping firmware data */
 535         void *unzip_buf;
 536 #endif
 537
 538         struct dbg_tools_data           dbg_info;
 539
 540         struct z_stream_s               *stream;
 541
 542         /* PWM region specific data */
 543         u32                             dpi_size;
 544         u32                             dpi_count;
 545         u32                             dpi_start_offset; /* this is used to
 546                                                            * calculate th
 547                                                            * doorbell address
 548                                                            */
 549 };
 550
 551 #ifndef __EXTRACT__LINUX__
 552 enum ecore_mf_mode {
 553         ECORE_MF_DEFAULT,
 554         ECORE_MF_OVLAN,
 555         ECORE_MF_NPAR,
 556 };
 557 #endif
 558
 559 struct ecore_dev {
 560         u32                             dp_module;
 561         u8                              dp_level;
 562         char                            name[NAME_SIZE];
 563         void                            *dp_ctx;
 564
 565         u8                              type;
 566 #define ECORE_DEV_TYPE_BB       (0 << 0)
 567 #define ECORE_DEV_TYPE_AH       (1 << 0)
 568 /* Translate type/revision combo into the proper conditions */
 569 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 570 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 571 #ifndef ASIC_ONLY
 572 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 573                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 574 #else
 575 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 576 #endif
 577 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 578 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 579
 580         u16 vendor_id;
 581         u16 device_id;
 582
 583         u16                             chip_num;
 584         #define CHIP_NUM_MASK                   0xffff
 585         #define CHIP_NUM_SHIFT                  16
 586
 587         u16                             chip_rev;
 588         #define CHIP_REV_MASK                   0xf
 589         #define CHIP_REV_SHIFT                  12
 590 #ifndef ASIC_ONLY
 591         #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
 592         #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
 593         #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
 594         #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 595                                           CHIP_REV_IS_EMUL_B0(_p_dev))
 596         #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
 597         #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
 598         #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
 599                                           CHIP_REV_IS_FPGA_B0(_p_dev))
 600         #define CHIP_REV_IS_SLOW(_p_dev) \
 601                 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 602         #define CHIP_REV_IS_A0(_p_dev) \
 603                 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 604                  CHIP_REV_IS_FPGA_A0(_p_dev) || \
 605                  !(_p_dev)->chip_rev)
 606         #define CHIP_REV_IS_B0(_p_dev) \
 607                 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
 608                  CHIP_REV_IS_FPGA_B0(_p_dev) || \
 609                  (_p_dev)->chip_rev == 1)
 610 #define CHIP_REV_IS_ASIC(_p_dev) (!CHIP_REV_IS_SLOW(_p_dev))
 611 #else
 612         #define CHIP_REV_IS_A0(_p_dev)  (!(_p_dev)->chip_rev)
 613         #define CHIP_REV_IS_B0(_p_dev)  ((_p_dev)->chip_rev == 1)
 614 #endif
 615
 616         u16                             chip_metal;
 617         #define CHIP_METAL_MASK                 0xff
 618         #define CHIP_METAL_SHIFT                4
 619
 620         u16                             chip_bond_id;
 621         #define CHIP_BOND_ID_MASK               0xf
 622         #define CHIP_BOND_ID_SHIFT              0
 623
 624         u8                              num_engines;
 625         u8                              num_ports_in_engines;
 626         u8                              num_funcs_in_port;
 627
 628         u8                              path_id;
 629         enum ecore_mf_mode              mf_mode;
 630         #define IS_MF_DEFAULT(_p_hwfn)  \
 631                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 632 #define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 633 #define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 634
 635         int                             pcie_width;
 636         int                             pcie_speed;
 637         u8 ver_str[VER_SIZE];
 638         /* Add MF related configuration */
 639         u8                              mcp_rev;
 640         u8                              boot_mode;
 641
 642         u8                              wol;
 643
 644         u32                             int_mode;
 645         enum ecore_coalescing_mode      int_coalescing_mode;
 646         u8 rx_coalesce_usecs;
 647         u8 tx_coalesce_usecs;
 648
 649         /* Start Bar offset of first hwfn */
 650         void OSAL_IOMEM                 *regview;
 651         void OSAL_IOMEM                 *doorbells;
 652         u64                             db_phys_addr;
 653         unsigned long                   db_size;
 654
 655         /* PCI */
 656         u8                              cache_shift;
 657
 658         /* Init */
 659         const struct iro                *iro_arr;
 660         #define IRO (p_hwfn->p_dev->iro_arr)
 661
 662         /* HW functions */
 663         u8                              num_hwfns;
 664         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 665
 666         /* SRIOV */
 667         struct ecore_hw_sriov_info sriov_info;
 668         unsigned long                   tunn_mode;
 669 #define IS_ECORE_SRIOV(edev)            (!!((edev)->sriov_info.total_vfs))
 670         bool                            b_is_vf;
 671
 672         u32                             drv_type;
 673
 674         struct ecore_eth_stats          *reset_stats;
 675         struct ecore_fw_data            *fw_data;
 676
 677         u32                             mcp_nvm_resp;
 678
 679         /* Recovery */
 680         bool                            recov_in_prog;
 681
 682 #ifndef ASIC_ONLY
 683         bool                            b_is_emul_full;
 684 #endif
 685
 686 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 687         void                            *firmware;
 688         u64                             fw_len;
 689 #endif
 690
 691 };
 692
 693 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 694                                                   : MAX_NUM_VFS_K2)
 695 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 696                                                   : MAX_NUM_L2_QUEUES_K2)
 697 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 698                                                   : MAX_NUM_PORTS_K2)
 699 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 700                                                   : MAX_SB_PER_PATH_K2)
 701 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 702                                                   : MAX_NUM_PFS_K2)
 703
 704 #define ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn) ( \
 705         (ECORE_IS_BB_A0(p_hwfn->p_dev)) && \
 706         (ECORE_PATH_ID(p_hwfn) == 1) && \
 707         ((p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X40G) || \
 708          (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X50G) || \
 709          (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X25G)))
 710
 711 /**
 712  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 713  *        the concrete value.
 714  *
 715  * @param concrete_fid
 716  *
 717  * @return OSAL_INLINE u8
 718  */
 719 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
 720                                           u32 concrete_fid)
 721 {
 722         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 723         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 724         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 725         u8 sw_fid;
 726
 727         if (vf_valid)
 728                 sw_fid = vfid + MAX_NUM_PFS;
 729         else
 730                 sw_fid = pfid;
 731
 732         return sw_fid;
 733 }
 734
 735 #define PURE_LB_TC 8
 736 #define OOO_LB_TC 9
 737
 738 static OSAL_INLINE u16 ecore_sriov_get_next_vf(struct ecore_hwfn *p_hwfn,
 739                                                u16 rel_vf_id)
 740 {
 741         u16 i;
 742
 743         for (i = rel_vf_id; i < p_hwfn->p_dev->sriov_info.total_vfs; i++)
 744                 if (ECORE_IS_VF_ACTIVE(p_hwfn->p_dev, i))
 745                         return i;
 746
 747         return p_hwfn->p_dev->sriov_info.total_vfs;
 748 }
 749
 750 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 751 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 752                                            u32 min_pf_rate);
 753
 754 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 755 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 756 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 757 int ecore_device_num_engines(struct ecore_dev *p_dev);
 758 int ecore_device_num_ports(struct ecore_dev *p_dev);
 759
 760 #define ecore_for_each_vf(_p_hwfn, _i)                          \
 761         for (_i = ecore_sriov_get_next_vf(_p_hwfn, 0);          \
 762              _i < _p_hwfn->p_dev->sriov_info.total_vfs;         \
 763              _i = ecore_sriov_get_next_vf(_p_hwfn, _i + 1))
 764
 765 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 766
 767 #endif /* __ECORE_H */