2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_hsi_common.h"
13 #include "ecore_hsi_debug_tools.h"
14 #include "ecore_hsi_init_func.h"
15 #include "ecore_hsi_init_tool.h"
16 #include "ecore_proto_if.h"
17 #include "mcp_public.h"
19 #define MAX_HWFNS_PER_DEVICE (4)
20 #define NAME_SIZE 64 /* @DPDK */
22 /* @DPDK ARRAY_DECL */
23 #define ECORE_WFQ_UNIT 100
24 #include "../qede_logs.h" /* @DPDK */
27 #define ECORE_WID_SIZE (1024)
30 #define ECORE_PF_DEMS_SIZE (4)
33 enum ecore_coalescing_mode {
34 ECORE_COAL_MODE_DISABLE,
35 ECORE_COAL_MODE_ENABLE
39 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
40 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
41 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
42 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
43 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
44 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
45 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
46 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
47 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
48 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
49 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
53 #if !defined(CONFIG_ECORE_L2)
54 #define CONFIG_ECORE_L2
55 #define CONFIG_ECORE_SRIOV
60 #ifndef __EXTRACT__LINUX__
61 #define MASK_FIELD(_name, _value) \
62 ((_value) &= (_name##_MASK))
64 #define FIELD_VALUE(_name, _value) \
65 ((_value & _name##_MASK) << _name##_SHIFT)
67 #define SET_FIELD(value, name, flag) \
69 (value) &= ~(name##_MASK << name##_SHIFT); \
70 (value) |= (((u64)flag) << (name##_SHIFT)); \
73 #define GET_FIELD(value, name) \
74 (((value) >> (name##_SHIFT)) & name##_MASK)
77 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
79 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
80 (cid * ECORE_PF_DEMS_SIZE);
85 /* @DPDK: This is a backport from latest ecore for TSS fix */
86 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
88 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
89 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
94 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
95 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
96 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
99 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
103 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
106 #ifndef __EXTRACT__LINUX__
108 ECORE_LEVEL_VERBOSE = 0x0,
109 ECORE_LEVEL_INFO = 0x1,
110 ECORE_LEVEL_NOTICE = 0x2,
111 ECORE_LEVEL_ERR = 0x3,
114 #define ECORE_LOG_LEVEL_SHIFT (30)
115 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
116 #define ECORE_LOG_INFO_MASK (0x40000000)
117 #define ECORE_LOG_NOTICE_MASK (0x80000000)
121 ECORE_MSG_DRV = 0x0001,
122 ECORE_MSG_PROBE = 0x0002,
123 ECORE_MSG_LINK = 0x0004,
124 ECORE_MSG_TIMER = 0x0008,
125 ECORE_MSG_IFDOWN = 0x0010,
126 ECORE_MSG_IFUP = 0x0020,
127 ECORE_MSG_RX_ERR = 0x0040,
128 ECORE_MSG_TX_ERR = 0x0080,
129 ECORE_MSG_TX_QUEUED = 0x0100,
130 ECORE_MSG_INTR = 0x0200,
131 ECORE_MSG_TX_DONE = 0x0400,
132 ECORE_MSG_RX_STATUS = 0x0800,
133 ECORE_MSG_PKTDATA = 0x1000,
134 ECORE_MSG_HW = 0x2000,
135 ECORE_MSG_WOL = 0x4000,
137 ECORE_MSG_SPQ = 0x10000,
138 ECORE_MSG_STATS = 0x20000,
139 ECORE_MSG_DCB = 0x40000,
140 ECORE_MSG_IOV = 0x80000,
141 ECORE_MSG_SP = 0x100000,
142 ECORE_MSG_STORAGE = 0x200000,
143 ECORE_MSG_CXT = 0x800000,
144 ECORE_MSG_ILT = 0x2000000,
145 ECORE_MSG_DEBUG = 0x8000000,
146 /* to be added...up to 0x8000000 */
150 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
152 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
153 (val == (cond1) ? true1 : \
154 (val == (cond2) ? true2 : def))
157 struct ecore_ptt_pool;
159 struct ecore_sb_info;
160 struct ecore_sb_attn_info;
161 struct ecore_cxt_mngr;
162 struct ecore_dma_mem;
163 struct ecore_sb_sp_info;
164 struct ecore_igu_info;
165 struct ecore_mcp_info;
166 struct ecore_dcbx_info;
168 struct ecore_rt_data {
173 enum ecore_tunn_mode {
174 ECORE_MODE_L2GENEVE_TUNN,
175 ECORE_MODE_IPGENEVE_TUNN,
176 ECORE_MODE_L2GRE_TUNN,
177 ECORE_MODE_IPGRE_TUNN,
178 ECORE_MODE_VXLAN_TUNN,
181 enum ecore_tunn_clss {
182 ECORE_TUNN_CLSS_MAC_VLAN,
183 ECORE_TUNN_CLSS_MAC_VNI,
184 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
185 ECORE_TUNN_CLSS_INNER_MAC_VNI,
189 struct ecore_tunn_start_params {
190 unsigned long tunn_mode;
193 u8 update_vxlan_udp_port;
194 u8 update_geneve_udp_port;
196 u8 tunn_clss_l2geneve;
197 u8 tunn_clss_ipgeneve;
202 struct ecore_tunn_update_params {
203 unsigned long tunn_mode_update_mask;
204 unsigned long tunn_mode;
207 u8 update_rx_pf_clss;
208 u8 update_tx_pf_clss;
209 u8 update_vxlan_udp_port;
210 u8 update_geneve_udp_port;
212 u8 tunn_clss_l2geneve;
213 u8 tunn_clss_ipgeneve;
218 struct ecore_hw_sriov_info {
219 /* standard SRIOV capability fields, mostly for debugging */
220 int pos; /* capability position */
221 int nres; /* number of resources */
222 u32 cap; /* SR-IOV Capabilities */
223 u16 ctrl; /* SR-IOV Control */
224 u16 total_vfs; /* total VFs associated with the PF */
225 u16 num_vfs; /* number of vfs that have been started */
226 u64 active_vfs[3]; /* bitfield of active vfs */
227 #define ECORE_IS_VF_ACTIVE(_p_dev, _rel_vf_id) \
228 (!!(_p_dev->sriov_info.active_vfs[_rel_vf_id / 64] & \
229 (1ULL << (_rel_vf_id % 64))))
230 u16 initial_vfs; /* initial VFs associated with the PF */
231 u16 nr_virtfn; /* number of VFs available */
232 u16 offset; /* first VF Routing ID offset */
233 u16 stride; /* following VF stride */
234 u16 vf_device_id; /* VF device id */
235 u32 pgsz; /* page size for BAR alignment */
236 u8 link; /* Function Dependency Link */
238 bool b_hw_channel; /* Whether PF uses the HW-channel */
241 /* The PCI personality is not quite synonymous to protocol ID:
242 * 1. All personalities need CORE connections
243 * 2. The Ethernet personality may support also the RoCE protocol
245 enum ecore_pci_personality {
247 ECORE_PCI_DEFAULT /* default in shmem */
250 /* All VFs are symmetric, all counters are PF + all VFs */
251 struct ecore_qm_iids {
257 #define MAX_PF_PER_PORT 8
259 /*@@@TBD MK RESC: need to remove and use MCP interface instead */
260 /* HW / FW resources, output of features supported below, most information
261 * is received from MFW.
263 enum ECORE_RESOURCES {
277 /* Features that require resources, given as input to the resource management
278 * algorithm, the output are the resources above
289 enum ECORE_PORT_MODE {
290 ECORE_PORT_MODE_DE_2X40G,
291 ECORE_PORT_MODE_DE_2X50G,
292 ECORE_PORT_MODE_DE_1X100G,
293 ECORE_PORT_MODE_DE_4X10G_F,
294 ECORE_PORT_MODE_DE_4X10G_E,
295 ECORE_PORT_MODE_DE_4X20G,
296 ECORE_PORT_MODE_DE_1X40G,
297 ECORE_PORT_MODE_DE_2X25G,
298 ECORE_PORT_MODE_DE_1X25G
305 #ifndef __EXTRACT__LINUX__
306 enum ecore_hw_err_type {
307 ECORE_HW_ERR_FAN_FAIL,
308 ECORE_HW_ERR_MFW_RESP_FAIL,
309 ECORE_HW_ERR_HW_ATTN,
310 ECORE_HW_ERR_DMAE_FAIL,
311 ECORE_HW_ERR_RAMROD_FAIL,
312 ECORE_HW_ERR_FW_ASSERT,
316 struct ecore_hw_info {
317 /* PCI personality */
318 enum ecore_pci_personality personality;
320 /* Resource Allocation scheme results */
321 u32 resc_start[ECORE_MAX_RESC];
322 u32 resc_num[ECORE_MAX_RESC];
323 u32 feat_num[ECORE_MAX_FEATURES];
325 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
326 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
327 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
328 RESC_NUM(_p_hwfn, resc))
329 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
341 unsigned char hw_mac_addr[ETH_ALEN];
343 struct ecore_igu_info *p_igu_info;
346 u8 max_chains_per_vf;
350 unsigned long device_capabilities;
353 struct ecore_hw_cid_data {
355 bool b_cid_allocated;
356 u8 vfid; /* 1-based; 0 signals this is for a PF */
358 /* Additional identifiers */
363 /* maximun size of read/write commands (HW limit) */
364 #define DMAE_MAX_RW_SIZE 0x2000
366 struct ecore_dmae_info {
367 /* Mutex for synchronizing access to functions */
372 dma_addr_t completion_word_phys_addr;
374 /* The memory location where the DMAE writes the completion
375 * value when an operation is finished on this context.
377 u32 *p_completion_word;
379 dma_addr_t intermediate_buffer_phys_addr;
381 /* An intermediate buffer for DMAE operations that use virtual
382 * addresses - data is DMA'd to/from this buffer and then
383 * memcpy'd to/from the virtual address
385 u32 *p_intermediate_buffer;
387 dma_addr_t dmae_cmd_phys_addr;
388 struct dmae_cmd *p_dmae_cmd;
391 struct ecore_wfq_data {
392 u32 default_min_speed; /* When wfq feature is not configured */
393 u32 min_speed; /* when feature is configured for any 1 vport */
397 struct ecore_qm_info {
398 struct init_qm_pq_params *qm_pq_params;
399 struct init_qm_vport_params *qm_vport_params;
400 struct init_qm_port_params *qm_port_params;
411 u8 max_phys_tcs_per_port;
418 struct ecore_wfq_data *wfq_data;
426 #define CONFIG_ECORE_BINARY_FW
427 #define CONFIG_ECORE_ZIPPED_FW
429 struct ecore_fw_data {
430 #ifdef CONFIG_ECORE_BINARY_FW
431 struct fw_ver_info *fw_ver_info;
433 const u8 *modes_tree_buf;
434 union init_op *init_ops;
440 struct ecore_dev *p_dev;
441 u8 my_id; /* ID inside the PF */
442 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
443 u8 rel_pf_id; /* Relative to engine */
445 #define ECORE_PATH_ID(_p_hwfn) \
446 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
452 char name[NAME_SIZE];
455 bool first_on_engine;
458 u8 num_funcs_on_engine;
461 void OSAL_IOMEM *regview;
462 void OSAL_IOMEM *doorbells;
464 unsigned long db_size;
467 struct ecore_ptt_pool *p_ptt_pool;
470 struct ecore_hw_info hw_info;
472 /* rt_array (for init-tool) */
473 struct ecore_rt_data rt_data;
476 struct ecore_spq *p_spq;
479 struct ecore_eq *p_eq;
482 struct ecore_consq *p_consq;
484 /* Slow-Path definitions */
486 bool b_sp_dpc_enabled;
488 struct ecore_ptt *p_main_ptt;
489 struct ecore_ptt *p_dpc_ptt;
491 struct ecore_sb_sp_info *p_sp_sb;
492 struct ecore_sb_attn_info *p_sb_attn;
494 /* Protocol related */
495 struct ecore_ooo_info *p_ooo_info;
496 struct ecore_pf_params pf_params;
498 /* Array of sb_info of all status blocks */
499 struct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
502 struct ecore_cxt_mngr *p_cxt_mngr;
504 /* Flag indicating whether interrupts are enabled or not */
506 bool b_int_requested;
508 /* True if the driver requests for the link */
509 bool b_drv_link_init;
511 struct ecore_vf_iov *vf_iov_info;
512 struct ecore_pf_iov *pf_iov_info;
513 struct ecore_mcp_info *mcp_info;
514 struct ecore_dcbx_info *p_dcbx_info;
516 struct ecore_hw_cid_data *p_tx_cids;
517 struct ecore_hw_cid_data *p_rx_cids;
519 struct ecore_dmae_info dmae_info;
522 struct ecore_qm_info qm_info;
524 /* Buffer for unzipping firmware data */
525 #ifdef CONFIG_ECORE_ZIPPED_FW
529 struct dbg_tools_data dbg_info;
531 struct z_stream_s *stream;
533 /* PWM region specific data */
536 u32 dpi_start_offset; /* this is used to
542 #ifndef __EXTRACT__LINUX__
553 char name[NAME_SIZE];
557 #define ECORE_DEV_TYPE_BB (0 << 0)
558 #define ECORE_DEV_TYPE_AH (1 << 0)
559 /* Translate type/revision combo into the proper conditions */
560 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
561 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
563 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
564 (CHIP_REV_IS_TEDIBEAR(dev)))
566 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
568 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
569 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
575 #define CHIP_NUM_MASK 0xffff
576 #define CHIP_NUM_SHIFT 16
579 #define CHIP_REV_MASK 0xf
580 #define CHIP_REV_SHIFT 12
582 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
583 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
584 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
585 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
586 CHIP_REV_IS_EMUL_B0(_p_dev))
587 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
588 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
589 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
590 CHIP_REV_IS_FPGA_B0(_p_dev))
591 #define CHIP_REV_IS_SLOW(_p_dev) \
592 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
593 #define CHIP_REV_IS_A0(_p_dev) \
594 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
595 CHIP_REV_IS_FPGA_A0(_p_dev) || \
597 #define CHIP_REV_IS_B0(_p_dev) \
598 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
599 CHIP_REV_IS_FPGA_B0(_p_dev) || \
600 (_p_dev)->chip_rev == 1)
601 #define CHIP_REV_IS_ASIC(_p_dev) (!CHIP_REV_IS_SLOW(_p_dev))
603 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev)
604 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1)
608 #define CHIP_METAL_MASK 0xff
609 #define CHIP_METAL_SHIFT 4
612 #define CHIP_BOND_ID_MASK 0xf
613 #define CHIP_BOND_ID_SHIFT 0
616 u8 num_ports_in_engines;
617 u8 num_funcs_in_port;
620 enum ecore_mf_mode mf_mode;
621 #define IS_MF_DEFAULT(_p_hwfn) \
622 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
623 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
624 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
628 u8 ver_str[VER_SIZE];
629 /* Add MF related configuration */
636 enum ecore_coalescing_mode int_coalescing_mode;
637 u8 rx_coalesce_usecs;
638 u8 tx_coalesce_usecs;
640 /* Start Bar offset of first hwfn */
641 void OSAL_IOMEM *regview;
642 void OSAL_IOMEM *doorbells;
644 unsigned long db_size;
650 const struct iro *iro_arr;
651 #define IRO (p_hwfn->p_dev->iro_arr)
655 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
658 struct ecore_hw_sriov_info sriov_info;
659 unsigned long tunn_mode;
660 #define IS_ECORE_SRIOV(edev) (!!((edev)->sriov_info.total_vfs))
665 struct ecore_eth_stats *reset_stats;
666 struct ecore_fw_data *fw_data;
683 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
685 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
686 : MAX_NUM_L2_QUEUES_K2)
687 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
689 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
690 : MAX_SB_PER_PATH_K2)
691 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
694 #define ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn) ( \
695 (ECORE_IS_BB_A0(p_hwfn->p_dev)) && \
696 (ECORE_PATH_ID(p_hwfn) == 1) && \
697 ((p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X40G) || \
698 (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X50G) || \
699 (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X25G)))
702 * @brief ecore_concrete_to_sw_fid - get the sw function id from
703 * the concrete value.
705 * @param concrete_fid
707 * @return OSAL_INLINE u8
709 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
712 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
713 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
714 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
718 sw_fid = vfid + MAX_NUM_PFS;
728 static OSAL_INLINE u16 ecore_sriov_get_next_vf(struct ecore_hwfn *p_hwfn,
733 for (i = rel_vf_id; i < p_hwfn->p_dev->sriov_info.total_vfs; i++)
734 if (ECORE_IS_VF_ACTIVE(p_hwfn->p_dev, i))
737 return p_hwfn->p_dev->sriov_info.total_vfs;
740 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
741 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
744 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
745 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
746 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
747 int ecore_device_num_engines(struct ecore_dev *p_dev);
748 int ecore_device_num_ports(struct ecore_dev *p_dev);
750 #define ecore_for_each_vf(_p_hwfn, _i) \
751 for (_i = ecore_sriov_get_next_vf(_p_hwfn, 0); \
752 _i < _p_hwfn->p_dev->sriov_info.total_vfs; \
753 _i = ecore_sriov_get_next_vf(_p_hwfn, _i + 1))
755 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
757 #endif /* __ECORE_H */