2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
17 #define CONFIG_ECORE_BINARY_FW
18 #undef CONFIG_ECORE_ZIPPED_FW
20 #ifdef CONFIG_ECORE_ZIPPED_FW
24 #include "ecore_hsi_common.h"
25 #include "ecore_hsi_debug_tools.h"
26 #include "ecore_hsi_init_func.h"
27 #include "ecore_hsi_init_tool.h"
28 #include "ecore_proto_if.h"
29 #include "mcp_public.h"
31 #define MAX_HWFNS_PER_DEVICE 2
32 #define NAME_SIZE 128 /* @DPDK */
33 #define ECORE_WFQ_UNIT 100
34 #include "../qede_logs.h" /* @DPDK */
36 #define ISCSI_BDQ_ID(_port_id) (_port_id)
37 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
39 #define ECORE_WID_SIZE (1024)
42 #define ECORE_PF_DEMS_SIZE (4)
45 enum ecore_coalescing_mode {
46 ECORE_COAL_MODE_DISABLE,
47 ECORE_COAL_MODE_ENABLE
51 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
52 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
53 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
54 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
55 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
56 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
57 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
58 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
59 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
60 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
61 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
65 #if !defined(CONFIG_ECORE_L2)
66 #define CONFIG_ECORE_L2
67 #define CONFIG_ECORE_SRIOV
72 #ifndef __EXTRACT__LINUX__
73 #define MASK_FIELD(_name, _value) \
74 ((_value) &= (_name##_MASK))
76 #define FIELD_VALUE(_name, _value) \
77 ((_value & _name##_MASK) << _name##_SHIFT)
79 #define SET_FIELD(value, name, flag) \
81 (value) &= ~(name##_MASK << name##_SHIFT); \
82 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
85 #define GET_FIELD(value, name) \
86 (((value) >> (name##_SHIFT)) & name##_MASK)
89 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
91 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
92 (cid * ECORE_PF_DEMS_SIZE);
97 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
99 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
100 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
105 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
106 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
107 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
111 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
115 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
119 #ifndef __EXTRACT__LINUX__
121 ECORE_LEVEL_VERBOSE = 0x0,
122 ECORE_LEVEL_INFO = 0x1,
123 ECORE_LEVEL_NOTICE = 0x2,
124 ECORE_LEVEL_ERR = 0x3,
127 #define ECORE_LOG_LEVEL_SHIFT (30)
128 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
129 #define ECORE_LOG_INFO_MASK (0x40000000)
130 #define ECORE_LOG_NOTICE_MASK (0x80000000)
134 ECORE_MSG_DRV = 0x0001,
135 ECORE_MSG_PROBE = 0x0002,
136 ECORE_MSG_LINK = 0x0004,
137 ECORE_MSG_TIMER = 0x0008,
138 ECORE_MSG_IFDOWN = 0x0010,
139 ECORE_MSG_IFUP = 0x0020,
140 ECORE_MSG_RX_ERR = 0x0040,
141 ECORE_MSG_TX_ERR = 0x0080,
142 ECORE_MSG_TX_QUEUED = 0x0100,
143 ECORE_MSG_INTR = 0x0200,
144 ECORE_MSG_TX_DONE = 0x0400,
145 ECORE_MSG_RX_STATUS = 0x0800,
146 ECORE_MSG_PKTDATA = 0x1000,
147 ECORE_MSG_HW = 0x2000,
148 ECORE_MSG_WOL = 0x4000,
150 ECORE_MSG_SPQ = 0x10000,
151 ECORE_MSG_STATS = 0x20000,
152 ECORE_MSG_DCB = 0x40000,
153 ECORE_MSG_IOV = 0x80000,
154 ECORE_MSG_SP = 0x100000,
155 ECORE_MSG_STORAGE = 0x200000,
156 ECORE_MSG_OOO = 0x200000,
157 ECORE_MSG_CXT = 0x800000,
158 ECORE_MSG_LL2 = 0x1000000,
159 ECORE_MSG_ILT = 0x2000000,
160 ECORE_MSG_RDMA = 0x4000000,
161 ECORE_MSG_DEBUG = 0x8000000,
162 /* to be added...up to 0x8000000 */
166 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
168 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
169 (val == (cond1) ? true1 : \
170 (val == (cond2) ? true2 : def))
173 struct ecore_ptt_pool;
175 struct ecore_sb_info;
176 struct ecore_sb_attn_info;
177 struct ecore_cxt_mngr;
178 struct ecore_dma_mem;
179 struct ecore_sb_sp_info;
180 struct ecore_ll2_info;
181 struct ecore_igu_info;
182 struct ecore_mcp_info;
183 struct ecore_dcbx_info;
185 struct ecore_rt_data {
190 enum ecore_tunn_mode {
191 ECORE_MODE_L2GENEVE_TUNN,
192 ECORE_MODE_IPGENEVE_TUNN,
193 ECORE_MODE_L2GRE_TUNN,
194 ECORE_MODE_IPGRE_TUNN,
195 ECORE_MODE_VXLAN_TUNN,
198 enum ecore_tunn_clss {
199 ECORE_TUNN_CLSS_MAC_VLAN,
200 ECORE_TUNN_CLSS_MAC_VNI,
201 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
202 ECORE_TUNN_CLSS_INNER_MAC_VNI,
203 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
207 struct ecore_tunn_update_type {
210 enum ecore_tunn_clss tun_cls;
213 struct ecore_tunn_update_udp_port {
218 struct ecore_tunnel_info {
219 struct ecore_tunn_update_type vxlan;
220 struct ecore_tunn_update_type l2_geneve;
221 struct ecore_tunn_update_type ip_geneve;
222 struct ecore_tunn_update_type l2_gre;
223 struct ecore_tunn_update_type ip_gre;
225 struct ecore_tunn_update_udp_port vxlan_port;
226 struct ecore_tunn_update_udp_port geneve_port;
228 bool b_update_rx_cls;
229 bool b_update_tx_cls;
232 /* The PCI personality is not quite synonymous to protocol ID:
233 * 1. All personalities need CORE connections
234 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
236 enum ecore_pci_personality {
243 ECORE_PCI_DEFAULT /* default in shmem */
246 /* All VFs are symmetric, all counters are PF + all VFs */
247 struct ecore_qm_iids {
253 #define MAX_PF_PER_PORT 8
255 /* HW / FW resources, output of features supported below, most information
256 * is received from MFW.
258 enum ecore_resources {
271 ECORE_RDMA_STATS_QUEUE,
272 ECORE_MAX_RESC, /* must be last */
275 /* Features that require resources, given as input to the resource management
276 * algorithm, the output are the resources above
291 enum ecore_port_mode {
292 ECORE_PORT_MODE_DE_2X40G,
293 ECORE_PORT_MODE_DE_2X50G,
294 ECORE_PORT_MODE_DE_1X100G,
295 ECORE_PORT_MODE_DE_4X10G_F,
296 ECORE_PORT_MODE_DE_4X10G_E,
297 ECORE_PORT_MODE_DE_4X20G,
298 ECORE_PORT_MODE_DE_1X40G,
299 ECORE_PORT_MODE_DE_2X25G,
300 ECORE_PORT_MODE_DE_1X25G,
301 ECORE_PORT_MODE_DE_4X25G,
302 ECORE_PORT_MODE_DE_2X10G,
313 #ifndef __EXTRACT__LINUX__
314 enum ecore_hw_err_type {
315 ECORE_HW_ERR_FAN_FAIL,
316 ECORE_HW_ERR_MFW_RESP_FAIL,
317 ECORE_HW_ERR_HW_ATTN,
318 ECORE_HW_ERR_DMAE_FAIL,
319 ECORE_HW_ERR_RAMROD_FAIL,
320 ECORE_HW_ERR_FW_ASSERT,
324 struct ecore_hw_info {
325 /* PCI personality */
326 enum ecore_pci_personality personality;
327 #define ECORE_IS_RDMA_PERSONALITY(dev) \
328 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
329 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
330 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
331 #define ECORE_IS_ROCE_PERSONALITY(dev) \
332 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
333 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
334 #define ECORE_IS_IWARP_PERSONALITY(dev) \
335 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
336 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
337 #define ECORE_IS_L2_PERSONALITY(dev) \
338 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
339 ECORE_IS_RDMA_PERSONALITY(dev))
341 /* Resource Allocation scheme results */
342 u32 resc_start[ECORE_MAX_RESC];
343 u32 resc_num[ECORE_MAX_RESC];
344 u32 feat_num[ECORE_MAX_FEATURES];
346 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
347 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
348 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
349 RESC_NUM(_p_hwfn, resc))
350 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
352 /* Amount of traffic classes HW supports */
355 /* Amount of TCs which should be active according to DCBx or upper layer driver
361 /* The traffic class used by PF for it's offloaded protocol */
369 unsigned char hw_mac_addr[ETH_ALEN];
370 u64 node_wwn; /* For FCoE only */
371 u64 port_wwn; /* For FCoE only */
376 struct ecore_igu_info *p_igu_info;
378 u8 max_chains_per_vf;
382 unsigned long device_capabilities;
384 /* Default DCBX mode */
390 /* maximun size of read/write commands (HW limit) */
391 #define DMAE_MAX_RW_SIZE 0x2000
393 struct ecore_dmae_info {
394 /* Mutex for synchronizing access to functions */
399 dma_addr_t completion_word_phys_addr;
401 /* The memory location where the DMAE writes the completion
402 * value when an operation is finished on this context.
404 u32 *p_completion_word;
406 dma_addr_t intermediate_buffer_phys_addr;
408 /* An intermediate buffer for DMAE operations that use virtual
409 * addresses - data is DMA'd to/from this buffer and then
410 * memcpy'd to/from the virtual address
412 u32 *p_intermediate_buffer;
414 dma_addr_t dmae_cmd_phys_addr;
415 struct dmae_cmd *p_dmae_cmd;
418 struct ecore_wfq_data {
419 u32 default_min_speed; /* When wfq feature is not configured */
420 u32 min_speed; /* when feature is configured for any 1 vport */
424 struct ecore_qm_info {
425 struct init_qm_pq_params *qm_pq_params;
426 struct init_qm_vport_params *qm_vport_params;
427 struct init_qm_port_params *qm_port_params;
440 u8 max_phys_tcs_per_port;
448 struct ecore_wfq_data *wfq_data;
457 struct ecore_fw_data {
458 #ifdef CONFIG_ECORE_BINARY_FW
459 struct fw_ver_info *fw_ver_info;
461 const u8 *modes_tree_buf;
462 union init_op *init_ops;
468 struct ecore_dev *p_dev;
469 u8 my_id; /* ID inside the PF */
470 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
471 u8 rel_pf_id; /* Relative to engine*/
473 #define ECORE_PATH_ID(_p_hwfn) \
474 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
480 char name[NAME_SIZE];
483 bool first_on_engine;
486 u8 num_funcs_on_engine;
490 void OSAL_IOMEM *regview;
491 void OSAL_IOMEM *doorbells;
493 unsigned long db_size;
496 struct ecore_ptt_pool *p_ptt_pool;
499 struct ecore_hw_info hw_info;
501 /* rt_array (for init-tool) */
502 struct ecore_rt_data rt_data;
505 struct ecore_spq *p_spq;
508 struct ecore_eq *p_eq;
511 struct ecore_consq *p_consq;
513 /* Slow-Path definitions */
515 bool b_sp_dpc_enabled;
517 struct ecore_ptt *p_main_ptt;
518 struct ecore_ptt *p_dpc_ptt;
520 struct ecore_sb_sp_info *p_sp_sb;
521 struct ecore_sb_attn_info *p_sb_attn;
523 /* Protocol related */
525 struct ecore_ll2_info *p_ll2_info;
526 struct ecore_ooo_info *p_ooo_info;
527 struct ecore_iscsi_info *p_iscsi_info;
528 struct ecore_fcoe_info *p_fcoe_info;
529 struct ecore_rdma_info *p_rdma_info;
530 struct ecore_pf_params pf_params;
532 bool b_rdma_enabled_in_prs;
533 u32 rdma_prs_search_reg;
535 /* Array of sb_info of all status blocks */
536 struct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
539 struct ecore_cxt_mngr *p_cxt_mngr;
541 /* Flag indicating whether interrupts are enabled or not*/
543 bool b_int_requested;
545 /* True if the driver requests for the link */
546 bool b_drv_link_init;
548 struct ecore_vf_iov *vf_iov_info;
549 struct ecore_pf_iov *pf_iov_info;
550 struct ecore_mcp_info *mcp_info;
551 struct ecore_dcbx_info *p_dcbx_info;
553 struct ecore_dmae_info dmae_info;
556 struct ecore_qm_info qm_info;
558 #ifdef CONFIG_ECORE_ZIPPED_FW
559 /* Buffer for unzipping firmware data */
563 struct dbg_tools_data dbg_info;
565 struct z_stream_s *stream;
567 /* PWM region specific data */
570 u32 dpi_start_offset; /* this is used to
575 /* If one of the following is set then EDPM shouldn't be used */
580 #ifndef __EXTRACT__LINUX__
589 struct ecore_dbg_feature {
595 enum qed_dbg_features {
598 DBG_FEATURE_IDLE_CHK,
599 DBG_FEATURE_MCP_TRACE,
600 DBG_FEATURE_REG_FIFO,
601 DBG_FEATURE_PROTECTION_OVERRIDE,
608 char name[NAME_SIZE];
612 #define ECORE_DEV_TYPE_BB (0 << 0)
613 #define ECORE_DEV_TYPE_AH (1 << 0)
614 /* Translate type/revision combo into the proper conditions */
615 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
616 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
618 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
619 (CHIP_REV_IS_TEDIBEAR(dev)))
621 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
623 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
624 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
626 #define ECORE_DEV_ID_MASK 0xff00
627 #define ECORE_DEV_ID_MASK_BB 0x1600
628 #define ECORE_DEV_ID_MASK_AH 0x8000
634 #define CHIP_NUM_MASK 0xffff
635 #define CHIP_NUM_SHIFT 16
638 #define CHIP_REV_MASK 0xf
639 #define CHIP_REV_SHIFT 12
641 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
642 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
643 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
644 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
645 CHIP_REV_IS_EMUL_B0(_p_dev))
646 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
647 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
648 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
649 CHIP_REV_IS_FPGA_B0(_p_dev))
650 #define CHIP_REV_IS_SLOW(_p_dev) \
651 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
652 #define CHIP_REV_IS_A0(_p_dev) \
653 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
654 CHIP_REV_IS_FPGA_A0(_p_dev) || \
656 #define CHIP_REV_IS_B0(_p_dev) \
657 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
658 CHIP_REV_IS_FPGA_B0(_p_dev) || \
659 (_p_dev)->chip_rev == 1)
660 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
662 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev)
663 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1)
667 #define CHIP_METAL_MASK 0xff
668 #define CHIP_METAL_SHIFT 4
671 #define CHIP_BOND_ID_MASK 0xf
672 #define CHIP_BOND_ID_SHIFT 0
675 u8 num_ports_in_engines;
676 u8 num_funcs_in_port;
679 enum ecore_mf_mode mf_mode;
680 #define IS_MF_DEFAULT(_p_hwfn) \
681 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
682 #define IS_MF_SI(_p_hwfn) \
683 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
684 #define IS_MF_SD(_p_hwfn) \
685 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
690 /* Add MF related configuration */
697 enum ecore_coalescing_mode int_coalescing_mode;
698 u16 rx_coalesce_usecs;
699 u16 tx_coalesce_usecs;
701 /* Start Bar offset of first hwfn */
702 void OSAL_IOMEM *regview;
703 void OSAL_IOMEM *doorbells;
705 unsigned long db_size;
711 const struct iro *iro_arr;
712 #define IRO (p_hwfn->p_dev->iro_arr)
716 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
719 struct ecore_hw_sriov_info *p_iov_info;
720 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
721 struct ecore_tunnel_info tunnel;
728 u32 rdma_max_srq_sge;
730 struct ecore_eth_stats *reset_stats;
731 struct ecore_fw_data *fw_data;
738 /* Indicates whether should prevent attentions from being reasserted */
742 /* Indicates whether allowing the MFW to collect a crash dump */
745 /* Indicates if the reg_fifo is checked after any register access */
752 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
758 struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
762 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
764 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
765 : MAX_NUM_L2_QUEUES_K2)
766 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
768 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
769 : MAX_SB_PER_PATH_K2)
770 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
774 * @brief ecore_concrete_to_sw_fid - get the sw function id from
775 * the concrete value.
777 * @param concrete_fid
779 * @return OSAL_INLINE u8
781 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
784 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
785 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
786 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
790 sw_fid = vfid + MAX_NUM_PFS;
800 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
801 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
804 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
805 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
806 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
807 int ecore_device_num_engines(struct ecore_dev *p_dev);
808 int ecore_device_num_ports(struct ecore_dev *p_dev);
809 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
812 /* Flags for indication of required queues */
813 #define PQ_FLAGS_RLS (1 << 0)
814 #define PQ_FLAGS_MCOS (1 << 1)
815 #define PQ_FLAGS_LB (1 << 2)
816 #define PQ_FLAGS_OOO (1 << 3)
817 #define PQ_FLAGS_ACK (1 << 4)
818 #define PQ_FLAGS_OFLD (1 << 5)
819 #define PQ_FLAGS_VFS (1 << 6)
821 /* physical queue index for cm context intialization */
822 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
823 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
824 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
825 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
827 /* amount of resources used in qm init */
828 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
829 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
830 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
831 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
832 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
834 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
836 #endif /* __ECORE_H */