1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
15 #define CONFIG_ECORE_BINARY_FW
16 #undef CONFIG_ECORE_ZIPPED_FW
18 #ifdef CONFIG_ECORE_ZIPPED_FW
22 #include "ecore_status.h"
23 #include "ecore_hsi_common.h"
24 #include "ecore_hsi_debug_tools.h"
25 #include "ecore_hsi_init_func.h"
26 #include "ecore_hsi_init_tool.h"
27 #include "ecore_proto_if.h"
28 #include "mcp_public.h"
30 #define ECORE_MAJOR_VERSION 8
31 #define ECORE_MINOR_VERSION 40
32 #define ECORE_REVISION_VERSION 26
33 #define ECORE_ENGINEERING_VERSION 0
35 #define ECORE_VERSION \
36 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \
37 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
39 #define STORM_FW_VERSION \
40 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
41 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
43 #define IS_ECORE_PACING(p_hwfn) \
44 (!!(p_hwfn->b_en_pacing))
46 #define MAX_HWFNS_PER_DEVICE 2
47 #define NAME_SIZE 128 /* @DPDK */
48 #define ECORE_WFQ_UNIT 100
49 #include "../qede_logs.h" /* @DPDK */
51 #define ISCSI_BDQ_ID(_port_id) (_port_id)
52 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
54 #define ECORE_WID_SIZE (1024)
55 #define ECORE_MIN_WIDS (4)
58 #define ECORE_PF_DEMS_SIZE (4)
61 enum ecore_coalescing_mode {
62 ECORE_COAL_MODE_DISABLE,
63 ECORE_COAL_MODE_ENABLE
67 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
68 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
69 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
70 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
71 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
72 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
73 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
74 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
75 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
76 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
77 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
78 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
82 #if !defined(CONFIG_ECORE_L2)
83 #define CONFIG_ECORE_L2
84 #define CONFIG_ECORE_SRIOV
89 #ifndef __EXTRACT__LINUX__
90 #define MASK_FIELD(_name, _value) \
91 ((_value) &= (_name##_MASK))
93 #define FIELD_VALUE(_name, _value) \
94 ((_value & _name##_MASK) << _name##_SHIFT)
96 #define SET_FIELD(value, name, flag) \
98 (value) &= ~(name##_MASK << name##_SHIFT); \
99 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
102 #define GET_FIELD(value, name) \
103 (((value) >> (name##_SHIFT)) & name##_MASK)
105 #define GET_MFW_FIELD(name, field) \
106 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
108 #define SET_MFW_FIELD(name, field, value) \
110 (name) &= ~((field ## _MASK)); \
111 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
115 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
117 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
118 (cid * ECORE_PF_DEMS_SIZE);
123 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
125 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
126 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
131 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
132 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
133 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
137 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
141 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
145 #ifndef __EXTRACT__LINUX__
147 ECORE_LEVEL_VERBOSE = 0x0,
148 ECORE_LEVEL_INFO = 0x1,
149 ECORE_LEVEL_NOTICE = 0x2,
150 ECORE_LEVEL_ERR = 0x3,
153 #define ECORE_LOG_LEVEL_SHIFT (30)
154 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
155 #define ECORE_LOG_INFO_MASK (0x40000000)
156 #define ECORE_LOG_NOTICE_MASK (0x80000000)
160 ECORE_MSG_DRV = 0x0001,
161 ECORE_MSG_PROBE = 0x0002,
162 ECORE_MSG_LINK = 0x0004,
163 ECORE_MSG_TIMER = 0x0008,
164 ECORE_MSG_IFDOWN = 0x0010,
165 ECORE_MSG_IFUP = 0x0020,
166 ECORE_MSG_RX_ERR = 0x0040,
167 ECORE_MSG_TX_ERR = 0x0080,
168 ECORE_MSG_TX_QUEUED = 0x0100,
169 ECORE_MSG_INTR = 0x0200,
170 ECORE_MSG_TX_DONE = 0x0400,
171 ECORE_MSG_RX_STATUS = 0x0800,
172 ECORE_MSG_PKTDATA = 0x1000,
173 ECORE_MSG_HW = 0x2000,
174 ECORE_MSG_WOL = 0x4000,
176 ECORE_MSG_SPQ = 0x10000,
177 ECORE_MSG_STATS = 0x20000,
178 ECORE_MSG_DCB = 0x40000,
179 ECORE_MSG_IOV = 0x80000,
180 ECORE_MSG_SP = 0x100000,
181 ECORE_MSG_STORAGE = 0x200000,
182 ECORE_MSG_OOO = 0x200000,
183 ECORE_MSG_CXT = 0x800000,
184 ECORE_MSG_LL2 = 0x1000000,
185 ECORE_MSG_ILT = 0x2000000,
186 ECORE_MSG_RDMA = 0x4000000,
187 ECORE_MSG_DEBUG = 0x8000000,
188 /* to be added...up to 0x8000000 */
192 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
194 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
195 (val == (cond1) ? true1 : \
196 (val == (cond2) ? true2 : def))
199 struct ecore_ptt_pool;
201 struct ecore_sb_info;
202 struct ecore_sb_attn_info;
203 struct ecore_cxt_mngr;
204 struct ecore_dma_mem;
205 struct ecore_sb_sp_info;
206 struct ecore_ll2_info;
207 struct ecore_l2_info;
208 struct ecore_igu_info;
209 struct ecore_mcp_info;
210 struct ecore_dcbx_info;
211 struct ecore_llh_info;
213 struct ecore_rt_data {
218 enum ecore_tunn_mode {
219 ECORE_MODE_L2GENEVE_TUNN,
220 ECORE_MODE_IPGENEVE_TUNN,
221 ECORE_MODE_L2GRE_TUNN,
222 ECORE_MODE_IPGRE_TUNN,
223 ECORE_MODE_VXLAN_TUNN,
226 enum ecore_tunn_clss {
227 ECORE_TUNN_CLSS_MAC_VLAN,
228 ECORE_TUNN_CLSS_MAC_VNI,
229 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
230 ECORE_TUNN_CLSS_INNER_MAC_VNI,
231 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
235 struct ecore_tunn_update_type {
238 enum ecore_tunn_clss tun_cls;
241 struct ecore_tunn_update_udp_port {
246 struct ecore_tunnel_info {
247 struct ecore_tunn_update_type vxlan;
248 struct ecore_tunn_update_type l2_geneve;
249 struct ecore_tunn_update_type ip_geneve;
250 struct ecore_tunn_update_type l2_gre;
251 struct ecore_tunn_update_type ip_gre;
253 struct ecore_tunn_update_udp_port vxlan_port;
254 struct ecore_tunn_update_udp_port geneve_port;
256 bool b_update_rx_cls;
257 bool b_update_tx_cls;
260 /* The PCI personality is not quite synonymous to protocol ID:
261 * 1. All personalities need CORE connections
262 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
264 enum ecore_pci_personality {
271 ECORE_PCI_DEFAULT /* default in shmem */
274 /* All VFs are symmetric, all counters are PF + all VFs */
275 struct ecore_qm_iids {
281 #define MAX_PF_PER_PORT 8
283 /* HW / FW resources, output of features supported below, most information
284 * is received from MFW.
286 enum ecore_resources {
298 ECORE_RDMA_STATS_QUEUE,
301 /* This is needed only internally for matching against the IGU.
302 * In case of legacy MFW, would be set to `0'.
309 /* Features that require resources, given as input to the resource management
310 * algorithm, the output are the resources above
325 enum ecore_port_mode {
326 ECORE_PORT_MODE_DE_2X40G,
327 ECORE_PORT_MODE_DE_2X50G,
328 ECORE_PORT_MODE_DE_1X100G,
329 ECORE_PORT_MODE_DE_4X10G_F,
330 ECORE_PORT_MODE_DE_4X10G_E,
331 ECORE_PORT_MODE_DE_4X20G,
332 ECORE_PORT_MODE_DE_1X40G,
333 ECORE_PORT_MODE_DE_2X25G,
334 ECORE_PORT_MODE_DE_1X25G,
335 ECORE_PORT_MODE_DE_4X25G,
336 ECORE_PORT_MODE_DE_2X10G,
347 #ifndef __EXTRACT__LINUX__
348 enum ecore_hw_err_type {
349 ECORE_HW_ERR_FAN_FAIL,
350 ECORE_HW_ERR_MFW_RESP_FAIL,
351 ECORE_HW_ERR_HW_ATTN,
352 ECORE_HW_ERR_DMAE_FAIL,
353 ECORE_HW_ERR_RAMROD_FAIL,
354 ECORE_HW_ERR_FW_ASSERT,
358 enum ecore_db_rec_exec {
364 struct ecore_hw_info {
365 /* PCI personality */
366 enum ecore_pci_personality personality;
367 #define ECORE_IS_RDMA_PERSONALITY(dev) \
368 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
369 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
370 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
371 #define ECORE_IS_ROCE_PERSONALITY(dev) \
372 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
373 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
374 #define ECORE_IS_IWARP_PERSONALITY(dev) \
375 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
376 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
377 #define ECORE_IS_L2_PERSONALITY(dev) \
378 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
379 ECORE_IS_RDMA_PERSONALITY(dev))
380 #define ECORE_IS_FCOE_PERSONALITY(dev) \
381 ((dev)->hw_info.personality == ECORE_PCI_FCOE)
382 #define ECORE_IS_ISCSI_PERSONALITY(dev) \
383 ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
385 /* Resource Allocation scheme results */
386 u32 resc_start[ECORE_MAX_RESC];
387 u32 resc_num[ECORE_MAX_RESC];
388 u32 feat_num[ECORE_MAX_FEATURES];
390 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
391 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
392 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
393 RESC_NUM(_p_hwfn, resc))
394 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
396 /* Amount of traffic classes HW supports */
399 /* Amount of TCs which should be active according to DCBx or upper layer driver
405 /* The traffic class used by PF for it's offloaded protocol */
413 unsigned char hw_mac_addr[ETH_ALEN];
414 u64 node_wwn; /* For FCoE only */
415 u64 port_wwn; /* For FCoE only */
420 struct ecore_igu_info *p_igu_info;
422 u8 max_chains_per_vf;
426 u32 device_capabilities;
428 /* Default DCBX mode */
434 /* maximun size of read/write commands (HW limit) */
435 #define DMAE_MAX_RW_SIZE 0x2000
437 struct ecore_dmae_info {
438 /* Spinlock for synchronizing access to functions */
439 osal_spinlock_t lock;
445 dma_addr_t completion_word_phys_addr;
447 /* The memory location where the DMAE writes the completion
448 * value when an operation is finished on this context.
450 u32 *p_completion_word;
452 dma_addr_t intermediate_buffer_phys_addr;
454 /* An intermediate buffer for DMAE operations that use virtual
455 * addresses - data is DMA'd to/from this buffer and then
456 * memcpy'd to/from the virtual address
458 u32 *p_intermediate_buffer;
460 dma_addr_t dmae_cmd_phys_addr;
461 struct dmae_cmd *p_dmae_cmd;
464 struct ecore_wfq_data {
465 u32 default_min_speed; /* When wfq feature is not configured */
466 u32 min_speed; /* when feature is configured for any 1 vport */
470 #define OFLD_GRP_SIZE 4
472 struct ecore_qm_info {
473 struct init_qm_pq_params *qm_pq_params;
474 struct init_qm_vport_params *qm_vport_params;
475 struct init_qm_port_params *qm_port_params;
488 u8 max_phys_tcs_per_port;
496 struct ecore_wfq_data *wfq_data;
500 struct ecore_db_recovery_info {
502 osal_spinlock_t lock;
503 u32 db_recovery_counter;
511 struct ecore_fw_data {
512 #ifdef CONFIG_ECORE_BINARY_FW
513 struct fw_ver_info *fw_ver_info;
515 const u8 *modes_tree_buf;
516 union init_op *init_ops;
518 const u32 *fw_overlays;
523 enum ecore_mf_mode_bit {
524 /* Supports PF-classification based on tag */
527 /* Supports PF-classification based on MAC */
528 ECORE_MF_LLH_MAC_CLSS,
530 /* Supports PF-classification based on protocol type */
531 ECORE_MF_LLH_PROTO_CLSS,
533 /* Requires a default PF to be set */
534 ECORE_MF_NEED_DEF_PF,
536 /* Allow LL2 to multicast/broadcast */
537 ECORE_MF_LL2_NON_UNICAST,
539 /* Allow Cross-PF [& child VFs] Tx-switching */
540 ECORE_MF_INTER_PF_SWITCH,
542 /* TODO - if we ever re-utilize any of this logic, we can rename */
543 ECORE_MF_UFP_SPECIFIC,
545 ECORE_MF_DISABLE_ARFS,
547 /* Use vlan for steering */
548 ECORE_MF_8021Q_TAGGING,
550 /* Use stag for steering */
551 ECORE_MF_8021AD_TAGGING,
553 /* Allow FIP discovery fallback */
554 ECORE_MF_FIP_SPECIAL,
557 enum ecore_ufp_mode {
559 ECORE_UFP_MODE_VNIC_BW,
562 enum ecore_ufp_pri_type {
567 struct ecore_ufp_info {
568 enum ecore_ufp_pri_type pri_type;
569 enum ecore_ufp_mode mode;
574 BAR_ID_0, /* used for GRC */
575 BAR_ID_1 /* Used for doorbells */
579 struct ecore_dev *p_dev;
580 u8 my_id; /* ID inside the PF */
581 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
582 u8 rel_pf_id; /* Relative to engine*/
584 #define ECORE_PATH_ID(_p_hwfn) \
585 (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
591 char name[NAME_SIZE];
594 bool first_on_engine;
597 u8 num_funcs_on_engine;
599 u8 num_funcs_on_port;
602 void OSAL_IOMEM *regview;
603 void OSAL_IOMEM *doorbells;
605 unsigned long db_size;
608 struct ecore_ptt_pool *p_ptt_pool;
611 struct ecore_hw_info hw_info;
613 /* rt_array (for init-tool) */
614 struct ecore_rt_data rt_data;
617 struct ecore_spq *p_spq;
620 struct ecore_eq *p_eq;
623 struct ecore_consq *p_consq;
625 /* Slow-Path definitions */
627 bool b_sp_dpc_enabled;
629 struct ecore_ptt *p_main_ptt;
630 struct ecore_ptt *p_dpc_ptt;
632 struct ecore_sb_sp_info *p_sp_sb;
633 struct ecore_sb_attn_info *p_sb_attn;
635 /* Protocol related */
637 struct ecore_ll2_info *p_ll2_info;
638 struct ecore_ooo_info *p_ooo_info;
639 struct ecore_iscsi_info *p_iscsi_info;
640 struct ecore_fcoe_info *p_fcoe_info;
641 struct ecore_rdma_info *p_rdma_info;
642 struct ecore_pf_params pf_params;
644 bool b_rdma_enabled_in_prs;
645 u32 rdma_prs_search_reg;
647 struct ecore_cxt_mngr *p_cxt_mngr;
649 /* Flag indicating whether interrupts are enabled or not*/
651 bool b_int_requested;
653 /* True if the driver requests for the link */
654 bool b_drv_link_init;
656 struct ecore_vf_iov *vf_iov_info;
657 struct ecore_pf_iov *pf_iov_info;
658 struct ecore_mcp_info *mcp_info;
659 struct ecore_dcbx_info *p_dcbx_info;
660 struct ecore_ufp_info ufp_info;
662 struct ecore_dmae_info dmae_info;
665 struct ecore_qm_info qm_info;
667 #ifdef CONFIG_ECORE_ZIPPED_FW
668 /* Buffer for unzipping firmware data */
672 struct dbg_tools_data dbg_info;
675 struct z_stream_s *stream;
677 /* PWM region specific data */
680 u32 dpi_start_offset; /* this is used to
685 /* If one of the following is set then EDPM shouldn't be used */
690 struct ecore_l2_info *p_l2_info;
692 /* Mechanism for recovering from doorbell drop */
693 struct ecore_db_recovery_info db_recovery_info;
695 /* Enable/disable pacing, if request to enable then
696 * IOV and mcos configuration will be skipped.
697 * this actually reflects the value requested in
698 * struct ecore_hw_prepare_params by ecore client.
702 struct phys_mem_desc *fw_overlay_mem;
705 struct ecore_ptt *p_arfs_ptt;
716 struct ecore_dbg_feature {
722 enum qed_dbg_features {
725 DBG_FEATURE_IDLE_CHK,
726 DBG_FEATURE_MCP_TRACE,
727 DBG_FEATURE_REG_FIFO,
728 DBG_FEATURE_PROTECTION_OVERRIDE,
732 enum ecore_dev_type {
740 char name[NAME_SIZE];
743 enum ecore_dev_type type;
744 /* Translate type/revision combo into the proper conditions */
745 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
746 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
748 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
749 (CHIP_REV_IS_TEDIBEAR(dev)))
751 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
753 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
754 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
758 #define ECORE_DEV_ID_MASK 0xff00
759 #define ECORE_DEV_ID_MASK_BB 0x1600
760 #define ECORE_DEV_ID_MASK_AH 0x8000
763 #define CHIP_NUM_MASK 0xffff
764 #define CHIP_NUM_SHIFT 0
767 #define CHIP_REV_MASK 0xf
768 #define CHIP_REV_SHIFT 0
770 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
771 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
772 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
773 #define CHIP_REV_IS_EMUL(_p_dev) \
774 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
775 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
776 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
777 #define CHIP_REV_IS_FPGA(_p_dev) \
778 (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
779 #define CHIP_REV_IS_SLOW(_p_dev) \
780 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
781 #define CHIP_REV_IS_A0(_p_dev) \
782 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
783 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
784 #define CHIP_REV_IS_B0(_p_dev) \
785 (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
786 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
787 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
789 #define CHIP_REV_IS_A0(_p_dev) \
790 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
791 #define CHIP_REV_IS_B0(_p_dev) \
792 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
796 #define CHIP_METAL_MASK 0xff
797 #define CHIP_METAL_SHIFT 0
800 #define CHIP_BOND_ID_MASK 0xff
801 #define CHIP_BOND_ID_SHIFT 0
805 u8 num_ports_in_engine;
806 u8 num_funcs_in_port;
811 enum ecore_mf_mode mf_mode;
812 #define IS_MF_DEFAULT(_p_hwfn) \
813 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
814 #define IS_MF_SI(_p_hwfn) \
815 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
816 #define IS_MF_SD(_p_hwfn) \
817 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
822 /* Add MF related configuration */
829 enum ecore_coalescing_mode int_coalescing_mode;
830 u16 rx_coalesce_usecs;
831 u16 tx_coalesce_usecs;
833 /* Start Bar offset of first hwfn */
834 void OSAL_IOMEM *regview;
835 void OSAL_IOMEM *doorbells;
837 unsigned long db_size;
844 #define IRO ((const struct iro *)p_hwfn->p_dev->iro_arr)
848 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
849 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
850 #define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1)
852 /* Engine affinity */
856 /* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */
857 #define ECORE_FIR_AFFIN_HWFN(dev) (&dev->hwfns[dev->fir_affin])
858 /* Macro for getting the engine-affinitized hwfn for iWARP */
859 #define ECORE_IWARP_AFFIN_HWFN(dev) (&dev->hwfns[dev->iwarp_affin])
860 /* Generic macro for getting the engine-affinitized hwfn */
861 #define ECORE_AFFIN_HWFN(dev) \
862 (ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \
863 ECORE_IWARP_AFFIN_HWFN(dev) : \
864 ECORE_FIR_AFFIN_HWFN(dev))
865 /* Macro for getting the index (0/1) of the engine-affinitized hwfn */
866 #define ECORE_AFFIN_HWFN_IDX(dev) \
867 (IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1)
870 struct ecore_hw_sriov_info *p_iov_info;
871 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
872 struct ecore_tunnel_info tunnel;
874 bool b_dont_override_vf_msix;
880 u32 rdma_max_srq_sge;
882 struct ecore_eth_stats *reset_stats;
883 struct ecore_fw_data *fw_data;
890 /* Indicates whether should prevent attentions from being reasserted */
894 /* Indicates whether allowing the MFW to collect a crash dump */
897 /* Indicates if the reg_fifo is checked after any register access */
906 struct ecore_llh_info *p_llh_info;
908 /* Indicates whether this PF serves a storage target */
911 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
917 struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
921 enum ecore_hsi_def_type {
922 ECORE_HSI_DEF_MAX_NUM_VFS,
923 ECORE_HSI_DEF_MAX_NUM_L2_QUEUES,
924 ECORE_HSI_DEF_MAX_NUM_PORTS,
925 ECORE_HSI_DEF_MAX_SB_PER_PATH,
926 ECORE_HSI_DEF_MAX_NUM_PFS,
927 ECORE_HSI_DEF_MAX_NUM_VPORTS,
928 ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE,
929 ECORE_HSI_DEF_MAX_QM_TX_QUEUES,
930 ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS,
931 ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
932 ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS,
933 ECORE_HSI_DEF_MAX_PBF_CMD_LINES,
934 ECORE_HSI_DEF_MAX_BTB_BLOCKS,
938 u32 ecore_get_hsi_def_val(struct ecore_dev *p_dev,
939 enum ecore_hsi_def_type type);
941 #define NUM_OF_VFS(dev) \
942 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VFS)
943 #define NUM_OF_L2_QUEUES(dev) \
944 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_L2_QUEUES)
945 #define NUM_OF_PORTS(dev) \
946 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PORTS)
947 #define NUM_OF_SBS(dev) \
948 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_SB_PER_PATH)
949 #define NUM_OF_ENG_PFS(dev) \
950 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PFS)
951 #define NUM_OF_VPORTS(dev) \
952 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VPORTS)
953 #define NUM_OF_RSS_ENGINES(dev) \
954 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE)
955 #define NUM_OF_QM_TX_QUEUES(dev) \
956 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_TX_QUEUES)
957 #define NUM_OF_PXP_ILT_RECORDS(dev) \
958 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS)
959 #define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
960 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
961 #define NUM_OF_QM_GLOBAL_RLS(dev) \
962 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS)
963 #define NUM_OF_PBF_CMD_LINES(dev) \
964 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_PBF_CMD_LINES)
965 #define NUM_OF_BTB_BLOCKS(dev) \
966 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_BTB_BLOCKS)
968 #define CRC8_TABLE_SIZE 256
971 * @brief ecore_concrete_to_sw_fid - get the sw function id from
972 * the concrete value.
974 * @param concrete_fid
976 * @return OSAL_INLINE u8
978 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
980 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
981 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
982 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
986 sw_fid = vfid + MAX_NUM_PFS;
995 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
996 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
997 struct ecore_ptt *p_ptt,
1000 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
1001 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
1002 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
1003 int ecore_device_num_engines(struct ecore_dev *p_dev);
1004 int ecore_device_num_ports(struct ecore_dev *p_dev);
1005 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
1008 /* Flags for indication of required queues */
1009 #define PQ_FLAGS_RLS (1 << 0)
1010 #define PQ_FLAGS_MCOS (1 << 1)
1011 #define PQ_FLAGS_LB (1 << 2)
1012 #define PQ_FLAGS_OOO (1 << 3)
1013 #define PQ_FLAGS_ACK (1 << 4)
1014 #define PQ_FLAGS_OFLD (1 << 5)
1015 #define PQ_FLAGS_VFS (1 << 6)
1016 #define PQ_FLAGS_LLT (1 << 7)
1018 /* physical queue index for cm context intialization */
1019 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
1020 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
1021 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
1022 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
1024 /* qm vport for rate limit configuration */
1025 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
1027 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
1029 /* doorbell recovery mechanism */
1030 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
1031 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
1032 enum ecore_db_rec_exec);
1034 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn);
1036 /* amount of resources used in qm init */
1037 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
1038 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
1039 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
1040 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
1041 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
1043 #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
1044 ecore_device_num_ports((_p_hwfn)->p_dev))
1046 /* The PFID<->PPFID calculation is based on the relative index of a PF on its
1047 * port. In BB there is a bug in the LLH in which the PPFID is actually engine
1048 * based, and thus it equals the PFID.
1050 #define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \
1051 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
1053 (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \
1055 #define ECORE_PPFID_BY_PFID(_p_hwfn) \
1056 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
1057 (_p_hwfn)->rel_pf_id : \
1058 (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine)
1060 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1061 struct ecore_ptt *p_ptt, u32 addr,
1064 /* Utility functions for dumping the content of the NIG LLH filters */
1065 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);
1066 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);
1068 #define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A
1070 #define MSTORM_QZONE_START(dev) \
1071 (TSTORM_QZONE_START + (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
1073 #endif /* __ECORE_H */