1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
15 #define CONFIG_ECORE_BINARY_FW
16 #undef CONFIG_ECORE_ZIPPED_FW
18 #ifdef CONFIG_ECORE_ZIPPED_FW
22 #include "ecore_status.h"
23 #include "ecore_hsi_common.h"
24 #include "ecore_hsi_debug_tools.h"
25 #include "ecore_hsi_init_func.h"
26 #include "ecore_hsi_init_tool.h"
27 #include "ecore_hsi_func_common.h"
28 #include "ecore_proto_if.h"
29 #include "mcp_public.h"
31 #define ECORE_MAJOR_VERSION 8
32 #define ECORE_MINOR_VERSION 40
33 #define ECORE_REVISION_VERSION 26
34 #define ECORE_ENGINEERING_VERSION 0
36 #define ECORE_VERSION \
37 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \
38 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
40 #define STORM_FW_VERSION \
41 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
42 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
44 #define IS_ECORE_PACING(p_hwfn) \
45 (!!(p_hwfn->b_en_pacing))
47 #define MAX_HWFNS_PER_DEVICE 2
48 #define NAME_SIZE 128 /* @DPDK */
49 #define ECORE_WFQ_UNIT 100
50 #include "../qede_logs.h" /* @DPDK */
52 #define ISCSI_BDQ_ID(_port_id) (_port_id)
53 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
55 #define ECORE_WID_SIZE (1024)
56 #define ECORE_MIN_WIDS (4)
59 #define ECORE_PF_DEMS_SIZE (4)
62 enum ecore_coalescing_mode {
63 ECORE_COAL_MODE_DISABLE,
64 ECORE_COAL_MODE_ENABLE
68 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
69 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
70 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
71 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
72 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
73 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
74 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
75 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
76 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
77 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
78 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
79 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
83 #if !defined(CONFIG_ECORE_L2)
84 #define CONFIG_ECORE_L2
85 #define CONFIG_ECORE_SRIOV
90 #ifndef __EXTRACT__LINUX__
91 #define MASK_FIELD(_name, _value) \
92 ((_value) &= (_name##_MASK))
94 #define FIELD_VALUE(_name, _value) \
95 ((_value & _name##_MASK) << _name##_SHIFT)
97 #define SET_FIELD(value, name, flag) \
99 (value) &= ~(name##_MASK << name##_SHIFT); \
100 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
103 #define GET_FIELD(value, name) \
104 (((value) >> (name##_SHIFT)) & name##_MASK)
106 #define GET_MFW_FIELD(name, field) \
107 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
109 #define SET_MFW_FIELD(name, field, value) \
111 (name) &= ~((field ## _MASK)); \
112 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
116 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
118 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
119 (cid * ECORE_PF_DEMS_SIZE);
124 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
126 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
127 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
132 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
133 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
134 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
138 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
142 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
146 #ifndef __EXTRACT__LINUX__
148 ECORE_LEVEL_VERBOSE = 0x0,
149 ECORE_LEVEL_INFO = 0x1,
150 ECORE_LEVEL_NOTICE = 0x2,
151 ECORE_LEVEL_ERR = 0x3,
154 #define ECORE_LOG_LEVEL_SHIFT (30)
155 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
156 #define ECORE_LOG_INFO_MASK (0x40000000)
157 #define ECORE_LOG_NOTICE_MASK (0x80000000)
161 ECORE_MSG_DRV = 0x0001,
162 ECORE_MSG_PROBE = 0x0002,
163 ECORE_MSG_LINK = 0x0004,
164 ECORE_MSG_TIMER = 0x0008,
165 ECORE_MSG_IFDOWN = 0x0010,
166 ECORE_MSG_IFUP = 0x0020,
167 ECORE_MSG_RX_ERR = 0x0040,
168 ECORE_MSG_TX_ERR = 0x0080,
169 ECORE_MSG_TX_QUEUED = 0x0100,
170 ECORE_MSG_INTR = 0x0200,
171 ECORE_MSG_TX_DONE = 0x0400,
172 ECORE_MSG_RX_STATUS = 0x0800,
173 ECORE_MSG_PKTDATA = 0x1000,
174 ECORE_MSG_HW = 0x2000,
175 ECORE_MSG_WOL = 0x4000,
177 ECORE_MSG_SPQ = 0x10000,
178 ECORE_MSG_STATS = 0x20000,
179 ECORE_MSG_DCB = 0x40000,
180 ECORE_MSG_IOV = 0x80000,
181 ECORE_MSG_SP = 0x100000,
182 ECORE_MSG_STORAGE = 0x200000,
183 ECORE_MSG_OOO = 0x200000,
184 ECORE_MSG_CXT = 0x800000,
185 ECORE_MSG_LL2 = 0x1000000,
186 ECORE_MSG_ILT = 0x2000000,
187 ECORE_MSG_RDMA = 0x4000000,
188 ECORE_MSG_DEBUG = 0x8000000,
189 /* to be added...up to 0x8000000 */
193 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
195 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
196 (val == (cond1) ? true1 : \
197 (val == (cond2) ? true2 : def))
200 struct ecore_ptt_pool;
202 struct ecore_sb_info;
203 struct ecore_sb_attn_info;
204 struct ecore_cxt_mngr;
205 struct ecore_dma_mem;
206 struct ecore_sb_sp_info;
207 struct ecore_ll2_info;
208 struct ecore_l2_info;
209 struct ecore_igu_info;
210 struct ecore_mcp_info;
211 struct ecore_dcbx_info;
212 struct ecore_llh_info;
214 struct ecore_rt_data {
219 enum ecore_tunn_mode {
220 ECORE_MODE_L2GENEVE_TUNN,
221 ECORE_MODE_IPGENEVE_TUNN,
222 ECORE_MODE_L2GRE_TUNN,
223 ECORE_MODE_IPGRE_TUNN,
224 ECORE_MODE_VXLAN_TUNN,
227 enum ecore_tunn_clss {
228 ECORE_TUNN_CLSS_MAC_VLAN,
229 ECORE_TUNN_CLSS_MAC_VNI,
230 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
231 ECORE_TUNN_CLSS_INNER_MAC_VNI,
232 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
236 struct ecore_tunn_update_type {
239 enum ecore_tunn_clss tun_cls;
242 struct ecore_tunn_update_udp_port {
247 struct ecore_tunnel_info {
248 struct ecore_tunn_update_type vxlan;
249 struct ecore_tunn_update_type l2_geneve;
250 struct ecore_tunn_update_type ip_geneve;
251 struct ecore_tunn_update_type l2_gre;
252 struct ecore_tunn_update_type ip_gre;
254 struct ecore_tunn_update_udp_port vxlan_port;
255 struct ecore_tunn_update_udp_port geneve_port;
257 bool b_update_rx_cls;
258 bool b_update_tx_cls;
261 /* The PCI personality is not quite synonymous to protocol ID:
262 * 1. All personalities need CORE connections
263 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
265 enum ecore_pci_personality {
272 ECORE_PCI_DEFAULT /* default in shmem */
275 /* All VFs are symmetric, all counters are PF + all VFs */
276 struct ecore_qm_iids {
282 #define MAX_PF_PER_PORT 8
284 /* HW / FW resources, output of features supported below, most information
285 * is received from MFW.
287 enum ecore_resources {
299 ECORE_RDMA_STATS_QUEUE,
302 /* This is needed only internally for matching against the IGU.
303 * In case of legacy MFW, would be set to `0'.
310 /* Features that require resources, given as input to the resource management
311 * algorithm, the output are the resources above
326 enum ecore_port_mode {
327 ECORE_PORT_MODE_DE_2X40G,
328 ECORE_PORT_MODE_DE_2X50G,
329 ECORE_PORT_MODE_DE_1X100G,
330 ECORE_PORT_MODE_DE_4X10G_F,
331 ECORE_PORT_MODE_DE_4X10G_E,
332 ECORE_PORT_MODE_DE_4X20G,
333 ECORE_PORT_MODE_DE_1X40G,
334 ECORE_PORT_MODE_DE_2X25G,
335 ECORE_PORT_MODE_DE_1X25G,
336 ECORE_PORT_MODE_DE_4X25G,
337 ECORE_PORT_MODE_DE_2X10G,
348 #ifndef __EXTRACT__LINUX__
349 enum ecore_hw_err_type {
350 ECORE_HW_ERR_FAN_FAIL,
351 ECORE_HW_ERR_MFW_RESP_FAIL,
352 ECORE_HW_ERR_HW_ATTN,
353 ECORE_HW_ERR_DMAE_FAIL,
354 ECORE_HW_ERR_RAMROD_FAIL,
355 ECORE_HW_ERR_FW_ASSERT,
359 enum ecore_db_rec_exec {
365 struct ecore_hw_info {
366 /* PCI personality */
367 enum ecore_pci_personality personality;
368 #define ECORE_IS_RDMA_PERSONALITY(dev) \
369 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
370 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
371 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
372 #define ECORE_IS_ROCE_PERSONALITY(dev) \
373 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
374 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
375 #define ECORE_IS_IWARP_PERSONALITY(dev) \
376 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
377 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
378 #define ECORE_IS_L2_PERSONALITY(dev) \
379 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
380 ECORE_IS_RDMA_PERSONALITY(dev))
381 #define ECORE_IS_FCOE_PERSONALITY(dev) \
382 ((dev)->hw_info.personality == ECORE_PCI_FCOE)
383 #define ECORE_IS_ISCSI_PERSONALITY(dev) \
384 ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
386 /* Resource Allocation scheme results */
387 u32 resc_start[ECORE_MAX_RESC];
388 u32 resc_num[ECORE_MAX_RESC];
389 u32 feat_num[ECORE_MAX_FEATURES];
391 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
392 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
393 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
394 RESC_NUM(_p_hwfn, resc))
395 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
397 /* Amount of traffic classes HW supports */
400 /* Amount of TCs which should be active according to DCBx or upper layer driver
406 /* The traffic class used by PF for it's offloaded protocol */
414 unsigned char hw_mac_addr[ETH_ALEN];
415 u64 node_wwn; /* For FCoE only */
416 u64 port_wwn; /* For FCoE only */
421 struct ecore_igu_info *p_igu_info;
423 u8 max_chains_per_vf;
427 u32 device_capabilities;
429 /* Default DCBX mode */
435 /* maximun size of read/write commands (HW limit) */
436 #define DMAE_MAX_RW_SIZE 0x2000
438 struct ecore_dmae_info {
439 /* Spinlock for synchronizing access to functions */
440 osal_spinlock_t lock;
446 dma_addr_t completion_word_phys_addr;
448 /* The memory location where the DMAE writes the completion
449 * value when an operation is finished on this context.
451 u32 *p_completion_word;
453 dma_addr_t intermediate_buffer_phys_addr;
455 /* An intermediate buffer for DMAE operations that use virtual
456 * addresses - data is DMA'd to/from this buffer and then
457 * memcpy'd to/from the virtual address
459 u32 *p_intermediate_buffer;
461 dma_addr_t dmae_cmd_phys_addr;
462 struct dmae_cmd *p_dmae_cmd;
465 struct ecore_wfq_data {
466 u32 default_min_speed; /* When wfq feature is not configured */
467 u32 min_speed; /* when feature is configured for any 1 vport */
471 #define OFLD_GRP_SIZE 4
473 struct ecore_qm_info {
474 struct init_qm_pq_params *qm_pq_params;
475 struct init_qm_vport_params *qm_vport_params;
476 struct init_qm_port_params *qm_port_params;
489 u8 max_phys_tcs_per_port;
497 struct ecore_wfq_data *wfq_data;
501 struct ecore_db_recovery_info {
503 osal_spinlock_t lock;
504 u32 db_recovery_counter;
512 struct ecore_fw_data {
513 #ifdef CONFIG_ECORE_BINARY_FW
514 struct fw_ver_info *fw_ver_info;
516 const u8 *modes_tree_buf;
517 union init_op *init_ops;
519 const u32 *fw_overlays;
524 enum ecore_mf_mode_bit {
525 /* Supports PF-classification based on tag */
528 /* Supports PF-classification based on MAC */
529 ECORE_MF_LLH_MAC_CLSS,
531 /* Supports PF-classification based on protocol type */
532 ECORE_MF_LLH_PROTO_CLSS,
534 /* Requires a default PF to be set */
535 ECORE_MF_NEED_DEF_PF,
537 /* Allow LL2 to multicast/broadcast */
538 ECORE_MF_LL2_NON_UNICAST,
540 /* Allow Cross-PF [& child VFs] Tx-switching */
541 ECORE_MF_INTER_PF_SWITCH,
543 /* TODO - if we ever re-utilize any of this logic, we can rename */
544 ECORE_MF_UFP_SPECIFIC,
546 ECORE_MF_DISABLE_ARFS,
548 /* Use vlan for steering */
549 ECORE_MF_8021Q_TAGGING,
551 /* Use stag for steering */
552 ECORE_MF_8021AD_TAGGING,
554 /* Allow FIP discovery fallback */
555 ECORE_MF_FIP_SPECIAL,
558 enum ecore_ufp_mode {
560 ECORE_UFP_MODE_VNIC_BW,
563 enum ecore_ufp_pri_type {
568 struct ecore_ufp_info {
569 enum ecore_ufp_pri_type pri_type;
570 enum ecore_ufp_mode mode;
575 BAR_ID_0, /* used for GRC */
576 BAR_ID_1 /* Used for doorbells */
579 struct ecore_nvm_image_info {
581 struct bist_nvm_image_att *image_att;
586 struct ecore_dev *p_dev;
587 u8 my_id; /* ID inside the PF */
588 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
589 u8 rel_pf_id; /* Relative to engine*/
591 #define ECORE_PATH_ID(_p_hwfn) \
592 (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
598 char name[NAME_SIZE];
601 bool first_on_engine;
604 u8 num_funcs_on_engine;
606 u8 num_funcs_on_port;
609 void OSAL_IOMEM *regview;
610 void OSAL_IOMEM *doorbells;
612 unsigned long db_size;
615 struct ecore_ptt_pool *p_ptt_pool;
618 struct ecore_hw_info hw_info;
620 /* rt_array (for init-tool) */
621 struct ecore_rt_data rt_data;
624 struct ecore_spq *p_spq;
627 struct ecore_eq *p_eq;
630 struct ecore_consq *p_consq;
632 /* Slow-Path definitions */
634 bool b_sp_dpc_enabled;
636 struct ecore_ptt *p_main_ptt;
637 struct ecore_ptt *p_dpc_ptt;
639 struct ecore_sb_sp_info *p_sp_sb;
640 struct ecore_sb_attn_info *p_sb_attn;
642 /* Protocol related */
644 struct ecore_ll2_info *p_ll2_info;
645 struct ecore_ooo_info *p_ooo_info;
646 struct ecore_iscsi_info *p_iscsi_info;
647 struct ecore_fcoe_info *p_fcoe_info;
648 struct ecore_rdma_info *p_rdma_info;
649 struct ecore_pf_params pf_params;
651 bool b_rdma_enabled_in_prs;
652 u32 rdma_prs_search_reg;
654 struct ecore_cxt_mngr *p_cxt_mngr;
656 /* Flag indicating whether interrupts are enabled or not*/
658 bool b_int_requested;
660 /* True if the driver requests for the link */
661 bool b_drv_link_init;
663 struct ecore_vf_iov *vf_iov_info;
664 struct ecore_pf_iov *pf_iov_info;
665 struct ecore_mcp_info *mcp_info;
666 struct ecore_dcbx_info *p_dcbx_info;
667 struct ecore_ufp_info ufp_info;
669 struct ecore_dmae_info dmae_info;
672 struct ecore_qm_info qm_info;
674 #ifdef CONFIG_ECORE_ZIPPED_FW
675 /* Buffer for unzipping firmware data */
679 struct dbg_tools_data dbg_info;
681 struct virt_mem_desc dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];
683 struct z_stream_s *stream;
685 /* PWM region specific data */
688 u32 dpi_start_offset; /* this is used to
693 /* If one of the following is set then EDPM shouldn't be used */
698 struct ecore_l2_info *p_l2_info;
700 /* Mechanism for recovering from doorbell drop */
701 struct ecore_db_recovery_info db_recovery_info;
703 /* Enable/disable pacing, if request to enable then
704 * IOV and mcos configuration will be skipped.
705 * this actually reflects the value requested in
706 * struct ecore_hw_prepare_params by ecore client.
710 /* Nvm images number and attributes */
711 struct ecore_nvm_image_info nvm_info;
713 struct phys_mem_desc *fw_overlay_mem;
716 struct ecore_ptt *p_arfs_ptt;
726 enum ecore_dev_type {
732 enum ecore_dbg_features {
734 DBG_FEATURE_IDLE_CHK,
735 DBG_FEATURE_MCP_TRACE,
736 DBG_FEATURE_REG_FIFO,
737 DBG_FEATURE_IGU_FIFO,
738 DBG_FEATURE_PROTECTION_OVERRIDE,
739 DBG_FEATURE_FW_ASSERTS,
744 struct ecore_dbg_feature {
750 struct ecore_dbg_params {
751 struct ecore_dbg_feature features[DBG_FEATURE_NUM];
759 char name[NAME_SIZE];
762 enum ecore_dev_type type;
763 /* Translate type/revision combo into the proper conditions */
764 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
765 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
767 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
768 (CHIP_REV_IS_TEDIBEAR(dev)))
770 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
772 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
773 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
777 #define ECORE_DEV_ID_MASK 0xff00
778 #define ECORE_DEV_ID_MASK_BB 0x1600
779 #define ECORE_DEV_ID_MASK_AH 0x8000
782 #define CHIP_NUM_MASK 0xffff
783 #define CHIP_NUM_SHIFT 0
786 #define CHIP_REV_MASK 0xf
787 #define CHIP_REV_SHIFT 0
789 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
790 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
791 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
792 #define CHIP_REV_IS_EMUL(_p_dev) \
793 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
794 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
795 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
796 #define CHIP_REV_IS_FPGA(_p_dev) \
797 (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
798 #define CHIP_REV_IS_SLOW(_p_dev) \
799 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
800 #define CHIP_REV_IS_A0(_p_dev) \
801 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
802 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
803 #define CHIP_REV_IS_B0(_p_dev) \
804 (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
805 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
806 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
808 #define CHIP_REV_IS_A0(_p_dev) \
809 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
810 #define CHIP_REV_IS_B0(_p_dev) \
811 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
815 #define CHIP_METAL_MASK 0xff
816 #define CHIP_METAL_SHIFT 0
819 #define CHIP_BOND_ID_MASK 0xff
820 #define CHIP_BOND_ID_SHIFT 0
824 u8 num_ports_in_engine;
825 u8 num_funcs_in_port;
830 enum ecore_mf_mode mf_mode;
831 #define IS_MF_DEFAULT(_p_hwfn) \
832 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
833 #define IS_MF_SI(_p_hwfn) \
834 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
835 #define IS_MF_SD(_p_hwfn) \
836 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
841 /* Add MF related configuration */
848 enum ecore_coalescing_mode int_coalescing_mode;
849 u16 rx_coalesce_usecs;
850 u16 tx_coalesce_usecs;
852 /* Start Bar offset of first hwfn */
853 void OSAL_IOMEM *regview;
854 void OSAL_IOMEM *doorbells;
856 unsigned long db_size;
863 #define IRO ((const struct iro *)p_hwfn->p_dev->iro_arr)
867 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
868 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
869 #define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1)
871 /* Engine affinity */
875 /* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */
876 #define ECORE_FIR_AFFIN_HWFN(dev) (&dev->hwfns[dev->fir_affin])
877 /* Macro for getting the engine-affinitized hwfn for iWARP */
878 #define ECORE_IWARP_AFFIN_HWFN(dev) (&dev->hwfns[dev->iwarp_affin])
879 /* Generic macro for getting the engine-affinitized hwfn */
880 #define ECORE_AFFIN_HWFN(dev) \
881 (ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \
882 ECORE_IWARP_AFFIN_HWFN(dev) : \
883 ECORE_FIR_AFFIN_HWFN(dev))
884 /* Macro for getting the index (0/1) of the engine-affinitized hwfn */
885 #define ECORE_AFFIN_HWFN_IDX(dev) \
886 (IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1)
889 struct ecore_hw_sriov_info *p_iov_info;
890 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
891 struct ecore_tunnel_info tunnel;
893 bool b_dont_override_vf_msix;
899 u32 rdma_max_srq_sge;
901 struct ecore_eth_stats *reset_stats;
902 struct ecore_fw_data *fw_data;
909 /* Indicates whether should prevent attentions from being reasserted */
913 /* Indicates whether allowing the MFW to collect a crash dump */
916 /* Indicates if the reg_fifo is checked after any register access */
925 struct ecore_llh_info *p_llh_info;
927 /* Indicates whether this PF serves a storage target */
930 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
934 bool disable_ilt_dump;
937 struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
938 struct ecore_dbg_params dbg_params;
939 osal_mutex_t dbg_lock;
941 /* DPDK specific ecore field */
942 struct rte_pci_device *pci_dev;
945 enum ecore_hsi_def_type {
946 ECORE_HSI_DEF_MAX_NUM_VFS,
947 ECORE_HSI_DEF_MAX_NUM_L2_QUEUES,
948 ECORE_HSI_DEF_MAX_NUM_PORTS,
949 ECORE_HSI_DEF_MAX_SB_PER_PATH,
950 ECORE_HSI_DEF_MAX_NUM_PFS,
951 ECORE_HSI_DEF_MAX_NUM_VPORTS,
952 ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE,
953 ECORE_HSI_DEF_MAX_QM_TX_QUEUES,
954 ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS,
955 ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
956 ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS,
957 ECORE_HSI_DEF_MAX_PBF_CMD_LINES,
958 ECORE_HSI_DEF_MAX_BTB_BLOCKS,
962 u32 ecore_get_hsi_def_val(struct ecore_dev *p_dev,
963 enum ecore_hsi_def_type type);
965 #define NUM_OF_VFS(dev) \
966 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VFS)
967 #define NUM_OF_L2_QUEUES(dev) \
968 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_L2_QUEUES)
969 #define NUM_OF_PORTS(dev) \
970 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PORTS)
971 #define NUM_OF_SBS(dev) \
972 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_SB_PER_PATH)
973 #define NUM_OF_ENG_PFS(dev) \
974 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PFS)
975 #define NUM_OF_VPORTS(dev) \
976 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VPORTS)
977 #define NUM_OF_RSS_ENGINES(dev) \
978 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE)
979 #define NUM_OF_QM_TX_QUEUES(dev) \
980 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_TX_QUEUES)
981 #define NUM_OF_PXP_ILT_RECORDS(dev) \
982 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS)
983 #define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
984 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
985 #define NUM_OF_QM_GLOBAL_RLS(dev) \
986 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS)
987 #define NUM_OF_PBF_CMD_LINES(dev) \
988 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_PBF_CMD_LINES)
989 #define NUM_OF_BTB_BLOCKS(dev) \
990 ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_BTB_BLOCKS)
992 #define CRC8_TABLE_SIZE 256
995 * @brief ecore_concrete_to_sw_fid - get the sw function id from
996 * the concrete value.
998 * @param concrete_fid
1000 * @return OSAL_INLINE u8
1002 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
1004 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
1005 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
1006 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
1010 sw_fid = vfid + MAX_NUM_PFS;
1019 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
1020 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
1021 struct ecore_ptt *p_ptt,
1024 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
1025 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
1026 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
1027 int ecore_device_num_engines(struct ecore_dev *p_dev);
1028 int ecore_device_num_ports(struct ecore_dev *p_dev);
1029 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
1032 /* Flags for indication of required queues */
1033 #define PQ_FLAGS_RLS (1 << 0)
1034 #define PQ_FLAGS_MCOS (1 << 1)
1035 #define PQ_FLAGS_LB (1 << 2)
1036 #define PQ_FLAGS_OOO (1 << 3)
1037 #define PQ_FLAGS_ACK (1 << 4)
1038 #define PQ_FLAGS_OFLD (1 << 5)
1039 #define PQ_FLAGS_VFS (1 << 6)
1040 #define PQ_FLAGS_LLT (1 << 7)
1042 /* physical queue index for cm context intialization */
1043 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
1044 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
1045 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
1046 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
1048 /* qm vport for rate limit configuration */
1049 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
1051 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
1053 /* doorbell recovery mechanism */
1054 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
1055 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
1056 enum ecore_db_rec_exec);
1058 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn);
1060 /* amount of resources used in qm init */
1061 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
1062 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
1063 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
1064 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
1065 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
1067 #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
1068 ecore_device_num_ports((_p_hwfn)->p_dev))
1070 /* The PFID<->PPFID calculation is based on the relative index of a PF on its
1071 * port. In BB there is a bug in the LLH in which the PPFID is actually engine
1072 * based, and thus it equals the PFID.
1074 #define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \
1075 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
1077 (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \
1079 #define ECORE_PPFID_BY_PFID(_p_hwfn) \
1080 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
1081 (_p_hwfn)->rel_pf_id : \
1082 (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine)
1084 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1085 struct ecore_ptt *p_ptt, u32 addr,
1088 /* Utility functions for dumping the content of the NIG LLH filters */
1089 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);
1090 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);
1093 * @brief ecore_set_platform_str - Set the debug dump platform string.
1094 * Write the ecore version and device's string to the given buffer.
1100 void ecore_set_platform_str(struct ecore_hwfn *p_hwfn,
1101 char *buf_str, u32 buf_size);
1103 #define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A
1105 #define MSTORM_QZONE_START(dev) \
1106 (TSTORM_QZONE_START + (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
1108 #endif /* __ECORE_H */