1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __ATTN_VALUES_H__
8 #define __ATTN_VALUES_H__
10 #ifndef __PREVENT_INT_ATTN__
12 /* HW Attention register */
14 u16 reg_idx; /* Index of this register in its block */
15 u16 num_of_bits; /* number of valid attention bits */
16 const u16 *bit_attn_idx; /* attention index per valid bit */
17 u32 sts_addr; /* Address of the STS register */
18 u32 sts_clr_addr; /* Address of the STS_CLR register */
19 u32 sts_wr_addr; /* Address of the STS_WR register */
20 u32 mask_addr; /* Address of the MASK register */
23 /* HW block attention registers */
25 u16 num_of_int_regs; /* Number of interrupt regs */
26 u16 num_of_prty_regs; /* Number of parity regs */
27 struct attn_hw_reg **int_regs; /* interrupt regs */
28 struct attn_hw_reg **prty_regs; /* parity regs */
31 /* HW block attention registers */
32 struct attn_hw_block {
33 const char *name; /* Block name */
34 const char **int_desc; /* Array of interrupt attention descriptions */
35 const char **prty_desc; /* Array of parity attention descriptions */
36 struct attn_hw_regs chip_regs[3]; /* attention regs per chip.*/
40 static const char *grc_int_attn_desc[5] = {
43 "grc_global_reserved_address",
44 "grc_path_isolation_error",
45 "grc_trace_fifo_valid_data",
48 #define grc_int_attn_desc OSAL_NULL
51 static const u16 grc_int0_bb_a0_attn_idx[4] = {
55 static struct attn_hw_reg grc_int0_bb_a0 = {
56 0, 4, grc_int0_bb_a0_attn_idx, 0x50180, 0x5018c, 0x50188, 0x50184
59 static struct attn_hw_reg *grc_int_bb_a0_regs[1] = {
63 static const u16 grc_int0_bb_b0_attn_idx[4] = {
67 static struct attn_hw_reg grc_int0_bb_b0 = {
68 0, 4, grc_int0_bb_b0_attn_idx, 0x50180, 0x5018c, 0x50188, 0x50184
71 static struct attn_hw_reg *grc_int_bb_b0_regs[1] = {
75 static const u16 grc_int0_k2_attn_idx[5] = {
79 static struct attn_hw_reg grc_int0_k2 = {
80 0, 5, grc_int0_k2_attn_idx, 0x50180, 0x5018c, 0x50188, 0x50184
83 static struct attn_hw_reg *grc_int_k2_regs[1] = {
88 static const char *grc_prty_attn_desc[3] = {
89 "grc_mem003_i_mem_prty",
90 "grc_mem002_i_mem_prty",
91 "grc_mem001_i_mem_prty",
94 #define grc_prty_attn_desc OSAL_NULL
97 static const u16 grc_prty1_bb_a0_attn_idx[2] = {
101 static struct attn_hw_reg grc_prty1_bb_a0 = {
102 0, 2, grc_prty1_bb_a0_attn_idx, 0x50200, 0x5020c, 0x50208, 0x50204
105 static struct attn_hw_reg *grc_prty_bb_a0_regs[1] = {
109 static const u16 grc_prty1_bb_b0_attn_idx[2] = {
113 static struct attn_hw_reg grc_prty1_bb_b0 = {
114 0, 2, grc_prty1_bb_b0_attn_idx, 0x50200, 0x5020c, 0x50208, 0x50204
117 static struct attn_hw_reg *grc_prty_bb_b0_regs[1] = {
121 static const u16 grc_prty1_k2_attn_idx[2] = {
125 static struct attn_hw_reg grc_prty1_k2 = {
126 0, 2, grc_prty1_k2_attn_idx, 0x50200, 0x5020c, 0x50208, 0x50204
129 static struct attn_hw_reg *grc_prty_k2_regs[1] = {
134 static const char *miscs_int_attn_desc[14] = {
135 "miscs_address_error",
137 "miscs_cnig_interrupt",
138 "miscs_opte_dorq_fifo_err_eng1",
139 "miscs_opte_dorq_fifo_err_eng0",
140 "miscs_opte_dbg_fifo_err_eng1",
141 "miscs_opte_dbg_fifo_err_eng0",
142 "miscs_opte_btb_if1_fifo_err_eng1",
143 "miscs_opte_btb_if1_fifo_err_eng0",
144 "miscs_opte_btb_if0_fifo_err_eng1",
145 "miscs_opte_btb_if0_fifo_err_eng0",
146 "miscs_opte_btb_sop_fifo_err_eng1",
147 "miscs_opte_btb_sop_fifo_err_eng0",
148 "miscs_opte_storm_fifo_err_eng0",
151 #define miscs_int_attn_desc OSAL_NULL
154 static const u16 miscs_int0_bb_a0_attn_idx[2] = {
158 static struct attn_hw_reg miscs_int0_bb_a0 = {
159 0, 2, miscs_int0_bb_a0_attn_idx, 0x9180, 0x918c, 0x9188, 0x9184
162 static const u16 miscs_int1_bb_a0_attn_idx[11] = {
163 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
166 static struct attn_hw_reg miscs_int1_bb_a0 = {
167 1, 11, miscs_int1_bb_a0_attn_idx, 0x9190, 0x919c, 0x9198, 0x9194
170 static struct attn_hw_reg *miscs_int_bb_a0_regs[2] = {
171 &miscs_int0_bb_a0, &miscs_int1_bb_a0,
174 static const u16 miscs_int0_bb_b0_attn_idx[3] = {
178 static struct attn_hw_reg miscs_int0_bb_b0 = {
179 0, 3, miscs_int0_bb_b0_attn_idx, 0x9180, 0x918c, 0x9188, 0x9184
182 static const u16 miscs_int1_bb_b0_attn_idx[11] = {
183 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
186 static struct attn_hw_reg miscs_int1_bb_b0 = {
187 1, 11, miscs_int1_bb_b0_attn_idx, 0x9190, 0x919c, 0x9198, 0x9194
190 static struct attn_hw_reg *miscs_int_bb_b0_regs[2] = {
191 &miscs_int0_bb_b0, &miscs_int1_bb_b0,
194 static const u16 miscs_int0_k2_attn_idx[3] = {
198 static struct attn_hw_reg miscs_int0_k2 = {
199 0, 3, miscs_int0_k2_attn_idx, 0x9180, 0x918c, 0x9188, 0x9184
202 static struct attn_hw_reg *miscs_int_k2_regs[1] = {
207 static const char *miscs_prty_attn_desc[1] = {
211 #define miscs_prty_attn_desc OSAL_NULL
214 static const u16 miscs_prty0_bb_b0_attn_idx[1] = {
218 static struct attn_hw_reg miscs_prty0_bb_b0 = {
219 0, 1, miscs_prty0_bb_b0_attn_idx, 0x91a0, 0x91ac, 0x91a8, 0x91a4
222 static struct attn_hw_reg *miscs_prty_bb_b0_regs[1] = {
226 static const u16 miscs_prty0_k2_attn_idx[1] = {
230 static struct attn_hw_reg miscs_prty0_k2 = {
231 0, 1, miscs_prty0_k2_attn_idx, 0x91a0, 0x91ac, 0x91a8, 0x91a4
234 static struct attn_hw_reg *miscs_prty_k2_regs[1] = {
239 static const char *misc_int_attn_desc[1] = {
240 "misc_address_error",
243 #define misc_int_attn_desc OSAL_NULL
246 static const u16 misc_int0_bb_a0_attn_idx[1] = {
250 static struct attn_hw_reg misc_int0_bb_a0 = {
251 0, 1, misc_int0_bb_a0_attn_idx, 0x8180, 0x818c, 0x8188, 0x8184
254 static struct attn_hw_reg *misc_int_bb_a0_regs[1] = {
258 static const u16 misc_int0_bb_b0_attn_idx[1] = {
262 static struct attn_hw_reg misc_int0_bb_b0 = {
263 0, 1, misc_int0_bb_b0_attn_idx, 0x8180, 0x818c, 0x8188, 0x8184
266 static struct attn_hw_reg *misc_int_bb_b0_regs[1] = {
270 static const u16 misc_int0_k2_attn_idx[1] = {
274 static struct attn_hw_reg misc_int0_k2 = {
275 0, 1, misc_int0_k2_attn_idx, 0x8180, 0x818c, 0x8188, 0x8184
278 static struct attn_hw_reg *misc_int_k2_regs[1] = {
283 static const char *pglue_b_int_attn_desc[24] = {
284 "pglue_b_address_error",
285 "pglue_b_incorrect_rcv_behavior",
286 "pglue_b_was_error_attn",
287 "pglue_b_vf_length_violation_attn",
288 "pglue_b_vf_grc_space_violation_attn",
289 "pglue_b_tcpl_error_attn",
290 "pglue_b_tcpl_in_two_rcbs_attn",
291 "pglue_b_cssnoop_fifo_overflow",
292 "pglue_b_tcpl_translation_size_different",
293 "pglue_b_pcie_rx_l0s_timeout",
294 "pglue_b_master_zlr_attn",
295 "pglue_b_admin_window_violation_attn",
296 "pglue_b_out_of_range_function_in_pretend",
297 "pglue_b_illegal_address",
298 "pglue_b_pgl_cpl_err",
299 "pglue_b_pgl_txw_of",
300 "pglue_b_pgl_cpl_aft",
301 "pglue_b_pgl_cpl_of",
302 "pglue_b_pgl_cpl_ecrc",
303 "pglue_b_pgl_pcie_attn",
304 "pglue_b_pgl_read_blocked",
305 "pglue_b_pgl_write_blocked",
306 "pglue_b_vf_ilt_err",
307 "pglue_b_rxobffexception_attn",
310 #define pglue_b_int_attn_desc OSAL_NULL
313 static const u16 pglue_b_int0_bb_a0_attn_idx[23] = {
314 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
319 static struct attn_hw_reg pglue_b_int0_bb_a0 = {
320 0, 23, pglue_b_int0_bb_a0_attn_idx, 0x2a8180, 0x2a818c, 0x2a8188,
324 static struct attn_hw_reg *pglue_b_int_bb_a0_regs[1] = {
328 static const u16 pglue_b_int0_bb_b0_attn_idx[23] = {
329 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
334 static struct attn_hw_reg pglue_b_int0_bb_b0 = {
335 0, 23, pglue_b_int0_bb_b0_attn_idx, 0x2a8180, 0x2a818c, 0x2a8188,
339 static struct attn_hw_reg *pglue_b_int_bb_b0_regs[1] = {
343 static const u16 pglue_b_int0_k2_attn_idx[24] = {
344 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
349 static struct attn_hw_reg pglue_b_int0_k2 = {
350 0, 24, pglue_b_int0_k2_attn_idx, 0x2a8180, 0x2a818c, 0x2a8188, 0x2a8184
353 static struct attn_hw_reg *pglue_b_int_k2_regs[1] = {
358 static const char *pglue_b_prty_attn_desc[35] = {
359 "pglue_b_datapath_registers",
360 "pglue_b_mem027_i_mem_prty",
361 "pglue_b_mem007_i_mem_prty",
362 "pglue_b_mem009_i_mem_prty",
363 "pglue_b_mem010_i_mem_prty",
364 "pglue_b_mem008_i_mem_prty",
365 "pglue_b_mem022_i_mem_prty",
366 "pglue_b_mem023_i_mem_prty",
367 "pglue_b_mem024_i_mem_prty",
368 "pglue_b_mem025_i_mem_prty",
369 "pglue_b_mem004_i_mem_prty",
370 "pglue_b_mem005_i_mem_prty",
371 "pglue_b_mem011_i_mem_prty",
372 "pglue_b_mem016_i_mem_prty",
373 "pglue_b_mem017_i_mem_prty",
374 "pglue_b_mem012_i_mem_prty",
375 "pglue_b_mem013_i_mem_prty",
376 "pglue_b_mem014_i_mem_prty",
377 "pglue_b_mem015_i_mem_prty",
378 "pglue_b_mem018_i_mem_prty",
379 "pglue_b_mem020_i_mem_prty",
380 "pglue_b_mem021_i_mem_prty",
381 "pglue_b_mem019_i_mem_prty",
382 "pglue_b_mem026_i_mem_prty",
383 "pglue_b_mem006_i_mem_prty",
384 "pglue_b_mem003_i_mem_prty",
385 "pglue_b_mem002_i_mem_prty_0",
386 "pglue_b_mem002_i_mem_prty_1",
387 "pglue_b_mem002_i_mem_prty_2",
388 "pglue_b_mem002_i_mem_prty_3",
389 "pglue_b_mem002_i_mem_prty_4",
390 "pglue_b_mem002_i_mem_prty_5",
391 "pglue_b_mem002_i_mem_prty_6",
392 "pglue_b_mem002_i_mem_prty_7",
393 "pglue_b_mem001_i_mem_prty",
396 #define pglue_b_prty_attn_desc OSAL_NULL
399 static const u16 pglue_b_prty1_bb_a0_attn_idx[22] = {
400 2, 3, 4, 5, 10, 11, 12, 15, 16, 17, 18, 24, 25, 26, 27, 28, 29, 30, 31,
404 static struct attn_hw_reg pglue_b_prty1_bb_a0 = {
405 0, 22, pglue_b_prty1_bb_a0_attn_idx, 0x2a8200, 0x2a820c, 0x2a8208,
409 static struct attn_hw_reg *pglue_b_prty_bb_a0_regs[1] = {
410 &pglue_b_prty1_bb_a0,
413 static const u16 pglue_b_prty0_bb_b0_attn_idx[1] = {
417 static struct attn_hw_reg pglue_b_prty0_bb_b0 = {
418 0, 1, pglue_b_prty0_bb_b0_attn_idx, 0x2a8190, 0x2a819c, 0x2a8198,
422 static const u16 pglue_b_prty1_bb_b0_attn_idx[22] = {
423 2, 3, 4, 5, 10, 11, 12, 15, 16, 17, 18, 24, 25, 26, 27, 28, 29, 30, 31,
427 static struct attn_hw_reg pglue_b_prty1_bb_b0 = {
428 1, 22, pglue_b_prty1_bb_b0_attn_idx, 0x2a8200, 0x2a820c, 0x2a8208,
432 static struct attn_hw_reg *pglue_b_prty_bb_b0_regs[2] = {
433 &pglue_b_prty0_bb_b0, &pglue_b_prty1_bb_b0,
436 static const u16 pglue_b_prty0_k2_attn_idx[1] = {
440 static struct attn_hw_reg pglue_b_prty0_k2 = {
441 0, 1, pglue_b_prty0_k2_attn_idx, 0x2a8190, 0x2a819c, 0x2a8198, 0x2a8194
444 static const u16 pglue_b_prty1_k2_attn_idx[31] = {
445 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
447 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
450 static struct attn_hw_reg pglue_b_prty1_k2 = {
451 1, 31, pglue_b_prty1_k2_attn_idx, 0x2a8200, 0x2a820c, 0x2a8208,
455 static const u16 pglue_b_prty2_k2_attn_idx[3] = {
459 static struct attn_hw_reg pglue_b_prty2_k2 = {
460 2, 3, pglue_b_prty2_k2_attn_idx, 0x2a8210, 0x2a821c, 0x2a8218, 0x2a8214
463 static struct attn_hw_reg *pglue_b_prty_k2_regs[3] = {
464 &pglue_b_prty0_k2, &pglue_b_prty1_k2, &pglue_b_prty2_k2,
468 static const char *cnig_int_attn_desc[10] = {
469 "cnig_address_error",
470 "cnig_tx_illegal_sop_port0",
471 "cnig_tx_illegal_sop_port1",
472 "cnig_tx_illegal_sop_port2",
473 "cnig_tx_illegal_sop_port3",
474 "cnig_tdm_lane_0_bandwidth_exceed",
475 "cnig_tdm_lane_1_bandwidth_exceed",
481 #define cnig_int_attn_desc OSAL_NULL
484 static const u16 cnig_int0_bb_a0_attn_idx[4] = {
488 static struct attn_hw_reg cnig_int0_bb_a0 = {
489 0, 4, cnig_int0_bb_a0_attn_idx, 0x2182e8, 0x2182f4, 0x2182f0, 0x2182ec
492 static struct attn_hw_reg *cnig_int_bb_a0_regs[1] = {
496 static const u16 cnig_int0_bb_b0_attn_idx[6] = {
500 static struct attn_hw_reg cnig_int0_bb_b0 = {
501 0, 6, cnig_int0_bb_b0_attn_idx, 0x2182e8, 0x2182f4, 0x2182f0, 0x2182ec
504 static struct attn_hw_reg *cnig_int_bb_b0_regs[1] = {
508 static const u16 cnig_int0_k2_attn_idx[7] = {
512 static struct attn_hw_reg cnig_int0_k2 = {
513 0, 7, cnig_int0_k2_attn_idx, 0x218218, 0x218224, 0x218220, 0x21821c
516 static struct attn_hw_reg *cnig_int_k2_regs[1] = {
521 static const char *cnig_prty_attn_desc[3] = {
527 #define cnig_prty_attn_desc OSAL_NULL
530 static const u16 cnig_prty0_bb_b0_attn_idx[2] = {
534 static struct attn_hw_reg cnig_prty0_bb_b0 = {
535 0, 2, cnig_prty0_bb_b0_attn_idx, 0x218348, 0x218354, 0x218350, 0x21834c
538 static struct attn_hw_reg *cnig_prty_bb_b0_regs[1] = {
542 static const u16 cnig_prty0_k2_attn_idx[1] = {
546 static struct attn_hw_reg cnig_prty0_k2 = {
547 0, 1, cnig_prty0_k2_attn_idx, 0x21822c, 0x218238, 0x218234, 0x218230
550 static struct attn_hw_reg *cnig_prty_k2_regs[1] = {
555 static const char *cpmu_int_attn_desc[1] = {
556 "cpmu_address_error",
559 #define cpmu_int_attn_desc OSAL_NULL
562 static const u16 cpmu_int0_bb_a0_attn_idx[1] = {
566 static struct attn_hw_reg cpmu_int0_bb_a0 = {
567 0, 1, cpmu_int0_bb_a0_attn_idx, 0x303e0, 0x303ec, 0x303e8, 0x303e4
570 static struct attn_hw_reg *cpmu_int_bb_a0_regs[1] = {
574 static const u16 cpmu_int0_bb_b0_attn_idx[1] = {
578 static struct attn_hw_reg cpmu_int0_bb_b0 = {
579 0, 1, cpmu_int0_bb_b0_attn_idx, 0x303e0, 0x303ec, 0x303e8, 0x303e4
582 static struct attn_hw_reg *cpmu_int_bb_b0_regs[1] = {
586 static const u16 cpmu_int0_k2_attn_idx[1] = {
590 static struct attn_hw_reg cpmu_int0_k2 = {
591 0, 1, cpmu_int0_k2_attn_idx, 0x303e0, 0x303ec, 0x303e8, 0x303e4
594 static struct attn_hw_reg *cpmu_int_k2_regs[1] = {
599 static const char *ncsi_int_attn_desc[1] = {
600 "ncsi_address_error",
603 #define ncsi_int_attn_desc OSAL_NULL
606 static const u16 ncsi_int0_bb_a0_attn_idx[1] = {
610 static struct attn_hw_reg ncsi_int0_bb_a0 = {
611 0, 1, ncsi_int0_bb_a0_attn_idx, 0x404cc, 0x404d8, 0x404d4, 0x404d0
614 static struct attn_hw_reg *ncsi_int_bb_a0_regs[1] = {
618 static const u16 ncsi_int0_bb_b0_attn_idx[1] = {
622 static struct attn_hw_reg ncsi_int0_bb_b0 = {
623 0, 1, ncsi_int0_bb_b0_attn_idx, 0x404cc, 0x404d8, 0x404d4, 0x404d0
626 static struct attn_hw_reg *ncsi_int_bb_b0_regs[1] = {
630 static const u16 ncsi_int0_k2_attn_idx[1] = {
634 static struct attn_hw_reg ncsi_int0_k2 = {
635 0, 1, ncsi_int0_k2_attn_idx, 0x404cc, 0x404d8, 0x404d4, 0x404d0
638 static struct attn_hw_reg *ncsi_int_k2_regs[1] = {
643 static const char *ncsi_prty_attn_desc[1] = {
644 "ncsi_mem002_i_mem_prty",
647 #define ncsi_prty_attn_desc OSAL_NULL
650 static const u16 ncsi_prty1_bb_a0_attn_idx[1] = {
654 static struct attn_hw_reg ncsi_prty1_bb_a0 = {
655 0, 1, ncsi_prty1_bb_a0_attn_idx, 0x40000, 0x4000c, 0x40008, 0x40004
658 static struct attn_hw_reg *ncsi_prty_bb_a0_regs[1] = {
662 static const u16 ncsi_prty1_bb_b0_attn_idx[1] = {
666 static struct attn_hw_reg ncsi_prty1_bb_b0 = {
667 0, 1, ncsi_prty1_bb_b0_attn_idx, 0x40000, 0x4000c, 0x40008, 0x40004
670 static struct attn_hw_reg *ncsi_prty_bb_b0_regs[1] = {
674 static const u16 ncsi_prty1_k2_attn_idx[1] = {
678 static struct attn_hw_reg ncsi_prty1_k2 = {
679 0, 1, ncsi_prty1_k2_attn_idx, 0x40000, 0x4000c, 0x40008, 0x40004
682 static struct attn_hw_reg *ncsi_prty_k2_regs[1] = {
687 static const char *opte_prty_attn_desc[12] = {
688 "opte_mem009_i_mem_prty",
689 "opte_mem010_i_mem_prty",
690 "opte_mem005_i_mem_prty",
691 "opte_mem006_i_mem_prty",
692 "opte_mem007_i_mem_prty",
693 "opte_mem008_i_mem_prty",
694 "opte_mem001_i_mem_prty",
695 "opte_mem002_i_mem_prty",
696 "opte_mem003_i_mem_prty",
697 "opte_mem004_i_mem_prty",
698 "opte_mem011_i_mem_prty",
699 "opte_datapath_parity_error",
702 #define opte_prty_attn_desc OSAL_NULL
705 static const u16 opte_prty1_bb_a0_attn_idx[11] = {
706 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
709 static struct attn_hw_reg opte_prty1_bb_a0 = {
710 0, 11, opte_prty1_bb_a0_attn_idx, 0x53000, 0x5300c, 0x53008, 0x53004
713 static struct attn_hw_reg *opte_prty_bb_a0_regs[1] = {
717 static const u16 opte_prty1_bb_b0_attn_idx[11] = {
718 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
721 static struct attn_hw_reg opte_prty1_bb_b0 = {
722 0, 11, opte_prty1_bb_b0_attn_idx, 0x53000, 0x5300c, 0x53008, 0x53004
725 static const u16 opte_prty0_bb_b0_attn_idx[1] = {
729 static struct attn_hw_reg opte_prty0_bb_b0 = {
730 1, 1, opte_prty0_bb_b0_attn_idx, 0x53208, 0x53214, 0x53210, 0x5320c
733 static struct attn_hw_reg *opte_prty_bb_b0_regs[2] = {
734 &opte_prty1_bb_b0, &opte_prty0_bb_b0,
737 static const u16 opte_prty1_k2_attn_idx[11] = {
738 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
741 static struct attn_hw_reg opte_prty1_k2 = {
742 0, 11, opte_prty1_k2_attn_idx, 0x53000, 0x5300c, 0x53008, 0x53004
745 static const u16 opte_prty0_k2_attn_idx[1] = {
749 static struct attn_hw_reg opte_prty0_k2 = {
750 1, 1, opte_prty0_k2_attn_idx, 0x53208, 0x53214, 0x53210, 0x5320c
753 static struct attn_hw_reg *opte_prty_k2_regs[2] = {
754 &opte_prty1_k2, &opte_prty0_k2,
758 static const char *bmb_int_attn_desc[297] = {
760 "bmb_rc_pkt0_rls_error",
762 "bmb_rc_pkt0_protocol_error",
763 "bmb_rc_pkt1_rls_error",
765 "bmb_rc_pkt1_protocol_error",
766 "bmb_rc_pkt2_rls_error",
768 "bmb_rc_pkt2_protocol_error",
769 "bmb_rc_pkt3_rls_error",
771 "bmb_rc_pkt3_protocol_error",
772 "bmb_rc_sop_req_tc_port_error",
774 "bmb_wc0_protocol_error",
775 "bmb_wc1_protocol_error",
776 "bmb_wc2_protocol_error",
777 "bmb_wc3_protocol_error",
781 "bmb_mac0_fc_cnt_error",
782 "bmb_ll_arb_calc_error",
783 "bmb_wc0_inp_fifo_error",
784 "bmb_wc0_sop_fifo_error",
785 "bmb_wc0_len_fifo_error",
786 "bmb_wc0_queue_fifo_error",
787 "bmb_wc0_free_point_fifo_error",
788 "bmb_wc0_next_point_fifo_error",
789 "bmb_wc0_strt_fifo_error",
790 "bmb_wc0_second_dscr_fifo_error",
791 "bmb_wc0_pkt_avail_fifo_error",
792 "bmb_wc0_cos_cnt_fifo_error",
793 "bmb_wc0_notify_fifo_error",
794 "bmb_wc0_ll_req_fifo_error",
795 "bmb_wc0_ll_pa_cnt_error",
796 "bmb_wc0_bb_pa_cnt_error",
797 "bmb_wc1_inp_fifo_error",
798 "bmb_wc1_sop_fifo_error",
799 "bmb_wc1_queue_fifo_error",
800 "bmb_wc1_free_point_fifo_error",
801 "bmb_wc1_next_point_fifo_error",
802 "bmb_wc1_strt_fifo_error",
803 "bmb_wc1_second_dscr_fifo_error",
804 "bmb_wc1_pkt_avail_fifo_error",
805 "bmb_wc1_cos_cnt_fifo_error",
806 "bmb_wc1_notify_fifo_error",
807 "bmb_wc1_ll_req_fifo_error",
808 "bmb_wc1_ll_pa_cnt_error",
809 "bmb_wc1_bb_pa_cnt_error",
810 "bmb_wc2_inp_fifo_error",
811 "bmb_wc2_sop_fifo_error",
812 "bmb_wc2_queue_fifo_error",
813 "bmb_wc2_free_point_fifo_error",
814 "bmb_wc2_next_point_fifo_error",
815 "bmb_wc2_strt_fifo_error",
816 "bmb_wc2_second_dscr_fifo_error",
817 "bmb_wc2_pkt_avail_fifo_error",
818 "bmb_wc2_cos_cnt_fifo_error",
819 "bmb_wc2_notify_fifo_error",
820 "bmb_wc2_ll_req_fifo_error",
821 "bmb_wc2_ll_pa_cnt_error",
822 "bmb_wc2_bb_pa_cnt_error",
823 "bmb_wc3_inp_fifo_error",
824 "bmb_wc3_sop_fifo_error",
825 "bmb_wc3_queue_fifo_error",
826 "bmb_wc3_free_point_fifo_error",
827 "bmb_wc3_next_point_fifo_error",
828 "bmb_wc3_strt_fifo_error",
829 "bmb_wc3_second_dscr_fifo_error",
830 "bmb_wc3_pkt_avail_fifo_error",
831 "bmb_wc3_cos_cnt_fifo_error",
832 "bmb_wc3_notify_fifo_error",
833 "bmb_wc3_ll_req_fifo_error",
834 "bmb_wc3_ll_pa_cnt_error",
835 "bmb_wc3_bb_pa_cnt_error",
836 "bmb_rc_pkt0_side_fifo_error",
837 "bmb_rc_pkt0_req_fifo_error",
838 "bmb_rc_pkt0_blk_fifo_error",
839 "bmb_rc_pkt0_rls_left_fifo_error",
840 "bmb_rc_pkt0_strt_ptr_fifo_error",
841 "bmb_rc_pkt0_second_ptr_fifo_error",
842 "bmb_rc_pkt0_rsp_fifo_error",
843 "bmb_rc_pkt0_dscr_fifo_error",
844 "bmb_rc_pkt1_side_fifo_error",
845 "bmb_rc_pkt1_req_fifo_error",
846 "bmb_rc_pkt1_blk_fifo_error",
847 "bmb_rc_pkt1_rls_left_fifo_error",
848 "bmb_rc_pkt1_strt_ptr_fifo_error",
849 "bmb_rc_pkt1_second_ptr_fifo_error",
850 "bmb_rc_pkt1_rsp_fifo_error",
851 "bmb_rc_pkt1_dscr_fifo_error",
852 "bmb_rc_pkt2_side_fifo_error",
853 "bmb_rc_pkt2_req_fifo_error",
854 "bmb_rc_pkt2_blk_fifo_error",
855 "bmb_rc_pkt2_rls_left_fifo_error",
856 "bmb_rc_pkt2_strt_ptr_fifo_error",
857 "bmb_rc_pkt2_second_ptr_fifo_error",
858 "bmb_rc_pkt2_rsp_fifo_error",
859 "bmb_rc_pkt2_dscr_fifo_error",
860 "bmb_rc_pkt3_side_fifo_error",
861 "bmb_rc_pkt3_req_fifo_error",
862 "bmb_rc_pkt3_blk_fifo_error",
863 "bmb_rc_pkt3_rls_left_fifo_error",
864 "bmb_rc_pkt3_strt_ptr_fifo_error",
865 "bmb_rc_pkt3_second_ptr_fifo_error",
866 "bmb_rc_pkt3_rsp_fifo_error",
867 "bmb_rc_pkt3_dscr_fifo_error",
868 "bmb_rc_sop_strt_fifo_error",
869 "bmb_rc_sop_req_fifo_error",
870 "bmb_rc_sop_dscr_fifo_error",
871 "bmb_rc_sop_queue_fifo_error",
872 "bmb_ll_arb_rls_fifo_error",
873 "bmb_ll_arb_prefetch_fifo_error",
874 "bmb_rc_pkt0_rls_fifo_error",
875 "bmb_rc_pkt1_rls_fifo_error",
876 "bmb_rc_pkt2_rls_fifo_error",
877 "bmb_rc_pkt3_rls_fifo_error",
878 "bmb_rc_pkt4_rls_fifo_error",
879 "bmb_rc_pkt5_rls_fifo_error",
880 "bmb_rc_pkt6_rls_fifo_error",
881 "bmb_rc_pkt7_rls_fifo_error",
882 "bmb_rc_pkt8_rls_fifo_error",
883 "bmb_rc_pkt9_rls_fifo_error",
884 "bmb_rc_pkt4_rls_error",
885 "bmb_rc_pkt4_protocol_error",
886 "bmb_rc_pkt4_side_fifo_error",
887 "bmb_rc_pkt4_req_fifo_error",
888 "bmb_rc_pkt4_blk_fifo_error",
889 "bmb_rc_pkt4_rls_left_fifo_error",
890 "bmb_rc_pkt4_strt_ptr_fifo_error",
891 "bmb_rc_pkt4_second_ptr_fifo_error",
892 "bmb_rc_pkt4_rsp_fifo_error",
893 "bmb_rc_pkt4_dscr_fifo_error",
894 "bmb_rc_pkt5_rls_error",
895 "bmb_rc_pkt5_protocol_error",
896 "bmb_rc_pkt5_side_fifo_error",
897 "bmb_rc_pkt5_req_fifo_error",
898 "bmb_rc_pkt5_blk_fifo_error",
899 "bmb_rc_pkt5_rls_left_fifo_error",
900 "bmb_rc_pkt5_strt_ptr_fifo_error",
901 "bmb_rc_pkt5_second_ptr_fifo_error",
902 "bmb_rc_pkt5_rsp_fifo_error",
903 "bmb_rc_pkt5_dscr_fifo_error",
904 "bmb_rc_pkt6_rls_error",
905 "bmb_rc_pkt6_protocol_error",
906 "bmb_rc_pkt6_side_fifo_error",
907 "bmb_rc_pkt6_req_fifo_error",
908 "bmb_rc_pkt6_blk_fifo_error",
909 "bmb_rc_pkt6_rls_left_fifo_error",
910 "bmb_rc_pkt6_strt_ptr_fifo_error",
911 "bmb_rc_pkt6_second_ptr_fifo_error",
912 "bmb_rc_pkt6_rsp_fifo_error",
913 "bmb_rc_pkt6_dscr_fifo_error",
914 "bmb_rc_pkt7_rls_error",
915 "bmb_rc_pkt7_protocol_error",
916 "bmb_rc_pkt7_side_fifo_error",
917 "bmb_rc_pkt7_req_fifo_error",
918 "bmb_rc_pkt7_blk_fifo_error",
919 "bmb_rc_pkt7_rls_left_fifo_error",
920 "bmb_rc_pkt7_strt_ptr_fifo_error",
921 "bmb_rc_pkt7_second_ptr_fifo_error",
922 "bmb_rc_pkt7_rsp_fifo_error",
923 "bmb_packet_available_sync_fifo_push_error",
924 "bmb_rc_pkt8_rls_error",
925 "bmb_rc_pkt8_protocol_error",
926 "bmb_rc_pkt8_side_fifo_error",
927 "bmb_rc_pkt8_req_fifo_error",
928 "bmb_rc_pkt8_blk_fifo_error",
929 "bmb_rc_pkt8_rls_left_fifo_error",
930 "bmb_rc_pkt8_strt_ptr_fifo_error",
931 "bmb_rc_pkt8_second_ptr_fifo_error",
932 "bmb_rc_pkt8_rsp_fifo_error",
933 "bmb_rc_pkt8_dscr_fifo_error",
934 "bmb_rc_pkt9_rls_error",
935 "bmb_rc_pkt9_protocol_error",
936 "bmb_rc_pkt9_side_fifo_error",
937 "bmb_rc_pkt9_req_fifo_error",
938 "bmb_rc_pkt9_blk_fifo_error",
939 "bmb_rc_pkt9_rls_left_fifo_error",
940 "bmb_rc_pkt9_strt_ptr_fifo_error",
941 "bmb_rc_pkt9_second_ptr_fifo_error",
942 "bmb_rc_pkt9_rsp_fifo_error",
943 "bmb_rc_pkt9_dscr_fifo_error",
944 "bmb_wc4_protocol_error",
945 "bmb_wc5_protocol_error",
946 "bmb_wc6_protocol_error",
947 "bmb_wc7_protocol_error",
948 "bmb_wc8_protocol_error",
949 "bmb_wc9_protocol_error",
950 "bmb_wc4_inp_fifo_error",
951 "bmb_wc4_sop_fifo_error",
952 "bmb_wc4_queue_fifo_error",
953 "bmb_wc4_free_point_fifo_error",
954 "bmb_wc4_next_point_fifo_error",
955 "bmb_wc4_strt_fifo_error",
956 "bmb_wc4_second_dscr_fifo_error",
957 "bmb_wc4_pkt_avail_fifo_error",
958 "bmb_wc4_cos_cnt_fifo_error",
959 "bmb_wc4_notify_fifo_error",
960 "bmb_wc4_ll_req_fifo_error",
961 "bmb_wc4_ll_pa_cnt_error",
962 "bmb_wc4_bb_pa_cnt_error",
963 "bmb_wc5_inp_fifo_error",
964 "bmb_wc5_sop_fifo_error",
965 "bmb_wc5_queue_fifo_error",
966 "bmb_wc5_free_point_fifo_error",
967 "bmb_wc5_next_point_fifo_error",
968 "bmb_wc5_strt_fifo_error",
969 "bmb_wc5_second_dscr_fifo_error",
970 "bmb_wc5_pkt_avail_fifo_error",
971 "bmb_wc5_cos_cnt_fifo_error",
972 "bmb_wc5_notify_fifo_error",
973 "bmb_wc5_ll_req_fifo_error",
974 "bmb_wc5_ll_pa_cnt_error",
975 "bmb_wc5_bb_pa_cnt_error",
976 "bmb_wc6_inp_fifo_error",
977 "bmb_wc6_sop_fifo_error",
978 "bmb_wc6_queue_fifo_error",
979 "bmb_wc6_free_point_fifo_error",
980 "bmb_wc6_next_point_fifo_error",
981 "bmb_wc6_strt_fifo_error",
982 "bmb_wc6_second_dscr_fifo_error",
983 "bmb_wc6_pkt_avail_fifo_error",
984 "bmb_wc6_cos_cnt_fifo_error",
985 "bmb_wc6_notify_fifo_error",
986 "bmb_wc6_ll_req_fifo_error",
987 "bmb_wc6_ll_pa_cnt_error",
988 "bmb_wc6_bb_pa_cnt_error",
989 "bmb_wc7_inp_fifo_error",
990 "bmb_wc7_sop_fifo_error",
991 "bmb_wc7_queue_fifo_error",
992 "bmb_wc7_free_point_fifo_error",
993 "bmb_wc7_next_point_fifo_error",
994 "bmb_wc7_strt_fifo_error",
995 "bmb_wc7_second_dscr_fifo_error",
996 "bmb_wc7_pkt_avail_fifo_error",
997 "bmb_wc7_cos_cnt_fifo_error",
998 "bmb_wc7_notify_fifo_error",
999 "bmb_wc7_ll_req_fifo_error",
1000 "bmb_wc7_ll_pa_cnt_error",
1001 "bmb_wc7_bb_pa_cnt_error",
1002 "bmb_wc8_inp_fifo_error",
1003 "bmb_wc8_sop_fifo_error",
1004 "bmb_wc8_queue_fifo_error",
1005 "bmb_wc8_free_point_fifo_error",
1006 "bmb_wc8_next_point_fifo_error",
1007 "bmb_wc8_strt_fifo_error",
1008 "bmb_wc8_second_dscr_fifo_error",
1009 "bmb_wc8_pkt_avail_fifo_error",
1010 "bmb_wc8_cos_cnt_fifo_error",
1011 "bmb_wc8_notify_fifo_error",
1012 "bmb_wc8_ll_req_fifo_error",
1013 "bmb_wc8_ll_pa_cnt_error",
1014 "bmb_wc8_bb_pa_cnt_error",
1015 "bmb_wc9_inp_fifo_error",
1016 "bmb_wc9_sop_fifo_error",
1017 "bmb_wc9_queue_fifo_error",
1018 "bmb_wc9_free_point_fifo_error",
1019 "bmb_wc9_next_point_fifo_error",
1020 "bmb_wc9_strt_fifo_error",
1021 "bmb_wc9_second_dscr_fifo_error",
1022 "bmb_wc9_pkt_avail_fifo_error",
1023 "bmb_wc9_cos_cnt_fifo_error",
1024 "bmb_wc9_notify_fifo_error",
1025 "bmb_wc9_ll_req_fifo_error",
1026 "bmb_wc9_ll_pa_cnt_error",
1027 "bmb_wc9_bb_pa_cnt_error",
1028 "bmb_rc9_sop_rc_out_sync_fifo_error",
1029 "bmb_rc9_sop_out_sync_fifo_push_error",
1030 "bmb_rc0_sop_pend_fifo_error",
1031 "bmb_rc1_sop_pend_fifo_error",
1032 "bmb_rc2_sop_pend_fifo_error",
1033 "bmb_rc3_sop_pend_fifo_error",
1034 "bmb_rc4_sop_pend_fifo_error",
1035 "bmb_rc5_sop_pend_fifo_error",
1036 "bmb_rc6_sop_pend_fifo_error",
1037 "bmb_rc7_sop_pend_fifo_error",
1038 "bmb_rc0_dscr_pend_fifo_error",
1039 "bmb_rc1_dscr_pend_fifo_error",
1040 "bmb_rc2_dscr_pend_fifo_error",
1041 "bmb_rc3_dscr_pend_fifo_error",
1042 "bmb_rc4_dscr_pend_fifo_error",
1043 "bmb_rc5_dscr_pend_fifo_error",
1044 "bmb_rc6_dscr_pend_fifo_error",
1045 "bmb_rc7_dscr_pend_fifo_error",
1046 "bmb_rc8_sop_inp_sync_fifo_push_error",
1047 "bmb_rc9_sop_inp_sync_fifo_push_error",
1048 "bmb_rc8_sop_out_sync_fifo_push_error",
1049 "bmb_rc_gnt_pend_fifo_error",
1050 "bmb_rc8_out_sync_fifo_push_error",
1051 "bmb_rc9_out_sync_fifo_push_error",
1052 "bmb_wc8_sync_fifo_push_error",
1053 "bmb_wc9_sync_fifo_push_error",
1054 "bmb_rc8_sop_rc_out_sync_fifo_error",
1055 "bmb_rc_pkt7_dscr_fifo_error",
1058 #define bmb_int_attn_desc OSAL_NULL
1061 static const u16 bmb_int0_bb_a0_attn_idx[16] = {
1062 0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22,
1065 static struct attn_hw_reg bmb_int0_bb_a0 = {
1066 0, 16, bmb_int0_bb_a0_attn_idx, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4
1069 static const u16 bmb_int1_bb_a0_attn_idx[28] = {
1070 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40,
1071 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
1074 static struct attn_hw_reg bmb_int1_bb_a0 = {
1075 1, 28, bmb_int1_bb_a0_attn_idx, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc
1078 static const u16 bmb_int2_bb_a0_attn_idx[26] = {
1079 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
1080 69, 70, 71, 72, 73, 74, 75, 76,
1083 static struct attn_hw_reg bmb_int2_bb_a0 = {
1084 2, 26, bmb_int2_bb_a0_attn_idx, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4
1087 static const u16 bmb_int3_bb_a0_attn_idx[31] = {
1088 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94,
1089 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
1092 static struct attn_hw_reg bmb_int3_bb_a0 = {
1093 3, 31, bmb_int3_bb_a0_attn_idx, 0x540108, 0x540114, 0x540110, 0x54010c
1096 static const u16 bmb_int4_bb_a0_attn_idx[27] = {
1097 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121,
1099 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
1102 static struct attn_hw_reg bmb_int4_bb_a0 = {
1103 4, 27, bmb_int4_bb_a0_attn_idx, 0x540120, 0x54012c, 0x540128, 0x540124
1106 static const u16 bmb_int5_bb_a0_attn_idx[29] = {
1107 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148,
1109 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163,
1112 static struct attn_hw_reg bmb_int5_bb_a0 = {
1113 5, 29, bmb_int5_bb_a0_attn_idx, 0x540138, 0x540144, 0x540140, 0x54013c
1116 static const u16 bmb_int6_bb_a0_attn_idx[30] = {
1117 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177,
1119 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
1123 static struct attn_hw_reg bmb_int6_bb_a0 = {
1124 6, 30, bmb_int6_bb_a0_attn_idx, 0x540150, 0x54015c, 0x540158, 0x540154
1127 static const u16 bmb_int7_bb_a0_attn_idx[32] = {
1128 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207,
1130 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222,
1135 static struct attn_hw_reg bmb_int7_bb_a0 = {
1136 7, 32, bmb_int7_bb_a0_attn_idx, 0x540168, 0x540174, 0x540170, 0x54016c
1139 static const u16 bmb_int8_bb_a0_attn_idx[32] = {
1140 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239,
1142 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254,
1147 static struct attn_hw_reg bmb_int8_bb_a0 = {
1148 8, 32, bmb_int8_bb_a0_attn_idx, 0x540184, 0x540190, 0x54018c, 0x540188
1151 static const u16 bmb_int9_bb_a0_attn_idx[32] = {
1152 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271,
1154 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286,
1159 static struct attn_hw_reg bmb_int9_bb_a0 = {
1160 9, 32, bmb_int9_bb_a0_attn_idx, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0
1163 static const u16 bmb_int10_bb_a0_attn_idx[3] = {
1167 static struct attn_hw_reg bmb_int10_bb_a0 = {
1168 10, 3, bmb_int10_bb_a0_attn_idx, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8
1171 static const u16 bmb_int11_bb_a0_attn_idx[4] = {
1175 static struct attn_hw_reg bmb_int11_bb_a0 = {
1176 11, 4, bmb_int11_bb_a0_attn_idx, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0
1179 static struct attn_hw_reg *bmb_int_bb_a0_regs[12] = {
1180 &bmb_int0_bb_a0, &bmb_int1_bb_a0, &bmb_int2_bb_a0, &bmb_int3_bb_a0,
1181 &bmb_int4_bb_a0, &bmb_int5_bb_a0, &bmb_int6_bb_a0, &bmb_int7_bb_a0,
1182 &bmb_int8_bb_a0, &bmb_int9_bb_a0,
1183 &bmb_int10_bb_a0, &bmb_int11_bb_a0,
1186 static const u16 bmb_int0_bb_b0_attn_idx[16] = {
1187 0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22,
1190 static struct attn_hw_reg bmb_int0_bb_b0 = {
1191 0, 16, bmb_int0_bb_b0_attn_idx, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4
1194 static const u16 bmb_int1_bb_b0_attn_idx[28] = {
1195 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40,
1196 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
1199 static struct attn_hw_reg bmb_int1_bb_b0 = {
1200 1, 28, bmb_int1_bb_b0_attn_idx, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc
1203 static const u16 bmb_int2_bb_b0_attn_idx[26] = {
1204 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
1205 69, 70, 71, 72, 73, 74, 75, 76,
1208 static struct attn_hw_reg bmb_int2_bb_b0 = {
1209 2, 26, bmb_int2_bb_b0_attn_idx, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4
1212 static const u16 bmb_int3_bb_b0_attn_idx[31] = {
1213 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94,
1214 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
1217 static struct attn_hw_reg bmb_int3_bb_b0 = {
1218 3, 31, bmb_int3_bb_b0_attn_idx, 0x540108, 0x540114, 0x540110, 0x54010c
1221 static const u16 bmb_int4_bb_b0_attn_idx[27] = {
1222 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121,
1224 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
1227 static struct attn_hw_reg bmb_int4_bb_b0 = {
1228 4, 27, bmb_int4_bb_b0_attn_idx, 0x540120, 0x54012c, 0x540128, 0x540124
1231 static const u16 bmb_int5_bb_b0_attn_idx[29] = {
1232 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148,
1234 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163,
1237 static struct attn_hw_reg bmb_int5_bb_b0 = {
1238 5, 29, bmb_int5_bb_b0_attn_idx, 0x540138, 0x540144, 0x540140, 0x54013c
1241 static const u16 bmb_int6_bb_b0_attn_idx[30] = {
1242 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177,
1244 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
1248 static struct attn_hw_reg bmb_int6_bb_b0 = {
1249 6, 30, bmb_int6_bb_b0_attn_idx, 0x540150, 0x54015c, 0x540158, 0x540154
1252 static const u16 bmb_int7_bb_b0_attn_idx[32] = {
1253 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207,
1255 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222,
1260 static struct attn_hw_reg bmb_int7_bb_b0 = {
1261 7, 32, bmb_int7_bb_b0_attn_idx, 0x540168, 0x540174, 0x540170, 0x54016c
1264 static const u16 bmb_int8_bb_b0_attn_idx[32] = {
1265 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239,
1267 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254,
1272 static struct attn_hw_reg bmb_int8_bb_b0 = {
1273 8, 32, bmb_int8_bb_b0_attn_idx, 0x540184, 0x540190, 0x54018c, 0x540188
1276 static const u16 bmb_int9_bb_b0_attn_idx[32] = {
1277 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271,
1279 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286,
1284 static struct attn_hw_reg bmb_int9_bb_b0 = {
1285 9, 32, bmb_int9_bb_b0_attn_idx, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0
1288 static const u16 bmb_int10_bb_b0_attn_idx[3] = {
1292 static struct attn_hw_reg bmb_int10_bb_b0 = {
1293 10, 3, bmb_int10_bb_b0_attn_idx, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8
1296 static const u16 bmb_int11_bb_b0_attn_idx[4] = {
1300 static struct attn_hw_reg bmb_int11_bb_b0 = {
1301 11, 4, bmb_int11_bb_b0_attn_idx, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0
1304 static struct attn_hw_reg *bmb_int_bb_b0_regs[12] = {
1305 &bmb_int0_bb_b0, &bmb_int1_bb_b0, &bmb_int2_bb_b0, &bmb_int3_bb_b0,
1306 &bmb_int4_bb_b0, &bmb_int5_bb_b0, &bmb_int6_bb_b0, &bmb_int7_bb_b0,
1307 &bmb_int8_bb_b0, &bmb_int9_bb_b0,
1308 &bmb_int10_bb_b0, &bmb_int11_bb_b0,
1311 static const u16 bmb_int0_k2_attn_idx[16] = {
1312 0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22,
1315 static struct attn_hw_reg bmb_int0_k2 = {
1316 0, 16, bmb_int0_k2_attn_idx, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4
1319 static const u16 bmb_int1_k2_attn_idx[28] = {
1320 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40,
1321 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
1324 static struct attn_hw_reg bmb_int1_k2 = {
1325 1, 28, bmb_int1_k2_attn_idx, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc
1328 static const u16 bmb_int2_k2_attn_idx[26] = {
1329 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
1330 69, 70, 71, 72, 73, 74, 75, 76,
1333 static struct attn_hw_reg bmb_int2_k2 = {
1334 2, 26, bmb_int2_k2_attn_idx, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4
1337 static const u16 bmb_int3_k2_attn_idx[31] = {
1338 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94,
1339 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
1342 static struct attn_hw_reg bmb_int3_k2 = {
1343 3, 31, bmb_int3_k2_attn_idx, 0x540108, 0x540114, 0x540110, 0x54010c
1346 static const u16 bmb_int4_k2_attn_idx[27] = {
1347 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121,
1349 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
1352 static struct attn_hw_reg bmb_int4_k2 = {
1353 4, 27, bmb_int4_k2_attn_idx, 0x540120, 0x54012c, 0x540128, 0x540124
1356 static const u16 bmb_int5_k2_attn_idx[29] = {
1357 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148,
1359 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163,
1362 static struct attn_hw_reg bmb_int5_k2 = {
1363 5, 29, bmb_int5_k2_attn_idx, 0x540138, 0x540144, 0x540140, 0x54013c
1366 static const u16 bmb_int6_k2_attn_idx[30] = {
1367 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177,
1369 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
1373 static struct attn_hw_reg bmb_int6_k2 = {
1374 6, 30, bmb_int6_k2_attn_idx, 0x540150, 0x54015c, 0x540158, 0x540154
1377 static const u16 bmb_int7_k2_attn_idx[32] = {
1378 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207,
1380 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222,
1385 static struct attn_hw_reg bmb_int7_k2 = {
1386 7, 32, bmb_int7_k2_attn_idx, 0x540168, 0x540174, 0x540170, 0x54016c
1389 static const u16 bmb_int8_k2_attn_idx[32] = {
1390 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239,
1392 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254,
1397 static struct attn_hw_reg bmb_int8_k2 = {
1398 8, 32, bmb_int8_k2_attn_idx, 0x540184, 0x540190, 0x54018c, 0x540188
1401 static const u16 bmb_int9_k2_attn_idx[32] = {
1402 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271,
1404 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286,
1409 static struct attn_hw_reg bmb_int9_k2 = {
1410 9, 32, bmb_int9_k2_attn_idx, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0
1413 static const u16 bmb_int10_k2_attn_idx[3] = {
1417 static struct attn_hw_reg bmb_int10_k2 = {
1418 10, 3, bmb_int10_k2_attn_idx, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8
1421 static const u16 bmb_int11_k2_attn_idx[4] = {
1425 static struct attn_hw_reg bmb_int11_k2 = {
1426 11, 4, bmb_int11_k2_attn_idx, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0
1429 static struct attn_hw_reg *bmb_int_k2_regs[12] = {
1430 &bmb_int0_k2, &bmb_int1_k2, &bmb_int2_k2, &bmb_int3_k2, &bmb_int4_k2,
1431 &bmb_int5_k2, &bmb_int6_k2, &bmb_int7_k2, &bmb_int8_k2, &bmb_int9_k2,
1432 &bmb_int10_k2, &bmb_int11_k2,
1436 static const char *bmb_prty_attn_desc[61] = {
1437 "bmb_ll_bank0_mem_prty",
1438 "bmb_ll_bank1_mem_prty",
1439 "bmb_ll_bank2_mem_prty",
1440 "bmb_ll_bank3_mem_prty",
1441 "bmb_datapath_registers",
1442 "bmb_mem001_i_ecc_rf_int",
1443 "bmb_mem008_i_ecc_rf_int",
1444 "bmb_mem009_i_ecc_rf_int",
1445 "bmb_mem010_i_ecc_rf_int",
1446 "bmb_mem011_i_ecc_rf_int",
1447 "bmb_mem012_i_ecc_rf_int",
1448 "bmb_mem013_i_ecc_rf_int",
1449 "bmb_mem014_i_ecc_rf_int",
1450 "bmb_mem015_i_ecc_rf_int",
1451 "bmb_mem016_i_ecc_rf_int",
1452 "bmb_mem002_i_ecc_rf_int",
1453 "bmb_mem003_i_ecc_rf_int",
1454 "bmb_mem004_i_ecc_rf_int",
1455 "bmb_mem005_i_ecc_rf_int",
1456 "bmb_mem006_i_ecc_rf_int",
1457 "bmb_mem007_i_ecc_rf_int",
1458 "bmb_mem059_i_mem_prty",
1459 "bmb_mem060_i_mem_prty",
1460 "bmb_mem037_i_mem_prty",
1461 "bmb_mem038_i_mem_prty",
1462 "bmb_mem039_i_mem_prty",
1463 "bmb_mem040_i_mem_prty",
1464 "bmb_mem041_i_mem_prty",
1465 "bmb_mem042_i_mem_prty",
1466 "bmb_mem043_i_mem_prty",
1467 "bmb_mem044_i_mem_prty",
1468 "bmb_mem045_i_mem_prty",
1469 "bmb_mem046_i_mem_prty",
1470 "bmb_mem047_i_mem_prty",
1471 "bmb_mem048_i_mem_prty",
1472 "bmb_mem049_i_mem_prty",
1473 "bmb_mem050_i_mem_prty",
1474 "bmb_mem051_i_mem_prty",
1475 "bmb_mem052_i_mem_prty",
1476 "bmb_mem053_i_mem_prty",
1477 "bmb_mem054_i_mem_prty",
1478 "bmb_mem055_i_mem_prty",
1479 "bmb_mem056_i_mem_prty",
1480 "bmb_mem057_i_mem_prty",
1481 "bmb_mem058_i_mem_prty",
1482 "bmb_mem033_i_mem_prty",
1483 "bmb_mem034_i_mem_prty",
1484 "bmb_mem035_i_mem_prty",
1485 "bmb_mem036_i_mem_prty",
1486 "bmb_mem021_i_mem_prty",
1487 "bmb_mem022_i_mem_prty",
1488 "bmb_mem023_i_mem_prty",
1489 "bmb_mem024_i_mem_prty",
1490 "bmb_mem025_i_mem_prty",
1491 "bmb_mem026_i_mem_prty",
1492 "bmb_mem027_i_mem_prty",
1493 "bmb_mem028_i_mem_prty",
1494 "bmb_mem029_i_mem_prty",
1495 "bmb_mem030_i_mem_prty",
1496 "bmb_mem031_i_mem_prty",
1497 "bmb_mem032_i_mem_prty",
1500 #define bmb_prty_attn_desc OSAL_NULL
1503 static const u16 bmb_prty1_bb_a0_attn_idx[31] = {
1504 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
1506 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,
1509 static struct attn_hw_reg bmb_prty1_bb_a0 = {
1510 0, 31, bmb_prty1_bb_a0_attn_idx, 0x540400, 0x54040c, 0x540408, 0x540404
1513 static const u16 bmb_prty2_bb_a0_attn_idx[25] = {
1514 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
1515 54, 55, 56, 57, 58, 59, 60,
1518 static struct attn_hw_reg bmb_prty2_bb_a0 = {
1519 1, 25, bmb_prty2_bb_a0_attn_idx, 0x540410, 0x54041c, 0x540418, 0x540414
1522 static struct attn_hw_reg *bmb_prty_bb_a0_regs[2] = {
1523 &bmb_prty1_bb_a0, &bmb_prty2_bb_a0,
1526 static const u16 bmb_prty0_bb_b0_attn_idx[5] = {
1530 static struct attn_hw_reg bmb_prty0_bb_b0 = {
1531 0, 5, bmb_prty0_bb_b0_attn_idx, 0x5401dc, 0x5401e8, 0x5401e4, 0x5401e0
1534 static const u16 bmb_prty1_bb_b0_attn_idx[31] = {
1535 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
1537 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,
1540 static struct attn_hw_reg bmb_prty1_bb_b0 = {
1541 1, 31, bmb_prty1_bb_b0_attn_idx, 0x540400, 0x54040c, 0x540408, 0x540404
1544 static const u16 bmb_prty2_bb_b0_attn_idx[15] = {
1545 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
1548 static struct attn_hw_reg bmb_prty2_bb_b0 = {
1549 2, 15, bmb_prty2_bb_b0_attn_idx, 0x540410, 0x54041c, 0x540418, 0x540414
1552 static struct attn_hw_reg *bmb_prty_bb_b0_regs[3] = {
1553 &bmb_prty0_bb_b0, &bmb_prty1_bb_b0, &bmb_prty2_bb_b0,
1556 static const u16 bmb_prty0_k2_attn_idx[5] = {
1560 static struct attn_hw_reg bmb_prty0_k2 = {
1561 0, 5, bmb_prty0_k2_attn_idx, 0x5401dc, 0x5401e8, 0x5401e4, 0x5401e0
1564 static const u16 bmb_prty1_k2_attn_idx[31] = {
1565 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
1567 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,
1570 static struct attn_hw_reg bmb_prty1_k2 = {
1571 1, 31, bmb_prty1_k2_attn_idx, 0x540400, 0x54040c, 0x540408, 0x540404
1574 static const u16 bmb_prty2_k2_attn_idx[15] = {
1575 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
1578 static struct attn_hw_reg bmb_prty2_k2 = {
1579 2, 15, bmb_prty2_k2_attn_idx, 0x540410, 0x54041c, 0x540418, 0x540414
1582 static struct attn_hw_reg *bmb_prty_k2_regs[3] = {
1583 &bmb_prty0_k2, &bmb_prty1_k2, &bmb_prty2_k2,
1587 static const char *pcie_int_attn_desc[17] = {
1588 "pcie_address_error",
1589 "pcie_link_down_detect",
1590 "pcie_link_up_detect",
1591 "pcie_cfg_link_eq_req_int",
1592 "pcie_pcie_bandwidth_change_detect",
1593 "pcie_early_hot_reset_detect",
1594 "pcie_hot_reset_detect",
1595 "pcie_l1_entry_detect",
1596 "pcie_l1_exit_detect",
1597 "pcie_ltssm_state_match_detect",
1598 "pcie_fc_timeout_detect",
1599 "pcie_pme_turnoff_message_detect",
1600 "pcie_cfg_send_cor_err",
1601 "pcie_cfg_send_nf_err",
1602 "pcie_cfg_send_f_err",
1603 "pcie_qoverflow_detect",
1607 #define pcie_int_attn_desc OSAL_NULL
1610 static const u16 pcie_int0_k2_attn_idx[17] = {
1611 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
1614 static struct attn_hw_reg pcie_int0_k2 = {
1615 0, 17, pcie_int0_k2_attn_idx, 0x547a0, 0x547ac, 0x547a8, 0x547a4
1618 static struct attn_hw_reg *pcie_int_k2_regs[1] = {
1623 static const char *pcie_prty_attn_desc[24] = {
1624 "pcie_mem003_i_ecc_rf_int",
1625 "pcie_mem004_i_ecc_rf_int",
1626 "pcie_mem008_i_mem_prty",
1627 "pcie_mem007_i_mem_prty",
1628 "pcie_mem005_i_mem_prty",
1629 "pcie_mem006_i_mem_prty",
1630 "pcie_mem001_i_mem_prty",
1631 "pcie_mem002_i_mem_prty",
1632 "pcie_mem001_i_ecc_rf_int",
1633 "pcie_mem005_i_ecc_rf_int",
1634 "pcie_mem010_i_ecc_rf_int",
1635 "pcie_mem009_i_ecc_rf_int",
1636 "pcie_mem007_i_ecc_rf_int",
1637 "pcie_mem004_i_mem_prty_0",
1638 "pcie_mem004_i_mem_prty_1",
1639 "pcie_mem004_i_mem_prty_2",
1640 "pcie_mem004_i_mem_prty_3",
1641 "pcie_mem011_i_mem_prty_1",
1642 "pcie_mem011_i_mem_prty_2",
1643 "pcie_mem012_i_mem_prty_1",
1644 "pcie_mem012_i_mem_prty_2",
1645 "pcie_app_parity_errs_0",
1646 "pcie_app_parity_errs_1",
1647 "pcie_app_parity_errs_2",
1650 #define pcie_prty_attn_desc OSAL_NULL
1653 static const u16 pcie_prty1_bb_a0_attn_idx[17] = {
1654 0, 2, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
1657 static struct attn_hw_reg pcie_prty1_bb_a0 = {
1658 0, 17, pcie_prty1_bb_a0_attn_idx, 0x54000, 0x5400c, 0x54008, 0x54004
1661 static struct attn_hw_reg *pcie_prty_bb_a0_regs[1] = {
1665 static const u16 pcie_prty1_bb_b0_attn_idx[17] = {
1666 0, 2, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
1669 static struct attn_hw_reg pcie_prty1_bb_b0 = {
1670 0, 17, pcie_prty1_bb_b0_attn_idx, 0x54000, 0x5400c, 0x54008, 0x54004
1673 static struct attn_hw_reg *pcie_prty_bb_b0_regs[1] = {
1677 static const u16 pcie_prty1_k2_attn_idx[8] = {
1678 0, 1, 2, 3, 4, 5, 6, 7,
1681 static struct attn_hw_reg pcie_prty1_k2 = {
1682 0, 8, pcie_prty1_k2_attn_idx, 0x54000, 0x5400c, 0x54008, 0x54004
1685 static const u16 pcie_prty0_k2_attn_idx[3] = {
1689 static struct attn_hw_reg pcie_prty0_k2 = {
1690 1, 3, pcie_prty0_k2_attn_idx, 0x547b0, 0x547bc, 0x547b8, 0x547b4
1693 static struct attn_hw_reg *pcie_prty_k2_regs[2] = {
1694 &pcie_prty1_k2, &pcie_prty0_k2,
1698 static const char *mcp2_prty_attn_desc[13] = {
1700 "mcp2_mem001_i_ecc_rf_int",
1701 "mcp2_mem006_i_ecc_0_rf_int",
1702 "mcp2_mem006_i_ecc_1_rf_int",
1703 "mcp2_mem006_i_ecc_2_rf_int",
1704 "mcp2_mem006_i_ecc_3_rf_int",
1705 "mcp2_mem007_i_ecc_rf_int",
1706 "mcp2_mem004_i_mem_prty",
1707 "mcp2_mem003_i_mem_prty",
1708 "mcp2_mem002_i_mem_prty",
1709 "mcp2_mem009_i_mem_prty",
1710 "mcp2_mem008_i_mem_prty",
1711 "mcp2_mem005_i_mem_prty",
1714 #define mcp2_prty_attn_desc OSAL_NULL
1717 static const u16 mcp2_prty0_bb_a0_attn_idx[1] = {
1721 static struct attn_hw_reg mcp2_prty0_bb_a0 = {
1722 0, 1, mcp2_prty0_bb_a0_attn_idx, 0x52040, 0x5204c, 0x52048, 0x52044
1725 static const u16 mcp2_prty1_bb_a0_attn_idx[12] = {
1726 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
1729 static struct attn_hw_reg mcp2_prty1_bb_a0 = {
1730 1, 12, mcp2_prty1_bb_a0_attn_idx, 0x52204, 0x52210, 0x5220c, 0x52208
1733 static struct attn_hw_reg *mcp2_prty_bb_a0_regs[2] = {
1734 &mcp2_prty0_bb_a0, &mcp2_prty1_bb_a0,
1737 static const u16 mcp2_prty0_bb_b0_attn_idx[1] = {
1741 static struct attn_hw_reg mcp2_prty0_bb_b0 = {
1742 0, 1, mcp2_prty0_bb_b0_attn_idx, 0x52040, 0x5204c, 0x52048, 0x52044
1745 static const u16 mcp2_prty1_bb_b0_attn_idx[12] = {
1746 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
1749 static struct attn_hw_reg mcp2_prty1_bb_b0 = {
1750 1, 12, mcp2_prty1_bb_b0_attn_idx, 0x52204, 0x52210, 0x5220c, 0x52208
1753 static struct attn_hw_reg *mcp2_prty_bb_b0_regs[2] = {
1754 &mcp2_prty0_bb_b0, &mcp2_prty1_bb_b0,
1757 static const u16 mcp2_prty0_k2_attn_idx[1] = {
1761 static struct attn_hw_reg mcp2_prty0_k2 = {
1762 0, 1, mcp2_prty0_k2_attn_idx, 0x52040, 0x5204c, 0x52048, 0x52044
1765 static const u16 mcp2_prty1_k2_attn_idx[12] = {
1766 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
1769 static struct attn_hw_reg mcp2_prty1_k2 = {
1770 1, 12, mcp2_prty1_k2_attn_idx, 0x52204, 0x52210, 0x5220c, 0x52208
1773 static struct attn_hw_reg *mcp2_prty_k2_regs[2] = {
1774 &mcp2_prty0_k2, &mcp2_prty1_k2,
1778 static const char *pswhst_int_attn_desc[18] = {
1779 "pswhst_address_error",
1780 "pswhst_hst_src_fifo1_err",
1781 "pswhst_hst_src_fifo2_err",
1782 "pswhst_hst_src_fifo3_err",
1783 "pswhst_hst_src_fifo4_err",
1784 "pswhst_hst_src_fifo5_err",
1785 "pswhst_hst_hdr_sync_fifo_err",
1786 "pswhst_hst_data_sync_fifo_err",
1787 "pswhst_hst_cpl_sync_fifo_err",
1788 "pswhst_hst_vf_disabled_access",
1789 "pswhst_hst_permission_violation",
1790 "pswhst_hst_incorrect_access",
1791 "pswhst_hst_src_fifo6_err",
1792 "pswhst_hst_src_fifo7_err",
1793 "pswhst_hst_src_fifo8_err",
1794 "pswhst_hst_src_fifo9_err",
1795 "pswhst_hst_source_credit_violation",
1796 "pswhst_hst_timeout",
1799 #define pswhst_int_attn_desc OSAL_NULL
1802 static const u16 pswhst_int0_bb_a0_attn_idx[18] = {
1803 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
1806 static struct attn_hw_reg pswhst_int0_bb_a0 = {
1807 0, 18, pswhst_int0_bb_a0_attn_idx, 0x2a0180, 0x2a018c, 0x2a0188,
1811 static struct attn_hw_reg *pswhst_int_bb_a0_regs[1] = {
1815 static const u16 pswhst_int0_bb_b0_attn_idx[18] = {
1816 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
1819 static struct attn_hw_reg pswhst_int0_bb_b0 = {
1820 0, 18, pswhst_int0_bb_b0_attn_idx, 0x2a0180, 0x2a018c, 0x2a0188,
1824 static struct attn_hw_reg *pswhst_int_bb_b0_regs[1] = {
1828 static const u16 pswhst_int0_k2_attn_idx[18] = {
1829 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
1832 static struct attn_hw_reg pswhst_int0_k2 = {
1833 0, 18, pswhst_int0_k2_attn_idx, 0x2a0180, 0x2a018c, 0x2a0188, 0x2a0184
1836 static struct attn_hw_reg *pswhst_int_k2_regs[1] = {
1841 static const char *pswhst_prty_attn_desc[18] = {
1842 "pswhst_datapath_registers",
1843 "pswhst_mem006_i_mem_prty",
1844 "pswhst_mem007_i_mem_prty",
1845 "pswhst_mem005_i_mem_prty",
1846 "pswhst_mem002_i_mem_prty",
1847 "pswhst_mem003_i_mem_prty",
1848 "pswhst_mem001_i_mem_prty",
1849 "pswhst_mem008_i_mem_prty",
1850 "pswhst_mem004_i_mem_prty",
1851 "pswhst_mem009_i_mem_prty",
1852 "pswhst_mem010_i_mem_prty",
1853 "pswhst_mem016_i_mem_prty",
1854 "pswhst_mem012_i_mem_prty",
1855 "pswhst_mem013_i_mem_prty",
1856 "pswhst_mem014_i_mem_prty",
1857 "pswhst_mem015_i_mem_prty",
1858 "pswhst_mem011_i_mem_prty",
1859 "pswhst_mem017_i_mem_prty",
1862 #define pswhst_prty_attn_desc OSAL_NULL
1865 static const u16 pswhst_prty1_bb_a0_attn_idx[17] = {
1866 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
1869 static struct attn_hw_reg pswhst_prty1_bb_a0 = {
1870 0, 17, pswhst_prty1_bb_a0_attn_idx, 0x2a0200, 0x2a020c, 0x2a0208,
1874 static struct attn_hw_reg *pswhst_prty_bb_a0_regs[1] = {
1875 &pswhst_prty1_bb_a0,
1878 static const u16 pswhst_prty0_bb_b0_attn_idx[1] = {
1882 static struct attn_hw_reg pswhst_prty0_bb_b0 = {
1883 0, 1, pswhst_prty0_bb_b0_attn_idx, 0x2a0190, 0x2a019c, 0x2a0198,
1887 static const u16 pswhst_prty1_bb_b0_attn_idx[17] = {
1888 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
1891 static struct attn_hw_reg pswhst_prty1_bb_b0 = {
1892 1, 17, pswhst_prty1_bb_b0_attn_idx, 0x2a0200, 0x2a020c, 0x2a0208,
1896 static struct attn_hw_reg *pswhst_prty_bb_b0_regs[2] = {
1897 &pswhst_prty0_bb_b0, &pswhst_prty1_bb_b0,
1900 static const u16 pswhst_prty0_k2_attn_idx[1] = {
1904 static struct attn_hw_reg pswhst_prty0_k2 = {
1905 0, 1, pswhst_prty0_k2_attn_idx, 0x2a0190, 0x2a019c, 0x2a0198, 0x2a0194
1908 static const u16 pswhst_prty1_k2_attn_idx[17] = {
1909 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
1912 static struct attn_hw_reg pswhst_prty1_k2 = {
1913 1, 17, pswhst_prty1_k2_attn_idx, 0x2a0200, 0x2a020c, 0x2a0208, 0x2a0204
1916 static struct attn_hw_reg *pswhst_prty_k2_regs[2] = {
1917 &pswhst_prty0_k2, &pswhst_prty1_k2,
1921 static const char *pswhst2_int_attn_desc[5] = {
1922 "pswhst2_address_error",
1923 "pswhst2_hst_header_fifo_err",
1924 "pswhst2_hst_data_fifo_err",
1925 "pswhst2_hst_cpl_fifo_err",
1926 "pswhst2_hst_ireq_fifo_err",
1929 #define pswhst2_int_attn_desc OSAL_NULL
1932 static const u16 pswhst2_int0_bb_a0_attn_idx[5] = {
1936 static struct attn_hw_reg pswhst2_int0_bb_a0 = {
1937 0, 5, pswhst2_int0_bb_a0_attn_idx, 0x29e180, 0x29e18c, 0x29e188,
1941 static struct attn_hw_reg *pswhst2_int_bb_a0_regs[1] = {
1942 &pswhst2_int0_bb_a0,
1945 static const u16 pswhst2_int0_bb_b0_attn_idx[5] = {
1949 static struct attn_hw_reg pswhst2_int0_bb_b0 = {
1950 0, 5, pswhst2_int0_bb_b0_attn_idx, 0x29e180, 0x29e18c, 0x29e188,
1954 static struct attn_hw_reg *pswhst2_int_bb_b0_regs[1] = {
1955 &pswhst2_int0_bb_b0,
1958 static const u16 pswhst2_int0_k2_attn_idx[5] = {
1962 static struct attn_hw_reg pswhst2_int0_k2 = {
1963 0, 5, pswhst2_int0_k2_attn_idx, 0x29e180, 0x29e18c, 0x29e188, 0x29e184
1966 static struct attn_hw_reg *pswhst2_int_k2_regs[1] = {
1971 static const char *pswhst2_prty_attn_desc[1] = {
1972 "pswhst2_datapath_registers",
1975 #define pswhst2_prty_attn_desc OSAL_NULL
1978 static const u16 pswhst2_prty0_bb_b0_attn_idx[1] = {
1982 static struct attn_hw_reg pswhst2_prty0_bb_b0 = {
1983 0, 1, pswhst2_prty0_bb_b0_attn_idx, 0x29e190, 0x29e19c, 0x29e198,
1987 static struct attn_hw_reg *pswhst2_prty_bb_b0_regs[1] = {
1988 &pswhst2_prty0_bb_b0,
1991 static const u16 pswhst2_prty0_k2_attn_idx[1] = {
1995 static struct attn_hw_reg pswhst2_prty0_k2 = {
1996 0, 1, pswhst2_prty0_k2_attn_idx, 0x29e190, 0x29e19c, 0x29e198, 0x29e194
1999 static struct attn_hw_reg *pswhst2_prty_k2_regs[1] = {
2004 static const char *pswrd_int_attn_desc[3] = {
2005 "pswrd_address_error",
2007 "pswrd_pop_pbf_error",
2010 #define pswrd_int_attn_desc OSAL_NULL
2013 static const u16 pswrd_int0_bb_a0_attn_idx[3] = {
2017 static struct attn_hw_reg pswrd_int0_bb_a0 = {
2018 0, 3, pswrd_int0_bb_a0_attn_idx, 0x29c180, 0x29c18c, 0x29c188, 0x29c184
2021 static struct attn_hw_reg *pswrd_int_bb_a0_regs[1] = {
2025 static const u16 pswrd_int0_bb_b0_attn_idx[3] = {
2029 static struct attn_hw_reg pswrd_int0_bb_b0 = {
2030 0, 3, pswrd_int0_bb_b0_attn_idx, 0x29c180, 0x29c18c, 0x29c188, 0x29c184
2033 static struct attn_hw_reg *pswrd_int_bb_b0_regs[1] = {
2037 static const u16 pswrd_int0_k2_attn_idx[3] = {
2041 static struct attn_hw_reg pswrd_int0_k2 = {
2042 0, 3, pswrd_int0_k2_attn_idx, 0x29c180, 0x29c18c, 0x29c188, 0x29c184
2045 static struct attn_hw_reg *pswrd_int_k2_regs[1] = {
2050 static const char *pswrd_prty_attn_desc[1] = {
2051 "pswrd_datapath_registers",
2054 #define pswrd_prty_attn_desc OSAL_NULL
2057 static const u16 pswrd_prty0_bb_b0_attn_idx[1] = {
2061 static struct attn_hw_reg pswrd_prty0_bb_b0 = {
2062 0, 1, pswrd_prty0_bb_b0_attn_idx, 0x29c190, 0x29c19c, 0x29c198,
2066 static struct attn_hw_reg *pswrd_prty_bb_b0_regs[1] = {
2070 static const u16 pswrd_prty0_k2_attn_idx[1] = {
2074 static struct attn_hw_reg pswrd_prty0_k2 = {
2075 0, 1, pswrd_prty0_k2_attn_idx, 0x29c190, 0x29c19c, 0x29c198, 0x29c194
2078 static struct attn_hw_reg *pswrd_prty_k2_regs[1] = {
2083 static const char *pswrd2_int_attn_desc[5] = {
2084 "pswrd2_address_error",
2085 "pswrd2_sr_fifo_error",
2086 "pswrd2_blk_fifo_error",
2087 "pswrd2_push_error",
2088 "pswrd2_push_pbf_error",
2091 #define pswrd2_int_attn_desc OSAL_NULL
2094 static const u16 pswrd2_int0_bb_a0_attn_idx[5] = {
2098 static struct attn_hw_reg pswrd2_int0_bb_a0 = {
2099 0, 5, pswrd2_int0_bb_a0_attn_idx, 0x29d180, 0x29d18c, 0x29d188,
2103 static struct attn_hw_reg *pswrd2_int_bb_a0_regs[1] = {
2107 static const u16 pswrd2_int0_bb_b0_attn_idx[5] = {
2111 static struct attn_hw_reg pswrd2_int0_bb_b0 = {
2112 0, 5, pswrd2_int0_bb_b0_attn_idx, 0x29d180, 0x29d18c, 0x29d188,
2116 static struct attn_hw_reg *pswrd2_int_bb_b0_regs[1] = {
2120 static const u16 pswrd2_int0_k2_attn_idx[5] = {
2124 static struct attn_hw_reg pswrd2_int0_k2 = {
2125 0, 5, pswrd2_int0_k2_attn_idx, 0x29d180, 0x29d18c, 0x29d188, 0x29d184
2128 static struct attn_hw_reg *pswrd2_int_k2_regs[1] = {
2133 static const char *pswrd2_prty_attn_desc[36] = {
2134 "pswrd2_datapath_registers",
2135 "pswrd2_mem017_i_ecc_rf_int",
2136 "pswrd2_mem018_i_ecc_rf_int",
2137 "pswrd2_mem019_i_ecc_rf_int",
2138 "pswrd2_mem020_i_ecc_rf_int",
2139 "pswrd2_mem021_i_ecc_rf_int",
2140 "pswrd2_mem022_i_ecc_rf_int",
2141 "pswrd2_mem023_i_ecc_rf_int",
2142 "pswrd2_mem024_i_ecc_rf_int",
2143 "pswrd2_mem025_i_ecc_rf_int",
2144 "pswrd2_mem015_i_ecc_rf_int",
2145 "pswrd2_mem034_i_mem_prty",
2146 "pswrd2_mem032_i_mem_prty",
2147 "pswrd2_mem028_i_mem_prty",
2148 "pswrd2_mem033_i_mem_prty",
2149 "pswrd2_mem030_i_mem_prty",
2150 "pswrd2_mem029_i_mem_prty",
2151 "pswrd2_mem031_i_mem_prty",
2152 "pswrd2_mem027_i_mem_prty",
2153 "pswrd2_mem026_i_mem_prty",
2154 "pswrd2_mem001_i_mem_prty",
2155 "pswrd2_mem007_i_mem_prty",
2156 "pswrd2_mem008_i_mem_prty",
2157 "pswrd2_mem009_i_mem_prty",
2158 "pswrd2_mem010_i_mem_prty",
2159 "pswrd2_mem011_i_mem_prty",
2160 "pswrd2_mem012_i_mem_prty",
2161 "pswrd2_mem013_i_mem_prty",
2162 "pswrd2_mem014_i_mem_prty",
2163 "pswrd2_mem002_i_mem_prty",
2164 "pswrd2_mem003_i_mem_prty",
2165 "pswrd2_mem004_i_mem_prty",
2166 "pswrd2_mem005_i_mem_prty",
2167 "pswrd2_mem006_i_mem_prty",
2168 "pswrd2_mem016_i_mem_prty",
2169 "pswrd2_mem015_i_mem_prty",
2172 #define pswrd2_prty_attn_desc OSAL_NULL
2175 static const u16 pswrd2_prty1_bb_a0_attn_idx[31] = {
2176 1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
2178 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
2181 static struct attn_hw_reg pswrd2_prty1_bb_a0 = {
2182 0, 31, pswrd2_prty1_bb_a0_attn_idx, 0x29d200, 0x29d20c, 0x29d208,
2186 static const u16 pswrd2_prty2_bb_a0_attn_idx[3] = {
2190 static struct attn_hw_reg pswrd2_prty2_bb_a0 = {
2191 1, 3, pswrd2_prty2_bb_a0_attn_idx, 0x29d210, 0x29d21c, 0x29d218,
2195 static struct attn_hw_reg *pswrd2_prty_bb_a0_regs[2] = {
2196 &pswrd2_prty1_bb_a0, &pswrd2_prty2_bb_a0,
2199 static const u16 pswrd2_prty0_bb_b0_attn_idx[1] = {
2203 static struct attn_hw_reg pswrd2_prty0_bb_b0 = {
2204 0, 1, pswrd2_prty0_bb_b0_attn_idx, 0x29d190, 0x29d19c, 0x29d198,
2208 static const u16 pswrd2_prty1_bb_b0_attn_idx[31] = {
2209 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
2211 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
2214 static struct attn_hw_reg pswrd2_prty1_bb_b0 = {
2215 1, 31, pswrd2_prty1_bb_b0_attn_idx, 0x29d200, 0x29d20c, 0x29d208,
2219 static const u16 pswrd2_prty2_bb_b0_attn_idx[3] = {
2223 static struct attn_hw_reg pswrd2_prty2_bb_b0 = {
2224 2, 3, pswrd2_prty2_bb_b0_attn_idx, 0x29d210, 0x29d21c, 0x29d218,
2228 static struct attn_hw_reg *pswrd2_prty_bb_b0_regs[3] = {
2229 &pswrd2_prty0_bb_b0, &pswrd2_prty1_bb_b0, &pswrd2_prty2_bb_b0,
2232 static const u16 pswrd2_prty0_k2_attn_idx[1] = {
2236 static struct attn_hw_reg pswrd2_prty0_k2 = {
2237 0, 1, pswrd2_prty0_k2_attn_idx, 0x29d190, 0x29d19c, 0x29d198, 0x29d194
2240 static const u16 pswrd2_prty1_k2_attn_idx[31] = {
2241 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
2243 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
2246 static struct attn_hw_reg pswrd2_prty1_k2 = {
2247 1, 31, pswrd2_prty1_k2_attn_idx, 0x29d200, 0x29d20c, 0x29d208, 0x29d204
2250 static const u16 pswrd2_prty2_k2_attn_idx[3] = {
2254 static struct attn_hw_reg pswrd2_prty2_k2 = {
2255 2, 3, pswrd2_prty2_k2_attn_idx, 0x29d210, 0x29d21c, 0x29d218, 0x29d214
2258 static struct attn_hw_reg *pswrd2_prty_k2_regs[3] = {
2259 &pswrd2_prty0_k2, &pswrd2_prty1_k2, &pswrd2_prty2_k2,
2263 static const char *pswwr_int_attn_desc[16] = {
2264 "pswwr_address_error",
2265 "pswwr_src_fifo_overflow",
2266 "pswwr_qm_fifo_overflow",
2267 "pswwr_tm_fifo_overflow",
2268 "pswwr_usdm_fifo_overflow",
2269 "pswwr_usdmdp_fifo_overflow",
2270 "pswwr_xsdm_fifo_overflow",
2271 "pswwr_tsdm_fifo_overflow",
2272 "pswwr_cduwr_fifo_overflow",
2273 "pswwr_dbg_fifo_overflow",
2274 "pswwr_dmae_fifo_overflow",
2275 "pswwr_hc_fifo_overflow",
2276 "pswwr_msdm_fifo_overflow",
2277 "pswwr_ysdm_fifo_overflow",
2278 "pswwr_psdm_fifo_overflow",
2279 "pswwr_m2p_fifo_overflow",
2282 #define pswwr_int_attn_desc OSAL_NULL
2285 static const u16 pswwr_int0_bb_a0_attn_idx[16] = {
2286 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
2289 static struct attn_hw_reg pswwr_int0_bb_a0 = {
2290 0, 16, pswwr_int0_bb_a0_attn_idx, 0x29a180, 0x29a18c, 0x29a188,
2294 static struct attn_hw_reg *pswwr_int_bb_a0_regs[1] = {
2298 static const u16 pswwr_int0_bb_b0_attn_idx[16] = {
2299 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
2302 static struct attn_hw_reg pswwr_int0_bb_b0 = {
2303 0, 16, pswwr_int0_bb_b0_attn_idx, 0x29a180, 0x29a18c, 0x29a188,
2307 static struct attn_hw_reg *pswwr_int_bb_b0_regs[1] = {
2311 static const u16 pswwr_int0_k2_attn_idx[16] = {
2312 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
2315 static struct attn_hw_reg pswwr_int0_k2 = {
2316 0, 16, pswwr_int0_k2_attn_idx, 0x29a180, 0x29a18c, 0x29a188, 0x29a184
2319 static struct attn_hw_reg *pswwr_int_k2_regs[1] = {
2324 static const char *pswwr_prty_attn_desc[1] = {
2325 "pswwr_datapath_registers",
2328 #define pswwr_prty_attn_desc OSAL_NULL
2331 static const u16 pswwr_prty0_bb_b0_attn_idx[1] = {
2335 static struct attn_hw_reg pswwr_prty0_bb_b0 = {
2336 0, 1, pswwr_prty0_bb_b0_attn_idx, 0x29a190, 0x29a19c, 0x29a198,
2340 static struct attn_hw_reg *pswwr_prty_bb_b0_regs[1] = {
2344 static const u16 pswwr_prty0_k2_attn_idx[1] = {
2348 static struct attn_hw_reg pswwr_prty0_k2 = {
2349 0, 1, pswwr_prty0_k2_attn_idx, 0x29a190, 0x29a19c, 0x29a198, 0x29a194
2352 static struct attn_hw_reg *pswwr_prty_k2_regs[1] = {
2357 static const char *pswwr2_int_attn_desc[19] = {
2358 "pswwr2_address_error",
2359 "pswwr2_pglue_eop_error",
2360 "pswwr2_pglue_lsr_error",
2361 "pswwr2_tm_underflow",
2362 "pswwr2_qm_underflow",
2363 "pswwr2_src_underflow",
2364 "pswwr2_usdm_underflow",
2365 "pswwr2_tsdm_underflow",
2366 "pswwr2_xsdm_underflow",
2367 "pswwr2_usdmdp_underflow",
2368 "pswwr2_cdu_underflow",
2369 "pswwr2_dbg_underflow",
2370 "pswwr2_dmae_underflow",
2371 "pswwr2_hc_underflow",
2372 "pswwr2_msdm_underflow",
2373 "pswwr2_ysdm_underflow",
2374 "pswwr2_psdm_underflow",
2375 "pswwr2_m2p_underflow",
2376 "pswwr2_pglue_eop_error_in_line",
2379 #define pswwr2_int_attn_desc OSAL_NULL
2382 static const u16 pswwr2_int0_bb_a0_attn_idx[19] = {
2383 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
2386 static struct attn_hw_reg pswwr2_int0_bb_a0 = {
2387 0, 19, pswwr2_int0_bb_a0_attn_idx, 0x29b180, 0x29b18c, 0x29b188,
2391 static struct attn_hw_reg *pswwr2_int_bb_a0_regs[1] = {
2395 static const u16 pswwr2_int0_bb_b0_attn_idx[19] = {
2396 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
2399 static struct attn_hw_reg pswwr2_int0_bb_b0 = {
2400 0, 19, pswwr2_int0_bb_b0_attn_idx, 0x29b180, 0x29b18c, 0x29b188,
2404 static struct attn_hw_reg *pswwr2_int_bb_b0_regs[1] = {
2408 static const u16 pswwr2_int0_k2_attn_idx[19] = {
2409 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
2412 static struct attn_hw_reg pswwr2_int0_k2 = {
2413 0, 19, pswwr2_int0_k2_attn_idx, 0x29b180, 0x29b18c, 0x29b188, 0x29b184
2416 static struct attn_hw_reg *pswwr2_int_k2_regs[1] = {
2421 static const char *pswwr2_prty_attn_desc[114] = {
2422 "pswwr2_datapath_registers",
2423 "pswwr2_mem008_i_ecc_rf_int",
2424 "pswwr2_mem001_i_mem_prty",
2425 "pswwr2_mem014_i_mem_prty_0",
2426 "pswwr2_mem014_i_mem_prty_1",
2427 "pswwr2_mem014_i_mem_prty_2",
2428 "pswwr2_mem014_i_mem_prty_3",
2429 "pswwr2_mem014_i_mem_prty_4",
2430 "pswwr2_mem014_i_mem_prty_5",
2431 "pswwr2_mem014_i_mem_prty_6",
2432 "pswwr2_mem014_i_mem_prty_7",
2433 "pswwr2_mem014_i_mem_prty_8",
2434 "pswwr2_mem016_i_mem_prty_0",
2435 "pswwr2_mem016_i_mem_prty_1",
2436 "pswwr2_mem016_i_mem_prty_2",
2437 "pswwr2_mem016_i_mem_prty_3",
2438 "pswwr2_mem016_i_mem_prty_4",
2439 "pswwr2_mem016_i_mem_prty_5",
2440 "pswwr2_mem016_i_mem_prty_6",
2441 "pswwr2_mem016_i_mem_prty_7",
2442 "pswwr2_mem016_i_mem_prty_8",
2443 "pswwr2_mem007_i_mem_prty_0",
2444 "pswwr2_mem007_i_mem_prty_1",
2445 "pswwr2_mem007_i_mem_prty_2",
2446 "pswwr2_mem007_i_mem_prty_3",
2447 "pswwr2_mem007_i_mem_prty_4",
2448 "pswwr2_mem007_i_mem_prty_5",
2449 "pswwr2_mem007_i_mem_prty_6",
2450 "pswwr2_mem007_i_mem_prty_7",
2451 "pswwr2_mem007_i_mem_prty_8",
2452 "pswwr2_mem017_i_mem_prty_0",
2453 "pswwr2_mem017_i_mem_prty_1",
2454 "pswwr2_mem017_i_mem_prty_2",
2455 "pswwr2_mem017_i_mem_prty_3",
2456 "pswwr2_mem017_i_mem_prty_4",
2457 "pswwr2_mem017_i_mem_prty_5",
2458 "pswwr2_mem017_i_mem_prty_6",
2459 "pswwr2_mem017_i_mem_prty_7",
2460 "pswwr2_mem017_i_mem_prty_8",
2461 "pswwr2_mem009_i_mem_prty_0",
2462 "pswwr2_mem009_i_mem_prty_1",
2463 "pswwr2_mem009_i_mem_prty_2",
2464 "pswwr2_mem009_i_mem_prty_3",
2465 "pswwr2_mem009_i_mem_prty_4",
2466 "pswwr2_mem009_i_mem_prty_5",
2467 "pswwr2_mem009_i_mem_prty_6",
2468 "pswwr2_mem009_i_mem_prty_7",
2469 "pswwr2_mem009_i_mem_prty_8",
2470 "pswwr2_mem013_i_mem_prty_0",
2471 "pswwr2_mem013_i_mem_prty_1",
2472 "pswwr2_mem013_i_mem_prty_2",
2473 "pswwr2_mem013_i_mem_prty_3",
2474 "pswwr2_mem013_i_mem_prty_4",
2475 "pswwr2_mem013_i_mem_prty_5",
2476 "pswwr2_mem013_i_mem_prty_6",
2477 "pswwr2_mem013_i_mem_prty_7",
2478 "pswwr2_mem013_i_mem_prty_8",
2479 "pswwr2_mem006_i_mem_prty_0",
2480 "pswwr2_mem006_i_mem_prty_1",
2481 "pswwr2_mem006_i_mem_prty_2",
2482 "pswwr2_mem006_i_mem_prty_3",
2483 "pswwr2_mem006_i_mem_prty_4",
2484 "pswwr2_mem006_i_mem_prty_5",
2485 "pswwr2_mem006_i_mem_prty_6",
2486 "pswwr2_mem006_i_mem_prty_7",
2487 "pswwr2_mem006_i_mem_prty_8",
2488 "pswwr2_mem010_i_mem_prty_0",
2489 "pswwr2_mem010_i_mem_prty_1",
2490 "pswwr2_mem010_i_mem_prty_2",
2491 "pswwr2_mem010_i_mem_prty_3",
2492 "pswwr2_mem010_i_mem_prty_4",
2493 "pswwr2_mem010_i_mem_prty_5",
2494 "pswwr2_mem010_i_mem_prty_6",
2495 "pswwr2_mem010_i_mem_prty_7",
2496 "pswwr2_mem010_i_mem_prty_8",
2497 "pswwr2_mem012_i_mem_prty",
2498 "pswwr2_mem011_i_mem_prty_0",
2499 "pswwr2_mem011_i_mem_prty_1",
2500 "pswwr2_mem011_i_mem_prty_2",
2501 "pswwr2_mem011_i_mem_prty_3",
2502 "pswwr2_mem011_i_mem_prty_4",
2503 "pswwr2_mem011_i_mem_prty_5",
2504 "pswwr2_mem011_i_mem_prty_6",
2505 "pswwr2_mem011_i_mem_prty_7",
2506 "pswwr2_mem011_i_mem_prty_8",
2507 "pswwr2_mem004_i_mem_prty_0",
2508 "pswwr2_mem004_i_mem_prty_1",
2509 "pswwr2_mem004_i_mem_prty_2",
2510 "pswwr2_mem004_i_mem_prty_3",
2511 "pswwr2_mem004_i_mem_prty_4",
2512 "pswwr2_mem004_i_mem_prty_5",
2513 "pswwr2_mem004_i_mem_prty_6",
2514 "pswwr2_mem004_i_mem_prty_7",
2515 "pswwr2_mem004_i_mem_prty_8",
2516 "pswwr2_mem015_i_mem_prty_0",
2517 "pswwr2_mem015_i_mem_prty_1",
2518 "pswwr2_mem015_i_mem_prty_2",
2519 "pswwr2_mem005_i_mem_prty_0",
2520 "pswwr2_mem005_i_mem_prty_1",
2521 "pswwr2_mem005_i_mem_prty_2",
2522 "pswwr2_mem005_i_mem_prty_3",
2523 "pswwr2_mem005_i_mem_prty_4",
2524 "pswwr2_mem005_i_mem_prty_5",
2525 "pswwr2_mem005_i_mem_prty_6",
2526 "pswwr2_mem005_i_mem_prty_7",
2527 "pswwr2_mem005_i_mem_prty_8",
2528 "pswwr2_mem002_i_mem_prty_0",
2529 "pswwr2_mem002_i_mem_prty_1",
2530 "pswwr2_mem002_i_mem_prty_2",
2531 "pswwr2_mem002_i_mem_prty_3",
2532 "pswwr2_mem002_i_mem_prty_4",
2533 "pswwr2_mem003_i_mem_prty_0",
2534 "pswwr2_mem003_i_mem_prty_1",
2535 "pswwr2_mem003_i_mem_prty_2",
2538 #define pswwr2_prty_attn_desc OSAL_NULL
2541 static const u16 pswwr2_prty1_bb_a0_attn_idx[31] = {
2542 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
2544 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
2547 static struct attn_hw_reg pswwr2_prty1_bb_a0 = {
2548 0, 31, pswwr2_prty1_bb_a0_attn_idx, 0x29b200, 0x29b20c, 0x29b208,
2552 static const u16 pswwr2_prty2_bb_a0_attn_idx[31] = {
2553 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
2554 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62,
2557 static struct attn_hw_reg pswwr2_prty2_bb_a0 = {
2558 1, 31, pswwr2_prty2_bb_a0_attn_idx, 0x29b210, 0x29b21c, 0x29b218,
2562 static const u16 pswwr2_prty3_bb_a0_attn_idx[31] = {
2563 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
2564 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93,
2567 static struct attn_hw_reg pswwr2_prty3_bb_a0 = {
2568 2, 31, pswwr2_prty3_bb_a0_attn_idx, 0x29b220, 0x29b22c, 0x29b228,
2572 static const u16 pswwr2_prty4_bb_a0_attn_idx[20] = {
2573 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108,
2578 static struct attn_hw_reg pswwr2_prty4_bb_a0 = {
2579 3, 20, pswwr2_prty4_bb_a0_attn_idx, 0x29b230, 0x29b23c, 0x29b238,
2583 static struct attn_hw_reg *pswwr2_prty_bb_a0_regs[4] = {
2584 &pswwr2_prty1_bb_a0, &pswwr2_prty2_bb_a0, &pswwr2_prty3_bb_a0,
2585 &pswwr2_prty4_bb_a0,
2588 static const u16 pswwr2_prty0_bb_b0_attn_idx[1] = {
2592 static struct attn_hw_reg pswwr2_prty0_bb_b0 = {
2593 0, 1, pswwr2_prty0_bb_b0_attn_idx, 0x29b190, 0x29b19c, 0x29b198,
2597 static const u16 pswwr2_prty1_bb_b0_attn_idx[31] = {
2598 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
2600 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
2603 static struct attn_hw_reg pswwr2_prty1_bb_b0 = {
2604 1, 31, pswwr2_prty1_bb_b0_attn_idx, 0x29b200, 0x29b20c, 0x29b208,
2608 static const u16 pswwr2_prty2_bb_b0_attn_idx[31] = {
2609 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
2610 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62,
2613 static struct attn_hw_reg pswwr2_prty2_bb_b0 = {
2614 2, 31, pswwr2_prty2_bb_b0_attn_idx, 0x29b210, 0x29b21c, 0x29b218,
2618 static const u16 pswwr2_prty3_bb_b0_attn_idx[31] = {
2619 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
2620 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93,
2623 static struct attn_hw_reg pswwr2_prty3_bb_b0 = {
2624 3, 31, pswwr2_prty3_bb_b0_attn_idx, 0x29b220, 0x29b22c, 0x29b228,
2628 static const u16 pswwr2_prty4_bb_b0_attn_idx[20] = {
2629 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108,
2634 static struct attn_hw_reg pswwr2_prty4_bb_b0 = {
2635 4, 20, pswwr2_prty4_bb_b0_attn_idx, 0x29b230, 0x29b23c, 0x29b238,
2639 static struct attn_hw_reg *pswwr2_prty_bb_b0_regs[5] = {
2640 &pswwr2_prty0_bb_b0, &pswwr2_prty1_bb_b0, &pswwr2_prty2_bb_b0,
2641 &pswwr2_prty3_bb_b0, &pswwr2_prty4_bb_b0,
2644 static const u16 pswwr2_prty0_k2_attn_idx[1] = {
2648 static struct attn_hw_reg pswwr2_prty0_k2 = {
2649 0, 1, pswwr2_prty0_k2_attn_idx, 0x29b190, 0x29b19c, 0x29b198, 0x29b194
2652 static const u16 pswwr2_prty1_k2_attn_idx[31] = {
2653 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
2655 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
2658 static struct attn_hw_reg pswwr2_prty1_k2 = {
2659 1, 31, pswwr2_prty1_k2_attn_idx, 0x29b200, 0x29b20c, 0x29b208, 0x29b204
2662 static const u16 pswwr2_prty2_k2_attn_idx[31] = {
2663 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
2664 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62,
2667 static struct attn_hw_reg pswwr2_prty2_k2 = {
2668 2, 31, pswwr2_prty2_k2_attn_idx, 0x29b210, 0x29b21c, 0x29b218, 0x29b214
2671 static const u16 pswwr2_prty3_k2_attn_idx[31] = {
2672 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
2673 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93,
2676 static struct attn_hw_reg pswwr2_prty3_k2 = {
2677 3, 31, pswwr2_prty3_k2_attn_idx, 0x29b220, 0x29b22c, 0x29b228, 0x29b224
2680 static const u16 pswwr2_prty4_k2_attn_idx[20] = {
2681 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108,
2686 static struct attn_hw_reg pswwr2_prty4_k2 = {
2687 4, 20, pswwr2_prty4_k2_attn_idx, 0x29b230, 0x29b23c, 0x29b238, 0x29b234
2690 static struct attn_hw_reg *pswwr2_prty_k2_regs[5] = {
2691 &pswwr2_prty0_k2, &pswwr2_prty1_k2, &pswwr2_prty2_k2, &pswwr2_prty3_k2,
2696 static const char *pswrq_int_attn_desc[21] = {
2697 "pswrq_address_error",
2698 "pswrq_pbf_fifo_overflow",
2699 "pswrq_src_fifo_overflow",
2700 "pswrq_qm_fifo_overflow",
2701 "pswrq_tm_fifo_overflow",
2702 "pswrq_usdm_fifo_overflow",
2703 "pswrq_m2p_fifo_overflow",
2704 "pswrq_xsdm_fifo_overflow",
2705 "pswrq_tsdm_fifo_overflow",
2706 "pswrq_ptu_fifo_overflow",
2707 "pswrq_cduwr_fifo_overflow",
2708 "pswrq_cdurd_fifo_overflow",
2709 "pswrq_dmae_fifo_overflow",
2710 "pswrq_hc_fifo_overflow",
2711 "pswrq_dbg_fifo_overflow",
2712 "pswrq_msdm_fifo_overflow",
2713 "pswrq_ysdm_fifo_overflow",
2714 "pswrq_psdm_fifo_overflow",
2715 "pswrq_prm_fifo_overflow",
2716 "pswrq_muld_fifo_overflow",
2717 "pswrq_xyld_fifo_overflow",
2720 #define pswrq_int_attn_desc OSAL_NULL
2723 static const u16 pswrq_int0_bb_a0_attn_idx[21] = {
2724 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
2728 static struct attn_hw_reg pswrq_int0_bb_a0 = {
2729 0, 21, pswrq_int0_bb_a0_attn_idx, 0x280180, 0x28018c, 0x280188,
2733 static struct attn_hw_reg *pswrq_int_bb_a0_regs[1] = {
2737 static const u16 pswrq_int0_bb_b0_attn_idx[21] = {
2738 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
2742 static struct attn_hw_reg pswrq_int0_bb_b0 = {
2743 0, 21, pswrq_int0_bb_b0_attn_idx, 0x280180, 0x28018c, 0x280188,
2747 static struct attn_hw_reg *pswrq_int_bb_b0_regs[1] = {
2751 static const u16 pswrq_int0_k2_attn_idx[21] = {
2752 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
2756 static struct attn_hw_reg pswrq_int0_k2 = {
2757 0, 21, pswrq_int0_k2_attn_idx, 0x280180, 0x28018c, 0x280188, 0x280184
2760 static struct attn_hw_reg *pswrq_int_k2_regs[1] = {
2765 static const char *pswrq_prty_attn_desc[1] = {
2766 "pswrq_pxp_busip_parity",
2769 #define pswrq_prty_attn_desc OSAL_NULL
2772 static const u16 pswrq_prty0_bb_b0_attn_idx[1] = {
2776 static struct attn_hw_reg pswrq_prty0_bb_b0 = {
2777 0, 1, pswrq_prty0_bb_b0_attn_idx, 0x280190, 0x28019c, 0x280198,
2781 static struct attn_hw_reg *pswrq_prty_bb_b0_regs[1] = {
2785 static const u16 pswrq_prty0_k2_attn_idx[1] = {
2789 static struct attn_hw_reg pswrq_prty0_k2 = {
2790 0, 1, pswrq_prty0_k2_attn_idx, 0x280190, 0x28019c, 0x280198, 0x280194
2793 static struct attn_hw_reg *pswrq_prty_k2_regs[1] = {
2798 static const char *pswrq2_int_attn_desc[15] = {
2799 "pswrq2_address_error",
2800 "pswrq2_l2p_fifo_overflow",
2801 "pswrq2_wdfifo_overflow",
2802 "pswrq2_phyaddr_fifo_of",
2803 "pswrq2_l2p_violation_1",
2804 "pswrq2_l2p_violation_2",
2805 "pswrq2_free_list_empty",
2807 "pswrq2_l2p_vf_err",
2808 "pswrq2_core_wdone_overflow",
2809 "pswrq2_treq_fifo_underflow",
2810 "pswrq2_treq_fifo_overflow",
2811 "pswrq2_icpl_fifo_underflow",
2812 "pswrq2_icpl_fifo_overflow",
2813 "pswrq2_back2back_atc_response",
2816 #define pswrq2_int_attn_desc OSAL_NULL
2819 static const u16 pswrq2_int0_bb_a0_attn_idx[15] = {
2820 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
2823 static struct attn_hw_reg pswrq2_int0_bb_a0 = {
2824 0, 15, pswrq2_int0_bb_a0_attn_idx, 0x240180, 0x24018c, 0x240188,
2828 static struct attn_hw_reg *pswrq2_int_bb_a0_regs[1] = {
2832 static const u16 pswrq2_int0_bb_b0_attn_idx[15] = {
2833 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
2836 static struct attn_hw_reg pswrq2_int0_bb_b0 = {
2837 0, 15, pswrq2_int0_bb_b0_attn_idx, 0x240180, 0x24018c, 0x240188,
2841 static struct attn_hw_reg *pswrq2_int_bb_b0_regs[1] = {
2845 static const u16 pswrq2_int0_k2_attn_idx[15] = {
2846 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
2849 static struct attn_hw_reg pswrq2_int0_k2 = {
2850 0, 15, pswrq2_int0_k2_attn_idx, 0x240180, 0x24018c, 0x240188, 0x240184
2853 static struct attn_hw_reg *pswrq2_int_k2_regs[1] = {
2858 static const char *pswrq2_prty_attn_desc[11] = {
2859 "pswrq2_mem004_i_ecc_rf_int",
2860 "pswrq2_mem005_i_ecc_rf_int",
2861 "pswrq2_mem001_i_ecc_rf_int",
2862 "pswrq2_mem006_i_mem_prty",
2863 "pswrq2_mem008_i_mem_prty",
2864 "pswrq2_mem009_i_mem_prty",
2865 "pswrq2_mem003_i_mem_prty",
2866 "pswrq2_mem002_i_mem_prty",
2867 "pswrq2_mem010_i_mem_prty",
2868 "pswrq2_mem007_i_mem_prty",
2869 "pswrq2_mem005_i_mem_prty",
2872 #define pswrq2_prty_attn_desc OSAL_NULL
2875 static const u16 pswrq2_prty1_bb_a0_attn_idx[9] = {
2876 0, 2, 3, 4, 5, 6, 7, 9, 10,
2879 static struct attn_hw_reg pswrq2_prty1_bb_a0 = {
2880 0, 9, pswrq2_prty1_bb_a0_attn_idx, 0x240200, 0x24020c, 0x240208,
2884 static struct attn_hw_reg *pswrq2_prty_bb_a0_regs[1] = {
2885 &pswrq2_prty1_bb_a0,
2888 static const u16 pswrq2_prty1_bb_b0_attn_idx[9] = {
2889 0, 2, 3, 4, 5, 6, 7, 9, 10,
2892 static struct attn_hw_reg pswrq2_prty1_bb_b0 = {
2893 0, 9, pswrq2_prty1_bb_b0_attn_idx, 0x240200, 0x24020c, 0x240208,
2897 static struct attn_hw_reg *pswrq2_prty_bb_b0_regs[1] = {
2898 &pswrq2_prty1_bb_b0,
2901 static const u16 pswrq2_prty1_k2_attn_idx[10] = {
2902 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
2905 static struct attn_hw_reg pswrq2_prty1_k2 = {
2906 0, 10, pswrq2_prty1_k2_attn_idx, 0x240200, 0x24020c, 0x240208, 0x240204
2909 static struct attn_hw_reg *pswrq2_prty_k2_regs[1] = {
2914 static const char *pglcs_int_attn_desc[2] = {
2915 "pglcs_address_error",
2916 "pglcs_rasdp_error",
2919 #define pglcs_int_attn_desc OSAL_NULL
2922 static const u16 pglcs_int0_bb_a0_attn_idx[1] = {
2926 static struct attn_hw_reg pglcs_int0_bb_a0 = {
2927 0, 1, pglcs_int0_bb_a0_attn_idx, 0x1d00, 0x1d0c, 0x1d08, 0x1d04
2930 static struct attn_hw_reg *pglcs_int_bb_a0_regs[1] = {
2934 static const u16 pglcs_int0_bb_b0_attn_idx[1] = {
2938 static struct attn_hw_reg pglcs_int0_bb_b0 = {
2939 0, 1, pglcs_int0_bb_b0_attn_idx, 0x1d00, 0x1d0c, 0x1d08, 0x1d04
2942 static struct attn_hw_reg *pglcs_int_bb_b0_regs[1] = {
2946 static const u16 pglcs_int0_k2_attn_idx[2] = {
2950 static struct attn_hw_reg pglcs_int0_k2 = {
2951 0, 2, pglcs_int0_k2_attn_idx, 0x1d00, 0x1d0c, 0x1d08, 0x1d04
2954 static struct attn_hw_reg *pglcs_int_k2_regs[1] = {
2959 static const char *dmae_int_attn_desc[2] = {
2960 "dmae_address_error",
2961 "dmae_pci_rd_buf_err",
2964 #define dmae_int_attn_desc OSAL_NULL
2967 static const u16 dmae_int0_bb_a0_attn_idx[2] = {
2971 static struct attn_hw_reg dmae_int0_bb_a0 = {
2972 0, 2, dmae_int0_bb_a0_attn_idx, 0xc180, 0xc18c, 0xc188, 0xc184
2975 static struct attn_hw_reg *dmae_int_bb_a0_regs[1] = {
2979 static const u16 dmae_int0_bb_b0_attn_idx[2] = {
2983 static struct attn_hw_reg dmae_int0_bb_b0 = {
2984 0, 2, dmae_int0_bb_b0_attn_idx, 0xc180, 0xc18c, 0xc188, 0xc184
2987 static struct attn_hw_reg *dmae_int_bb_b0_regs[1] = {
2991 static const u16 dmae_int0_k2_attn_idx[2] = {
2995 static struct attn_hw_reg dmae_int0_k2 = {
2996 0, 2, dmae_int0_k2_attn_idx, 0xc180, 0xc18c, 0xc188, 0xc184
2999 static struct attn_hw_reg *dmae_int_k2_regs[1] = {
3004 static const char *dmae_prty_attn_desc[3] = {
3005 "dmae_mem002_i_mem_prty",
3006 "dmae_mem001_i_mem_prty",
3007 "dmae_mem003_i_mem_prty",
3010 #define dmae_prty_attn_desc OSAL_NULL
3013 static const u16 dmae_prty1_bb_a0_attn_idx[3] = {
3017 static struct attn_hw_reg dmae_prty1_bb_a0 = {
3018 0, 3, dmae_prty1_bb_a0_attn_idx, 0xc200, 0xc20c, 0xc208, 0xc204
3021 static struct attn_hw_reg *dmae_prty_bb_a0_regs[1] = {
3025 static const u16 dmae_prty1_bb_b0_attn_idx[3] = {
3029 static struct attn_hw_reg dmae_prty1_bb_b0 = {
3030 0, 3, dmae_prty1_bb_b0_attn_idx, 0xc200, 0xc20c, 0xc208, 0xc204
3033 static struct attn_hw_reg *dmae_prty_bb_b0_regs[1] = {
3037 static const u16 dmae_prty1_k2_attn_idx[3] = {
3041 static struct attn_hw_reg dmae_prty1_k2 = {
3042 0, 3, dmae_prty1_k2_attn_idx, 0xc200, 0xc20c, 0xc208, 0xc204
3045 static struct attn_hw_reg *dmae_prty_k2_regs[1] = {
3050 static const char *ptu_int_attn_desc[8] = {
3051 "ptu_address_error",
3052 "ptu_atc_tcpl_to_not_pend",
3053 "ptu_atc_gpa_multiple_hits",
3054 "ptu_atc_rcpl_to_empty_cnt",
3055 "ptu_atc_tcpl_error",
3057 "ptu_atc_reuse_transpend",
3058 "ptu_atc_ireq_less_than_stu",
3061 #define ptu_int_attn_desc OSAL_NULL
3064 static const u16 ptu_int0_bb_a0_attn_idx[8] = {
3065 0, 1, 2, 3, 4, 5, 6, 7,
3068 static struct attn_hw_reg ptu_int0_bb_a0 = {
3069 0, 8, ptu_int0_bb_a0_attn_idx, 0x560180, 0x56018c, 0x560188, 0x560184
3072 static struct attn_hw_reg *ptu_int_bb_a0_regs[1] = {
3076 static const u16 ptu_int0_bb_b0_attn_idx[8] = {
3077 0, 1, 2, 3, 4, 5, 6, 7,
3080 static struct attn_hw_reg ptu_int0_bb_b0 = {
3081 0, 8, ptu_int0_bb_b0_attn_idx, 0x560180, 0x56018c, 0x560188, 0x560184
3084 static struct attn_hw_reg *ptu_int_bb_b0_regs[1] = {
3088 static const u16 ptu_int0_k2_attn_idx[8] = {
3089 0, 1, 2, 3, 4, 5, 6, 7,
3092 static struct attn_hw_reg ptu_int0_k2 = {
3093 0, 8, ptu_int0_k2_attn_idx, 0x560180, 0x56018c, 0x560188, 0x560184
3096 static struct attn_hw_reg *ptu_int_k2_regs[1] = {
3101 static const char *ptu_prty_attn_desc[18] = {
3102 "ptu_mem017_i_ecc_rf_int",
3103 "ptu_mem018_i_mem_prty",
3104 "ptu_mem006_i_mem_prty",
3105 "ptu_mem001_i_mem_prty",
3106 "ptu_mem002_i_mem_prty",
3107 "ptu_mem003_i_mem_prty",
3108 "ptu_mem004_i_mem_prty",
3109 "ptu_mem005_i_mem_prty",
3110 "ptu_mem009_i_mem_prty",
3111 "ptu_mem010_i_mem_prty",
3112 "ptu_mem016_i_mem_prty",
3113 "ptu_mem007_i_mem_prty",
3114 "ptu_mem015_i_mem_prty",
3115 "ptu_mem013_i_mem_prty",
3116 "ptu_mem012_i_mem_prty",
3117 "ptu_mem014_i_mem_prty",
3118 "ptu_mem011_i_mem_prty",
3119 "ptu_mem008_i_mem_prty",
3122 #define ptu_prty_attn_desc OSAL_NULL
3125 static const u16 ptu_prty1_bb_a0_attn_idx[18] = {
3126 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
3129 static struct attn_hw_reg ptu_prty1_bb_a0 = {
3130 0, 18, ptu_prty1_bb_a0_attn_idx, 0x560200, 0x56020c, 0x560208, 0x560204
3133 static struct attn_hw_reg *ptu_prty_bb_a0_regs[1] = {
3137 static const u16 ptu_prty1_bb_b0_attn_idx[18] = {
3138 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
3141 static struct attn_hw_reg ptu_prty1_bb_b0 = {
3142 0, 18, ptu_prty1_bb_b0_attn_idx, 0x560200, 0x56020c, 0x560208, 0x560204
3145 static struct attn_hw_reg *ptu_prty_bb_b0_regs[1] = {
3149 static const u16 ptu_prty1_k2_attn_idx[18] = {
3150 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
3153 static struct attn_hw_reg ptu_prty1_k2 = {
3154 0, 18, ptu_prty1_k2_attn_idx, 0x560200, 0x56020c, 0x560208, 0x560204
3157 static struct attn_hw_reg *ptu_prty_k2_regs[1] = {
3162 static const char *tcm_int_attn_desc[41] = {
3163 "tcm_address_error",
3164 "tcm_is_storm_ovfl_err",
3165 "tcm_is_storm_under_err",
3166 "tcm_is_tsdm_ovfl_err",
3167 "tcm_is_tsdm_under_err",
3168 "tcm_is_msem_ovfl_err",
3169 "tcm_is_msem_under_err",
3170 "tcm_is_ysem_ovfl_err",
3171 "tcm_is_ysem_under_err",
3172 "tcm_is_dorq_ovfl_err",
3173 "tcm_is_dorq_under_err",
3174 "tcm_is_pbf_ovfl_err",
3175 "tcm_is_pbf_under_err",
3176 "tcm_is_prs_ovfl_err",
3177 "tcm_is_prs_under_err",
3178 "tcm_is_tm_ovfl_err",
3179 "tcm_is_tm_under_err",
3180 "tcm_is_qm_p_ovfl_err",
3181 "tcm_is_qm_p_under_err",
3182 "tcm_is_qm_s_ovfl_err",
3183 "tcm_is_qm_s_under_err",
3184 "tcm_is_grc_ovfl_err0",
3185 "tcm_is_grc_under_err0",
3186 "tcm_is_grc_ovfl_err1",
3187 "tcm_is_grc_under_err1",
3188 "tcm_is_grc_ovfl_err2",
3189 "tcm_is_grc_under_err2",
3190 "tcm_is_grc_ovfl_err3",
3191 "tcm_is_grc_under_err3",
3192 "tcm_in_prcs_tbl_ovfl",
3193 "tcm_agg_con_data_buf_ovfl",
3194 "tcm_agg_con_cmd_buf_ovfl",
3195 "tcm_sm_con_data_buf_ovfl",
3196 "tcm_sm_con_cmd_buf_ovfl",
3197 "tcm_agg_task_data_buf_ovfl",
3198 "tcm_agg_task_cmd_buf_ovfl",
3199 "tcm_sm_task_data_buf_ovfl",
3200 "tcm_sm_task_cmd_buf_ovfl",
3201 "tcm_fi_desc_input_violate",
3202 "tcm_se_desc_input_violate",
3206 #define tcm_int_attn_desc OSAL_NULL
3209 static const u16 tcm_int0_bb_a0_attn_idx[8] = {
3210 0, 1, 2, 3, 4, 5, 6, 7,
3213 static struct attn_hw_reg tcm_int0_bb_a0 = {
3214 0, 8, tcm_int0_bb_a0_attn_idx, 0x1180180, 0x118018c, 0x1180188,
3218 static const u16 tcm_int1_bb_a0_attn_idx[32] = {
3219 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
3221 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
3224 static struct attn_hw_reg tcm_int1_bb_a0 = {
3225 1, 32, tcm_int1_bb_a0_attn_idx, 0x1180190, 0x118019c, 0x1180198,
3229 static const u16 tcm_int2_bb_a0_attn_idx[1] = {
3233 static struct attn_hw_reg tcm_int2_bb_a0 = {
3234 2, 1, tcm_int2_bb_a0_attn_idx, 0x11801a0, 0x11801ac, 0x11801a8,
3238 static struct attn_hw_reg *tcm_int_bb_a0_regs[3] = {
3239 &tcm_int0_bb_a0, &tcm_int1_bb_a0, &tcm_int2_bb_a0,
3242 static const u16 tcm_int0_bb_b0_attn_idx[8] = {
3243 0, 1, 2, 3, 4, 5, 6, 7,
3246 static struct attn_hw_reg tcm_int0_bb_b0 = {
3247 0, 8, tcm_int0_bb_b0_attn_idx, 0x1180180, 0x118018c, 0x1180188,
3251 static const u16 tcm_int1_bb_b0_attn_idx[32] = {
3252 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
3254 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
3257 static struct attn_hw_reg tcm_int1_bb_b0 = {
3258 1, 32, tcm_int1_bb_b0_attn_idx, 0x1180190, 0x118019c, 0x1180198,
3262 static const u16 tcm_int2_bb_b0_attn_idx[1] = {
3266 static struct attn_hw_reg tcm_int2_bb_b0 = {
3267 2, 1, tcm_int2_bb_b0_attn_idx, 0x11801a0, 0x11801ac, 0x11801a8,
3271 static struct attn_hw_reg *tcm_int_bb_b0_regs[3] = {
3272 &tcm_int0_bb_b0, &tcm_int1_bb_b0, &tcm_int2_bb_b0,
3275 static const u16 tcm_int0_k2_attn_idx[8] = {
3276 0, 1, 2, 3, 4, 5, 6, 7,
3279 static struct attn_hw_reg tcm_int0_k2 = {
3280 0, 8, tcm_int0_k2_attn_idx, 0x1180180, 0x118018c, 0x1180188, 0x1180184
3283 static const u16 tcm_int1_k2_attn_idx[32] = {
3284 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
3286 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
3289 static struct attn_hw_reg tcm_int1_k2 = {
3290 1, 32, tcm_int1_k2_attn_idx, 0x1180190, 0x118019c, 0x1180198, 0x1180194
3293 static const u16 tcm_int2_k2_attn_idx[1] = {
3297 static struct attn_hw_reg tcm_int2_k2 = {
3298 2, 1, tcm_int2_k2_attn_idx, 0x11801a0, 0x11801ac, 0x11801a8, 0x11801a4
3301 static struct attn_hw_reg *tcm_int_k2_regs[3] = {
3302 &tcm_int0_k2, &tcm_int1_k2, &tcm_int2_k2,
3306 static const char *tcm_prty_attn_desc[51] = {
3307 "tcm_mem026_i_ecc_rf_int",
3308 "tcm_mem003_i_ecc_0_rf_int",
3309 "tcm_mem003_i_ecc_1_rf_int",
3310 "tcm_mem022_i_ecc_0_rf_int",
3311 "tcm_mem022_i_ecc_1_rf_int",
3312 "tcm_mem005_i_ecc_0_rf_int",
3313 "tcm_mem005_i_ecc_1_rf_int",
3314 "tcm_mem024_i_ecc_0_rf_int",
3315 "tcm_mem024_i_ecc_1_rf_int",
3316 "tcm_mem018_i_mem_prty",
3317 "tcm_mem019_i_mem_prty",
3318 "tcm_mem015_i_mem_prty",
3319 "tcm_mem016_i_mem_prty",
3320 "tcm_mem017_i_mem_prty",
3321 "tcm_mem010_i_mem_prty",
3322 "tcm_mem020_i_mem_prty",
3323 "tcm_mem011_i_mem_prty",
3324 "tcm_mem012_i_mem_prty",
3325 "tcm_mem013_i_mem_prty",
3326 "tcm_mem014_i_mem_prty",
3327 "tcm_mem029_i_mem_prty",
3328 "tcm_mem028_i_mem_prty",
3329 "tcm_mem027_i_mem_prty",
3330 "tcm_mem004_i_mem_prty",
3331 "tcm_mem023_i_mem_prty",
3332 "tcm_mem006_i_mem_prty",
3333 "tcm_mem025_i_mem_prty",
3334 "tcm_mem021_i_mem_prty",
3335 "tcm_mem007_i_mem_prty_0",
3336 "tcm_mem007_i_mem_prty_1",
3337 "tcm_mem008_i_mem_prty",
3338 "tcm_mem025_i_ecc_rf_int",
3339 "tcm_mem021_i_ecc_0_rf_int",
3340 "tcm_mem021_i_ecc_1_rf_int",
3341 "tcm_mem023_i_ecc_0_rf_int",
3342 "tcm_mem023_i_ecc_1_rf_int",
3343 "tcm_mem026_i_mem_prty",
3344 "tcm_mem022_i_mem_prty",
3345 "tcm_mem024_i_mem_prty",
3346 "tcm_mem009_i_mem_prty",
3347 "tcm_mem024_i_ecc_rf_int",
3348 "tcm_mem001_i_ecc_0_rf_int",
3349 "tcm_mem001_i_ecc_1_rf_int",
3350 "tcm_mem019_i_ecc_0_rf_int",
3351 "tcm_mem019_i_ecc_1_rf_int",
3352 "tcm_mem022_i_ecc_rf_int",
3353 "tcm_mem002_i_mem_prty",
3354 "tcm_mem005_i_mem_prty_0",
3355 "tcm_mem005_i_mem_prty_1",
3356 "tcm_mem001_i_mem_prty",
3357 "tcm_mem007_i_mem_prty",
3360 #define tcm_prty_attn_desc OSAL_NULL
3363 static const u16 tcm_prty1_bb_a0_attn_idx[31] = {
3364 1, 2, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 30, 32,
3365 33, 36, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
3368 static struct attn_hw_reg tcm_prty1_bb_a0 = {
3369 0, 31, tcm_prty1_bb_a0_attn_idx, 0x1180200, 0x118020c, 0x1180208,
3373 static const u16 tcm_prty2_bb_a0_attn_idx[3] = {
3377 static struct attn_hw_reg tcm_prty2_bb_a0 = {
3378 1, 3, tcm_prty2_bb_a0_attn_idx, 0x1180210, 0x118021c, 0x1180218,
3382 static struct attn_hw_reg *tcm_prty_bb_a0_regs[2] = {
3383 &tcm_prty1_bb_a0, &tcm_prty2_bb_a0,
3386 static const u16 tcm_prty1_bb_b0_attn_idx[31] = {
3387 1, 2, 5, 6, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 25,
3389 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
3392 static struct attn_hw_reg tcm_prty1_bb_b0 = {
3393 0, 31, tcm_prty1_bb_b0_attn_idx, 0x1180200, 0x118020c, 0x1180208,
3397 static const u16 tcm_prty2_bb_b0_attn_idx[2] = {
3401 static struct attn_hw_reg tcm_prty2_bb_b0 = {
3402 1, 2, tcm_prty2_bb_b0_attn_idx, 0x1180210, 0x118021c, 0x1180218,
3406 static struct attn_hw_reg *tcm_prty_bb_b0_regs[2] = {
3407 &tcm_prty1_bb_b0, &tcm_prty2_bb_b0,
3410 static const u16 tcm_prty1_k2_attn_idx[31] = {
3411 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
3413 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
3416 static struct attn_hw_reg tcm_prty1_k2 = {
3417 0, 31, tcm_prty1_k2_attn_idx, 0x1180200, 0x118020c, 0x1180208,
3421 static const u16 tcm_prty2_k2_attn_idx[3] = {
3425 static struct attn_hw_reg tcm_prty2_k2 = {
3426 1, 3, tcm_prty2_k2_attn_idx, 0x1180210, 0x118021c, 0x1180218, 0x1180214
3429 static struct attn_hw_reg *tcm_prty_k2_regs[2] = {
3430 &tcm_prty1_k2, &tcm_prty2_k2,
3434 static const char *mcm_int_attn_desc[41] = {
3435 "mcm_address_error",
3436 "mcm_is_storm_ovfl_err",
3437 "mcm_is_storm_under_err",
3438 "mcm_is_msdm_ovfl_err",
3439 "mcm_is_msdm_under_err",
3440 "mcm_is_ysdm_ovfl_err",
3441 "mcm_is_ysdm_under_err",
3442 "mcm_is_usdm_ovfl_err",
3443 "mcm_is_usdm_under_err",
3444 "mcm_is_tmld_ovfl_err",
3445 "mcm_is_tmld_under_err",
3446 "mcm_is_usem_ovfl_err",
3447 "mcm_is_usem_under_err",
3448 "mcm_is_ysem_ovfl_err",
3449 "mcm_is_ysem_under_err",
3450 "mcm_is_pbf_ovfl_err",
3451 "mcm_is_pbf_under_err",
3452 "mcm_is_qm_p_ovfl_err",
3453 "mcm_is_qm_p_under_err",
3454 "mcm_is_qm_s_ovfl_err",
3455 "mcm_is_qm_s_under_err",
3456 "mcm_is_grc_ovfl_err0",
3457 "mcm_is_grc_under_err0",
3458 "mcm_is_grc_ovfl_err1",
3459 "mcm_is_grc_under_err1",
3460 "mcm_is_grc_ovfl_err2",
3461 "mcm_is_grc_under_err2",
3462 "mcm_is_grc_ovfl_err3",
3463 "mcm_is_grc_under_err3",
3464 "mcm_in_prcs_tbl_ovfl",
3465 "mcm_agg_con_data_buf_ovfl",
3466 "mcm_agg_con_cmd_buf_ovfl",
3467 "mcm_sm_con_data_buf_ovfl",
3468 "mcm_sm_con_cmd_buf_ovfl",
3469 "mcm_agg_task_data_buf_ovfl",
3470 "mcm_agg_task_cmd_buf_ovfl",
3471 "mcm_sm_task_data_buf_ovfl",
3472 "mcm_sm_task_cmd_buf_ovfl",
3473 "mcm_fi_desc_input_violate",
3474 "mcm_se_desc_input_violate",
3478 #define mcm_int_attn_desc OSAL_NULL
3481 static const u16 mcm_int0_bb_a0_attn_idx[14] = {
3482 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
3485 static struct attn_hw_reg mcm_int0_bb_a0 = {
3486 0, 14, mcm_int0_bb_a0_attn_idx, 0x1200180, 0x120018c, 0x1200188,
3490 static const u16 mcm_int1_bb_a0_attn_idx[26] = {
3491 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
3492 32, 33, 34, 35, 36, 37, 38, 39,
3495 static struct attn_hw_reg mcm_int1_bb_a0 = {
3496 1, 26, mcm_int1_bb_a0_attn_idx, 0x1200190, 0x120019c, 0x1200198,
3500 static const u16 mcm_int2_bb_a0_attn_idx[1] = {
3504 static struct attn_hw_reg mcm_int2_bb_a0 = {
3505 2, 1, mcm_int2_bb_a0_attn_idx, 0x12001a0, 0x12001ac, 0x12001a8,
3509 static struct attn_hw_reg *mcm_int_bb_a0_regs[3] = {
3510 &mcm_int0_bb_a0, &mcm_int1_bb_a0, &mcm_int2_bb_a0,
3513 static const u16 mcm_int0_bb_b0_attn_idx[14] = {
3514 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
3517 static struct attn_hw_reg mcm_int0_bb_b0 = {
3518 0, 14, mcm_int0_bb_b0_attn_idx, 0x1200180, 0x120018c, 0x1200188,
3522 static const u16 mcm_int1_bb_b0_attn_idx[26] = {
3523 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
3524 32, 33, 34, 35, 36, 37, 38, 39,
3527 static struct attn_hw_reg mcm_int1_bb_b0 = {
3528 1, 26, mcm_int1_bb_b0_attn_idx, 0x1200190, 0x120019c, 0x1200198,
3532 static const u16 mcm_int2_bb_b0_attn_idx[1] = {
3536 static struct attn_hw_reg mcm_int2_bb_b0 = {
3537 2, 1, mcm_int2_bb_b0_attn_idx, 0x12001a0, 0x12001ac, 0x12001a8,
3541 static struct attn_hw_reg *mcm_int_bb_b0_regs[3] = {
3542 &mcm_int0_bb_b0, &mcm_int1_bb_b0, &mcm_int2_bb_b0,
3545 static const u16 mcm_int0_k2_attn_idx[14] = {
3546 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
3549 static struct attn_hw_reg mcm_int0_k2 = {
3550 0, 14, mcm_int0_k2_attn_idx, 0x1200180, 0x120018c, 0x1200188, 0x1200184
3553 static const u16 mcm_int1_k2_attn_idx[26] = {
3554 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
3555 32, 33, 34, 35, 36, 37, 38, 39,
3558 static struct attn_hw_reg mcm_int1_k2 = {
3559 1, 26, mcm_int1_k2_attn_idx, 0x1200190, 0x120019c, 0x1200198, 0x1200194
3562 static const u16 mcm_int2_k2_attn_idx[1] = {
3566 static struct attn_hw_reg mcm_int2_k2 = {
3567 2, 1, mcm_int2_k2_attn_idx, 0x12001a0, 0x12001ac, 0x12001a8, 0x12001a4
3570 static struct attn_hw_reg *mcm_int_k2_regs[3] = {
3571 &mcm_int0_k2, &mcm_int1_k2, &mcm_int2_k2,
3575 static const char *mcm_prty_attn_desc[46] = {
3576 "mcm_mem028_i_ecc_rf_int",
3577 "mcm_mem003_i_ecc_rf_int",
3578 "mcm_mem023_i_ecc_0_rf_int",
3579 "mcm_mem023_i_ecc_1_rf_int",
3580 "mcm_mem005_i_ecc_0_rf_int",
3581 "mcm_mem005_i_ecc_1_rf_int",
3582 "mcm_mem025_i_ecc_0_rf_int",
3583 "mcm_mem025_i_ecc_1_rf_int",
3584 "mcm_mem026_i_ecc_rf_int",
3585 "mcm_mem017_i_mem_prty",
3586 "mcm_mem019_i_mem_prty",
3587 "mcm_mem016_i_mem_prty",
3588 "mcm_mem015_i_mem_prty",
3589 "mcm_mem020_i_mem_prty",
3590 "mcm_mem021_i_mem_prty",
3591 "mcm_mem018_i_mem_prty",
3592 "mcm_mem011_i_mem_prty",
3593 "mcm_mem012_i_mem_prty",
3594 "mcm_mem013_i_mem_prty",
3595 "mcm_mem014_i_mem_prty",
3596 "mcm_mem031_i_mem_prty",
3597 "mcm_mem030_i_mem_prty",
3598 "mcm_mem029_i_mem_prty",
3599 "mcm_mem004_i_mem_prty",
3600 "mcm_mem024_i_mem_prty",
3601 "mcm_mem006_i_mem_prty",
3602 "mcm_mem027_i_mem_prty",
3603 "mcm_mem022_i_mem_prty",
3604 "mcm_mem007_i_mem_prty_0",
3605 "mcm_mem007_i_mem_prty_1",
3606 "mcm_mem008_i_mem_prty",
3607 "mcm_mem001_i_ecc_rf_int",
3608 "mcm_mem021_i_ecc_0_rf_int",
3609 "mcm_mem021_i_ecc_1_rf_int",
3610 "mcm_mem003_i_ecc_0_rf_int",
3611 "mcm_mem003_i_ecc_1_rf_int",
3612 "mcm_mem024_i_ecc_rf_int",
3613 "mcm_mem009_i_mem_prty",
3614 "mcm_mem010_i_mem_prty",
3615 "mcm_mem028_i_mem_prty",
3616 "mcm_mem002_i_mem_prty",
3617 "mcm_mem025_i_mem_prty",
3618 "mcm_mem005_i_mem_prty_0",
3619 "mcm_mem005_i_mem_prty_1",
3620 "mcm_mem001_i_mem_prty",
3621 "mcm_mem007_i_mem_prty",
3624 #define mcm_prty_attn_desc OSAL_NULL
3627 static const u16 mcm_prty1_bb_a0_attn_idx[31] = {
3628 2, 3, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, 22, 23, 25, 26, 27, 31,
3629 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
3632 static struct attn_hw_reg mcm_prty1_bb_a0 = {
3633 0, 31, mcm_prty1_bb_a0_attn_idx, 0x1200200, 0x120020c, 0x1200208,
3637 static const u16 mcm_prty2_bb_a0_attn_idx[4] = {
3641 static struct attn_hw_reg mcm_prty2_bb_a0 = {
3642 1, 4, mcm_prty2_bb_a0_attn_idx, 0x1200210, 0x120021c, 0x1200218,
3646 static struct attn_hw_reg *mcm_prty_bb_a0_regs[2] = {
3647 &mcm_prty1_bb_a0, &mcm_prty2_bb_a0,
3650 static const u16 mcm_prty1_bb_b0_attn_idx[31] = {
3651 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
3653 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
3656 static struct attn_hw_reg mcm_prty1_bb_b0 = {
3657 0, 31, mcm_prty1_bb_b0_attn_idx, 0x1200200, 0x120020c, 0x1200208,
3661 static const u16 mcm_prty2_bb_b0_attn_idx[4] = {
3665 static struct attn_hw_reg mcm_prty2_bb_b0 = {
3666 1, 4, mcm_prty2_bb_b0_attn_idx, 0x1200210, 0x120021c, 0x1200218,
3670 static struct attn_hw_reg *mcm_prty_bb_b0_regs[2] = {
3671 &mcm_prty1_bb_b0, &mcm_prty2_bb_b0,
3674 static const u16 mcm_prty1_k2_attn_idx[31] = {
3675 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
3677 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
3680 static struct attn_hw_reg mcm_prty1_k2 = {
3681 0, 31, mcm_prty1_k2_attn_idx, 0x1200200, 0x120020c, 0x1200208,
3685 static const u16 mcm_prty2_k2_attn_idx[4] = {
3689 static struct attn_hw_reg mcm_prty2_k2 = {
3690 1, 4, mcm_prty2_k2_attn_idx, 0x1200210, 0x120021c, 0x1200218, 0x1200214
3693 static struct attn_hw_reg *mcm_prty_k2_regs[2] = {
3694 &mcm_prty1_k2, &mcm_prty2_k2,
3698 static const char *ucm_int_attn_desc[47] = {
3699 "ucm_address_error",
3700 "ucm_is_storm_ovfl_err",
3701 "ucm_is_storm_under_err",
3702 "ucm_is_xsdm_ovfl_err",
3703 "ucm_is_xsdm_under_err",
3704 "ucm_is_ysdm_ovfl_err",
3705 "ucm_is_ysdm_under_err",
3706 "ucm_is_usdm_ovfl_err",
3707 "ucm_is_usdm_under_err",
3708 "ucm_is_rdif_ovfl_err",
3709 "ucm_is_rdif_under_err",
3710 "ucm_is_tdif_ovfl_err",
3711 "ucm_is_tdif_under_err",
3712 "ucm_is_muld_ovfl_err",
3713 "ucm_is_muld_under_err",
3714 "ucm_is_yuld_ovfl_err",
3715 "ucm_is_yuld_under_err",
3716 "ucm_is_dorq_ovfl_err",
3717 "ucm_is_dorq_under_err",
3718 "ucm_is_pbf_ovfl_err",
3719 "ucm_is_pbf_under_err",
3720 "ucm_is_tm_ovfl_err",
3721 "ucm_is_tm_under_err",
3722 "ucm_is_qm_p_ovfl_err",
3723 "ucm_is_qm_p_under_err",
3724 "ucm_is_qm_s_ovfl_err",
3725 "ucm_is_qm_s_under_err",
3726 "ucm_is_grc_ovfl_err0",
3727 "ucm_is_grc_under_err0",
3728 "ucm_is_grc_ovfl_err1",
3729 "ucm_is_grc_under_err1",
3730 "ucm_is_grc_ovfl_err2",
3731 "ucm_is_grc_under_err2",
3732 "ucm_is_grc_ovfl_err3",
3733 "ucm_is_grc_under_err3",
3734 "ucm_in_prcs_tbl_ovfl",
3735 "ucm_agg_con_data_buf_ovfl",
3736 "ucm_agg_con_cmd_buf_ovfl",
3737 "ucm_sm_con_data_buf_ovfl",
3738 "ucm_sm_con_cmd_buf_ovfl",
3739 "ucm_agg_task_data_buf_ovfl",
3740 "ucm_agg_task_cmd_buf_ovfl",
3741 "ucm_sm_task_data_buf_ovfl",
3742 "ucm_sm_task_cmd_buf_ovfl",
3743 "ucm_fi_desc_input_violate",
3744 "ucm_se_desc_input_violate",
3748 #define ucm_int_attn_desc OSAL_NULL
3751 static const u16 ucm_int0_bb_a0_attn_idx[17] = {
3752 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
3755 static struct attn_hw_reg ucm_int0_bb_a0 = {
3756 0, 17, ucm_int0_bb_a0_attn_idx, 0x1280180, 0x128018c, 0x1280188,
3760 static const u16 ucm_int1_bb_a0_attn_idx[29] = {
3761 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
3762 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
3765 static struct attn_hw_reg ucm_int1_bb_a0 = {
3766 1, 29, ucm_int1_bb_a0_attn_idx, 0x1280190, 0x128019c, 0x1280198,
3770 static const u16 ucm_int2_bb_a0_attn_idx[1] = {
3774 static struct attn_hw_reg ucm_int2_bb_a0 = {
3775 2, 1, ucm_int2_bb_a0_attn_idx, 0x12801a0, 0x12801ac, 0x12801a8,
3779 static struct attn_hw_reg *ucm_int_bb_a0_regs[3] = {
3780 &ucm_int0_bb_a0, &ucm_int1_bb_a0, &ucm_int2_bb_a0,
3783 static const u16 ucm_int0_bb_b0_attn_idx[17] = {
3784 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
3787 static struct attn_hw_reg ucm_int0_bb_b0 = {
3788 0, 17, ucm_int0_bb_b0_attn_idx, 0x1280180, 0x128018c, 0x1280188,
3792 static const u16 ucm_int1_bb_b0_attn_idx[29] = {
3793 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
3794 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
3797 static struct attn_hw_reg ucm_int1_bb_b0 = {
3798 1, 29, ucm_int1_bb_b0_attn_idx, 0x1280190, 0x128019c, 0x1280198,
3802 static const u16 ucm_int2_bb_b0_attn_idx[1] = {
3806 static struct attn_hw_reg ucm_int2_bb_b0 = {
3807 2, 1, ucm_int2_bb_b0_attn_idx, 0x12801a0, 0x12801ac, 0x12801a8,
3811 static struct attn_hw_reg *ucm_int_bb_b0_regs[3] = {
3812 &ucm_int0_bb_b0, &ucm_int1_bb_b0, &ucm_int2_bb_b0,
3815 static const u16 ucm_int0_k2_attn_idx[17] = {
3816 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
3819 static struct attn_hw_reg ucm_int0_k2 = {
3820 0, 17, ucm_int0_k2_attn_idx, 0x1280180, 0x128018c, 0x1280188, 0x1280184
3823 static const u16 ucm_int1_k2_attn_idx[29] = {
3824 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
3825 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
3828 static struct attn_hw_reg ucm_int1_k2 = {
3829 1, 29, ucm_int1_k2_attn_idx, 0x1280190, 0x128019c, 0x1280198, 0x1280194
3832 static const u16 ucm_int2_k2_attn_idx[1] = {
3836 static struct attn_hw_reg ucm_int2_k2 = {
3837 2, 1, ucm_int2_k2_attn_idx, 0x12801a0, 0x12801ac, 0x12801a8, 0x12801a4
3840 static struct attn_hw_reg *ucm_int_k2_regs[3] = {
3841 &ucm_int0_k2, &ucm_int1_k2, &ucm_int2_k2,
3845 static const char *ucm_prty_attn_desc[54] = {
3846 "ucm_mem030_i_ecc_rf_int",
3847 "ucm_mem005_i_ecc_0_rf_int",
3848 "ucm_mem005_i_ecc_1_rf_int",
3849 "ucm_mem024_i_ecc_0_rf_int",
3850 "ucm_mem024_i_ecc_1_rf_int",
3851 "ucm_mem025_i_ecc_rf_int",
3852 "ucm_mem007_i_ecc_0_rf_int",
3853 "ucm_mem007_i_ecc_1_rf_int",
3854 "ucm_mem008_i_ecc_rf_int",
3855 "ucm_mem027_i_ecc_0_rf_int",
3856 "ucm_mem027_i_ecc_1_rf_int",
3857 "ucm_mem028_i_ecc_rf_int",
3858 "ucm_mem020_i_mem_prty",
3859 "ucm_mem021_i_mem_prty",
3860 "ucm_mem019_i_mem_prty",
3861 "ucm_mem013_i_mem_prty",
3862 "ucm_mem018_i_mem_prty",
3863 "ucm_mem022_i_mem_prty",
3864 "ucm_mem014_i_mem_prty",
3865 "ucm_mem015_i_mem_prty",
3866 "ucm_mem016_i_mem_prty",
3867 "ucm_mem017_i_mem_prty",
3868 "ucm_mem033_i_mem_prty",
3869 "ucm_mem032_i_mem_prty",
3870 "ucm_mem031_i_mem_prty",
3871 "ucm_mem006_i_mem_prty",
3872 "ucm_mem026_i_mem_prty",
3873 "ucm_mem009_i_mem_prty",
3874 "ucm_mem029_i_mem_prty",
3875 "ucm_mem023_i_mem_prty",
3876 "ucm_mem010_i_mem_prty_0",
3877 "ucm_mem003_i_ecc_0_rf_int",
3878 "ucm_mem003_i_ecc_1_rf_int",
3879 "ucm_mem022_i_ecc_0_rf_int",
3880 "ucm_mem022_i_ecc_1_rf_int",
3881 "ucm_mem023_i_ecc_rf_int",
3882 "ucm_mem006_i_ecc_rf_int",
3883 "ucm_mem025_i_ecc_0_rf_int",
3884 "ucm_mem025_i_ecc_1_rf_int",
3885 "ucm_mem026_i_ecc_rf_int",
3886 "ucm_mem011_i_mem_prty",
3887 "ucm_mem012_i_mem_prty",
3888 "ucm_mem030_i_mem_prty",
3889 "ucm_mem004_i_mem_prty",
3890 "ucm_mem024_i_mem_prty",
3891 "ucm_mem007_i_mem_prty",
3892 "ucm_mem027_i_mem_prty",
3893 "ucm_mem008_i_mem_prty_0",
3894 "ucm_mem010_i_mem_prty_1",
3895 "ucm_mem003_i_mem_prty",
3896 "ucm_mem001_i_mem_prty",
3897 "ucm_mem002_i_mem_prty",
3898 "ucm_mem008_i_mem_prty_1",
3899 "ucm_mem010_i_mem_prty",
3902 #define ucm_prty_attn_desc OSAL_NULL
3905 static const u16 ucm_prty1_bb_a0_attn_idx[31] = {
3906 1, 2, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 24, 28, 31, 32, 33, 34,
3908 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
3911 static struct attn_hw_reg ucm_prty1_bb_a0 = {
3912 0, 31, ucm_prty1_bb_a0_attn_idx, 0x1280200, 0x128020c, 0x1280208,
3916 static const u16 ucm_prty2_bb_a0_attn_idx[7] = {
3917 50, 51, 52, 27, 53, 23, 22,
3920 static struct attn_hw_reg ucm_prty2_bb_a0 = {
3921 1, 7, ucm_prty2_bb_a0_attn_idx, 0x1280210, 0x128021c, 0x1280218,
3925 static struct attn_hw_reg *ucm_prty_bb_a0_regs[2] = {
3926 &ucm_prty1_bb_a0, &ucm_prty2_bb_a0,
3929 static const u16 ucm_prty1_bb_b0_attn_idx[31] = {
3930 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
3932 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
3935 static struct attn_hw_reg ucm_prty1_bb_b0 = {
3936 0, 31, ucm_prty1_bb_b0_attn_idx, 0x1280200, 0x128020c, 0x1280208,
3940 static const u16 ucm_prty2_bb_b0_attn_idx[7] = {
3941 48, 40, 41, 49, 43, 50, 51,
3944 static struct attn_hw_reg ucm_prty2_bb_b0 = {
3945 1, 7, ucm_prty2_bb_b0_attn_idx, 0x1280210, 0x128021c, 0x1280218,
3949 static struct attn_hw_reg *ucm_prty_bb_b0_regs[2] = {
3950 &ucm_prty1_bb_b0, &ucm_prty2_bb_b0,
3953 static const u16 ucm_prty1_k2_attn_idx[31] = {
3954 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
3956 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
3959 static struct attn_hw_reg ucm_prty1_k2 = {
3960 0, 31, ucm_prty1_k2_attn_idx, 0x1280200, 0x128020c, 0x1280208,
3964 static const u16 ucm_prty2_k2_attn_idx[7] = {
3965 48, 40, 41, 49, 43, 50, 51,
3968 static struct attn_hw_reg ucm_prty2_k2 = {
3969 1, 7, ucm_prty2_k2_attn_idx, 0x1280210, 0x128021c, 0x1280218, 0x1280214
3972 static struct attn_hw_reg *ucm_prty_k2_regs[2] = {
3973 &ucm_prty1_k2, &ucm_prty2_k2,
3977 static const char *xcm_int_attn_desc[49] = {
3978 "xcm_address_error",
3979 "xcm_is_storm_ovfl_err",
3980 "xcm_is_storm_under_err",
3981 "xcm_is_msdm_ovfl_err",
3982 "xcm_is_msdm_under_err",
3983 "xcm_is_xsdm_ovfl_err",
3984 "xcm_is_xsdm_under_err",
3985 "xcm_is_ysdm_ovfl_err",
3986 "xcm_is_ysdm_under_err",
3987 "xcm_is_usdm_ovfl_err",
3988 "xcm_is_usdm_under_err",
3989 "xcm_is_msem_ovfl_err",
3990 "xcm_is_msem_under_err",
3991 "xcm_is_usem_ovfl_err",
3992 "xcm_is_usem_under_err",
3993 "xcm_is_ysem_ovfl_err",
3994 "xcm_is_ysem_under_err",
3995 "xcm_is_dorq_ovfl_err",
3996 "xcm_is_dorq_under_err",
3997 "xcm_is_pbf_ovfl_err",
3998 "xcm_is_pbf_under_err",
3999 "xcm_is_tm_ovfl_err",
4000 "xcm_is_tm_under_err",
4001 "xcm_is_qm_p_ovfl_err",
4002 "xcm_is_qm_p_under_err",
4003 "xcm_is_qm_s_ovfl_err",
4004 "xcm_is_qm_s_under_err",
4005 "xcm_is_grc_ovfl_err0",
4006 "xcm_is_grc_under_err0",
4007 "xcm_is_grc_ovfl_err1",
4008 "xcm_is_grc_under_err1",
4009 "xcm_is_grc_ovfl_err2",
4010 "xcm_is_grc_under_err2",
4011 "xcm_is_grc_ovfl_err3",
4012 "xcm_is_grc_under_err3",
4013 "xcm_in_prcs_tbl_ovfl",
4014 "xcm_agg_con_data_buf_ovfl",
4015 "xcm_agg_con_cmd_buf_ovfl",
4016 "xcm_sm_con_data_buf_ovfl",
4017 "xcm_sm_con_cmd_buf_ovfl",
4018 "xcm_fi_desc_input_violate",
4019 "xcm_qm_act_st_cnt_msg_prcs_under",
4020 "xcm_qm_act_st_cnt_msg_prcs_ovfl",
4021 "xcm_qm_act_st_cnt_ext_ld_under",
4022 "xcm_qm_act_st_cnt_ext_ld_ovfl",
4023 "xcm_qm_act_st_cnt_rbc_under",
4024 "xcm_qm_act_st_cnt_rbc_ovfl",
4025 "xcm_qm_act_st_cnt_drop_under",
4026 "xcm_qm_act_st_cnt_illeg_pqnum",
4029 #define xcm_int_attn_desc OSAL_NULL
4032 static const u16 xcm_int0_bb_a0_attn_idx[16] = {
4033 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
4036 static struct attn_hw_reg xcm_int0_bb_a0 = {
4037 0, 16, xcm_int0_bb_a0_attn_idx, 0x1000180, 0x100018c, 0x1000188,
4041 static const u16 xcm_int1_bb_a0_attn_idx[25] = {
4042 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
4043 34, 35, 36, 37, 38, 39, 40,
4046 static struct attn_hw_reg xcm_int1_bb_a0 = {
4047 1, 25, xcm_int1_bb_a0_attn_idx, 0x1000190, 0x100019c, 0x1000198,
4051 static const u16 xcm_int2_bb_a0_attn_idx[8] = {
4052 41, 42, 43, 44, 45, 46, 47, 48,
4055 static struct attn_hw_reg xcm_int2_bb_a0 = {
4056 2, 8, xcm_int2_bb_a0_attn_idx, 0x10001a0, 0x10001ac, 0x10001a8,
4060 static struct attn_hw_reg *xcm_int_bb_a0_regs[3] = {
4061 &xcm_int0_bb_a0, &xcm_int1_bb_a0, &xcm_int2_bb_a0,
4064 static const u16 xcm_int0_bb_b0_attn_idx[16] = {
4065 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
4068 static struct attn_hw_reg xcm_int0_bb_b0 = {
4069 0, 16, xcm_int0_bb_b0_attn_idx, 0x1000180, 0x100018c, 0x1000188,
4073 static const u16 xcm_int1_bb_b0_attn_idx[25] = {
4074 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
4075 34, 35, 36, 37, 38, 39, 40,
4078 static struct attn_hw_reg xcm_int1_bb_b0 = {
4079 1, 25, xcm_int1_bb_b0_attn_idx, 0x1000190, 0x100019c, 0x1000198,
4083 static const u16 xcm_int2_bb_b0_attn_idx[8] = {
4084 41, 42, 43, 44, 45, 46, 47, 48,
4087 static struct attn_hw_reg xcm_int2_bb_b0 = {
4088 2, 8, xcm_int2_bb_b0_attn_idx, 0x10001a0, 0x10001ac, 0x10001a8,
4092 static struct attn_hw_reg *xcm_int_bb_b0_regs[3] = {
4093 &xcm_int0_bb_b0, &xcm_int1_bb_b0, &xcm_int2_bb_b0,
4096 static const u16 xcm_int0_k2_attn_idx[16] = {
4097 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
4100 static struct attn_hw_reg xcm_int0_k2 = {
4101 0, 16, xcm_int0_k2_attn_idx, 0x1000180, 0x100018c, 0x1000188, 0x1000184
4104 static const u16 xcm_int1_k2_attn_idx[25] = {
4105 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
4106 34, 35, 36, 37, 38, 39, 40,
4109 static struct attn_hw_reg xcm_int1_k2 = {
4110 1, 25, xcm_int1_k2_attn_idx, 0x1000190, 0x100019c, 0x1000198, 0x1000194
4113 static const u16 xcm_int2_k2_attn_idx[8] = {
4114 41, 42, 43, 44, 45, 46, 47, 48,
4117 static struct attn_hw_reg xcm_int2_k2 = {
4118 2, 8, xcm_int2_k2_attn_idx, 0x10001a0, 0x10001ac, 0x10001a8, 0x10001a4
4121 static struct attn_hw_reg *xcm_int_k2_regs[3] = {
4122 &xcm_int0_k2, &xcm_int1_k2, &xcm_int2_k2,
4126 static const char *xcm_prty_attn_desc[59] = {
4127 "xcm_mem036_i_ecc_rf_int",
4128 "xcm_mem003_i_ecc_0_rf_int",
4129 "xcm_mem003_i_ecc_1_rf_int",
4130 "xcm_mem003_i_ecc_2_rf_int",
4131 "xcm_mem003_i_ecc_3_rf_int",
4132 "xcm_mem004_i_ecc_rf_int",
4133 "xcm_mem033_i_ecc_0_rf_int",
4134 "xcm_mem033_i_ecc_1_rf_int",
4135 "xcm_mem034_i_ecc_rf_int",
4136 "xcm_mem026_i_mem_prty",
4137 "xcm_mem025_i_mem_prty",
4138 "xcm_mem022_i_mem_prty",
4139 "xcm_mem029_i_mem_prty",
4140 "xcm_mem023_i_mem_prty",
4141 "xcm_mem028_i_mem_prty",
4142 "xcm_mem030_i_mem_prty",
4143 "xcm_mem017_i_mem_prty",
4144 "xcm_mem024_i_mem_prty",
4145 "xcm_mem027_i_mem_prty",
4146 "xcm_mem018_i_mem_prty",
4147 "xcm_mem019_i_mem_prty",
4148 "xcm_mem020_i_mem_prty",
4149 "xcm_mem021_i_mem_prty",
4150 "xcm_mem039_i_mem_prty",
4151 "xcm_mem038_i_mem_prty",
4152 "xcm_mem037_i_mem_prty",
4153 "xcm_mem005_i_mem_prty",
4154 "xcm_mem035_i_mem_prty",
4155 "xcm_mem031_i_mem_prty",
4156 "xcm_mem006_i_mem_prty",
4157 "xcm_mem015_i_mem_prty",
4158 "xcm_mem035_i_ecc_rf_int",
4159 "xcm_mem032_i_ecc_0_rf_int",
4160 "xcm_mem032_i_ecc_1_rf_int",
4161 "xcm_mem033_i_ecc_rf_int",
4162 "xcm_mem036_i_mem_prty",
4163 "xcm_mem034_i_mem_prty",
4164 "xcm_mem016_i_mem_prty",
4165 "xcm_mem002_i_ecc_0_rf_int",
4166 "xcm_mem002_i_ecc_1_rf_int",
4167 "xcm_mem002_i_ecc_2_rf_int",
4168 "xcm_mem002_i_ecc_3_rf_int",
4169 "xcm_mem003_i_ecc_rf_int",
4170 "xcm_mem031_i_ecc_0_rf_int",
4171 "xcm_mem031_i_ecc_1_rf_int",
4172 "xcm_mem032_i_ecc_rf_int",
4173 "xcm_mem004_i_mem_prty",
4174 "xcm_mem033_i_mem_prty",
4175 "xcm_mem014_i_mem_prty",
4176 "xcm_mem032_i_mem_prty",
4177 "xcm_mem007_i_mem_prty",
4178 "xcm_mem008_i_mem_prty",
4179 "xcm_mem009_i_mem_prty",
4180 "xcm_mem010_i_mem_prty",
4181 "xcm_mem011_i_mem_prty",
4182 "xcm_mem012_i_mem_prty",
4183 "xcm_mem013_i_mem_prty",
4184 "xcm_mem001_i_mem_prty",
4185 "xcm_mem002_i_mem_prty",
4188 #define xcm_prty_attn_desc OSAL_NULL
4191 static const u16 xcm_prty1_bb_a0_attn_idx[31] = {
4192 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 25, 26, 27, 30,
4194 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
4197 static struct attn_hw_reg xcm_prty1_bb_a0 = {
4198 0, 31, xcm_prty1_bb_a0_attn_idx, 0x1000200, 0x100020c, 0x1000208,
4202 static const u16 xcm_prty2_bb_a0_attn_idx[11] = {
4203 50, 51, 52, 53, 54, 55, 56, 57, 15, 29, 24,
4206 static struct attn_hw_reg xcm_prty2_bb_a0 = {
4207 1, 11, xcm_prty2_bb_a0_attn_idx, 0x1000210, 0x100021c, 0x1000218,
4211 static struct attn_hw_reg *xcm_prty_bb_a0_regs[2] = {
4212 &xcm_prty1_bb_a0, &xcm_prty2_bb_a0,
4215 static const u16 xcm_prty1_bb_b0_attn_idx[31] = {
4216 1, 2, 3, 4, 5, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
4218 25, 26, 29, 30, 31, 32, 33, 34, 35, 36, 37,
4221 static struct attn_hw_reg xcm_prty1_bb_b0 = {
4222 0, 31, xcm_prty1_bb_b0_attn_idx, 0x1000200, 0x100020c, 0x1000208,
4226 static const u16 xcm_prty2_bb_b0_attn_idx[11] = {
4227 50, 51, 52, 53, 54, 55, 56, 48, 57, 58, 28,
4230 static struct attn_hw_reg xcm_prty2_bb_b0 = {
4231 1, 11, xcm_prty2_bb_b0_attn_idx, 0x1000210, 0x100021c, 0x1000218,
4235 static struct attn_hw_reg *xcm_prty_bb_b0_regs[2] = {
4236 &xcm_prty1_bb_b0, &xcm_prty2_bb_b0,
4239 static const u16 xcm_prty1_k2_attn_idx[31] = {
4240 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
4242 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
4245 static struct attn_hw_reg xcm_prty1_k2 = {
4246 0, 31, xcm_prty1_k2_attn_idx, 0x1000200, 0x100020c, 0x1000208,
4250 static const u16 xcm_prty2_k2_attn_idx[12] = {
4251 37, 49, 50, 51, 52, 53, 54, 55, 56, 48, 57, 58,
4254 static struct attn_hw_reg xcm_prty2_k2 = {
4255 1, 12, xcm_prty2_k2_attn_idx, 0x1000210, 0x100021c, 0x1000218,
4259 static struct attn_hw_reg *xcm_prty_k2_regs[2] = {
4260 &xcm_prty1_k2, &xcm_prty2_k2,
4264 static const char *ycm_int_attn_desc[37] = {
4265 "ycm_address_error",
4266 "ycm_is_storm_ovfl_err",
4267 "ycm_is_storm_under_err",
4268 "ycm_is_msdm_ovfl_err",
4269 "ycm_is_msdm_under_err",
4270 "ycm_is_ysdm_ovfl_err",
4271 "ycm_is_ysdm_under_err",
4272 "ycm_is_xyld_ovfl_err",
4273 "ycm_is_xyld_under_err",
4274 "ycm_is_msem_ovfl_err",
4275 "ycm_is_msem_under_err",
4276 "ycm_is_usem_ovfl_err",
4277 "ycm_is_usem_under_err",
4278 "ycm_is_pbf_ovfl_err",
4279 "ycm_is_pbf_under_err",
4280 "ycm_is_qm_p_ovfl_err",
4281 "ycm_is_qm_p_under_err",
4282 "ycm_is_qm_s_ovfl_err",
4283 "ycm_is_qm_s_under_err",
4284 "ycm_is_grc_ovfl_err0",
4285 "ycm_is_grc_under_err0",
4286 "ycm_is_grc_ovfl_err1",
4287 "ycm_is_grc_under_err1",
4288 "ycm_is_grc_ovfl_err2",
4289 "ycm_is_grc_under_err2",
4290 "ycm_is_grc_ovfl_err3",
4291 "ycm_is_grc_under_err3",
4292 "ycm_in_prcs_tbl_ovfl",
4293 "ycm_sm_con_data_buf_ovfl",
4294 "ycm_sm_con_cmd_buf_ovfl",
4295 "ycm_agg_task_data_buf_ovfl",
4296 "ycm_agg_task_cmd_buf_ovfl",
4297 "ycm_sm_task_data_buf_ovfl",
4298 "ycm_sm_task_cmd_buf_ovfl",
4299 "ycm_fi_desc_input_violate",
4300 "ycm_se_desc_input_violate",
4304 #define ycm_int_attn_desc OSAL_NULL
4307 static const u16 ycm_int0_bb_a0_attn_idx[13] = {
4308 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
4311 static struct attn_hw_reg ycm_int0_bb_a0 = {
4312 0, 13, ycm_int0_bb_a0_attn_idx, 0x1080180, 0x108018c, 0x1080188,
4316 static const u16 ycm_int1_bb_a0_attn_idx[23] = {
4317 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
4321 static struct attn_hw_reg ycm_int1_bb_a0 = {
4322 1, 23, ycm_int1_bb_a0_attn_idx, 0x1080190, 0x108019c, 0x1080198,
4326 static const u16 ycm_int2_bb_a0_attn_idx[1] = {
4330 static struct attn_hw_reg ycm_int2_bb_a0 = {
4331 2, 1, ycm_int2_bb_a0_attn_idx, 0x10801a0, 0x10801ac, 0x10801a8,
4335 static struct attn_hw_reg *ycm_int_bb_a0_regs[3] = {
4336 &ycm_int0_bb_a0, &ycm_int1_bb_a0, &ycm_int2_bb_a0,
4339 static const u16 ycm_int0_bb_b0_attn_idx[13] = {
4340 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
4343 static struct attn_hw_reg ycm_int0_bb_b0 = {
4344 0, 13, ycm_int0_bb_b0_attn_idx, 0x1080180, 0x108018c, 0x1080188,
4348 static const u16 ycm_int1_bb_b0_attn_idx[23] = {
4349 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
4353 static struct attn_hw_reg ycm_int1_bb_b0 = {
4354 1, 23, ycm_int1_bb_b0_attn_idx, 0x1080190, 0x108019c, 0x1080198,
4358 static const u16 ycm_int2_bb_b0_attn_idx[1] = {
4362 static struct attn_hw_reg ycm_int2_bb_b0 = {
4363 2, 1, ycm_int2_bb_b0_attn_idx, 0x10801a0, 0x10801ac, 0x10801a8,
4367 static struct attn_hw_reg *ycm_int_bb_b0_regs[3] = {
4368 &ycm_int0_bb_b0, &ycm_int1_bb_b0, &ycm_int2_bb_b0,
4371 static const u16 ycm_int0_k2_attn_idx[13] = {
4372 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
4375 static struct attn_hw_reg ycm_int0_k2 = {
4376 0, 13, ycm_int0_k2_attn_idx, 0x1080180, 0x108018c, 0x1080188, 0x1080184
4379 static const u16 ycm_int1_k2_attn_idx[23] = {
4380 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
4384 static struct attn_hw_reg ycm_int1_k2 = {
4385 1, 23, ycm_int1_k2_attn_idx, 0x1080190, 0x108019c, 0x1080198, 0x1080194
4388 static const u16 ycm_int2_k2_attn_idx[1] = {
4392 static struct attn_hw_reg ycm_int2_k2 = {
4393 2, 1, ycm_int2_k2_attn_idx, 0x10801a0, 0x10801ac, 0x10801a8, 0x10801a4
4396 static struct attn_hw_reg *ycm_int_k2_regs[3] = {
4397 &ycm_int0_k2, &ycm_int1_k2, &ycm_int2_k2,
4401 static const char *ycm_prty_attn_desc[44] = {
4402 "ycm_mem027_i_ecc_rf_int",
4403 "ycm_mem003_i_ecc_0_rf_int",
4404 "ycm_mem003_i_ecc_1_rf_int",
4405 "ycm_mem022_i_ecc_0_rf_int",
4406 "ycm_mem022_i_ecc_1_rf_int",
4407 "ycm_mem023_i_ecc_rf_int",
4408 "ycm_mem005_i_ecc_0_rf_int",
4409 "ycm_mem005_i_ecc_1_rf_int",
4410 "ycm_mem025_i_ecc_0_rf_int",
4411 "ycm_mem025_i_ecc_1_rf_int",
4412 "ycm_mem018_i_mem_prty",
4413 "ycm_mem020_i_mem_prty",
4414 "ycm_mem017_i_mem_prty",
4415 "ycm_mem016_i_mem_prty",
4416 "ycm_mem019_i_mem_prty",
4417 "ycm_mem015_i_mem_prty",
4418 "ycm_mem011_i_mem_prty",
4419 "ycm_mem012_i_mem_prty",
4420 "ycm_mem013_i_mem_prty",
4421 "ycm_mem014_i_mem_prty",
4422 "ycm_mem030_i_mem_prty",
4423 "ycm_mem029_i_mem_prty",
4424 "ycm_mem028_i_mem_prty",
4425 "ycm_mem004_i_mem_prty",
4426 "ycm_mem024_i_mem_prty",
4427 "ycm_mem006_i_mem_prty",
4428 "ycm_mem026_i_mem_prty",
4429 "ycm_mem021_i_mem_prty",
4430 "ycm_mem007_i_mem_prty_0",
4431 "ycm_mem007_i_mem_prty_1",
4432 "ycm_mem008_i_mem_prty",
4433 "ycm_mem026_i_ecc_rf_int",
4434 "ycm_mem021_i_ecc_0_rf_int",
4435 "ycm_mem021_i_ecc_1_rf_int",
4436 "ycm_mem022_i_ecc_rf_int",
4437 "ycm_mem024_i_ecc_0_rf_int",
4438 "ycm_mem024_i_ecc_1_rf_int",
4439 "ycm_mem027_i_mem_prty",
4440 "ycm_mem023_i_mem_prty",
4441 "ycm_mem025_i_mem_prty",
4442 "ycm_mem009_i_mem_prty",
4443 "ycm_mem010_i_mem_prty",
4444 "ycm_mem001_i_mem_prty",
4445 "ycm_mem002_i_mem_prty",
4448 #define ycm_prty_attn_desc OSAL_NULL
4451 static const u16 ycm_prty1_bb_a0_attn_idx[31] = {
4452 1, 2, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 25, 28,
4453 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40,
4456 static struct attn_hw_reg ycm_prty1_bb_a0 = {
4457 0, 31, ycm_prty1_bb_a0_attn_idx, 0x1080200, 0x108020c, 0x1080208,
4461 static const u16 ycm_prty2_bb_a0_attn_idx[3] = {
4465 static struct attn_hw_reg ycm_prty2_bb_a0 = {
4466 1, 3, ycm_prty2_bb_a0_attn_idx, 0x1080210, 0x108021c, 0x1080218,
4470 static struct attn_hw_reg *ycm_prty_bb_a0_regs[2] = {
4471 &ycm_prty1_bb_a0, &ycm_prty2_bb_a0,
4474 static const u16 ycm_prty1_bb_b0_attn_idx[31] = {
4475 1, 2, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 25, 28,
4476 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40,
4479 static struct attn_hw_reg ycm_prty1_bb_b0 = {
4480 0, 31, ycm_prty1_bb_b0_attn_idx, 0x1080200, 0x108020c, 0x1080208,
4484 static const u16 ycm_prty2_bb_b0_attn_idx[3] = {
4488 static struct attn_hw_reg ycm_prty2_bb_b0 = {
4489 1, 3, ycm_prty2_bb_b0_attn_idx, 0x1080210, 0x108021c, 0x1080218,
4493 static struct attn_hw_reg *ycm_prty_bb_b0_regs[2] = {
4494 &ycm_prty1_bb_b0, &ycm_prty2_bb_b0,
4497 static const u16 ycm_prty1_k2_attn_idx[31] = {
4498 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
4500 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
4503 static struct attn_hw_reg ycm_prty1_k2 = {
4504 0, 31, ycm_prty1_k2_attn_idx, 0x1080200, 0x108020c, 0x1080208,
4508 static const u16 ycm_prty2_k2_attn_idx[4] = {
4512 static struct attn_hw_reg ycm_prty2_k2 = {
4513 1, 4, ycm_prty2_k2_attn_idx, 0x1080210, 0x108021c, 0x1080218, 0x1080214
4516 static struct attn_hw_reg *ycm_prty_k2_regs[2] = {
4517 &ycm_prty1_k2, &ycm_prty2_k2,
4521 static const char *pcm_int_attn_desc[20] = {
4522 "pcm_address_error",
4523 "pcm_is_storm_ovfl_err",
4524 "pcm_is_storm_under_err",
4525 "pcm_is_psdm_ovfl_err",
4526 "pcm_is_psdm_under_err",
4527 "pcm_is_pbf_ovfl_err",
4528 "pcm_is_pbf_under_err",
4529 "pcm_is_grc_ovfl_err0",
4530 "pcm_is_grc_under_err0",
4531 "pcm_is_grc_ovfl_err1",
4532 "pcm_is_grc_under_err1",
4533 "pcm_is_grc_ovfl_err2",
4534 "pcm_is_grc_under_err2",
4535 "pcm_is_grc_ovfl_err3",
4536 "pcm_is_grc_under_err3",
4537 "pcm_in_prcs_tbl_ovfl",
4538 "pcm_sm_con_data_buf_ovfl",
4539 "pcm_sm_con_cmd_buf_ovfl",
4540 "pcm_fi_desc_input_violate",
4544 #define pcm_int_attn_desc OSAL_NULL
4547 static const u16 pcm_int0_bb_a0_attn_idx[5] = {
4551 static struct attn_hw_reg pcm_int0_bb_a0 = {
4552 0, 5, pcm_int0_bb_a0_attn_idx, 0x1100180, 0x110018c, 0x1100188,
4556 static const u16 pcm_int1_bb_a0_attn_idx[14] = {
4557 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
4560 static struct attn_hw_reg pcm_int1_bb_a0 = {
4561 1, 14, pcm_int1_bb_a0_attn_idx, 0x1100190, 0x110019c, 0x1100198,
4565 static const u16 pcm_int2_bb_a0_attn_idx[1] = {
4569 static struct attn_hw_reg pcm_int2_bb_a0 = {
4570 2, 1, pcm_int2_bb_a0_attn_idx, 0x11001a0, 0x11001ac, 0x11001a8,
4574 static struct attn_hw_reg *pcm_int_bb_a0_regs[3] = {
4575 &pcm_int0_bb_a0, &pcm_int1_bb_a0, &pcm_int2_bb_a0,
4578 static const u16 pcm_int0_bb_b0_attn_idx[5] = {
4582 static struct attn_hw_reg pcm_int0_bb_b0 = {
4583 0, 5, pcm_int0_bb_b0_attn_idx, 0x1100180, 0x110018c, 0x1100188,
4587 static const u16 pcm_int1_bb_b0_attn_idx[14] = {
4588 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
4591 static struct attn_hw_reg pcm_int1_bb_b0 = {
4592 1, 14, pcm_int1_bb_b0_attn_idx, 0x1100190, 0x110019c, 0x1100198,
4596 static const u16 pcm_int2_bb_b0_attn_idx[1] = {
4600 static struct attn_hw_reg pcm_int2_bb_b0 = {
4601 2, 1, pcm_int2_bb_b0_attn_idx, 0x11001a0, 0x11001ac, 0x11001a8,
4605 static struct attn_hw_reg *pcm_int_bb_b0_regs[3] = {
4606 &pcm_int0_bb_b0, &pcm_int1_bb_b0, &pcm_int2_bb_b0,
4609 static const u16 pcm_int0_k2_attn_idx[5] = {
4613 static struct attn_hw_reg pcm_int0_k2 = {
4614 0, 5, pcm_int0_k2_attn_idx, 0x1100180, 0x110018c, 0x1100188, 0x1100184
4617 static const u16 pcm_int1_k2_attn_idx[14] = {
4618 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
4621 static struct attn_hw_reg pcm_int1_k2 = {
4622 1, 14, pcm_int1_k2_attn_idx, 0x1100190, 0x110019c, 0x1100198, 0x1100194
4625 static const u16 pcm_int2_k2_attn_idx[1] = {
4629 static struct attn_hw_reg pcm_int2_k2 = {
4630 2, 1, pcm_int2_k2_attn_idx, 0x11001a0, 0x11001ac, 0x11001a8, 0x11001a4
4633 static struct attn_hw_reg *pcm_int_k2_regs[3] = {
4634 &pcm_int0_k2, &pcm_int1_k2, &pcm_int2_k2,
4638 static const char *pcm_prty_attn_desc[18] = {
4639 "pcm_mem012_i_ecc_rf_int",
4640 "pcm_mem010_i_ecc_0_rf_int",
4641 "pcm_mem010_i_ecc_1_rf_int",
4642 "pcm_mem008_i_mem_prty",
4643 "pcm_mem007_i_mem_prty",
4644 "pcm_mem006_i_mem_prty",
4645 "pcm_mem002_i_mem_prty",
4646 "pcm_mem003_i_mem_prty",
4647 "pcm_mem004_i_mem_prty",
4648 "pcm_mem005_i_mem_prty",
4649 "pcm_mem011_i_mem_prty",
4650 "pcm_mem001_i_mem_prty",
4651 "pcm_mem011_i_ecc_rf_int",
4652 "pcm_mem009_i_ecc_0_rf_int",
4653 "pcm_mem009_i_ecc_1_rf_int",
4654 "pcm_mem010_i_mem_prty",
4655 "pcm_mem013_i_mem_prty",
4656 "pcm_mem012_i_mem_prty",
4659 #define pcm_prty_attn_desc OSAL_NULL
4662 static const u16 pcm_prty1_bb_a0_attn_idx[14] = {
4663 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17,
4666 static struct attn_hw_reg pcm_prty1_bb_a0 = {
4667 0, 14, pcm_prty1_bb_a0_attn_idx, 0x1100200, 0x110020c, 0x1100208,
4671 static struct attn_hw_reg *pcm_prty_bb_a0_regs[1] = {
4675 static const u16 pcm_prty1_bb_b0_attn_idx[11] = {
4676 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15,
4679 static struct attn_hw_reg pcm_prty1_bb_b0 = {
4680 0, 11, pcm_prty1_bb_b0_attn_idx, 0x1100200, 0x110020c, 0x1100208,
4684 static struct attn_hw_reg *pcm_prty_bb_b0_regs[1] = {
4688 static const u16 pcm_prty1_k2_attn_idx[12] = {
4689 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
4692 static struct attn_hw_reg pcm_prty1_k2 = {
4693 0, 12, pcm_prty1_k2_attn_idx, 0x1100200, 0x110020c, 0x1100208,
4697 static struct attn_hw_reg *pcm_prty_k2_regs[1] = {
4702 static const char *qm_int_attn_desc[22] = {
4706 "qm_pf_usg_cnt_err",
4707 "qm_vf_usg_cnt_err",
4708 "qm_voq_crd_inc_err",
4709 "qm_voq_crd_dec_err",
4710 "qm_byte_crd_inc_err",
4711 "qm_byte_crd_dec_err",
4712 "qm_err_incdec_rlglblcrd",
4713 "qm_err_incdec_rlpfcrd",
4714 "qm_err_incdec_wfqpfcrd",
4715 "qm_err_incdec_wfqvpcrd",
4716 "qm_err_incdec_voqlinecrd",
4717 "qm_err_incdec_voqbytecrd",
4719 "qm_qm_rl_dc_exp_pf_controller_pop_error",
4720 "qm_qm_rl_dc_exp_pf_controller_push_error",
4721 "qm_qm_rl_dc_rf_req_controller_pop_error",
4722 "qm_qm_rl_dc_rf_req_controller_push_error",
4723 "qm_qm_rl_dc_rf_res_controller_pop_error",
4724 "qm_qm_rl_dc_rf_res_controller_push_error",
4727 #define qm_int_attn_desc OSAL_NULL
4730 static const u16 qm_int0_bb_a0_attn_idx[16] = {
4731 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
4734 static struct attn_hw_reg qm_int0_bb_a0 = {
4735 0, 16, qm_int0_bb_a0_attn_idx, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184
4738 static struct attn_hw_reg *qm_int_bb_a0_regs[1] = {
4742 static const u16 qm_int0_bb_b0_attn_idx[22] = {
4743 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
4748 static struct attn_hw_reg qm_int0_bb_b0 = {
4749 0, 22, qm_int0_bb_b0_attn_idx, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184
4752 static struct attn_hw_reg *qm_int_bb_b0_regs[1] = {
4756 static const u16 qm_int0_k2_attn_idx[22] = {
4757 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
4762 static struct attn_hw_reg qm_int0_k2 = {
4763 0, 22, qm_int0_k2_attn_idx, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184
4766 static struct attn_hw_reg *qm_int_k2_regs[1] = {
4771 static const char *qm_prty_attn_desc[109] = {
4780 "qm_bigramhigh_ext_a",
4781 "qm_bigramlow_ext_a",
4782 "qm_base_address_ext_a",
4783 "qm_mem006_i_ecc_0_rf_int",
4784 "qm_mem006_i_ecc_1_rf_int",
4785 "qm_mem005_i_ecc_0_rf_int",
4786 "qm_mem005_i_ecc_1_rf_int",
4787 "qm_mem012_i_ecc_rf_int",
4788 "qm_mem037_i_mem_prty",
4789 "qm_mem036_i_mem_prty",
4790 "qm_mem039_i_mem_prty",
4791 "qm_mem038_i_mem_prty",
4792 "qm_mem040_i_mem_prty",
4793 "qm_mem042_i_mem_prty",
4794 "qm_mem041_i_mem_prty",
4795 "qm_mem056_i_mem_prty",
4796 "qm_mem055_i_mem_prty",
4797 "qm_mem053_i_mem_prty",
4798 "qm_mem054_i_mem_prty",
4799 "qm_mem057_i_mem_prty",
4800 "qm_mem058_i_mem_prty",
4801 "qm_mem062_i_mem_prty",
4802 "qm_mem061_i_mem_prty",
4803 "qm_mem059_i_mem_prty",
4804 "qm_mem060_i_mem_prty",
4805 "qm_mem063_i_mem_prty",
4806 "qm_mem064_i_mem_prty",
4807 "qm_mem033_i_mem_prty",
4808 "qm_mem032_i_mem_prty",
4809 "qm_mem030_i_mem_prty",
4810 "qm_mem031_i_mem_prty",
4811 "qm_mem034_i_mem_prty",
4812 "qm_mem035_i_mem_prty",
4813 "qm_mem051_i_mem_prty",
4814 "qm_mem042_i_ecc_0_rf_int",
4815 "qm_mem042_i_ecc_1_rf_int",
4816 "qm_mem041_i_ecc_0_rf_int",
4817 "qm_mem041_i_ecc_1_rf_int",
4818 "qm_mem048_i_ecc_rf_int",
4819 "qm_mem009_i_mem_prty",
4820 "qm_mem008_i_mem_prty",
4821 "qm_mem011_i_mem_prty",
4822 "qm_mem010_i_mem_prty",
4823 "qm_mem012_i_mem_prty",
4824 "qm_mem014_i_mem_prty",
4825 "qm_mem013_i_mem_prty",
4826 "qm_mem028_i_mem_prty",
4827 "qm_mem027_i_mem_prty",
4828 "qm_mem025_i_mem_prty",
4829 "qm_mem026_i_mem_prty",
4830 "qm_mem029_i_mem_prty",
4831 "qm_mem005_i_mem_prty",
4832 "qm_mem004_i_mem_prty",
4833 "qm_mem002_i_mem_prty",
4834 "qm_mem003_i_mem_prty",
4835 "qm_mem006_i_mem_prty",
4836 "qm_mem007_i_mem_prty",
4837 "qm_mem023_i_mem_prty",
4838 "qm_mem047_i_mem_prty",
4839 "qm_mem049_i_mem_prty",
4840 "qm_mem048_i_mem_prty",
4841 "qm_mem052_i_mem_prty",
4842 "qm_mem050_i_mem_prty",
4843 "qm_mem045_i_mem_prty",
4844 "qm_mem046_i_mem_prty",
4845 "qm_mem043_i_mem_prty",
4846 "qm_mem044_i_mem_prty",
4847 "qm_mem017_i_mem_prty",
4848 "qm_mem016_i_mem_prty",
4849 "qm_mem021_i_mem_prty",
4850 "qm_mem024_i_mem_prty",
4851 "qm_mem019_i_mem_prty",
4852 "qm_mem018_i_mem_prty",
4853 "qm_mem015_i_mem_prty",
4854 "qm_mem022_i_mem_prty",
4855 "qm_mem020_i_mem_prty",
4856 "qm_mem007_i_mem_prty_0",
4857 "qm_mem007_i_mem_prty_1",
4858 "qm_mem007_i_mem_prty_2",
4859 "qm_mem001_i_mem_prty",
4860 "qm_mem043_i_mem_prty_0",
4861 "qm_mem043_i_mem_prty_1",
4862 "qm_mem043_i_mem_prty_2",
4863 "qm_mem007_i_mem_prty_3",
4864 "qm_mem007_i_mem_prty_4",
4865 "qm_mem007_i_mem_prty_5",
4866 "qm_mem007_i_mem_prty_6",
4867 "qm_mem007_i_mem_prty_7",
4868 "qm_mem007_i_mem_prty_8",
4869 "qm_mem007_i_mem_prty_9",
4870 "qm_mem007_i_mem_prty_10",
4871 "qm_mem007_i_mem_prty_11",
4872 "qm_mem007_i_mem_prty_12",
4873 "qm_mem007_i_mem_prty_13",
4874 "qm_mem007_i_mem_prty_14",
4875 "qm_mem007_i_mem_prty_15",
4876 "qm_mem043_i_mem_prty_3",
4877 "qm_mem043_i_mem_prty_4",
4878 "qm_mem043_i_mem_prty_5",
4879 "qm_mem043_i_mem_prty_6",
4880 "qm_mem043_i_mem_prty_7",
4883 #define qm_prty_attn_desc OSAL_NULL
4886 static const u16 qm_prty0_bb_a0_attn_idx[11] = {
4887 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
4890 static struct attn_hw_reg qm_prty0_bb_a0 = {
4891 0, 11, qm_prty0_bb_a0_attn_idx, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194
4894 static const u16 qm_prty1_bb_a0_attn_idx[31] = {
4895 17, 35, 36, 37, 38, 39, 40, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52,
4896 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,
4899 static struct attn_hw_reg qm_prty1_bb_a0 = {
4900 1, 31, qm_prty1_bb_a0_attn_idx, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204
4903 static const u16 qm_prty2_bb_a0_attn_idx[31] = {
4904 66, 67, 69, 70, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 87, 20, 18, 25,
4905 27, 32, 24, 26, 41, 31, 29, 28, 30, 23, 88, 89, 90,
4908 static struct attn_hw_reg qm_prty2_bb_a0 = {
4909 2, 31, qm_prty2_bb_a0_attn_idx, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214
4912 static const u16 qm_prty3_bb_a0_attn_idx[11] = {
4913 104, 105, 106, 107, 108, 33, 16, 34, 19, 72, 71,
4916 static struct attn_hw_reg qm_prty3_bb_a0 = {
4917 3, 11, qm_prty3_bb_a0_attn_idx, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224
4920 static struct attn_hw_reg *qm_prty_bb_a0_regs[4] = {
4921 &qm_prty0_bb_a0, &qm_prty1_bb_a0, &qm_prty2_bb_a0, &qm_prty3_bb_a0,
4924 static const u16 qm_prty0_bb_b0_attn_idx[11] = {
4925 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
4928 static struct attn_hw_reg qm_prty0_bb_b0 = {
4929 0, 11, qm_prty0_bb_b0_attn_idx, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194
4932 static const u16 qm_prty1_bb_b0_attn_idx[31] = {
4933 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,
4934 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
4937 static struct attn_hw_reg qm_prty1_bb_b0 = {
4938 1, 31, qm_prty1_bb_b0_attn_idx, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204
4941 static const u16 qm_prty2_bb_b0_attn_idx[31] = {
4942 66, 67, 68, 69, 70, 71, 72, 73, 74, 58, 60, 62, 49, 75, 76, 53, 77, 78,
4943 79, 80, 81, 52, 65, 57, 82, 56, 83, 48, 84, 85, 86,
4946 static struct attn_hw_reg qm_prty2_bb_b0 = {
4947 2, 31, qm_prty2_bb_b0_attn_idx, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214
4950 static const u16 qm_prty3_bb_b0_attn_idx[11] = {
4951 91, 92, 93, 94, 95, 55, 87, 54, 61, 50, 47,
4954 static struct attn_hw_reg qm_prty3_bb_b0 = {
4955 3, 11, qm_prty3_bb_b0_attn_idx, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224
4958 static struct attn_hw_reg *qm_prty_bb_b0_regs[4] = {
4959 &qm_prty0_bb_b0, &qm_prty1_bb_b0, &qm_prty2_bb_b0, &qm_prty3_bb_b0,
4962 static const u16 qm_prty0_k2_attn_idx[11] = {
4963 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
4966 static struct attn_hw_reg qm_prty0_k2 = {
4967 0, 11, qm_prty0_k2_attn_idx, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194
4970 static const u16 qm_prty1_k2_attn_idx[31] = {
4971 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,
4972 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
4975 static struct attn_hw_reg qm_prty1_k2 = {
4976 1, 31, qm_prty1_k2_attn_idx, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204
4979 static const u16 qm_prty2_k2_attn_idx[31] = {
4980 66, 67, 68, 69, 70, 71, 72, 73, 74, 58, 60, 62, 49, 75, 76, 53, 77, 78,
4981 79, 80, 81, 52, 65, 57, 82, 56, 83, 48, 84, 85, 86,
4984 static struct attn_hw_reg qm_prty2_k2 = {
4985 2, 31, qm_prty2_k2_attn_idx, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214
4988 static const u16 qm_prty3_k2_attn_idx[19] = {
4989 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 55, 87, 54, 61,
4993 static struct attn_hw_reg qm_prty3_k2 = {
4994 3, 19, qm_prty3_k2_attn_idx, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224
4997 static struct attn_hw_reg *qm_prty_k2_regs[4] = {
4998 &qm_prty0_k2, &qm_prty1_k2, &qm_prty2_k2, &qm_prty3_k2,
5002 static const char *tm_int_attn_desc[43] = {
5004 "tm_pxp_read_data_fifo_ov",
5005 "tm_pxp_read_data_fifo_un",
5006 "tm_pxp_read_ctrl_fifo_ov",
5007 "tm_pxp_read_ctrl_fifo_un",
5008 "tm_cfc_load_command_fifo_ov",
5009 "tm_cfc_load_command_fifo_un",
5010 "tm_cfc_load_echo_fifo_ov",
5011 "tm_cfc_load_echo_fifo_un",
5012 "tm_client_out_fifo_ov",
5013 "tm_client_out_fifo_un",
5014 "tm_ac_command_fifo_ov",
5015 "tm_ac_command_fifo_un",
5016 "tm_client_in_pbf_fifo_ov",
5017 "tm_client_in_pbf_fifo_un",
5018 "tm_client_in_ucm_fifo_ov",
5019 "tm_client_in_ucm_fifo_un",
5020 "tm_client_in_tcm_fifo_ov",
5021 "tm_client_in_tcm_fifo_un",
5022 "tm_client_in_xcm_fifo_ov",
5023 "tm_client_in_xcm_fifo_un",
5024 "tm_expiration_cmd_fifo_ov",
5025 "tm_expiration_cmd_fifo_un",
5026 "tm_stop_all_lc_invalid",
5027 "tm_command_lc_invalid_0",
5028 "tm_command_lc_invalid_1",
5029 "tm_init_command_lc_valid",
5030 "tm_stop_all_exp_lc_valid",
5031 "tm_command_cid_invalid_0",
5032 "tm_reserved_command",
5033 "tm_command_cid_invalid_1",
5034 "tm_cload_res_loaderr_conn",
5035 "tm_cload_res_loadcancel_conn",
5036 "tm_cload_res_validerr_conn",
5037 "tm_context_rd_last",
5038 "tm_context_wr_last",
5039 "tm_pxp_rd_data_eop_bvalid",
5040 "tm_pend_conn_scan",
5041 "tm_pend_task_scan",
5042 "tm_pxp_rd_data_eop_error",
5043 "tm_cload_res_loaderr_task",
5044 "tm_cload_res_loadcancel_task",
5045 "tm_cload_res_validerr_task",
5048 #define tm_int_attn_desc OSAL_NULL
5051 static const u16 tm_int0_bb_a0_attn_idx[32] = {
5052 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
5054 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
5057 static struct attn_hw_reg tm_int0_bb_a0 = {
5058 0, 32, tm_int0_bb_a0_attn_idx, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184
5061 static const u16 tm_int1_bb_a0_attn_idx[11] = {
5062 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42,
5065 static struct attn_hw_reg tm_int1_bb_a0 = {
5066 1, 11, tm_int1_bb_a0_attn_idx, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194
5069 static struct attn_hw_reg *tm_int_bb_a0_regs[2] = {
5070 &tm_int0_bb_a0, &tm_int1_bb_a0,
5073 static const u16 tm_int0_bb_b0_attn_idx[32] = {
5074 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
5076 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
5079 static struct attn_hw_reg tm_int0_bb_b0 = {
5080 0, 32, tm_int0_bb_b0_attn_idx, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184
5083 static const u16 tm_int1_bb_b0_attn_idx[11] = {
5084 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42,
5087 static struct attn_hw_reg tm_int1_bb_b0 = {
5088 1, 11, tm_int1_bb_b0_attn_idx, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194
5091 static struct attn_hw_reg *tm_int_bb_b0_regs[2] = {
5092 &tm_int0_bb_b0, &tm_int1_bb_b0,
5095 static const u16 tm_int0_k2_attn_idx[32] = {
5096 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
5098 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
5101 static struct attn_hw_reg tm_int0_k2 = {
5102 0, 32, tm_int0_k2_attn_idx, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184
5105 static const u16 tm_int1_k2_attn_idx[11] = {
5106 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42,
5109 static struct attn_hw_reg tm_int1_k2 = {
5110 1, 11, tm_int1_k2_attn_idx, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194
5113 static struct attn_hw_reg *tm_int_k2_regs[2] = {
5114 &tm_int0_k2, &tm_int1_k2,
5118 static const char *tm_prty_attn_desc[17] = {
5119 "tm_mem012_i_ecc_0_rf_int",
5120 "tm_mem012_i_ecc_1_rf_int",
5121 "tm_mem003_i_ecc_rf_int",
5122 "tm_mem016_i_mem_prty",
5123 "tm_mem007_i_mem_prty",
5124 "tm_mem010_i_mem_prty",
5125 "tm_mem008_i_mem_prty",
5126 "tm_mem009_i_mem_prty",
5127 "tm_mem013_i_mem_prty",
5128 "tm_mem015_i_mem_prty",
5129 "tm_mem014_i_mem_prty",
5130 "tm_mem004_i_mem_prty",
5131 "tm_mem005_i_mem_prty",
5132 "tm_mem006_i_mem_prty",
5133 "tm_mem011_i_mem_prty",
5134 "tm_mem001_i_mem_prty",
5135 "tm_mem002_i_mem_prty",
5138 #define tm_prty_attn_desc OSAL_NULL
5141 static const u16 tm_prty1_bb_a0_attn_idx[17] = {
5142 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
5145 static struct attn_hw_reg tm_prty1_bb_a0 = {
5146 0, 17, tm_prty1_bb_a0_attn_idx, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204
5149 static struct attn_hw_reg *tm_prty_bb_a0_regs[1] = {
5153 static const u16 tm_prty1_bb_b0_attn_idx[17] = {
5154 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
5157 static struct attn_hw_reg tm_prty1_bb_b0 = {
5158 0, 17, tm_prty1_bb_b0_attn_idx, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204
5161 static struct attn_hw_reg *tm_prty_bb_b0_regs[1] = {
5165 static const u16 tm_prty1_k2_attn_idx[17] = {
5166 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
5169 static struct attn_hw_reg tm_prty1_k2 = {
5170 0, 17, tm_prty1_k2_attn_idx, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204
5173 static struct attn_hw_reg *tm_prty_k2_regs[1] = {
5178 static const char *dorq_int_attn_desc[9] = {
5179 "dorq_address_error",
5181 "dorq_dorq_fifo_ovfl_err",
5182 "dorq_dorq_fifo_afull",
5183 "dorq_cfc_byp_validation_err",
5184 "dorq_cfc_ld_resp_err",
5185 "dorq_xcm_done_cnt_err",
5186 "dorq_cfc_ld_req_fifo_ovfl_err",
5187 "dorq_cfc_ld_req_fifo_under_err",
5190 #define dorq_int_attn_desc OSAL_NULL
5193 static const u16 dorq_int0_bb_a0_attn_idx[9] = {
5194 0, 1, 2, 3, 4, 5, 6, 7, 8,
5197 static struct attn_hw_reg dorq_int0_bb_a0 = {
5198 0, 9, dorq_int0_bb_a0_attn_idx, 0x100180, 0x10018c, 0x100188, 0x100184
5201 static struct attn_hw_reg *dorq_int_bb_a0_regs[1] = {
5205 static const u16 dorq_int0_bb_b0_attn_idx[9] = {
5206 0, 1, 2, 3, 4, 5, 6, 7, 8,
5209 static struct attn_hw_reg dorq_int0_bb_b0 = {
5210 0, 9, dorq_int0_bb_b0_attn_idx, 0x100180, 0x10018c, 0x100188, 0x100184
5213 static struct attn_hw_reg *dorq_int_bb_b0_regs[1] = {
5217 static const u16 dorq_int0_k2_attn_idx[9] = {
5218 0, 1, 2, 3, 4, 5, 6, 7, 8,
5221 static struct attn_hw_reg dorq_int0_k2 = {
5222 0, 9, dorq_int0_k2_attn_idx, 0x100180, 0x10018c, 0x100188, 0x100184
5225 static struct attn_hw_reg *dorq_int_k2_regs[1] = {
5230 static const char *dorq_prty_attn_desc[7] = {
5231 "dorq_datapath_registers",
5232 "dorq_mem002_i_ecc_rf_int",
5233 "dorq_mem001_i_mem_prty",
5234 "dorq_mem003_i_mem_prty",
5235 "dorq_mem004_i_mem_prty",
5236 "dorq_mem005_i_mem_prty",
5237 "dorq_mem006_i_mem_prty",
5240 #define dorq_prty_attn_desc OSAL_NULL
5243 static const u16 dorq_prty1_bb_a0_attn_idx[6] = {
5247 static struct attn_hw_reg dorq_prty1_bb_a0 = {
5248 0, 6, dorq_prty1_bb_a0_attn_idx, 0x100200, 0x10020c, 0x100208, 0x100204
5251 static struct attn_hw_reg *dorq_prty_bb_a0_regs[1] = {
5255 static const u16 dorq_prty0_bb_b0_attn_idx[1] = {
5259 static struct attn_hw_reg dorq_prty0_bb_b0 = {
5260 0, 1, dorq_prty0_bb_b0_attn_idx, 0x100190, 0x10019c, 0x100198, 0x100194
5263 static const u16 dorq_prty1_bb_b0_attn_idx[6] = {
5267 static struct attn_hw_reg dorq_prty1_bb_b0 = {
5268 1, 6, dorq_prty1_bb_b0_attn_idx, 0x100200, 0x10020c, 0x100208, 0x100204
5271 static struct attn_hw_reg *dorq_prty_bb_b0_regs[2] = {
5272 &dorq_prty0_bb_b0, &dorq_prty1_bb_b0,
5275 static const u16 dorq_prty0_k2_attn_idx[1] = {
5279 static struct attn_hw_reg dorq_prty0_k2 = {
5280 0, 1, dorq_prty0_k2_attn_idx, 0x100190, 0x10019c, 0x100198, 0x100194
5283 static const u16 dorq_prty1_k2_attn_idx[6] = {
5287 static struct attn_hw_reg dorq_prty1_k2 = {
5288 1, 6, dorq_prty1_k2_attn_idx, 0x100200, 0x10020c, 0x100208, 0x100204
5291 static struct attn_hw_reg *dorq_prty_k2_regs[2] = {
5292 &dorq_prty0_k2, &dorq_prty1_k2,
5296 static const char *brb_int_attn_desc[237] = {
5297 "brb_address_error",
5298 "brb_rc_pkt0_rls_error",
5299 "brb_rc_pkt0_1st_error",
5300 "brb_rc_pkt0_len_error",
5301 "brb_rc_pkt0_middle_error",
5302 "brb_rc_pkt0_protocol_error",
5303 "brb_rc_pkt1_rls_error",
5304 "brb_rc_pkt1_1st_error",
5305 "brb_rc_pkt1_len_error",
5306 "brb_rc_pkt1_middle_error",
5307 "brb_rc_pkt1_protocol_error",
5308 "brb_rc_pkt2_rls_error",
5309 "brb_rc_pkt2_1st_error",
5310 "brb_rc_pkt2_len_error",
5311 "brb_rc_pkt2_middle_error",
5312 "brb_rc_pkt2_protocol_error",
5313 "brb_rc_pkt3_rls_error",
5314 "brb_rc_pkt3_1st_error",
5315 "brb_rc_pkt3_len_error",
5316 "brb_rc_pkt3_middle_error",
5317 "brb_rc_pkt3_protocol_error",
5318 "brb_rc_sop_req_tc_port_error",
5319 "brb_uncomplient_lossless_error",
5320 "brb_wc0_protocol_error",
5321 "brb_wc1_protocol_error",
5322 "brb_wc2_protocol_error",
5323 "brb_wc3_protocol_error",
5324 "brb_ll_arb_prefetch_sop_error",
5326 "brb_packet_counter_error",
5327 "brb_byte_counter_error",
5328 "brb_mac0_fc_cnt_error",
5329 "brb_mac1_fc_cnt_error",
5330 "brb_ll_arb_calc_error",
5332 "brb_wc0_inp_fifo_error",
5333 "brb_wc0_sop_fifo_error",
5335 "brb_wc0_eop_fifo_error",
5336 "brb_wc0_queue_fifo_error",
5337 "brb_wc0_free_point_fifo_error",
5338 "brb_wc0_next_point_fifo_error",
5339 "brb_wc0_strt_fifo_error",
5340 "brb_wc0_second_dscr_fifo_error",
5341 "brb_wc0_pkt_avail_fifo_error",
5342 "brb_wc0_cos_cnt_fifo_error",
5343 "brb_wc0_notify_fifo_error",
5344 "brb_wc0_ll_req_fifo_error",
5345 "brb_wc0_ll_pa_cnt_error",
5346 "brb_wc0_bb_pa_cnt_error",
5347 "brb_wc1_inp_fifo_error",
5348 "brb_wc1_sop_fifo_error",
5349 "brb_wc1_eop_fifo_error",
5350 "brb_wc1_queue_fifo_error",
5351 "brb_wc1_free_point_fifo_error",
5352 "brb_wc1_next_point_fifo_error",
5353 "brb_wc1_strt_fifo_error",
5354 "brb_wc1_second_dscr_fifo_error",
5355 "brb_wc1_pkt_avail_fifo_error",
5356 "brb_wc1_cos_cnt_fifo_error",
5357 "brb_wc1_notify_fifo_error",
5358 "brb_wc1_ll_req_fifo_error",
5359 "brb_wc1_ll_pa_cnt_error",
5360 "brb_wc1_bb_pa_cnt_error",
5361 "brb_wc2_inp_fifo_error",
5362 "brb_wc2_sop_fifo_error",
5363 "brb_wc2_eop_fifo_error",
5364 "brb_wc2_queue_fifo_error",
5365 "brb_wc2_free_point_fifo_error",
5366 "brb_wc2_next_point_fifo_error",
5367 "brb_wc2_strt_fifo_error",
5368 "brb_wc2_second_dscr_fifo_error",
5369 "brb_wc2_pkt_avail_fifo_error",
5370 "brb_wc2_cos_cnt_fifo_error",
5371 "brb_wc2_notify_fifo_error",
5372 "brb_wc2_ll_req_fifo_error",
5373 "brb_wc2_ll_pa_cnt_error",
5374 "brb_wc2_bb_pa_cnt_error",
5375 "brb_wc3_inp_fifo_error",
5376 "brb_wc3_sop_fifo_error",
5377 "brb_wc3_eop_fifo_error",
5378 "brb_wc3_queue_fifo_error",
5379 "brb_wc3_free_point_fifo_error",
5380 "brb_wc3_next_point_fifo_error",
5381 "brb_wc3_strt_fifo_error",
5382 "brb_wc3_second_dscr_fifo_error",
5383 "brb_wc3_pkt_avail_fifo_error",
5384 "brb_wc3_cos_cnt_fifo_error",
5385 "brb_wc3_notify_fifo_error",
5386 "brb_wc3_ll_req_fifo_error",
5387 "brb_wc3_ll_pa_cnt_error",
5388 "brb_wc3_bb_pa_cnt_error",
5389 "brb_rc_pkt0_side_fifo_error",
5390 "brb_rc_pkt0_req_fifo_error",
5391 "brb_rc_pkt0_blk_fifo_error",
5392 "brb_rc_pkt0_rls_left_fifo_error",
5393 "brb_rc_pkt0_strt_ptr_fifo_error",
5394 "brb_rc_pkt0_second_ptr_fifo_error",
5395 "brb_rc_pkt0_rsp_fifo_error",
5396 "brb_rc_pkt0_dscr_fifo_error",
5397 "brb_rc_pkt1_side_fifo_error",
5398 "brb_rc_pkt1_req_fifo_error",
5399 "brb_rc_pkt1_blk_fifo_error",
5400 "brb_rc_pkt1_rls_left_fifo_error",
5401 "brb_rc_pkt1_strt_ptr_fifo_error",
5402 "brb_rc_pkt1_second_ptr_fifo_error",
5403 "brb_rc_pkt1_rsp_fifo_error",
5404 "brb_rc_pkt1_dscr_fifo_error",
5405 "brb_rc_pkt2_side_fifo_error",
5406 "brb_rc_pkt2_req_fifo_error",
5407 "brb_rc_pkt2_blk_fifo_error",
5408 "brb_rc_pkt2_rls_left_fifo_error",
5409 "brb_rc_pkt2_strt_ptr_fifo_error",
5410 "brb_rc_pkt2_second_ptr_fifo_error",
5411 "brb_rc_pkt2_rsp_fifo_error",
5412 "brb_rc_pkt2_dscr_fifo_error",
5413 "brb_rc_pkt3_side_fifo_error",
5414 "brb_rc_pkt3_req_fifo_error",
5415 "brb_rc_pkt3_blk_fifo_error",
5416 "brb_rc_pkt3_rls_left_fifo_error",
5417 "brb_rc_pkt3_strt_ptr_fifo_error",
5418 "brb_rc_pkt3_second_ptr_fifo_error",
5419 "brb_rc_pkt3_rsp_fifo_error",
5420 "brb_rc_pkt3_dscr_fifo_error",
5421 "brb_rc_sop_strt_fifo_error",
5422 "brb_rc_sop_req_fifo_error",
5423 "brb_rc_sop_dscr_fifo_error",
5424 "brb_rc_sop_queue_fifo_error",
5425 "brb_rc0_eop_error",
5426 "brb_rc1_eop_error",
5427 "brb_ll_arb_rls_fifo_error",
5428 "brb_ll_arb_prefetch_fifo_error",
5429 "brb_rc_pkt0_rls_fifo_error",
5430 "brb_rc_pkt1_rls_fifo_error",
5431 "brb_rc_pkt2_rls_fifo_error",
5432 "brb_rc_pkt3_rls_fifo_error",
5433 "brb_rc_pkt4_rls_fifo_error",
5434 "brb_rc_pkt4_rls_error",
5435 "brb_rc_pkt4_1st_error",
5436 "brb_rc_pkt4_len_error",
5437 "brb_rc_pkt4_middle_error",
5438 "brb_rc_pkt4_protocol_error",
5439 "brb_rc_pkt4_side_fifo_error",
5440 "brb_rc_pkt4_req_fifo_error",
5441 "brb_rc_pkt4_blk_fifo_error",
5442 "brb_rc_pkt4_rls_left_fifo_error",
5443 "brb_rc_pkt4_strt_ptr_fifo_error",
5444 "brb_rc_pkt4_second_ptr_fifo_error",
5445 "brb_rc_pkt4_rsp_fifo_error",
5446 "brb_rc_pkt4_dscr_fifo_error",
5447 "brb_rc_pkt5_rls_error",
5448 "brb_packet_available_sync_fifo_push_error",
5449 "brb_wc4_protocol_error",
5450 "brb_wc5_protocol_error",
5451 "brb_wc6_protocol_error",
5452 "brb_wc7_protocol_error",
5453 "brb_wc4_inp_fifo_error",
5454 "brb_wc4_sop_fifo_error",
5455 "brb_wc4_queue_fifo_error",
5456 "brb_wc4_free_point_fifo_error",
5457 "brb_wc4_next_point_fifo_error",
5458 "brb_wc4_strt_fifo_error",
5459 "brb_wc4_second_dscr_fifo_error",
5460 "brb_wc4_pkt_avail_fifo_error",
5461 "brb_wc4_cos_cnt_fifo_error",
5462 "brb_wc4_notify_fifo_error",
5463 "brb_wc4_ll_req_fifo_error",
5464 "brb_wc4_ll_pa_cnt_error",
5465 "brb_wc4_bb_pa_cnt_error",
5466 "brb_wc5_inp_fifo_error",
5467 "brb_wc5_sop_fifo_error",
5468 "brb_wc5_queue_fifo_error",
5469 "brb_wc5_free_point_fifo_error",
5470 "brb_wc5_next_point_fifo_error",
5471 "brb_wc5_strt_fifo_error",
5472 "brb_wc5_second_dscr_fifo_error",
5473 "brb_wc5_pkt_avail_fifo_error",
5474 "brb_wc5_cos_cnt_fifo_error",
5475 "brb_wc5_notify_fifo_error",
5476 "brb_wc5_ll_req_fifo_error",
5477 "brb_wc5_ll_pa_cnt_error",
5478 "brb_wc5_bb_pa_cnt_error",
5479 "brb_wc6_inp_fifo_error",
5480 "brb_wc6_sop_fifo_error",
5481 "brb_wc6_queue_fifo_error",
5482 "brb_wc6_free_point_fifo_error",
5483 "brb_wc6_next_point_fifo_error",
5484 "brb_wc6_strt_fifo_error",
5485 "brb_wc6_second_dscr_fifo_error",
5486 "brb_wc6_pkt_avail_fifo_error",
5487 "brb_wc6_cos_cnt_fifo_error",
5488 "brb_wc6_notify_fifo_error",
5489 "brb_wc6_ll_req_fifo_error",
5490 "brb_wc6_ll_pa_cnt_error",
5491 "brb_wc6_bb_pa_cnt_error",
5492 "brb_wc7_inp_fifo_error",
5493 "brb_wc7_sop_fifo_error",
5494 "brb_wc7_queue_fifo_error",
5495 "brb_wc7_free_point_fifo_error",
5496 "brb_wc7_next_point_fifo_error",
5497 "brb_wc7_strt_fifo_error",
5498 "brb_wc7_second_dscr_fifo_error",
5499 "brb_wc7_pkt_avail_fifo_error",
5500 "brb_wc7_cos_cnt_fifo_error",
5501 "brb_wc7_notify_fifo_error",
5502 "brb_wc7_ll_req_fifo_error",
5503 "brb_wc7_ll_pa_cnt_error",
5504 "brb_wc7_bb_pa_cnt_error",
5505 "brb_wc9_queue_fifo_error",
5506 "brb_rc_sop_inp_sync_fifo_push_error",
5507 "brb_rc0_inp_sync_fifo_push_error",
5508 "brb_rc1_inp_sync_fifo_push_error",
5509 "brb_rc2_inp_sync_fifo_push_error",
5510 "brb_rc3_inp_sync_fifo_push_error",
5511 "brb_rc0_out_sync_fifo_push_error",
5512 "brb_rc1_out_sync_fifo_push_error",
5513 "brb_rc2_out_sync_fifo_push_error",
5514 "brb_rc3_out_sync_fifo_push_error",
5515 "brb_rc4_out_sync_fifo_push_error",
5517 "brb_rc0_eop_inp_sync_fifo_push_error",
5518 "brb_rc1_eop_inp_sync_fifo_push_error",
5519 "brb_rc2_eop_inp_sync_fifo_push_error",
5520 "brb_rc3_eop_inp_sync_fifo_push_error",
5521 "brb_rc0_eop_out_sync_fifo_push_error",
5522 "brb_rc1_eop_out_sync_fifo_push_error",
5523 "brb_rc2_eop_out_sync_fifo_push_error",
5524 "brb_rc3_eop_out_sync_fifo_push_error",
5526 "brb_rc2_eop_error",
5527 "brb_rc3_eop_error",
5528 "brb_mac2_fc_cnt_error",
5529 "brb_mac3_fc_cnt_error",
5530 "brb_wc4_eop_fifo_error",
5531 "brb_wc5_eop_fifo_error",
5532 "brb_wc6_eop_fifo_error",
5533 "brb_wc7_eop_fifo_error",
5536 #define brb_int_attn_desc OSAL_NULL
5539 static const u16 brb_int0_bb_a0_attn_idx[32] = {
5540 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
5542 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
5545 static struct attn_hw_reg brb_int0_bb_a0 = {
5546 0, 32, brb_int0_bb_a0_attn_idx, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4
5549 static const u16 brb_int1_bb_a0_attn_idx[30] = {
5550 32, 33, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
5551 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
5554 static struct attn_hw_reg brb_int1_bb_a0 = {
5555 1, 30, brb_int1_bb_a0_attn_idx, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc
5558 static const u16 brb_int2_bb_a0_attn_idx[28] = {
5559 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,
5560 82, 83, 84, 85, 86, 87, 88, 89, 90, 91,
5563 static struct attn_hw_reg brb_int2_bb_a0 = {
5564 2, 28, brb_int2_bb_a0_attn_idx, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4
5567 static const u16 brb_int3_bb_a0_attn_idx[31] = {
5568 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
5569 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121,
5573 static struct attn_hw_reg brb_int3_bb_a0 = {
5574 3, 31, brb_int3_bb_a0_attn_idx, 0x340108, 0x340114, 0x340110, 0x34010c
5577 static const u16 brb_int4_bb_a0_attn_idx[27] = {
5578 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,
5580 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
5583 static struct attn_hw_reg brb_int4_bb_a0 = {
5584 4, 27, brb_int4_bb_a0_attn_idx, 0x340120, 0x34012c, 0x340128, 0x340124
5587 static const u16 brb_int5_bb_a0_attn_idx[1] = {
5591 static struct attn_hw_reg brb_int5_bb_a0 = {
5592 5, 1, brb_int5_bb_a0_attn_idx, 0x340138, 0x340144, 0x340140, 0x34013c
5595 static const u16 brb_int6_bb_a0_attn_idx[8] = {
5596 151, 152, 153, 154, 155, 156, 157, 158,
5599 static struct attn_hw_reg brb_int6_bb_a0 = {
5600 6, 8, brb_int6_bb_a0_attn_idx, 0x340150, 0x34015c, 0x340158, 0x340154
5603 static const u16 brb_int7_bb_a0_attn_idx[32] = {
5604 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172,
5606 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
5611 static struct attn_hw_reg brb_int7_bb_a0 = {
5612 7, 32, brb_int7_bb_a0_attn_idx, 0x340168, 0x340174, 0x340170, 0x34016c
5615 static const u16 brb_int8_bb_a0_attn_idx[17] = {
5616 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204,
5621 static struct attn_hw_reg brb_int8_bb_a0 = {
5622 8, 17, brb_int8_bb_a0_attn_idx, 0x340184, 0x340190, 0x34018c, 0x340188
5625 static const u16 brb_int9_bb_a0_attn_idx[1] = {
5629 static struct attn_hw_reg brb_int9_bb_a0 = {
5630 9, 1, brb_int9_bb_a0_attn_idx, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0
5633 static const u16 brb_int10_bb_a0_attn_idx[14] = {
5634 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 220, 221, 224, 225,
5637 static struct attn_hw_reg brb_int10_bb_a0 = {
5638 10, 14, brb_int10_bb_a0_attn_idx, 0x3401b4, 0x3401c0, 0x3401bc,
5642 static const u16 brb_int11_bb_a0_attn_idx[8] = {
5643 229, 230, 231, 232, 233, 234, 235, 236,
5646 static struct attn_hw_reg brb_int11_bb_a0 = {
5647 11, 8, brb_int11_bb_a0_attn_idx, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0
5650 static struct attn_hw_reg *brb_int_bb_a0_regs[12] = {
5651 &brb_int0_bb_a0, &brb_int1_bb_a0, &brb_int2_bb_a0, &brb_int3_bb_a0,
5652 &brb_int4_bb_a0, &brb_int5_bb_a0, &brb_int6_bb_a0, &brb_int7_bb_a0,
5653 &brb_int8_bb_a0, &brb_int9_bb_a0,
5654 &brb_int10_bb_a0, &brb_int11_bb_a0,
5657 static const u16 brb_int0_bb_b0_attn_idx[32] = {
5658 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
5660 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
5663 static struct attn_hw_reg brb_int0_bb_b0 = {
5664 0, 32, brb_int0_bb_b0_attn_idx, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4
5667 static const u16 brb_int1_bb_b0_attn_idx[30] = {
5668 32, 33, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
5669 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
5672 static struct attn_hw_reg brb_int1_bb_b0 = {
5673 1, 30, brb_int1_bb_b0_attn_idx, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc
5676 static const u16 brb_int2_bb_b0_attn_idx[28] = {
5677 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,
5678 82, 83, 84, 85, 86, 87, 88, 89, 90, 91,
5681 static struct attn_hw_reg brb_int2_bb_b0 = {
5682 2, 28, brb_int2_bb_b0_attn_idx, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4
5685 static const u16 brb_int3_bb_b0_attn_idx[31] = {
5686 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
5687 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121,
5691 static struct attn_hw_reg brb_int3_bb_b0 = {
5692 3, 31, brb_int3_bb_b0_attn_idx, 0x340108, 0x340114, 0x340110, 0x34010c
5695 static const u16 brb_int4_bb_b0_attn_idx[27] = {
5696 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,
5698 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
5701 static struct attn_hw_reg brb_int4_bb_b0 = {
5702 4, 27, brb_int4_bb_b0_attn_idx, 0x340120, 0x34012c, 0x340128, 0x340124
5705 static const u16 brb_int5_bb_b0_attn_idx[1] = {
5709 static struct attn_hw_reg brb_int5_bb_b0 = {
5710 5, 1, brb_int5_bb_b0_attn_idx, 0x340138, 0x340144, 0x340140, 0x34013c
5713 static const u16 brb_int6_bb_b0_attn_idx[8] = {
5714 151, 152, 153, 154, 155, 156, 157, 158,
5717 static struct attn_hw_reg brb_int6_bb_b0 = {
5718 6, 8, brb_int6_bb_b0_attn_idx, 0x340150, 0x34015c, 0x340158, 0x340154
5721 static const u16 brb_int7_bb_b0_attn_idx[32] = {
5722 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172,
5724 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
5729 static struct attn_hw_reg brb_int7_bb_b0 = {
5730 7, 32, brb_int7_bb_b0_attn_idx, 0x340168, 0x340174, 0x340170, 0x34016c
5733 static const u16 brb_int8_bb_b0_attn_idx[17] = {
5734 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204,
5739 static struct attn_hw_reg brb_int8_bb_b0 = {
5740 8, 17, brb_int8_bb_b0_attn_idx, 0x340184, 0x340190, 0x34018c, 0x340188
5743 static const u16 brb_int9_bb_b0_attn_idx[1] = {
5747 static struct attn_hw_reg brb_int9_bb_b0 = {
5748 9, 1, brb_int9_bb_b0_attn_idx, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0
5751 static const u16 brb_int10_bb_b0_attn_idx[14] = {
5752 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 220, 221, 224, 225,
5755 static struct attn_hw_reg brb_int10_bb_b0 = {
5756 10, 14, brb_int10_bb_b0_attn_idx, 0x3401b4, 0x3401c0, 0x3401bc,
5760 static const u16 brb_int11_bb_b0_attn_idx[8] = {
5761 229, 230, 231, 232, 233, 234, 235, 236,
5764 static struct attn_hw_reg brb_int11_bb_b0 = {
5765 11, 8, brb_int11_bb_b0_attn_idx, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0
5768 static struct attn_hw_reg *brb_int_bb_b0_regs[12] = {
5769 &brb_int0_bb_b0, &brb_int1_bb_b0, &brb_int2_bb_b0, &brb_int3_bb_b0,
5770 &brb_int4_bb_b0, &brb_int5_bb_b0, &brb_int6_bb_b0, &brb_int7_bb_b0,
5771 &brb_int8_bb_b0, &brb_int9_bb_b0,
5772 &brb_int10_bb_b0, &brb_int11_bb_b0,
5775 static const u16 brb_int0_k2_attn_idx[32] = {
5776 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
5778 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
5781 static struct attn_hw_reg brb_int0_k2 = {
5782 0, 32, brb_int0_k2_attn_idx, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4
5785 static const u16 brb_int1_k2_attn_idx[30] = {
5786 32, 33, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
5787 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
5790 static struct attn_hw_reg brb_int1_k2 = {
5791 1, 30, brb_int1_k2_attn_idx, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc
5794 static const u16 brb_int2_k2_attn_idx[28] = {
5795 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,
5796 82, 83, 84, 85, 86, 87, 88, 89, 90, 91,
5799 static struct attn_hw_reg brb_int2_k2 = {
5800 2, 28, brb_int2_k2_attn_idx, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4
5803 static const u16 brb_int3_k2_attn_idx[31] = {
5804 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
5805 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121,
5809 static struct attn_hw_reg brb_int3_k2 = {
5810 3, 31, brb_int3_k2_attn_idx, 0x340108, 0x340114, 0x340110, 0x34010c
5813 static const u16 brb_int4_k2_attn_idx[27] = {
5814 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,
5816 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
5819 static struct attn_hw_reg brb_int4_k2 = {
5820 4, 27, brb_int4_k2_attn_idx, 0x340120, 0x34012c, 0x340128, 0x340124
5823 static const u16 brb_int5_k2_attn_idx[1] = {
5827 static struct attn_hw_reg brb_int5_k2 = {
5828 5, 1, brb_int5_k2_attn_idx, 0x340138, 0x340144, 0x340140, 0x34013c
5831 static const u16 brb_int6_k2_attn_idx[8] = {
5832 151, 152, 153, 154, 155, 156, 157, 158,
5835 static struct attn_hw_reg brb_int6_k2 = {
5836 6, 8, brb_int6_k2_attn_idx, 0x340150, 0x34015c, 0x340158, 0x340154
5839 static const u16 brb_int7_k2_attn_idx[32] = {
5840 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172,
5842 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
5847 static struct attn_hw_reg brb_int7_k2 = {
5848 7, 32, brb_int7_k2_attn_idx, 0x340168, 0x340174, 0x340170, 0x34016c
5851 static const u16 brb_int8_k2_attn_idx[17] = {
5852 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204,
5857 static struct attn_hw_reg brb_int8_k2 = {
5858 8, 17, brb_int8_k2_attn_idx, 0x340184, 0x340190, 0x34018c, 0x340188
5861 static const u16 brb_int9_k2_attn_idx[1] = {
5865 static struct attn_hw_reg brb_int9_k2 = {
5866 9, 1, brb_int9_k2_attn_idx, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0
5869 static const u16 brb_int10_k2_attn_idx[18] = {
5870 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 220, 221, 222, 223,
5875 static struct attn_hw_reg brb_int10_k2 = {
5876 10, 18, brb_int10_k2_attn_idx, 0x3401b4, 0x3401c0, 0x3401bc, 0x3401b8
5879 static const u16 brb_int11_k2_attn_idx[8] = {
5880 229, 230, 231, 232, 233, 234, 235, 236,
5883 static struct attn_hw_reg brb_int11_k2 = {
5884 11, 8, brb_int11_k2_attn_idx, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0
5887 static struct attn_hw_reg *brb_int_k2_regs[12] = {
5888 &brb_int0_k2, &brb_int1_k2, &brb_int2_k2, &brb_int3_k2, &brb_int4_k2,
5889 &brb_int5_k2, &brb_int6_k2, &brb_int7_k2, &brb_int8_k2, &brb_int9_k2,
5890 &brb_int10_k2, &brb_int11_k2,
5894 static const char *brb_prty_attn_desc[75] = {
5895 "brb_ll_bank0_mem_prty",
5896 "brb_ll_bank1_mem_prty",
5897 "brb_ll_bank2_mem_prty",
5898 "brb_ll_bank3_mem_prty",
5899 "brb_datapath_registers",
5900 "brb_mem001_i_ecc_rf_int",
5901 "brb_mem008_i_ecc_rf_int",
5902 "brb_mem009_i_ecc_rf_int",
5903 "brb_mem010_i_ecc_rf_int",
5904 "brb_mem011_i_ecc_rf_int",
5905 "brb_mem012_i_ecc_rf_int",
5906 "brb_mem013_i_ecc_rf_int",
5907 "brb_mem014_i_ecc_rf_int",
5908 "brb_mem015_i_ecc_rf_int",
5909 "brb_mem016_i_ecc_rf_int",
5910 "brb_mem002_i_ecc_rf_int",
5911 "brb_mem003_i_ecc_rf_int",
5912 "brb_mem004_i_ecc_rf_int",
5913 "brb_mem005_i_ecc_rf_int",
5914 "brb_mem006_i_ecc_rf_int",
5915 "brb_mem007_i_ecc_rf_int",
5916 "brb_mem070_i_mem_prty",
5917 "brb_mem069_i_mem_prty",
5918 "brb_mem053_i_mem_prty",
5919 "brb_mem054_i_mem_prty",
5920 "brb_mem055_i_mem_prty",
5921 "brb_mem056_i_mem_prty",
5922 "brb_mem057_i_mem_prty",
5923 "brb_mem058_i_mem_prty",
5924 "brb_mem059_i_mem_prty",
5925 "brb_mem060_i_mem_prty",
5926 "brb_mem061_i_mem_prty",
5927 "brb_mem062_i_mem_prty",
5928 "brb_mem063_i_mem_prty",
5929 "brb_mem064_i_mem_prty",
5930 "brb_mem065_i_mem_prty",
5931 "brb_mem045_i_mem_prty",
5932 "brb_mem046_i_mem_prty",
5933 "brb_mem047_i_mem_prty",
5934 "brb_mem048_i_mem_prty",
5935 "brb_mem049_i_mem_prty",
5936 "brb_mem050_i_mem_prty",
5937 "brb_mem051_i_mem_prty",
5938 "brb_mem052_i_mem_prty",
5939 "brb_mem041_i_mem_prty",
5940 "brb_mem042_i_mem_prty",
5941 "brb_mem043_i_mem_prty",
5942 "brb_mem044_i_mem_prty",
5943 "brb_mem040_i_mem_prty",
5944 "brb_mem035_i_mem_prty",
5945 "brb_mem066_i_mem_prty",
5946 "brb_mem067_i_mem_prty",
5947 "brb_mem068_i_mem_prty",
5948 "brb_mem030_i_mem_prty",
5949 "brb_mem031_i_mem_prty",
5950 "brb_mem032_i_mem_prty",
5951 "brb_mem033_i_mem_prty",
5952 "brb_mem037_i_mem_prty",
5953 "brb_mem038_i_mem_prty",
5954 "brb_mem034_i_mem_prty",
5955 "brb_mem036_i_mem_prty",
5956 "brb_mem017_i_mem_prty",
5957 "brb_mem018_i_mem_prty",
5958 "brb_mem019_i_mem_prty",
5959 "brb_mem020_i_mem_prty",
5960 "brb_mem021_i_mem_prty",
5961 "brb_mem022_i_mem_prty",
5962 "brb_mem023_i_mem_prty",
5963 "brb_mem024_i_mem_prty",
5964 "brb_mem029_i_mem_prty",
5965 "brb_mem026_i_mem_prty",
5966 "brb_mem027_i_mem_prty",
5967 "brb_mem028_i_mem_prty",
5968 "brb_mem025_i_mem_prty",
5969 "brb_mem039_i_mem_prty",
5972 #define brb_prty_attn_desc OSAL_NULL
5975 static const u16 brb_prty1_bb_a0_attn_idx[31] = {
5976 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 23, 24, 36,
5978 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 49,
5981 static struct attn_hw_reg brb_prty1_bb_a0 = {
5982 0, 31, brb_prty1_bb_a0_attn_idx, 0x340400, 0x34040c, 0x340408, 0x340404
5985 static const u16 brb_prty2_bb_a0_attn_idx[19] = {
5986 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74,
5990 static struct attn_hw_reg brb_prty2_bb_a0 = {
5991 1, 19, brb_prty2_bb_a0_attn_idx, 0x340410, 0x34041c, 0x340418, 0x340414
5994 static struct attn_hw_reg *brb_prty_bb_a0_regs[2] = {
5995 &brb_prty1_bb_a0, &brb_prty2_bb_a0,
5998 static const u16 brb_prty0_bb_b0_attn_idx[5] = {
6002 static struct attn_hw_reg brb_prty0_bb_b0 = {
6003 0, 5, brb_prty0_bb_b0_attn_idx, 0x3401dc, 0x3401e8, 0x3401e4, 0x3401e0
6006 static const u16 brb_prty1_bb_b0_attn_idx[31] = {
6007 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 23, 24, 36,
6009 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
6012 static struct attn_hw_reg brb_prty1_bb_b0 = {
6013 1, 31, brb_prty1_bb_b0_attn_idx, 0x340400, 0x34040c, 0x340408, 0x340404
6016 static const u16 brb_prty2_bb_b0_attn_idx[14] = {
6017 53, 54, 55, 56, 59, 61, 62, 63, 64, 69, 70, 71, 72, 73,
6020 static struct attn_hw_reg brb_prty2_bb_b0 = {
6021 2, 14, brb_prty2_bb_b0_attn_idx, 0x340410, 0x34041c, 0x340418, 0x340414
6024 static struct attn_hw_reg *brb_prty_bb_b0_regs[3] = {
6025 &brb_prty0_bb_b0, &brb_prty1_bb_b0, &brb_prty2_bb_b0,
6028 static const u16 brb_prty0_k2_attn_idx[5] = {
6032 static struct attn_hw_reg brb_prty0_k2 = {
6033 0, 5, brb_prty0_k2_attn_idx, 0x3401dc, 0x3401e8, 0x3401e4, 0x3401e0
6036 static const u16 brb_prty1_k2_attn_idx[31] = {
6037 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
6039 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,
6042 static struct attn_hw_reg brb_prty1_k2 = {
6043 1, 31, brb_prty1_k2_attn_idx, 0x340400, 0x34040c, 0x340408, 0x340404
6046 static const u16 brb_prty2_k2_attn_idx[30] = {
6047 50, 51, 52, 36, 37, 38, 39, 40, 41, 42, 43, 47, 53, 54, 55, 56, 57, 58,
6048 59, 49, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
6051 static struct attn_hw_reg brb_prty2_k2 = {
6052 2, 30, brb_prty2_k2_attn_idx, 0x340410, 0x34041c, 0x340418, 0x340414
6055 static struct attn_hw_reg *brb_prty_k2_regs[3] = {
6056 &brb_prty0_k2, &brb_prty1_k2, &brb_prty2_k2,
6060 static const char *src_int_attn_desc[1] = {
6061 "src_address_error",
6064 #define src_int_attn_desc OSAL_NULL
6067 static const u16 src_int0_bb_a0_attn_idx[1] = {
6071 static struct attn_hw_reg src_int0_bb_a0 = {
6072 0, 1, src_int0_bb_a0_attn_idx, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4
6075 static struct attn_hw_reg *src_int_bb_a0_regs[1] = {
6079 static const u16 src_int0_bb_b0_attn_idx[1] = {
6083 static struct attn_hw_reg src_int0_bb_b0 = {
6084 0, 1, src_int0_bb_b0_attn_idx, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4
6087 static struct attn_hw_reg *src_int_bb_b0_regs[1] = {
6091 static const u16 src_int0_k2_attn_idx[1] = {
6095 static struct attn_hw_reg src_int0_k2 = {
6096 0, 1, src_int0_k2_attn_idx, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4
6099 static struct attn_hw_reg *src_int_k2_regs[1] = {
6104 static const char *prs_int_attn_desc[2] = {
6105 "prs_address_error",
6106 "prs_lcid_validation_err",
6109 #define prs_int_attn_desc OSAL_NULL
6112 static const u16 prs_int0_bb_a0_attn_idx[2] = {
6116 static struct attn_hw_reg prs_int0_bb_a0 = {
6117 0, 2, prs_int0_bb_a0_attn_idx, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044
6120 static struct attn_hw_reg *prs_int_bb_a0_regs[1] = {
6124 static const u16 prs_int0_bb_b0_attn_idx[2] = {
6128 static struct attn_hw_reg prs_int0_bb_b0 = {
6129 0, 2, prs_int0_bb_b0_attn_idx, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044
6132 static struct attn_hw_reg *prs_int_bb_b0_regs[1] = {
6136 static const u16 prs_int0_k2_attn_idx[2] = {
6140 static struct attn_hw_reg prs_int0_k2 = {
6141 0, 2, prs_int0_k2_attn_idx, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044
6144 static struct attn_hw_reg *prs_int_k2_regs[1] = {
6149 static const char *prs_prty_attn_desc[75] = {
6151 "prs_gft_cam_parity",
6152 "prs_mem011_i_ecc_rf_int",
6153 "prs_mem012_i_ecc_rf_int",
6154 "prs_mem016_i_ecc_rf_int",
6155 "prs_mem017_i_ecc_rf_int",
6156 "prs_mem021_i_ecc_rf_int",
6157 "prs_mem022_i_ecc_rf_int",
6158 "prs_mem026_i_ecc_rf_int",
6159 "prs_mem027_i_ecc_rf_int",
6160 "prs_mem064_i_mem_prty",
6161 "prs_mem044_i_mem_prty",
6162 "prs_mem043_i_mem_prty",
6163 "prs_mem037_i_mem_prty",
6164 "prs_mem033_i_mem_prty",
6165 "prs_mem034_i_mem_prty",
6166 "prs_mem035_i_mem_prty",
6167 "prs_mem036_i_mem_prty",
6168 "prs_mem029_i_mem_prty",
6169 "prs_mem030_i_mem_prty",
6170 "prs_mem031_i_mem_prty",
6171 "prs_mem032_i_mem_prty",
6172 "prs_mem007_i_mem_prty",
6173 "prs_mem028_i_mem_prty",
6174 "prs_mem039_i_mem_prty",
6175 "prs_mem040_i_mem_prty",
6176 "prs_mem058_i_mem_prty",
6177 "prs_mem059_i_mem_prty",
6178 "prs_mem041_i_mem_prty",
6179 "prs_mem042_i_mem_prty",
6180 "prs_mem060_i_mem_prty",
6181 "prs_mem061_i_mem_prty",
6182 "prs_mem009_i_mem_prty",
6183 "prs_mem009_i_ecc_rf_int",
6184 "prs_mem010_i_ecc_rf_int",
6185 "prs_mem014_i_ecc_rf_int",
6186 "prs_mem015_i_ecc_rf_int",
6187 "prs_mem026_i_mem_prty",
6188 "prs_mem025_i_mem_prty",
6189 "prs_mem021_i_mem_prty",
6190 "prs_mem019_i_mem_prty",
6191 "prs_mem020_i_mem_prty",
6192 "prs_mem017_i_mem_prty",
6193 "prs_mem018_i_mem_prty",
6194 "prs_mem005_i_mem_prty",
6195 "prs_mem016_i_mem_prty",
6196 "prs_mem023_i_mem_prty",
6197 "prs_mem024_i_mem_prty",
6198 "prs_mem008_i_mem_prty",
6199 "prs_mem012_i_mem_prty",
6200 "prs_mem013_i_mem_prty",
6201 "prs_mem006_i_mem_prty",
6202 "prs_mem011_i_mem_prty",
6203 "prs_mem003_i_mem_prty",
6204 "prs_mem004_i_mem_prty",
6205 "prs_mem027_i_mem_prty",
6206 "prs_mem010_i_mem_prty",
6207 "prs_mem014_i_mem_prty",
6208 "prs_mem015_i_mem_prty",
6209 "prs_mem054_i_mem_prty",
6210 "prs_mem055_i_mem_prty",
6211 "prs_mem056_i_mem_prty",
6212 "prs_mem057_i_mem_prty",
6213 "prs_mem046_i_mem_prty",
6214 "prs_mem047_i_mem_prty",
6215 "prs_mem048_i_mem_prty",
6216 "prs_mem049_i_mem_prty",
6217 "prs_mem050_i_mem_prty",
6218 "prs_mem051_i_mem_prty",
6219 "prs_mem052_i_mem_prty",
6220 "prs_mem053_i_mem_prty",
6221 "prs_mem062_i_mem_prty",
6222 "prs_mem045_i_mem_prty",
6223 "prs_mem002_i_mem_prty",
6224 "prs_mem001_i_mem_prty",
6227 #define prs_prty_attn_desc OSAL_NULL
6230 static const u16 prs_prty0_bb_a0_attn_idx[1] = {
6234 static struct attn_hw_reg prs_prty0_bb_a0 = {
6235 0, 1, prs_prty0_bb_a0_attn_idx, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054
6238 static const u16 prs_prty1_bb_a0_attn_idx[31] = {
6239 13, 14, 15, 16, 18, 21, 22, 23, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42,
6240 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
6243 static struct attn_hw_reg prs_prty1_bb_a0 = {
6244 1, 31, prs_prty1_bb_a0_attn_idx, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208
6247 static const u16 prs_prty2_bb_a0_attn_idx[5] = {
6251 static struct attn_hw_reg prs_prty2_bb_a0 = {
6252 2, 5, prs_prty2_bb_a0_attn_idx, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218
6255 static struct attn_hw_reg *prs_prty_bb_a0_regs[3] = {
6256 &prs_prty0_bb_a0, &prs_prty1_bb_a0, &prs_prty2_bb_a0,
6259 static const u16 prs_prty0_bb_b0_attn_idx[2] = {
6263 static struct attn_hw_reg prs_prty0_bb_b0 = {
6264 0, 2, prs_prty0_bb_b0_attn_idx, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054
6267 static const u16 prs_prty1_bb_b0_attn_idx[31] = {
6268 13, 14, 15, 16, 18, 19, 21, 22, 23, 33, 34, 35, 36, 37, 38, 39, 40, 41,
6269 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
6272 static struct attn_hw_reg prs_prty1_bb_b0 = {
6273 1, 31, prs_prty1_bb_b0_attn_idx, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208
6276 static const u16 prs_prty2_bb_b0_attn_idx[5] = {
6280 static struct attn_hw_reg prs_prty2_bb_b0 = {
6281 2, 5, prs_prty2_bb_b0_attn_idx, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218
6284 static struct attn_hw_reg *prs_prty_bb_b0_regs[3] = {
6285 &prs_prty0_bb_b0, &prs_prty1_bb_b0, &prs_prty2_bb_b0,
6288 static const u16 prs_prty0_k2_attn_idx[2] = {
6292 static struct attn_hw_reg prs_prty0_k2 = {
6293 0, 2, prs_prty0_k2_attn_idx, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054
6296 static const u16 prs_prty1_k2_attn_idx[31] = {
6297 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
6298 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
6301 static struct attn_hw_reg prs_prty1_k2 = {
6302 1, 31, prs_prty1_k2_attn_idx, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208
6305 static const u16 prs_prty2_k2_attn_idx[31] = {
6306 56, 57, 58, 40, 41, 47, 38, 48, 50, 43, 46, 59, 60, 61, 62, 53, 54, 44,
6307 51, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
6310 static struct attn_hw_reg prs_prty2_k2 = {
6311 2, 31, prs_prty2_k2_attn_idx, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218
6314 static struct attn_hw_reg *prs_prty_k2_regs[3] = {
6315 &prs_prty0_k2, &prs_prty1_k2, &prs_prty2_k2,
6319 static const char *tsdm_int_attn_desc[28] = {
6320 "tsdm_address_error",
6321 "tsdm_inp_queue_error",
6322 "tsdm_delay_fifo_error",
6323 "tsdm_async_host_error",
6324 "tsdm_prm_fifo_error",
6325 "tsdm_ccfc_load_pend_error",
6326 "tsdm_tcfc_load_pend_error",
6327 "tsdm_dst_int_ram_wait_error",
6328 "tsdm_dst_pas_buf_wait_error",
6329 "tsdm_dst_pxp_immed_error",
6330 "tsdm_dst_pxp_dst_pend_error",
6331 "tsdm_dst_brb_src_pend_error",
6332 "tsdm_dst_brb_src_addr_error",
6333 "tsdm_rsp_brb_pend_error",
6334 "tsdm_rsp_int_ram_pend_error",
6335 "tsdm_rsp_brb_rd_data_error",
6336 "tsdm_rsp_int_ram_rd_data_error",
6337 "tsdm_rsp_pxp_rd_data_error",
6338 "tsdm_cm_delay_error",
6339 "tsdm_sh_delay_error",
6340 "tsdm_cmpl_pend_error",
6341 "tsdm_cprm_pend_error",
6342 "tsdm_timer_addr_error",
6343 "tsdm_timer_pend_error",
6344 "tsdm_dorq_dpm_error",
6345 "tsdm_dst_pxp_done_error",
6346 "tsdm_xcm_rmt_buffer_error",
6347 "tsdm_ycm_rmt_buffer_error",
6350 #define tsdm_int_attn_desc OSAL_NULL
6353 static const u16 tsdm_int0_bb_a0_attn_idx[26] = {
6354 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6359 static struct attn_hw_reg tsdm_int0_bb_a0 = {
6360 0, 26, tsdm_int0_bb_a0_attn_idx, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044
6363 static struct attn_hw_reg *tsdm_int_bb_a0_regs[1] = {
6367 static const u16 tsdm_int0_bb_b0_attn_idx[26] = {
6368 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6373 static struct attn_hw_reg tsdm_int0_bb_b0 = {
6374 0, 26, tsdm_int0_bb_b0_attn_idx, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044
6377 static struct attn_hw_reg *tsdm_int_bb_b0_regs[1] = {
6381 static const u16 tsdm_int0_k2_attn_idx[28] = {
6382 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6384 21, 22, 23, 24, 25, 26, 27,
6387 static struct attn_hw_reg tsdm_int0_k2 = {
6388 0, 28, tsdm_int0_k2_attn_idx, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044
6391 static struct attn_hw_reg *tsdm_int_k2_regs[1] = {
6396 static const char *tsdm_prty_attn_desc[10] = {
6397 "tsdm_mem009_i_mem_prty",
6398 "tsdm_mem008_i_mem_prty",
6399 "tsdm_mem007_i_mem_prty",
6400 "tsdm_mem006_i_mem_prty",
6401 "tsdm_mem005_i_mem_prty",
6402 "tsdm_mem002_i_mem_prty",
6403 "tsdm_mem010_i_mem_prty",
6404 "tsdm_mem001_i_mem_prty",
6405 "tsdm_mem003_i_mem_prty",
6406 "tsdm_mem004_i_mem_prty",
6409 #define tsdm_prty_attn_desc OSAL_NULL
6412 static const u16 tsdm_prty1_bb_a0_attn_idx[10] = {
6413 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
6416 static struct attn_hw_reg tsdm_prty1_bb_a0 = {
6417 0, 10, tsdm_prty1_bb_a0_attn_idx, 0xfb0200, 0xfb020c, 0xfb0208,
6421 static struct attn_hw_reg *tsdm_prty_bb_a0_regs[1] = {
6425 static const u16 tsdm_prty1_bb_b0_attn_idx[10] = {
6426 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
6429 static struct attn_hw_reg tsdm_prty1_bb_b0 = {
6430 0, 10, tsdm_prty1_bb_b0_attn_idx, 0xfb0200, 0xfb020c, 0xfb0208,
6434 static struct attn_hw_reg *tsdm_prty_bb_b0_regs[1] = {
6438 static const u16 tsdm_prty1_k2_attn_idx[10] = {
6439 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
6442 static struct attn_hw_reg tsdm_prty1_k2 = {
6443 0, 10, tsdm_prty1_k2_attn_idx, 0xfb0200, 0xfb020c, 0xfb0208, 0xfb0204
6446 static struct attn_hw_reg *tsdm_prty_k2_regs[1] = {
6451 static const char *msdm_int_attn_desc[28] = {
6452 "msdm_address_error",
6453 "msdm_inp_queue_error",
6454 "msdm_delay_fifo_error",
6455 "msdm_async_host_error",
6456 "msdm_prm_fifo_error",
6457 "msdm_ccfc_load_pend_error",
6458 "msdm_tcfc_load_pend_error",
6459 "msdm_dst_int_ram_wait_error",
6460 "msdm_dst_pas_buf_wait_error",
6461 "msdm_dst_pxp_immed_error",
6462 "msdm_dst_pxp_dst_pend_error",
6463 "msdm_dst_brb_src_pend_error",
6464 "msdm_dst_brb_src_addr_error",
6465 "msdm_rsp_brb_pend_error",
6466 "msdm_rsp_int_ram_pend_error",
6467 "msdm_rsp_brb_rd_data_error",
6468 "msdm_rsp_int_ram_rd_data_error",
6469 "msdm_rsp_pxp_rd_data_error",
6470 "msdm_cm_delay_error",
6471 "msdm_sh_delay_error",
6472 "msdm_cmpl_pend_error",
6473 "msdm_cprm_pend_error",
6474 "msdm_timer_addr_error",
6475 "msdm_timer_pend_error",
6476 "msdm_dorq_dpm_error",
6477 "msdm_dst_pxp_done_error",
6478 "msdm_xcm_rmt_buffer_error",
6479 "msdm_ycm_rmt_buffer_error",
6482 #define msdm_int_attn_desc OSAL_NULL
6485 static const u16 msdm_int0_bb_a0_attn_idx[26] = {
6486 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6491 static struct attn_hw_reg msdm_int0_bb_a0 = {
6492 0, 26, msdm_int0_bb_a0_attn_idx, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044
6495 static struct attn_hw_reg *msdm_int_bb_a0_regs[1] = {
6499 static const u16 msdm_int0_bb_b0_attn_idx[26] = {
6500 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6505 static struct attn_hw_reg msdm_int0_bb_b0 = {
6506 0, 26, msdm_int0_bb_b0_attn_idx, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044
6509 static struct attn_hw_reg *msdm_int_bb_b0_regs[1] = {
6513 static const u16 msdm_int0_k2_attn_idx[28] = {
6514 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6516 21, 22, 23, 24, 25, 26, 27,
6519 static struct attn_hw_reg msdm_int0_k2 = {
6520 0, 28, msdm_int0_k2_attn_idx, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044
6523 static struct attn_hw_reg *msdm_int_k2_regs[1] = {
6528 static const char *msdm_prty_attn_desc[11] = {
6529 "msdm_mem009_i_mem_prty",
6530 "msdm_mem008_i_mem_prty",
6531 "msdm_mem007_i_mem_prty",
6532 "msdm_mem006_i_mem_prty",
6533 "msdm_mem005_i_mem_prty",
6534 "msdm_mem002_i_mem_prty",
6535 "msdm_mem011_i_mem_prty",
6536 "msdm_mem001_i_mem_prty",
6537 "msdm_mem003_i_mem_prty",
6538 "msdm_mem004_i_mem_prty",
6539 "msdm_mem010_i_mem_prty",
6542 #define msdm_prty_attn_desc OSAL_NULL
6545 static const u16 msdm_prty1_bb_a0_attn_idx[11] = {
6546 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
6549 static struct attn_hw_reg msdm_prty1_bb_a0 = {
6550 0, 11, msdm_prty1_bb_a0_attn_idx, 0xfc0200, 0xfc020c, 0xfc0208,
6554 static struct attn_hw_reg *msdm_prty_bb_a0_regs[1] = {
6558 static const u16 msdm_prty1_bb_b0_attn_idx[11] = {
6559 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
6562 static struct attn_hw_reg msdm_prty1_bb_b0 = {
6563 0, 11, msdm_prty1_bb_b0_attn_idx, 0xfc0200, 0xfc020c, 0xfc0208,
6567 static struct attn_hw_reg *msdm_prty_bb_b0_regs[1] = {
6571 static const u16 msdm_prty1_k2_attn_idx[11] = {
6572 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
6575 static struct attn_hw_reg msdm_prty1_k2 = {
6576 0, 11, msdm_prty1_k2_attn_idx, 0xfc0200, 0xfc020c, 0xfc0208, 0xfc0204
6579 static struct attn_hw_reg *msdm_prty_k2_regs[1] = {
6584 static const char *usdm_int_attn_desc[28] = {
6585 "usdm_address_error",
6586 "usdm_inp_queue_error",
6587 "usdm_delay_fifo_error",
6588 "usdm_async_host_error",
6589 "usdm_prm_fifo_error",
6590 "usdm_ccfc_load_pend_error",
6591 "usdm_tcfc_load_pend_error",
6592 "usdm_dst_int_ram_wait_error",
6593 "usdm_dst_pas_buf_wait_error",
6594 "usdm_dst_pxp_immed_error",
6595 "usdm_dst_pxp_dst_pend_error",
6596 "usdm_dst_brb_src_pend_error",
6597 "usdm_dst_brb_src_addr_error",
6598 "usdm_rsp_brb_pend_error",
6599 "usdm_rsp_int_ram_pend_error",
6600 "usdm_rsp_brb_rd_data_error",
6601 "usdm_rsp_int_ram_rd_data_error",
6602 "usdm_rsp_pxp_rd_data_error",
6603 "usdm_cm_delay_error",
6604 "usdm_sh_delay_error",
6605 "usdm_cmpl_pend_error",
6606 "usdm_cprm_pend_error",
6607 "usdm_timer_addr_error",
6608 "usdm_timer_pend_error",
6609 "usdm_dorq_dpm_error",
6610 "usdm_dst_pxp_done_error",
6611 "usdm_xcm_rmt_buffer_error",
6612 "usdm_ycm_rmt_buffer_error",
6615 #define usdm_int_attn_desc OSAL_NULL
6618 static const u16 usdm_int0_bb_a0_attn_idx[26] = {
6619 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6624 static struct attn_hw_reg usdm_int0_bb_a0 = {
6625 0, 26, usdm_int0_bb_a0_attn_idx, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044
6628 static struct attn_hw_reg *usdm_int_bb_a0_regs[1] = {
6632 static const u16 usdm_int0_bb_b0_attn_idx[26] = {
6633 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6638 static struct attn_hw_reg usdm_int0_bb_b0 = {
6639 0, 26, usdm_int0_bb_b0_attn_idx, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044
6642 static struct attn_hw_reg *usdm_int_bb_b0_regs[1] = {
6646 static const u16 usdm_int0_k2_attn_idx[28] = {
6647 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6649 21, 22, 23, 24, 25, 26, 27,
6652 static struct attn_hw_reg usdm_int0_k2 = {
6653 0, 28, usdm_int0_k2_attn_idx, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044
6656 static struct attn_hw_reg *usdm_int_k2_regs[1] = {
6661 static const char *usdm_prty_attn_desc[10] = {
6662 "usdm_mem008_i_mem_prty",
6663 "usdm_mem007_i_mem_prty",
6664 "usdm_mem006_i_mem_prty",
6665 "usdm_mem005_i_mem_prty",
6666 "usdm_mem002_i_mem_prty",
6667 "usdm_mem010_i_mem_prty",
6668 "usdm_mem001_i_mem_prty",
6669 "usdm_mem003_i_mem_prty",
6670 "usdm_mem004_i_mem_prty",
6671 "usdm_mem009_i_mem_prty",
6674 #define usdm_prty_attn_desc OSAL_NULL
6677 static const u16 usdm_prty1_bb_a0_attn_idx[10] = {
6678 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
6681 static struct attn_hw_reg usdm_prty1_bb_a0 = {
6682 0, 10, usdm_prty1_bb_a0_attn_idx, 0xfd0200, 0xfd020c, 0xfd0208,
6686 static struct attn_hw_reg *usdm_prty_bb_a0_regs[1] = {
6690 static const u16 usdm_prty1_bb_b0_attn_idx[10] = {
6691 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
6694 static struct attn_hw_reg usdm_prty1_bb_b0 = {
6695 0, 10, usdm_prty1_bb_b0_attn_idx, 0xfd0200, 0xfd020c, 0xfd0208,
6699 static struct attn_hw_reg *usdm_prty_bb_b0_regs[1] = {
6703 static const u16 usdm_prty1_k2_attn_idx[10] = {
6704 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
6707 static struct attn_hw_reg usdm_prty1_k2 = {
6708 0, 10, usdm_prty1_k2_attn_idx, 0xfd0200, 0xfd020c, 0xfd0208, 0xfd0204
6711 static struct attn_hw_reg *usdm_prty_k2_regs[1] = {
6716 static const char *xsdm_int_attn_desc[28] = {
6717 "xsdm_address_error",
6718 "xsdm_inp_queue_error",
6719 "xsdm_delay_fifo_error",
6720 "xsdm_async_host_error",
6721 "xsdm_prm_fifo_error",
6722 "xsdm_ccfc_load_pend_error",
6723 "xsdm_tcfc_load_pend_error",
6724 "xsdm_dst_int_ram_wait_error",
6725 "xsdm_dst_pas_buf_wait_error",
6726 "xsdm_dst_pxp_immed_error",
6727 "xsdm_dst_pxp_dst_pend_error",
6728 "xsdm_dst_brb_src_pend_error",
6729 "xsdm_dst_brb_src_addr_error",
6730 "xsdm_rsp_brb_pend_error",
6731 "xsdm_rsp_int_ram_pend_error",
6732 "xsdm_rsp_brb_rd_data_error",
6733 "xsdm_rsp_int_ram_rd_data_error",
6734 "xsdm_rsp_pxp_rd_data_error",
6735 "xsdm_cm_delay_error",
6736 "xsdm_sh_delay_error",
6737 "xsdm_cmpl_pend_error",
6738 "xsdm_cprm_pend_error",
6739 "xsdm_timer_addr_error",
6740 "xsdm_timer_pend_error",
6741 "xsdm_dorq_dpm_error",
6742 "xsdm_dst_pxp_done_error",
6743 "xsdm_xcm_rmt_buffer_error",
6744 "xsdm_ycm_rmt_buffer_error",
6747 #define xsdm_int_attn_desc OSAL_NULL
6750 static const u16 xsdm_int0_bb_a0_attn_idx[26] = {
6751 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6756 static struct attn_hw_reg xsdm_int0_bb_a0 = {
6757 0, 26, xsdm_int0_bb_a0_attn_idx, 0xf80040, 0xf8004c, 0xf80048, 0xf80044
6760 static struct attn_hw_reg *xsdm_int_bb_a0_regs[1] = {
6764 static const u16 xsdm_int0_bb_b0_attn_idx[26] = {
6765 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6770 static struct attn_hw_reg xsdm_int0_bb_b0 = {
6771 0, 26, xsdm_int0_bb_b0_attn_idx, 0xf80040, 0xf8004c, 0xf80048, 0xf80044
6774 static struct attn_hw_reg *xsdm_int_bb_b0_regs[1] = {
6778 static const u16 xsdm_int0_k2_attn_idx[28] = {
6779 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6781 21, 22, 23, 24, 25, 26, 27,
6784 static struct attn_hw_reg xsdm_int0_k2 = {
6785 0, 28, xsdm_int0_k2_attn_idx, 0xf80040, 0xf8004c, 0xf80048, 0xf80044
6788 static struct attn_hw_reg *xsdm_int_k2_regs[1] = {
6793 static const char *xsdm_prty_attn_desc[10] = {
6794 "xsdm_mem009_i_mem_prty",
6795 "xsdm_mem008_i_mem_prty",
6796 "xsdm_mem007_i_mem_prty",
6797 "xsdm_mem006_i_mem_prty",
6798 "xsdm_mem003_i_mem_prty",
6799 "xsdm_mem010_i_mem_prty",
6800 "xsdm_mem002_i_mem_prty",
6801 "xsdm_mem004_i_mem_prty",
6802 "xsdm_mem005_i_mem_prty",
6803 "xsdm_mem001_i_mem_prty",
6806 #define xsdm_prty_attn_desc OSAL_NULL
6809 static const u16 xsdm_prty1_bb_a0_attn_idx[10] = {
6810 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
6813 static struct attn_hw_reg xsdm_prty1_bb_a0 = {
6814 0, 10, xsdm_prty1_bb_a0_attn_idx, 0xf80200, 0xf8020c, 0xf80208,
6818 static struct attn_hw_reg *xsdm_prty_bb_a0_regs[1] = {
6822 static const u16 xsdm_prty1_bb_b0_attn_idx[10] = {
6823 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
6826 static struct attn_hw_reg xsdm_prty1_bb_b0 = {
6827 0, 10, xsdm_prty1_bb_b0_attn_idx, 0xf80200, 0xf8020c, 0xf80208,
6831 static struct attn_hw_reg *xsdm_prty_bb_b0_regs[1] = {
6835 static const u16 xsdm_prty1_k2_attn_idx[10] = {
6836 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
6839 static struct attn_hw_reg xsdm_prty1_k2 = {
6840 0, 10, xsdm_prty1_k2_attn_idx, 0xf80200, 0xf8020c, 0xf80208, 0xf80204
6843 static struct attn_hw_reg *xsdm_prty_k2_regs[1] = {
6848 static const char *ysdm_int_attn_desc[28] = {
6849 "ysdm_address_error",
6850 "ysdm_inp_queue_error",
6851 "ysdm_delay_fifo_error",
6852 "ysdm_async_host_error",
6853 "ysdm_prm_fifo_error",
6854 "ysdm_ccfc_load_pend_error",
6855 "ysdm_tcfc_load_pend_error",
6856 "ysdm_dst_int_ram_wait_error",
6857 "ysdm_dst_pas_buf_wait_error",
6858 "ysdm_dst_pxp_immed_error",
6859 "ysdm_dst_pxp_dst_pend_error",
6860 "ysdm_dst_brb_src_pend_error",
6861 "ysdm_dst_brb_src_addr_error",
6862 "ysdm_rsp_brb_pend_error",
6863 "ysdm_rsp_int_ram_pend_error",
6864 "ysdm_rsp_brb_rd_data_error",
6865 "ysdm_rsp_int_ram_rd_data_error",
6866 "ysdm_rsp_pxp_rd_data_error",
6867 "ysdm_cm_delay_error",
6868 "ysdm_sh_delay_error",
6869 "ysdm_cmpl_pend_error",
6870 "ysdm_cprm_pend_error",
6871 "ysdm_timer_addr_error",
6872 "ysdm_timer_pend_error",
6873 "ysdm_dorq_dpm_error",
6874 "ysdm_dst_pxp_done_error",
6875 "ysdm_xcm_rmt_buffer_error",
6876 "ysdm_ycm_rmt_buffer_error",
6879 #define ysdm_int_attn_desc OSAL_NULL
6882 static const u16 ysdm_int0_bb_a0_attn_idx[26] = {
6883 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6888 static struct attn_hw_reg ysdm_int0_bb_a0 = {
6889 0, 26, ysdm_int0_bb_a0_attn_idx, 0xf90040, 0xf9004c, 0xf90048, 0xf90044
6892 static struct attn_hw_reg *ysdm_int_bb_a0_regs[1] = {
6896 static const u16 ysdm_int0_bb_b0_attn_idx[26] = {
6897 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6902 static struct attn_hw_reg ysdm_int0_bb_b0 = {
6903 0, 26, ysdm_int0_bb_b0_attn_idx, 0xf90040, 0xf9004c, 0xf90048, 0xf90044
6906 static struct attn_hw_reg *ysdm_int_bb_b0_regs[1] = {
6910 static const u16 ysdm_int0_k2_attn_idx[28] = {
6911 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
6913 21, 22, 23, 24, 25, 26, 27,
6916 static struct attn_hw_reg ysdm_int0_k2 = {
6917 0, 28, ysdm_int0_k2_attn_idx, 0xf90040, 0xf9004c, 0xf90048, 0xf90044
6920 static struct attn_hw_reg *ysdm_int_k2_regs[1] = {
6925 static const char *ysdm_prty_attn_desc[9] = {
6926 "ysdm_mem008_i_mem_prty",
6927 "ysdm_mem007_i_mem_prty",
6928 "ysdm_mem006_i_mem_prty",
6929 "ysdm_mem005_i_mem_prty",
6930 "ysdm_mem002_i_mem_prty",
6931 "ysdm_mem009_i_mem_prty",
6932 "ysdm_mem001_i_mem_prty",
6933 "ysdm_mem003_i_mem_prty",
6934 "ysdm_mem004_i_mem_prty",
6937 #define ysdm_prty_attn_desc OSAL_NULL
6940 static const u16 ysdm_prty1_bb_a0_attn_idx[9] = {
6941 0, 1, 2, 3, 4, 5, 6, 7, 8,
6944 static struct attn_hw_reg ysdm_prty1_bb_a0 = {
6945 0, 9, ysdm_prty1_bb_a0_attn_idx, 0xf90200, 0xf9020c, 0xf90208, 0xf90204
6948 static struct attn_hw_reg *ysdm_prty_bb_a0_regs[1] = {
6952 static const u16 ysdm_prty1_bb_b0_attn_idx[9] = {
6953 0, 1, 2, 3, 4, 5, 6, 7, 8,
6956 static struct attn_hw_reg ysdm_prty1_bb_b0 = {
6957 0, 9, ysdm_prty1_bb_b0_attn_idx, 0xf90200, 0xf9020c, 0xf90208, 0xf90204
6960 static struct attn_hw_reg *ysdm_prty_bb_b0_regs[1] = {
6964 static const u16 ysdm_prty1_k2_attn_idx[9] = {
6965 0, 1, 2, 3, 4, 5, 6, 7, 8,
6968 static struct attn_hw_reg ysdm_prty1_k2 = {
6969 0, 9, ysdm_prty1_k2_attn_idx, 0xf90200, 0xf9020c, 0xf90208, 0xf90204
6972 static struct attn_hw_reg *ysdm_prty_k2_regs[1] = {
6977 static const char *psdm_int_attn_desc[28] = {
6978 "psdm_address_error",
6979 "psdm_inp_queue_error",
6980 "psdm_delay_fifo_error",
6981 "psdm_async_host_error",
6982 "psdm_prm_fifo_error",
6983 "psdm_ccfc_load_pend_error",
6984 "psdm_tcfc_load_pend_error",
6985 "psdm_dst_int_ram_wait_error",
6986 "psdm_dst_pas_buf_wait_error",
6987 "psdm_dst_pxp_immed_error",
6988 "psdm_dst_pxp_dst_pend_error",
6989 "psdm_dst_brb_src_pend_error",
6990 "psdm_dst_brb_src_addr_error",
6991 "psdm_rsp_brb_pend_error",
6992 "psdm_rsp_int_ram_pend_error",
6993 "psdm_rsp_brb_rd_data_error",
6994 "psdm_rsp_int_ram_rd_data_error",
6995 "psdm_rsp_pxp_rd_data_error",
6996 "psdm_cm_delay_error",
6997 "psdm_sh_delay_error",
6998 "psdm_cmpl_pend_error",
6999 "psdm_cprm_pend_error",
7000 "psdm_timer_addr_error",
7001 "psdm_timer_pend_error",
7002 "psdm_dorq_dpm_error",
7003 "psdm_dst_pxp_done_error",
7004 "psdm_xcm_rmt_buffer_error",
7005 "psdm_ycm_rmt_buffer_error",
7008 #define psdm_int_attn_desc OSAL_NULL
7011 static const u16 psdm_int0_bb_a0_attn_idx[26] = {
7012 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7017 static struct attn_hw_reg psdm_int0_bb_a0 = {
7018 0, 26, psdm_int0_bb_a0_attn_idx, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044
7021 static struct attn_hw_reg *psdm_int_bb_a0_regs[1] = {
7025 static const u16 psdm_int0_bb_b0_attn_idx[26] = {
7026 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7031 static struct attn_hw_reg psdm_int0_bb_b0 = {
7032 0, 26, psdm_int0_bb_b0_attn_idx, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044
7035 static struct attn_hw_reg *psdm_int_bb_b0_regs[1] = {
7039 static const u16 psdm_int0_k2_attn_idx[28] = {
7040 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7042 21, 22, 23, 24, 25, 26, 27,
7045 static struct attn_hw_reg psdm_int0_k2 = {
7046 0, 28, psdm_int0_k2_attn_idx, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044
7049 static struct attn_hw_reg *psdm_int_k2_regs[1] = {
7054 static const char *psdm_prty_attn_desc[9] = {
7055 "psdm_mem008_i_mem_prty",
7056 "psdm_mem007_i_mem_prty",
7057 "psdm_mem006_i_mem_prty",
7058 "psdm_mem005_i_mem_prty",
7059 "psdm_mem002_i_mem_prty",
7060 "psdm_mem009_i_mem_prty",
7061 "psdm_mem001_i_mem_prty",
7062 "psdm_mem003_i_mem_prty",
7063 "psdm_mem004_i_mem_prty",
7066 #define psdm_prty_attn_desc OSAL_NULL
7069 static const u16 psdm_prty1_bb_a0_attn_idx[9] = {
7070 0, 1, 2, 3, 4, 5, 6, 7, 8,
7073 static struct attn_hw_reg psdm_prty1_bb_a0 = {
7074 0, 9, psdm_prty1_bb_a0_attn_idx, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204
7077 static struct attn_hw_reg *psdm_prty_bb_a0_regs[1] = {
7081 static const u16 psdm_prty1_bb_b0_attn_idx[9] = {
7082 0, 1, 2, 3, 4, 5, 6, 7, 8,
7085 static struct attn_hw_reg psdm_prty1_bb_b0 = {
7086 0, 9, psdm_prty1_bb_b0_attn_idx, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204
7089 static struct attn_hw_reg *psdm_prty_bb_b0_regs[1] = {
7093 static const u16 psdm_prty1_k2_attn_idx[9] = {
7094 0, 1, 2, 3, 4, 5, 6, 7, 8,
7097 static struct attn_hw_reg psdm_prty1_k2 = {
7098 0, 9, psdm_prty1_k2_attn_idx, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204
7101 static struct attn_hw_reg *psdm_prty_k2_regs[1] = {
7106 static const char *tsem_int_attn_desc[46] = {
7107 "tsem_address_error",
7108 "tsem_fic_last_error",
7109 "tsem_fic_length_error",
7110 "tsem_fic_fifo_error",
7111 "tsem_pas_buf_fifo_error",
7112 "tsem_sync_fin_pop_error",
7113 "tsem_sync_dra_wr_push_error",
7114 "tsem_sync_dra_wr_pop_error",
7115 "tsem_sync_dra_rd_push_error",
7116 "tsem_sync_dra_rd_pop_error",
7117 "tsem_sync_fin_push_error",
7118 "tsem_sem_fast_address_error",
7119 "tsem_cam_lsb_inp_fifo",
7120 "tsem_cam_msb_inp_fifo",
7121 "tsem_cam_out_fifo",
7123 "tsem_thread_fifo_error",
7124 "tsem_thread_overrun",
7125 "tsem_sync_ext_store_push_error",
7126 "tsem_sync_ext_store_pop_error",
7127 "tsem_sync_ext_load_push_error",
7128 "tsem_sync_ext_load_pop_error",
7129 "tsem_sync_ram_rd_push_error",
7130 "tsem_sync_ram_rd_pop_error",
7131 "tsem_sync_ram_wr_pop_error",
7132 "tsem_sync_ram_wr_push_error",
7133 "tsem_sync_dbg_push_error",
7134 "tsem_sync_dbg_pop_error",
7135 "tsem_dbg_fifo_error",
7136 "tsem_cam_msb2_inp_fifo",
7137 "tsem_vfc_interrupt",
7138 "tsem_vfc_out_fifo_error",
7139 "tsem_storm_stack_uf_attn",
7140 "tsem_storm_stack_of_attn",
7141 "tsem_storm_runtime_error",
7142 "tsem_ext_load_pend_wr_error",
7143 "tsem_thread_rls_orun_error",
7144 "tsem_thread_rls_aloc_error",
7145 "tsem_thread_rls_vld_error",
7146 "tsem_ext_thread_oor_error",
7147 "tsem_ord_id_fifo_error",
7148 "tsem_invld_foc_error",
7149 "tsem_ext_ld_len_error",
7150 "tsem_thrd_ord_fifo_error",
7151 "tsem_invld_thrd_ord_error",
7152 "tsem_fast_memory_address_error",
7155 #define tsem_int_attn_desc OSAL_NULL
7158 static const u16 tsem_int0_bb_a0_attn_idx[32] = {
7159 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7161 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
7164 static struct attn_hw_reg tsem_int0_bb_a0 = {
7165 0, 32, tsem_int0_bb_a0_attn_idx, 0x1700040, 0x170004c, 0x1700048,
7169 static const u16 tsem_int1_bb_a0_attn_idx[13] = {
7170 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
7173 static struct attn_hw_reg tsem_int1_bb_a0 = {
7174 1, 13, tsem_int1_bb_a0_attn_idx, 0x1700050, 0x170005c, 0x1700058,
7178 static const u16 tsem_fast_memory_int0_bb_a0_attn_idx[1] = {
7182 static struct attn_hw_reg tsem_fast_memory_int0_bb_a0 = {
7183 2, 1, tsem_fast_memory_int0_bb_a0_attn_idx, 0x1740040, 0x174004c,
7184 0x1740048, 0x1740044
7187 static struct attn_hw_reg *tsem_int_bb_a0_regs[3] = {
7188 &tsem_int0_bb_a0, &tsem_int1_bb_a0, &tsem_fast_memory_int0_bb_a0,
7191 static const u16 tsem_int0_bb_b0_attn_idx[32] = {
7192 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7194 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
7197 static struct attn_hw_reg tsem_int0_bb_b0 = {
7198 0, 32, tsem_int0_bb_b0_attn_idx, 0x1700040, 0x170004c, 0x1700048,
7202 static const u16 tsem_int1_bb_b0_attn_idx[13] = {
7203 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
7206 static struct attn_hw_reg tsem_int1_bb_b0 = {
7207 1, 13, tsem_int1_bb_b0_attn_idx, 0x1700050, 0x170005c, 0x1700058,
7211 static const u16 tsem_fast_memory_int0_bb_b0_attn_idx[1] = {
7215 static struct attn_hw_reg tsem_fast_memory_int0_bb_b0 = {
7216 2, 1, tsem_fast_memory_int0_bb_b0_attn_idx, 0x1740040, 0x174004c,
7217 0x1740048, 0x1740044
7220 static struct attn_hw_reg *tsem_int_bb_b0_regs[3] = {
7221 &tsem_int0_bb_b0, &tsem_int1_bb_b0, &tsem_fast_memory_int0_bb_b0,
7224 static const u16 tsem_int0_k2_attn_idx[32] = {
7225 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7227 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
7230 static struct attn_hw_reg tsem_int0_k2 = {
7231 0, 32, tsem_int0_k2_attn_idx, 0x1700040, 0x170004c, 0x1700048,
7235 static const u16 tsem_int1_k2_attn_idx[13] = {
7236 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
7239 static struct attn_hw_reg tsem_int1_k2 = {
7240 1, 13, tsem_int1_k2_attn_idx, 0x1700050, 0x170005c, 0x1700058,
7244 static const u16 tsem_fast_memory_int0_k2_attn_idx[1] = {
7248 static struct attn_hw_reg tsem_fast_memory_int0_k2 = {
7249 2, 1, tsem_fast_memory_int0_k2_attn_idx, 0x1740040, 0x174004c,
7254 static struct attn_hw_reg *tsem_int_k2_regs[3] = {
7255 &tsem_int0_k2, &tsem_int1_k2, &tsem_fast_memory_int0_k2,
7259 static const char *tsem_prty_attn_desc[23] = {
7260 "tsem_vfc_rbc_parity_error",
7261 "tsem_storm_rf_parity_error",
7262 "tsem_reg_gen_parity_error",
7263 "tsem_mem005_i_ecc_0_rf_int",
7264 "tsem_mem005_i_ecc_1_rf_int",
7265 "tsem_mem004_i_mem_prty",
7266 "tsem_mem002_i_mem_prty",
7267 "tsem_mem003_i_mem_prty",
7268 "tsem_mem001_i_mem_prty",
7269 "tsem_fast_memory_mem024_i_mem_prty",
7270 "tsem_fast_memory_mem023_i_mem_prty",
7271 "tsem_fast_memory_mem022_i_mem_prty",
7272 "tsem_fast_memory_mem021_i_mem_prty",
7273 "tsem_fast_memory_mem020_i_mem_prty",
7274 "tsem_fast_memory_mem019_i_mem_prty",
7275 "tsem_fast_memory_mem018_i_mem_prty",
7276 "tsem_fast_memory_vfc_config_mem005_i_ecc_rf_int",
7277 "tsem_fast_memory_vfc_config_mem002_i_ecc_rf_int",
7278 "tsem_fast_memory_vfc_config_mem006_i_mem_prty",
7279 "tsem_fast_memory_vfc_config_mem001_i_mem_prty",
7280 "tsem_fast_memory_vfc_config_mem004_i_mem_prty",
7281 "tsem_fast_memory_vfc_config_mem003_i_mem_prty",
7282 "tsem_fast_memory_vfc_config_mem007_i_mem_prty",
7285 #define tsem_prty_attn_desc OSAL_NULL
7288 static const u16 tsem_prty0_bb_a0_attn_idx[3] = {
7292 static struct attn_hw_reg tsem_prty0_bb_a0 = {
7293 0, 3, tsem_prty0_bb_a0_attn_idx, 0x17000c8, 0x17000d4, 0x17000d0,
7297 static const u16 tsem_prty1_bb_a0_attn_idx[6] = {
7301 static struct attn_hw_reg tsem_prty1_bb_a0 = {
7302 1, 6, tsem_prty1_bb_a0_attn_idx, 0x1700200, 0x170020c, 0x1700208,
7306 static const u16 tsem_fast_memory_vfc_config_prty1_bb_a0_attn_idx[6] = {
7307 16, 17, 19, 20, 21, 22,
7310 static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_bb_a0 = {
7311 2, 6, tsem_fast_memory_vfc_config_prty1_bb_a0_attn_idx, 0x174a200,
7312 0x174a20c, 0x174a208, 0x174a204
7315 static struct attn_hw_reg *tsem_prty_bb_a0_regs[3] = {
7316 &tsem_prty0_bb_a0, &tsem_prty1_bb_a0,
7317 &tsem_fast_memory_vfc_config_prty1_bb_a0,
7320 static const u16 tsem_prty0_bb_b0_attn_idx[3] = {
7324 static struct attn_hw_reg tsem_prty0_bb_b0 = {
7325 0, 3, tsem_prty0_bb_b0_attn_idx, 0x17000c8, 0x17000d4, 0x17000d0,
7329 static const u16 tsem_prty1_bb_b0_attn_idx[6] = {
7333 static struct attn_hw_reg tsem_prty1_bb_b0 = {
7334 1, 6, tsem_prty1_bb_b0_attn_idx, 0x1700200, 0x170020c, 0x1700208,
7338 static const u16 tsem_fast_memory_vfc_config_prty1_bb_b0_attn_idx[6] = {
7339 16, 17, 19, 20, 21, 22,
7342 static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_bb_b0 = {
7343 2, 6, tsem_fast_memory_vfc_config_prty1_bb_b0_attn_idx, 0x174a200,
7344 0x174a20c, 0x174a208, 0x174a204
7347 static struct attn_hw_reg *tsem_prty_bb_b0_regs[3] = {
7348 &tsem_prty0_bb_b0, &tsem_prty1_bb_b0,
7349 &tsem_fast_memory_vfc_config_prty1_bb_b0,
7352 static const u16 tsem_prty0_k2_attn_idx[3] = {
7356 static struct attn_hw_reg tsem_prty0_k2 = {
7357 0, 3, tsem_prty0_k2_attn_idx, 0x17000c8, 0x17000d4, 0x17000d0,
7361 static const u16 tsem_prty1_k2_attn_idx[6] = {
7365 static struct attn_hw_reg tsem_prty1_k2 = {
7366 1, 6, tsem_prty1_k2_attn_idx, 0x1700200, 0x170020c, 0x1700208,
7370 static const u16 tsem_fast_memory_prty1_k2_attn_idx[7] = {
7371 9, 10, 11, 12, 13, 14, 15,
7374 static struct attn_hw_reg tsem_fast_memory_prty1_k2 = {
7375 2, 7, tsem_fast_memory_prty1_k2_attn_idx, 0x1740200, 0x174020c,
7380 static const u16 tsem_fast_memory_vfc_config_prty1_k2_attn_idx[6] = {
7381 16, 17, 18, 19, 20, 21,
7384 static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_k2 = {
7385 3, 6, tsem_fast_memory_vfc_config_prty1_k2_attn_idx, 0x174a200,
7387 0x174a208, 0x174a204
7390 static struct attn_hw_reg *tsem_prty_k2_regs[4] = {
7391 &tsem_prty0_k2, &tsem_prty1_k2, &tsem_fast_memory_prty1_k2,
7392 &tsem_fast_memory_vfc_config_prty1_k2,
7396 static const char *msem_int_attn_desc[46] = {
7397 "msem_address_error",
7398 "msem_fic_last_error",
7399 "msem_fic_length_error",
7400 "msem_fic_fifo_error",
7401 "msem_pas_buf_fifo_error",
7402 "msem_sync_fin_pop_error",
7403 "msem_sync_dra_wr_push_error",
7404 "msem_sync_dra_wr_pop_error",
7405 "msem_sync_dra_rd_push_error",
7406 "msem_sync_dra_rd_pop_error",
7407 "msem_sync_fin_push_error",
7408 "msem_sem_fast_address_error",
7409 "msem_cam_lsb_inp_fifo",
7410 "msem_cam_msb_inp_fifo",
7411 "msem_cam_out_fifo",
7413 "msem_thread_fifo_error",
7414 "msem_thread_overrun",
7415 "msem_sync_ext_store_push_error",
7416 "msem_sync_ext_store_pop_error",
7417 "msem_sync_ext_load_push_error",
7418 "msem_sync_ext_load_pop_error",
7419 "msem_sync_ram_rd_push_error",
7420 "msem_sync_ram_rd_pop_error",
7421 "msem_sync_ram_wr_pop_error",
7422 "msem_sync_ram_wr_push_error",
7423 "msem_sync_dbg_push_error",
7424 "msem_sync_dbg_pop_error",
7425 "msem_dbg_fifo_error",
7426 "msem_cam_msb2_inp_fifo",
7427 "msem_vfc_interrupt",
7428 "msem_vfc_out_fifo_error",
7429 "msem_storm_stack_uf_attn",
7430 "msem_storm_stack_of_attn",
7431 "msem_storm_runtime_error",
7432 "msem_ext_load_pend_wr_error",
7433 "msem_thread_rls_orun_error",
7434 "msem_thread_rls_aloc_error",
7435 "msem_thread_rls_vld_error",
7436 "msem_ext_thread_oor_error",
7437 "msem_ord_id_fifo_error",
7438 "msem_invld_foc_error",
7439 "msem_ext_ld_len_error",
7440 "msem_thrd_ord_fifo_error",
7441 "msem_invld_thrd_ord_error",
7442 "msem_fast_memory_address_error",
7445 #define msem_int_attn_desc OSAL_NULL
7448 static const u16 msem_int0_bb_a0_attn_idx[32] = {
7449 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7451 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
7454 static struct attn_hw_reg msem_int0_bb_a0 = {
7455 0, 32, msem_int0_bb_a0_attn_idx, 0x1800040, 0x180004c, 0x1800048,
7459 static const u16 msem_int1_bb_a0_attn_idx[13] = {
7460 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
7463 static struct attn_hw_reg msem_int1_bb_a0 = {
7464 1, 13, msem_int1_bb_a0_attn_idx, 0x1800050, 0x180005c, 0x1800058,
7468 static const u16 msem_fast_memory_int0_bb_a0_attn_idx[1] = {
7472 static struct attn_hw_reg msem_fast_memory_int0_bb_a0 = {
7473 2, 1, msem_fast_memory_int0_bb_a0_attn_idx, 0x1840040, 0x184004c,
7474 0x1840048, 0x1840044
7477 static struct attn_hw_reg *msem_int_bb_a0_regs[3] = {
7478 &msem_int0_bb_a0, &msem_int1_bb_a0, &msem_fast_memory_int0_bb_a0,
7481 static const u16 msem_int0_bb_b0_attn_idx[32] = {
7482 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7484 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
7487 static struct attn_hw_reg msem_int0_bb_b0 = {
7488 0, 32, msem_int0_bb_b0_attn_idx, 0x1800040, 0x180004c, 0x1800048,
7492 static const u16 msem_int1_bb_b0_attn_idx[13] = {
7493 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
7496 static struct attn_hw_reg msem_int1_bb_b0 = {
7497 1, 13, msem_int1_bb_b0_attn_idx, 0x1800050, 0x180005c, 0x1800058,
7501 static const u16 msem_fast_memory_int0_bb_b0_attn_idx[1] = {
7505 static struct attn_hw_reg msem_fast_memory_int0_bb_b0 = {
7506 2, 1, msem_fast_memory_int0_bb_b0_attn_idx, 0x1840040, 0x184004c,
7507 0x1840048, 0x1840044
7510 static struct attn_hw_reg *msem_int_bb_b0_regs[3] = {
7511 &msem_int0_bb_b0, &msem_int1_bb_b0, &msem_fast_memory_int0_bb_b0,
7514 static const u16 msem_int0_k2_attn_idx[32] = {
7515 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7517 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
7520 static struct attn_hw_reg msem_int0_k2 = {
7521 0, 32, msem_int0_k2_attn_idx, 0x1800040, 0x180004c, 0x1800048,
7525 static const u16 msem_int1_k2_attn_idx[13] = {
7526 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
7529 static struct attn_hw_reg msem_int1_k2 = {
7530 1, 13, msem_int1_k2_attn_idx, 0x1800050, 0x180005c, 0x1800058,
7534 static const u16 msem_fast_memory_int0_k2_attn_idx[1] = {
7538 static struct attn_hw_reg msem_fast_memory_int0_k2 = {
7539 2, 1, msem_fast_memory_int0_k2_attn_idx, 0x1840040, 0x184004c,
7544 static struct attn_hw_reg *msem_int_k2_regs[3] = {
7545 &msem_int0_k2, &msem_int1_k2, &msem_fast_memory_int0_k2,
7549 static const char *msem_prty_attn_desc[23] = {
7550 "msem_vfc_rbc_parity_error",
7551 "msem_storm_rf_parity_error",
7552 "msem_reg_gen_parity_error",
7553 "msem_mem005_i_ecc_0_rf_int",
7554 "msem_mem005_i_ecc_1_rf_int",
7555 "msem_mem004_i_mem_prty",
7556 "msem_mem002_i_mem_prty",
7557 "msem_mem003_i_mem_prty",
7558 "msem_mem001_i_mem_prty",
7559 "msem_fast_memory_mem024_i_mem_prty",
7560 "msem_fast_memory_mem023_i_mem_prty",
7561 "msem_fast_memory_mem022_i_mem_prty",
7562 "msem_fast_memory_mem021_i_mem_prty",
7563 "msem_fast_memory_mem020_i_mem_prty",
7564 "msem_fast_memory_mem019_i_mem_prty",
7565 "msem_fast_memory_mem018_i_mem_prty",
7566 "msem_fast_memory_vfc_config_mem005_i_ecc_rf_int",
7567 "msem_fast_memory_vfc_config_mem002_i_ecc_rf_int",
7568 "msem_fast_memory_vfc_config_mem006_i_mem_prty",
7569 "msem_fast_memory_vfc_config_mem001_i_mem_prty",
7570 "msem_fast_memory_vfc_config_mem004_i_mem_prty",
7571 "msem_fast_memory_vfc_config_mem003_i_mem_prty",
7572 "msem_fast_memory_vfc_config_mem007_i_mem_prty",
7575 #define msem_prty_attn_desc OSAL_NULL
7578 static const u16 msem_prty0_bb_a0_attn_idx[3] = {
7582 static struct attn_hw_reg msem_prty0_bb_a0 = {
7583 0, 3, msem_prty0_bb_a0_attn_idx, 0x18000c8, 0x18000d4, 0x18000d0,
7587 static const u16 msem_prty1_bb_a0_attn_idx[6] = {
7591 static struct attn_hw_reg msem_prty1_bb_a0 = {
7592 1, 6, msem_prty1_bb_a0_attn_idx, 0x1800200, 0x180020c, 0x1800208,
7596 static struct attn_hw_reg *msem_prty_bb_a0_regs[2] = {
7597 &msem_prty0_bb_a0, &msem_prty1_bb_a0,
7600 static const u16 msem_prty0_bb_b0_attn_idx[3] = {
7604 static struct attn_hw_reg msem_prty0_bb_b0 = {
7605 0, 3, msem_prty0_bb_b0_attn_idx, 0x18000c8, 0x18000d4, 0x18000d0,
7609 static const u16 msem_prty1_bb_b0_attn_idx[6] = {
7613 static struct attn_hw_reg msem_prty1_bb_b0 = {
7614 1, 6, msem_prty1_bb_b0_attn_idx, 0x1800200, 0x180020c, 0x1800208,
7618 static struct attn_hw_reg *msem_prty_bb_b0_regs[2] = {
7619 &msem_prty0_bb_b0, &msem_prty1_bb_b0,
7622 static const u16 msem_prty0_k2_attn_idx[3] = {
7626 static struct attn_hw_reg msem_prty0_k2 = {
7627 0, 3, msem_prty0_k2_attn_idx, 0x18000c8, 0x18000d4, 0x18000d0,
7631 static const u16 msem_prty1_k2_attn_idx[6] = {
7635 static struct attn_hw_reg msem_prty1_k2 = {
7636 1, 6, msem_prty1_k2_attn_idx, 0x1800200, 0x180020c, 0x1800208,
7640 static const u16 msem_fast_memory_prty1_k2_attn_idx[7] = {
7641 9, 10, 11, 12, 13, 14, 15,
7644 static struct attn_hw_reg msem_fast_memory_prty1_k2 = {
7645 2, 7, msem_fast_memory_prty1_k2_attn_idx, 0x1840200, 0x184020c,
7650 static struct attn_hw_reg *msem_prty_k2_regs[3] = {
7651 &msem_prty0_k2, &msem_prty1_k2, &msem_fast_memory_prty1_k2,
7655 static const char *usem_int_attn_desc[46] = {
7656 "usem_address_error",
7657 "usem_fic_last_error",
7658 "usem_fic_length_error",
7659 "usem_fic_fifo_error",
7660 "usem_pas_buf_fifo_error",
7661 "usem_sync_fin_pop_error",
7662 "usem_sync_dra_wr_push_error",
7663 "usem_sync_dra_wr_pop_error",
7664 "usem_sync_dra_rd_push_error",
7665 "usem_sync_dra_rd_pop_error",
7666 "usem_sync_fin_push_error",
7667 "usem_sem_fast_address_error",
7668 "usem_cam_lsb_inp_fifo",
7669 "usem_cam_msb_inp_fifo",
7670 "usem_cam_out_fifo",
7672 "usem_thread_fifo_error",
7673 "usem_thread_overrun",
7674 "usem_sync_ext_store_push_error",
7675 "usem_sync_ext_store_pop_error",
7676 "usem_sync_ext_load_push_error",
7677 "usem_sync_ext_load_pop_error",
7678 "usem_sync_ram_rd_push_error",
7679 "usem_sync_ram_rd_pop_error",
7680 "usem_sync_ram_wr_pop_error",
7681 "usem_sync_ram_wr_push_error",
7682 "usem_sync_dbg_push_error",
7683 "usem_sync_dbg_pop_error",
7684 "usem_dbg_fifo_error",
7685 "usem_cam_msb2_inp_fifo",
7686 "usem_vfc_interrupt",
7687 "usem_vfc_out_fifo_error",
7688 "usem_storm_stack_uf_attn",
7689 "usem_storm_stack_of_attn",
7690 "usem_storm_runtime_error",
7691 "usem_ext_load_pend_wr_error",
7692 "usem_thread_rls_orun_error",
7693 "usem_thread_rls_aloc_error",
7694 "usem_thread_rls_vld_error",
7695 "usem_ext_thread_oor_error",
7696 "usem_ord_id_fifo_error",
7697 "usem_invld_foc_error",
7698 "usem_ext_ld_len_error",
7699 "usem_thrd_ord_fifo_error",
7700 "usem_invld_thrd_ord_error",
7701 "usem_fast_memory_address_error",
7704 #define usem_int_attn_desc OSAL_NULL
7707 static const u16 usem_int0_bb_a0_attn_idx[32] = {
7708 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7710 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
7713 static struct attn_hw_reg usem_int0_bb_a0 = {
7714 0, 32, usem_int0_bb_a0_attn_idx, 0x1900040, 0x190004c, 0x1900048,
7718 static const u16 usem_int1_bb_a0_attn_idx[13] = {
7719 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
7722 static struct attn_hw_reg usem_int1_bb_a0 = {
7723 1, 13, usem_int1_bb_a0_attn_idx, 0x1900050, 0x190005c, 0x1900058,
7727 static const u16 usem_fast_memory_int0_bb_a0_attn_idx[1] = {
7731 static struct attn_hw_reg usem_fast_memory_int0_bb_a0 = {
7732 2, 1, usem_fast_memory_int0_bb_a0_attn_idx, 0x1940040, 0x194004c,
7733 0x1940048, 0x1940044
7736 static struct attn_hw_reg *usem_int_bb_a0_regs[3] = {
7737 &usem_int0_bb_a0, &usem_int1_bb_a0, &usem_fast_memory_int0_bb_a0,
7740 static const u16 usem_int0_bb_b0_attn_idx[32] = {
7741 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7743 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
7746 static struct attn_hw_reg usem_int0_bb_b0 = {
7747 0, 32, usem_int0_bb_b0_attn_idx, 0x1900040, 0x190004c, 0x1900048,
7751 static const u16 usem_int1_bb_b0_attn_idx[13] = {
7752 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
7755 static struct attn_hw_reg usem_int1_bb_b0 = {
7756 1, 13, usem_int1_bb_b0_attn_idx, 0x1900050, 0x190005c, 0x1900058,
7760 static const u16 usem_fast_memory_int0_bb_b0_attn_idx[1] = {
7764 static struct attn_hw_reg usem_fast_memory_int0_bb_b0 = {
7765 2, 1, usem_fast_memory_int0_bb_b0_attn_idx, 0x1940040, 0x194004c,
7766 0x1940048, 0x1940044
7769 static struct attn_hw_reg *usem_int_bb_b0_regs[3] = {
7770 &usem_int0_bb_b0, &usem_int1_bb_b0, &usem_fast_memory_int0_bb_b0,
7773 static const u16 usem_int0_k2_attn_idx[32] = {
7774 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7776 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
7779 static struct attn_hw_reg usem_int0_k2 = {
7780 0, 32, usem_int0_k2_attn_idx, 0x1900040, 0x190004c, 0x1900048,
7784 static const u16 usem_int1_k2_attn_idx[13] = {
7785 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
7788 static struct attn_hw_reg usem_int1_k2 = {
7789 1, 13, usem_int1_k2_attn_idx, 0x1900050, 0x190005c, 0x1900058,
7793 static const u16 usem_fast_memory_int0_k2_attn_idx[1] = {
7797 static struct attn_hw_reg usem_fast_memory_int0_k2 = {
7798 2, 1, usem_fast_memory_int0_k2_attn_idx, 0x1940040, 0x194004c,
7803 static struct attn_hw_reg *usem_int_k2_regs[3] = {
7804 &usem_int0_k2, &usem_int1_k2, &usem_fast_memory_int0_k2,
7808 static const char *usem_prty_attn_desc[23] = {
7809 "usem_vfc_rbc_parity_error",
7810 "usem_storm_rf_parity_error",
7811 "usem_reg_gen_parity_error",
7812 "usem_mem005_i_ecc_0_rf_int",
7813 "usem_mem005_i_ecc_1_rf_int",
7814 "usem_mem004_i_mem_prty",
7815 "usem_mem002_i_mem_prty",
7816 "usem_mem003_i_mem_prty",
7817 "usem_mem001_i_mem_prty",
7818 "usem_fast_memory_mem024_i_mem_prty",
7819 "usem_fast_memory_mem023_i_mem_prty",
7820 "usem_fast_memory_mem022_i_mem_prty",
7821 "usem_fast_memory_mem021_i_mem_prty",
7822 "usem_fast_memory_mem020_i_mem_prty",
7823 "usem_fast_memory_mem019_i_mem_prty",
7824 "usem_fast_memory_mem018_i_mem_prty",
7825 "usem_fast_memory_vfc_config_mem005_i_ecc_rf_int",
7826 "usem_fast_memory_vfc_config_mem002_i_ecc_rf_int",
7827 "usem_fast_memory_vfc_config_mem006_i_mem_prty",
7828 "usem_fast_memory_vfc_config_mem001_i_mem_prty",
7829 "usem_fast_memory_vfc_config_mem004_i_mem_prty",
7830 "usem_fast_memory_vfc_config_mem003_i_mem_prty",
7831 "usem_fast_memory_vfc_config_mem007_i_mem_prty",
7834 #define usem_prty_attn_desc OSAL_NULL
7837 static const u16 usem_prty0_bb_a0_attn_idx[3] = {
7841 static struct attn_hw_reg usem_prty0_bb_a0 = {
7842 0, 3, usem_prty0_bb_a0_attn_idx, 0x19000c8, 0x19000d4, 0x19000d0,
7846 static const u16 usem_prty1_bb_a0_attn_idx[6] = {
7850 static struct attn_hw_reg usem_prty1_bb_a0 = {
7851 1, 6, usem_prty1_bb_a0_attn_idx, 0x1900200, 0x190020c, 0x1900208,
7855 static struct attn_hw_reg *usem_prty_bb_a0_regs[2] = {
7856 &usem_prty0_bb_a0, &usem_prty1_bb_a0,
7859 static const u16 usem_prty0_bb_b0_attn_idx[3] = {
7863 static struct attn_hw_reg usem_prty0_bb_b0 = {
7864 0, 3, usem_prty0_bb_b0_attn_idx, 0x19000c8, 0x19000d4, 0x19000d0,
7868 static const u16 usem_prty1_bb_b0_attn_idx[6] = {
7872 static struct attn_hw_reg usem_prty1_bb_b0 = {
7873 1, 6, usem_prty1_bb_b0_attn_idx, 0x1900200, 0x190020c, 0x1900208,
7877 static struct attn_hw_reg *usem_prty_bb_b0_regs[2] = {
7878 &usem_prty0_bb_b0, &usem_prty1_bb_b0,
7881 static const u16 usem_prty0_k2_attn_idx[3] = {
7885 static struct attn_hw_reg usem_prty0_k2 = {
7886 0, 3, usem_prty0_k2_attn_idx, 0x19000c8, 0x19000d4, 0x19000d0,
7890 static const u16 usem_prty1_k2_attn_idx[6] = {
7894 static struct attn_hw_reg usem_prty1_k2 = {
7895 1, 6, usem_prty1_k2_attn_idx, 0x1900200, 0x190020c, 0x1900208,
7899 static const u16 usem_fast_memory_prty1_k2_attn_idx[7] = {
7900 9, 10, 11, 12, 13, 14, 15,
7903 static struct attn_hw_reg usem_fast_memory_prty1_k2 = {
7904 2, 7, usem_fast_memory_prty1_k2_attn_idx, 0x1940200, 0x194020c,
7909 static struct attn_hw_reg *usem_prty_k2_regs[3] = {
7910 &usem_prty0_k2, &usem_prty1_k2, &usem_fast_memory_prty1_k2,
7914 static const char *xsem_int_attn_desc[46] = {
7915 "xsem_address_error",
7916 "xsem_fic_last_error",
7917 "xsem_fic_length_error",
7918 "xsem_fic_fifo_error",
7919 "xsem_pas_buf_fifo_error",
7920 "xsem_sync_fin_pop_error",
7921 "xsem_sync_dra_wr_push_error",
7922 "xsem_sync_dra_wr_pop_error",
7923 "xsem_sync_dra_rd_push_error",
7924 "xsem_sync_dra_rd_pop_error",
7925 "xsem_sync_fin_push_error",
7926 "xsem_sem_fast_address_error",
7927 "xsem_cam_lsb_inp_fifo",
7928 "xsem_cam_msb_inp_fifo",
7929 "xsem_cam_out_fifo",
7931 "xsem_thread_fifo_error",
7932 "xsem_thread_overrun",
7933 "xsem_sync_ext_store_push_error",
7934 "xsem_sync_ext_store_pop_error",
7935 "xsem_sync_ext_load_push_error",
7936 "xsem_sync_ext_load_pop_error",
7937 "xsem_sync_ram_rd_push_error",
7938 "xsem_sync_ram_rd_pop_error",
7939 "xsem_sync_ram_wr_pop_error",
7940 "xsem_sync_ram_wr_push_error",
7941 "xsem_sync_dbg_push_error",
7942 "xsem_sync_dbg_pop_error",
7943 "xsem_dbg_fifo_error",
7944 "xsem_cam_msb2_inp_fifo",
7945 "xsem_vfc_interrupt",
7946 "xsem_vfc_out_fifo_error",
7947 "xsem_storm_stack_uf_attn",
7948 "xsem_storm_stack_of_attn",
7949 "xsem_storm_runtime_error",
7950 "xsem_ext_load_pend_wr_error",
7951 "xsem_thread_rls_orun_error",
7952 "xsem_thread_rls_aloc_error",
7953 "xsem_thread_rls_vld_error",
7954 "xsem_ext_thread_oor_error",
7955 "xsem_ord_id_fifo_error",
7956 "xsem_invld_foc_error",
7957 "xsem_ext_ld_len_error",
7958 "xsem_thrd_ord_fifo_error",
7959 "xsem_invld_thrd_ord_error",
7960 "xsem_fast_memory_address_error",
7963 #define xsem_int_attn_desc OSAL_NULL
7966 static const u16 xsem_int0_bb_a0_attn_idx[32] = {
7967 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
7969 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
7972 static struct attn_hw_reg xsem_int0_bb_a0 = {
7973 0, 32, xsem_int0_bb_a0_attn_idx, 0x1400040, 0x140004c, 0x1400048,
7977 static const u16 xsem_int1_bb_a0_attn_idx[13] = {
7978 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
7981 static struct attn_hw_reg xsem_int1_bb_a0 = {
7982 1, 13, xsem_int1_bb_a0_attn_idx, 0x1400050, 0x140005c, 0x1400058,
7986 static const u16 xsem_fast_memory_int0_bb_a0_attn_idx[1] = {
7990 static struct attn_hw_reg xsem_fast_memory_int0_bb_a0 = {
7991 2, 1, xsem_fast_memory_int0_bb_a0_attn_idx, 0x1440040, 0x144004c,
7992 0x1440048, 0x1440044
7995 static struct attn_hw_reg *xsem_int_bb_a0_regs[3] = {
7996 &xsem_int0_bb_a0, &xsem_int1_bb_a0, &xsem_fast_memory_int0_bb_a0,
7999 static const u16 xsem_int0_bb_b0_attn_idx[32] = {
8000 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
8002 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
8005 static struct attn_hw_reg xsem_int0_bb_b0 = {
8006 0, 32, xsem_int0_bb_b0_attn_idx, 0x1400040, 0x140004c, 0x1400048,
8010 static const u16 xsem_int1_bb_b0_attn_idx[13] = {
8011 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
8014 static struct attn_hw_reg xsem_int1_bb_b0 = {
8015 1, 13, xsem_int1_bb_b0_attn_idx, 0x1400050, 0x140005c, 0x1400058,
8019 static const u16 xsem_fast_memory_int0_bb_b0_attn_idx[1] = {
8023 static struct attn_hw_reg xsem_fast_memory_int0_bb_b0 = {
8024 2, 1, xsem_fast_memory_int0_bb_b0_attn_idx, 0x1440040, 0x144004c,
8025 0x1440048, 0x1440044
8028 static struct attn_hw_reg *xsem_int_bb_b0_regs[3] = {
8029 &xsem_int0_bb_b0, &xsem_int1_bb_b0, &xsem_fast_memory_int0_bb_b0,
8032 static const u16 xsem_int0_k2_attn_idx[32] = {
8033 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
8035 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
8038 static struct attn_hw_reg xsem_int0_k2 = {
8039 0, 32, xsem_int0_k2_attn_idx, 0x1400040, 0x140004c, 0x1400048,
8043 static const u16 xsem_int1_k2_attn_idx[13] = {
8044 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
8047 static struct attn_hw_reg xsem_int1_k2 = {
8048 1, 13, xsem_int1_k2_attn_idx, 0x1400050, 0x140005c, 0x1400058,
8052 static const u16 xsem_fast_memory_int0_k2_attn_idx[1] = {
8056 static struct attn_hw_reg xsem_fast_memory_int0_k2 = {
8057 2, 1, xsem_fast_memory_int0_k2_attn_idx, 0x1440040, 0x144004c,
8062 static struct attn_hw_reg *xsem_int_k2_regs[3] = {
8063 &xsem_int0_k2, &xsem_int1_k2, &xsem_fast_memory_int0_k2,
8067 static const char *xsem_prty_attn_desc[24] = {
8068 "xsem_vfc_rbc_parity_error",
8069 "xsem_storm_rf_parity_error",
8070 "xsem_reg_gen_parity_error",
8071 "xsem_mem006_i_ecc_0_rf_int",
8072 "xsem_mem006_i_ecc_1_rf_int",
8073 "xsem_mem005_i_mem_prty",
8074 "xsem_mem002_i_mem_prty",
8075 "xsem_mem004_i_mem_prty",
8076 "xsem_mem003_i_mem_prty",
8077 "xsem_mem001_i_mem_prty",
8078 "xsem_fast_memory_mem024_i_mem_prty",
8079 "xsem_fast_memory_mem023_i_mem_prty",
8080 "xsem_fast_memory_mem022_i_mem_prty",
8081 "xsem_fast_memory_mem021_i_mem_prty",
8082 "xsem_fast_memory_mem020_i_mem_prty",
8083 "xsem_fast_memory_mem019_i_mem_prty",
8084 "xsem_fast_memory_mem018_i_mem_prty",
8085 "xsem_fast_memory_vfc_config_mem005_i_ecc_rf_int",
8086 "xsem_fast_memory_vfc_config_mem002_i_ecc_rf_int",
8087 "xsem_fast_memory_vfc_config_mem006_i_mem_prty",
8088 "xsem_fast_memory_vfc_config_mem001_i_mem_prty",
8089 "xsem_fast_memory_vfc_config_mem004_i_mem_prty",
8090 "xsem_fast_memory_vfc_config_mem003_i_mem_prty",
8091 "xsem_fast_memory_vfc_config_mem007_i_mem_prty",
8094 #define xsem_prty_attn_desc OSAL_NULL
8097 static const u16 xsem_prty0_bb_a0_attn_idx[3] = {
8101 static struct attn_hw_reg xsem_prty0_bb_a0 = {
8102 0, 3, xsem_prty0_bb_a0_attn_idx, 0x14000c8, 0x14000d4, 0x14000d0,
8106 static const u16 xsem_prty1_bb_a0_attn_idx[7] = {
8107 3, 4, 5, 6, 7, 8, 9,
8110 static struct attn_hw_reg xsem_prty1_bb_a0 = {
8111 1, 7, xsem_prty1_bb_a0_attn_idx, 0x1400200, 0x140020c, 0x1400208,
8115 static struct attn_hw_reg *xsem_prty_bb_a0_regs[2] = {
8116 &xsem_prty0_bb_a0, &xsem_prty1_bb_a0,
8119 static const u16 xsem_prty0_bb_b0_attn_idx[3] = {
8123 static struct attn_hw_reg xsem_prty0_bb_b0 = {
8124 0, 3, xsem_prty0_bb_b0_attn_idx, 0x14000c8, 0x14000d4, 0x14000d0,
8128 static const u16 xsem_prty1_bb_b0_attn_idx[7] = {
8129 3, 4, 5, 6, 7, 8, 9,
8132 static struct attn_hw_reg xsem_prty1_bb_b0 = {
8133 1, 7, xsem_prty1_bb_b0_attn_idx, 0x1400200, 0x140020c, 0x1400208,
8137 static struct attn_hw_reg *xsem_prty_bb_b0_regs[2] = {
8138 &xsem_prty0_bb_b0, &xsem_prty1_bb_b0,
8141 static const u16 xsem_prty0_k2_attn_idx[3] = {
8145 static struct attn_hw_reg xsem_prty0_k2 = {
8146 0, 3, xsem_prty0_k2_attn_idx, 0x14000c8, 0x14000d4, 0x14000d0,
8150 static const u16 xsem_prty1_k2_attn_idx[7] = {
8151 3, 4, 5, 6, 7, 8, 9,
8154 static struct attn_hw_reg xsem_prty1_k2 = {
8155 1, 7, xsem_prty1_k2_attn_idx, 0x1400200, 0x140020c, 0x1400208,
8159 static const u16 xsem_fast_memory_prty1_k2_attn_idx[7] = {
8160 10, 11, 12, 13, 14, 15, 16,
8163 static struct attn_hw_reg xsem_fast_memory_prty1_k2 = {
8164 2, 7, xsem_fast_memory_prty1_k2_attn_idx, 0x1440200, 0x144020c,
8169 static struct attn_hw_reg *xsem_prty_k2_regs[3] = {
8170 &xsem_prty0_k2, &xsem_prty1_k2, &xsem_fast_memory_prty1_k2,
8174 static const char *ysem_int_attn_desc[46] = {
8175 "ysem_address_error",
8176 "ysem_fic_last_error",
8177 "ysem_fic_length_error",
8178 "ysem_fic_fifo_error",
8179 "ysem_pas_buf_fifo_error",
8180 "ysem_sync_fin_pop_error",
8181 "ysem_sync_dra_wr_push_error",
8182 "ysem_sync_dra_wr_pop_error",
8183 "ysem_sync_dra_rd_push_error",
8184 "ysem_sync_dra_rd_pop_error",
8185 "ysem_sync_fin_push_error",
8186 "ysem_sem_fast_address_error",
8187 "ysem_cam_lsb_inp_fifo",
8188 "ysem_cam_msb_inp_fifo",
8189 "ysem_cam_out_fifo",
8191 "ysem_thread_fifo_error",
8192 "ysem_thread_overrun",
8193 "ysem_sync_ext_store_push_error",
8194 "ysem_sync_ext_store_pop_error",
8195 "ysem_sync_ext_load_push_error",
8196 "ysem_sync_ext_load_pop_error",
8197 "ysem_sync_ram_rd_push_error",
8198 "ysem_sync_ram_rd_pop_error",
8199 "ysem_sync_ram_wr_pop_error",
8200 "ysem_sync_ram_wr_push_error",
8201 "ysem_sync_dbg_push_error",
8202 "ysem_sync_dbg_pop_error",
8203 "ysem_dbg_fifo_error",
8204 "ysem_cam_msb2_inp_fifo",
8205 "ysem_vfc_interrupt",
8206 "ysem_vfc_out_fifo_error",
8207 "ysem_storm_stack_uf_attn",
8208 "ysem_storm_stack_of_attn",
8209 "ysem_storm_runtime_error",
8210 "ysem_ext_load_pend_wr_error",
8211 "ysem_thread_rls_orun_error",
8212 "ysem_thread_rls_aloc_error",
8213 "ysem_thread_rls_vld_error",
8214 "ysem_ext_thread_oor_error",
8215 "ysem_ord_id_fifo_error",
8216 "ysem_invld_foc_error",
8217 "ysem_ext_ld_len_error",
8218 "ysem_thrd_ord_fifo_error",
8219 "ysem_invld_thrd_ord_error",
8220 "ysem_fast_memory_address_error",
8223 #define ysem_int_attn_desc OSAL_NULL
8226 static const u16 ysem_int0_bb_a0_attn_idx[32] = {
8227 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
8229 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
8232 static struct attn_hw_reg ysem_int0_bb_a0 = {
8233 0, 32, ysem_int0_bb_a0_attn_idx, 0x1500040, 0x150004c, 0x1500048,
8237 static const u16 ysem_int1_bb_a0_attn_idx[13] = {
8238 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
8241 static struct attn_hw_reg ysem_int1_bb_a0 = {
8242 1, 13, ysem_int1_bb_a0_attn_idx, 0x1500050, 0x150005c, 0x1500058,
8246 static const u16 ysem_fast_memory_int0_bb_a0_attn_idx[1] = {
8250 static struct attn_hw_reg ysem_fast_memory_int0_bb_a0 = {
8251 2, 1, ysem_fast_memory_int0_bb_a0_attn_idx, 0x1540040, 0x154004c,
8252 0x1540048, 0x1540044
8255 static struct attn_hw_reg *ysem_int_bb_a0_regs[3] = {
8256 &ysem_int0_bb_a0, &ysem_int1_bb_a0, &ysem_fast_memory_int0_bb_a0,
8259 static const u16 ysem_int0_bb_b0_attn_idx[32] = {
8260 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
8262 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
8265 static struct attn_hw_reg ysem_int0_bb_b0 = {
8266 0, 32, ysem_int0_bb_b0_attn_idx, 0x1500040, 0x150004c, 0x1500048,
8270 static const u16 ysem_int1_bb_b0_attn_idx[13] = {
8271 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
8274 static struct attn_hw_reg ysem_int1_bb_b0 = {
8275 1, 13, ysem_int1_bb_b0_attn_idx, 0x1500050, 0x150005c, 0x1500058,
8279 static const u16 ysem_fast_memory_int0_bb_b0_attn_idx[1] = {
8283 static struct attn_hw_reg ysem_fast_memory_int0_bb_b0 = {
8284 2, 1, ysem_fast_memory_int0_bb_b0_attn_idx, 0x1540040, 0x154004c,
8285 0x1540048, 0x1540044
8288 static struct attn_hw_reg *ysem_int_bb_b0_regs[3] = {
8289 &ysem_int0_bb_b0, &ysem_int1_bb_b0, &ysem_fast_memory_int0_bb_b0,
8292 static const u16 ysem_int0_k2_attn_idx[32] = {
8293 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
8295 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
8298 static struct attn_hw_reg ysem_int0_k2 = {
8299 0, 32, ysem_int0_k2_attn_idx, 0x1500040, 0x150004c, 0x1500048,
8303 static const u16 ysem_int1_k2_attn_idx[13] = {
8304 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
8307 static struct attn_hw_reg ysem_int1_k2 = {
8308 1, 13, ysem_int1_k2_attn_idx, 0x1500050, 0x150005c, 0x1500058,
8312 static const u16 ysem_fast_memory_int0_k2_attn_idx[1] = {
8316 static struct attn_hw_reg ysem_fast_memory_int0_k2 = {
8317 2, 1, ysem_fast_memory_int0_k2_attn_idx, 0x1540040, 0x154004c,
8322 static struct attn_hw_reg *ysem_int_k2_regs[3] = {
8323 &ysem_int0_k2, &ysem_int1_k2, &ysem_fast_memory_int0_k2,
8327 static const char *ysem_prty_attn_desc[24] = {
8328 "ysem_vfc_rbc_parity_error",
8329 "ysem_storm_rf_parity_error",
8330 "ysem_reg_gen_parity_error",
8331 "ysem_mem006_i_ecc_0_rf_int",
8332 "ysem_mem006_i_ecc_1_rf_int",
8333 "ysem_mem005_i_mem_prty",
8334 "ysem_mem002_i_mem_prty",
8335 "ysem_mem004_i_mem_prty",
8336 "ysem_mem003_i_mem_prty",
8337 "ysem_mem001_i_mem_prty",
8338 "ysem_fast_memory_mem024_i_mem_prty",
8339 "ysem_fast_memory_mem023_i_mem_prty",
8340 "ysem_fast_memory_mem022_i_mem_prty",
8341 "ysem_fast_memory_mem021_i_mem_prty",
8342 "ysem_fast_memory_mem020_i_mem_prty",
8343 "ysem_fast_memory_mem019_i_mem_prty",
8344 "ysem_fast_memory_mem018_i_mem_prty",
8345 "ysem_fast_memory_vfc_config_mem005_i_ecc_rf_int",
8346 "ysem_fast_memory_vfc_config_mem002_i_ecc_rf_int",
8347 "ysem_fast_memory_vfc_config_mem006_i_mem_prty",
8348 "ysem_fast_memory_vfc_config_mem001_i_mem_prty",
8349 "ysem_fast_memory_vfc_config_mem004_i_mem_prty",
8350 "ysem_fast_memory_vfc_config_mem003_i_mem_prty",
8351 "ysem_fast_memory_vfc_config_mem007_i_mem_prty",
8354 #define ysem_prty_attn_desc OSAL_NULL
8357 static const u16 ysem_prty0_bb_a0_attn_idx[3] = {
8361 static struct attn_hw_reg ysem_prty0_bb_a0 = {
8362 0, 3, ysem_prty0_bb_a0_attn_idx, 0x15000c8, 0x15000d4, 0x15000d0,
8366 static const u16 ysem_prty1_bb_a0_attn_idx[7] = {
8367 3, 4, 5, 6, 7, 8, 9,
8370 static struct attn_hw_reg ysem_prty1_bb_a0 = {
8371 1, 7, ysem_prty1_bb_a0_attn_idx, 0x1500200, 0x150020c, 0x1500208,
8375 static struct attn_hw_reg *ysem_prty_bb_a0_regs[2] = {
8376 &ysem_prty0_bb_a0, &ysem_prty1_bb_a0,
8379 static const u16 ysem_prty0_bb_b0_attn_idx[3] = {
8383 static struct attn_hw_reg ysem_prty0_bb_b0 = {
8384 0, 3, ysem_prty0_bb_b0_attn_idx, 0x15000c8, 0x15000d4, 0x15000d0,
8388 static const u16 ysem_prty1_bb_b0_attn_idx[7] = {
8389 3, 4, 5, 6, 7, 8, 9,
8392 static struct attn_hw_reg ysem_prty1_bb_b0 = {
8393 1, 7, ysem_prty1_bb_b0_attn_idx, 0x1500200, 0x150020c, 0x1500208,
8397 static struct attn_hw_reg *ysem_prty_bb_b0_regs[2] = {
8398 &ysem_prty0_bb_b0, &ysem_prty1_bb_b0,
8401 static const u16 ysem_prty0_k2_attn_idx[3] = {
8405 static struct attn_hw_reg ysem_prty0_k2 = {
8406 0, 3, ysem_prty0_k2_attn_idx, 0x15000c8, 0x15000d4, 0x15000d0,
8410 static const u16 ysem_prty1_k2_attn_idx[7] = {
8411 3, 4, 5, 6, 7, 8, 9,
8414 static struct attn_hw_reg ysem_prty1_k2 = {
8415 1, 7, ysem_prty1_k2_attn_idx, 0x1500200, 0x150020c, 0x1500208,
8419 static const u16 ysem_fast_memory_prty1_k2_attn_idx[7] = {
8420 10, 11, 12, 13, 14, 15, 16,
8423 static struct attn_hw_reg ysem_fast_memory_prty1_k2 = {
8424 2, 7, ysem_fast_memory_prty1_k2_attn_idx, 0x1540200, 0x154020c,
8429 static struct attn_hw_reg *ysem_prty_k2_regs[3] = {
8430 &ysem_prty0_k2, &ysem_prty1_k2, &ysem_fast_memory_prty1_k2,
8434 static const char *psem_int_attn_desc[46] = {
8435 "psem_address_error",
8436 "psem_fic_last_error",
8437 "psem_fic_length_error",
8438 "psem_fic_fifo_error",
8439 "psem_pas_buf_fifo_error",
8440 "psem_sync_fin_pop_error",
8441 "psem_sync_dra_wr_push_error",
8442 "psem_sync_dra_wr_pop_error",
8443 "psem_sync_dra_rd_push_error",
8444 "psem_sync_dra_rd_pop_error",
8445 "psem_sync_fin_push_error",
8446 "psem_sem_fast_address_error",
8447 "psem_cam_lsb_inp_fifo",
8448 "psem_cam_msb_inp_fifo",
8449 "psem_cam_out_fifo",
8451 "psem_thread_fifo_error",
8452 "psem_thread_overrun",
8453 "psem_sync_ext_store_push_error",
8454 "psem_sync_ext_store_pop_error",
8455 "psem_sync_ext_load_push_error",
8456 "psem_sync_ext_load_pop_error",
8457 "psem_sync_ram_rd_push_error",
8458 "psem_sync_ram_rd_pop_error",
8459 "psem_sync_ram_wr_pop_error",
8460 "psem_sync_ram_wr_push_error",
8461 "psem_sync_dbg_push_error",
8462 "psem_sync_dbg_pop_error",
8463 "psem_dbg_fifo_error",
8464 "psem_cam_msb2_inp_fifo",
8465 "psem_vfc_interrupt",
8466 "psem_vfc_out_fifo_error",
8467 "psem_storm_stack_uf_attn",
8468 "psem_storm_stack_of_attn",
8469 "psem_storm_runtime_error",
8470 "psem_ext_load_pend_wr_error",
8471 "psem_thread_rls_orun_error",
8472 "psem_thread_rls_aloc_error",
8473 "psem_thread_rls_vld_error",
8474 "psem_ext_thread_oor_error",
8475 "psem_ord_id_fifo_error",
8476 "psem_invld_foc_error",
8477 "psem_ext_ld_len_error",
8478 "psem_thrd_ord_fifo_error",
8479 "psem_invld_thrd_ord_error",
8480 "psem_fast_memory_address_error",
8483 #define psem_int_attn_desc OSAL_NULL
8486 static const u16 psem_int0_bb_a0_attn_idx[32] = {
8487 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
8489 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
8492 static struct attn_hw_reg psem_int0_bb_a0 = {
8493 0, 32, psem_int0_bb_a0_attn_idx, 0x1600040, 0x160004c, 0x1600048,
8497 static const u16 psem_int1_bb_a0_attn_idx[13] = {
8498 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
8501 static struct attn_hw_reg psem_int1_bb_a0 = {
8502 1, 13, psem_int1_bb_a0_attn_idx, 0x1600050, 0x160005c, 0x1600058,
8506 static const u16 psem_fast_memory_int0_bb_a0_attn_idx[1] = {
8510 static struct attn_hw_reg psem_fast_memory_int0_bb_a0 = {
8511 2, 1, psem_fast_memory_int0_bb_a0_attn_idx, 0x1640040, 0x164004c,
8512 0x1640048, 0x1640044
8515 static struct attn_hw_reg *psem_int_bb_a0_regs[3] = {
8516 &psem_int0_bb_a0, &psem_int1_bb_a0, &psem_fast_memory_int0_bb_a0,
8519 static const u16 psem_int0_bb_b0_attn_idx[32] = {
8520 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
8522 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
8525 static struct attn_hw_reg psem_int0_bb_b0 = {
8526 0, 32, psem_int0_bb_b0_attn_idx, 0x1600040, 0x160004c, 0x1600048,
8530 static const u16 psem_int1_bb_b0_attn_idx[13] = {
8531 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
8534 static struct attn_hw_reg psem_int1_bb_b0 = {
8535 1, 13, psem_int1_bb_b0_attn_idx, 0x1600050, 0x160005c, 0x1600058,
8539 static const u16 psem_fast_memory_int0_bb_b0_attn_idx[1] = {
8543 static struct attn_hw_reg psem_fast_memory_int0_bb_b0 = {
8544 2, 1, psem_fast_memory_int0_bb_b0_attn_idx, 0x1640040, 0x164004c,
8545 0x1640048, 0x1640044
8548 static struct attn_hw_reg *psem_int_bb_b0_regs[3] = {
8549 &psem_int0_bb_b0, &psem_int1_bb_b0, &psem_fast_memory_int0_bb_b0,
8552 static const u16 psem_int0_k2_attn_idx[32] = {
8553 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
8555 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
8558 static struct attn_hw_reg psem_int0_k2 = {
8559 0, 32, psem_int0_k2_attn_idx, 0x1600040, 0x160004c, 0x1600048,
8563 static const u16 psem_int1_k2_attn_idx[13] = {
8564 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
8567 static struct attn_hw_reg psem_int1_k2 = {
8568 1, 13, psem_int1_k2_attn_idx, 0x1600050, 0x160005c, 0x1600058,
8572 static const u16 psem_fast_memory_int0_k2_attn_idx[1] = {
8576 static struct attn_hw_reg psem_fast_memory_int0_k2 = {
8577 2, 1, psem_fast_memory_int0_k2_attn_idx, 0x1640040, 0x164004c,
8582 static struct attn_hw_reg *psem_int_k2_regs[3] = {
8583 &psem_int0_k2, &psem_int1_k2, &psem_fast_memory_int0_k2,
8587 static const char *psem_prty_attn_desc[23] = {
8588 "psem_vfc_rbc_parity_error",
8589 "psem_storm_rf_parity_error",
8590 "psem_reg_gen_parity_error",
8591 "psem_mem005_i_ecc_0_rf_int",
8592 "psem_mem005_i_ecc_1_rf_int",
8593 "psem_mem004_i_mem_prty",
8594 "psem_mem002_i_mem_prty",
8595 "psem_mem003_i_mem_prty",
8596 "psem_mem001_i_mem_prty",
8597 "psem_fast_memory_mem024_i_mem_prty",
8598 "psem_fast_memory_mem023_i_mem_prty",
8599 "psem_fast_memory_mem022_i_mem_prty",
8600 "psem_fast_memory_mem021_i_mem_prty",
8601 "psem_fast_memory_mem020_i_mem_prty",
8602 "psem_fast_memory_mem019_i_mem_prty",
8603 "psem_fast_memory_mem018_i_mem_prty",
8604 "psem_fast_memory_vfc_config_mem005_i_ecc_rf_int",
8605 "psem_fast_memory_vfc_config_mem002_i_ecc_rf_int",
8606 "psem_fast_memory_vfc_config_mem006_i_mem_prty",
8607 "psem_fast_memory_vfc_config_mem001_i_mem_prty",
8608 "psem_fast_memory_vfc_config_mem004_i_mem_prty",
8609 "psem_fast_memory_vfc_config_mem003_i_mem_prty",
8610 "psem_fast_memory_vfc_config_mem007_i_mem_prty",
8613 #define psem_prty_attn_desc OSAL_NULL
8616 static const u16 psem_prty0_bb_a0_attn_idx[3] = {
8620 static struct attn_hw_reg psem_prty0_bb_a0 = {
8621 0, 3, psem_prty0_bb_a0_attn_idx, 0x16000c8, 0x16000d4, 0x16000d0,
8625 static const u16 psem_prty1_bb_a0_attn_idx[6] = {
8629 static struct attn_hw_reg psem_prty1_bb_a0 = {
8630 1, 6, psem_prty1_bb_a0_attn_idx, 0x1600200, 0x160020c, 0x1600208,
8634 static const u16 psem_fast_memory_vfc_config_prty1_bb_a0_attn_idx[6] = {
8635 16, 17, 19, 20, 21, 22,
8638 static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_bb_a0 = {
8639 2, 6, psem_fast_memory_vfc_config_prty1_bb_a0_attn_idx, 0x164a200,
8640 0x164a20c, 0x164a208, 0x164a204
8643 static struct attn_hw_reg *psem_prty_bb_a0_regs[3] = {
8644 &psem_prty0_bb_a0, &psem_prty1_bb_a0,
8645 &psem_fast_memory_vfc_config_prty1_bb_a0,
8648 static const u16 psem_prty0_bb_b0_attn_idx[3] = {
8652 static struct attn_hw_reg psem_prty0_bb_b0 = {
8653 0, 3, psem_prty0_bb_b0_attn_idx, 0x16000c8, 0x16000d4, 0x16000d0,
8657 static const u16 psem_prty1_bb_b0_attn_idx[6] = {
8661 static struct attn_hw_reg psem_prty1_bb_b0 = {
8662 1, 6, psem_prty1_bb_b0_attn_idx, 0x1600200, 0x160020c, 0x1600208,
8666 static const u16 psem_fast_memory_vfc_config_prty1_bb_b0_attn_idx[6] = {
8667 16, 17, 19, 20, 21, 22,
8670 static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_bb_b0 = {
8671 2, 6, psem_fast_memory_vfc_config_prty1_bb_b0_attn_idx, 0x164a200,
8672 0x164a20c, 0x164a208, 0x164a204
8675 static struct attn_hw_reg *psem_prty_bb_b0_regs[3] = {
8676 &psem_prty0_bb_b0, &psem_prty1_bb_b0,
8677 &psem_fast_memory_vfc_config_prty1_bb_b0,
8680 static const u16 psem_prty0_k2_attn_idx[3] = {
8684 static struct attn_hw_reg psem_prty0_k2 = {
8685 0, 3, psem_prty0_k2_attn_idx, 0x16000c8, 0x16000d4, 0x16000d0,
8689 static const u16 psem_prty1_k2_attn_idx[6] = {
8693 static struct attn_hw_reg psem_prty1_k2 = {
8694 1, 6, psem_prty1_k2_attn_idx, 0x1600200, 0x160020c, 0x1600208,
8698 static const u16 psem_fast_memory_prty1_k2_attn_idx[7] = {
8699 9, 10, 11, 12, 13, 14, 15,
8702 static struct attn_hw_reg psem_fast_memory_prty1_k2 = {
8703 2, 7, psem_fast_memory_prty1_k2_attn_idx, 0x1640200, 0x164020c,
8708 static const u16 psem_fast_memory_vfc_config_prty1_k2_attn_idx[6] = {
8709 16, 17, 18, 19, 20, 21,
8712 static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_k2 = {
8713 3, 6, psem_fast_memory_vfc_config_prty1_k2_attn_idx, 0x164a200,
8715 0x164a208, 0x164a204
8718 static struct attn_hw_reg *psem_prty_k2_regs[4] = {
8719 &psem_prty0_k2, &psem_prty1_k2, &psem_fast_memory_prty1_k2,
8720 &psem_fast_memory_vfc_config_prty1_k2,
8724 static const char *rss_int_attn_desc[12] = {
8725 "rss_address_error",
8726 "rss_msg_inp_cnt_error",
8727 "rss_msg_out_cnt_error",
8728 "rss_inp_state_error",
8729 "rss_out_state_error",
8730 "rss_main_state_error",
8731 "rss_calc_state_error",
8732 "rss_inp_fifo_error",
8733 "rss_cmd_fifo_error",
8734 "rss_msg_fifo_error",
8735 "rss_rsp_fifo_error",
8736 "rss_hdr_fifo_error",
8739 #define rss_int_attn_desc OSAL_NULL
8742 static const u16 rss_int0_bb_a0_attn_idx[12] = {
8743 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
8746 static struct attn_hw_reg rss_int0_bb_a0 = {
8747 0, 12, rss_int0_bb_a0_attn_idx, 0x238980, 0x23898c, 0x238988, 0x238984
8750 static struct attn_hw_reg *rss_int_bb_a0_regs[1] = {
8754 static const u16 rss_int0_bb_b0_attn_idx[12] = {
8755 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
8758 static struct attn_hw_reg rss_int0_bb_b0 = {
8759 0, 12, rss_int0_bb_b0_attn_idx, 0x238980, 0x23898c, 0x238988, 0x238984
8762 static struct attn_hw_reg *rss_int_bb_b0_regs[1] = {
8766 static const u16 rss_int0_k2_attn_idx[12] = {
8767 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
8770 static struct attn_hw_reg rss_int0_k2 = {
8771 0, 12, rss_int0_k2_attn_idx, 0x238980, 0x23898c, 0x238988, 0x238984
8774 static struct attn_hw_reg *rss_int_k2_regs[1] = {
8779 static const char *rss_prty_attn_desc[4] = {
8780 "rss_mem002_i_ecc_rf_int",
8781 "rss_mem001_i_ecc_rf_int",
8782 "rss_mem003_i_mem_prty",
8783 "rss_mem004_i_mem_prty",
8786 #define rss_prty_attn_desc OSAL_NULL
8789 static const u16 rss_prty1_bb_a0_attn_idx[4] = {
8793 static struct attn_hw_reg rss_prty1_bb_a0 = {
8794 0, 4, rss_prty1_bb_a0_attn_idx, 0x238a00, 0x238a0c, 0x238a08, 0x238a04
8797 static struct attn_hw_reg *rss_prty_bb_a0_regs[1] = {
8801 static const u16 rss_prty1_bb_b0_attn_idx[4] = {
8805 static struct attn_hw_reg rss_prty1_bb_b0 = {
8806 0, 4, rss_prty1_bb_b0_attn_idx, 0x238a00, 0x238a0c, 0x238a08, 0x238a04
8809 static struct attn_hw_reg *rss_prty_bb_b0_regs[1] = {
8813 static const u16 rss_prty1_k2_attn_idx[4] = {
8817 static struct attn_hw_reg rss_prty1_k2 = {
8818 0, 4, rss_prty1_k2_attn_idx, 0x238a00, 0x238a0c, 0x238a08, 0x238a04
8821 static struct attn_hw_reg *rss_prty_k2_regs[1] = {
8826 static const char *tmld_int_attn_desc[6] = {
8827 "tmld_address_error",
8829 "tmld_ld_seg_msg_err",
8830 "tmld_ld_tid_mini_cache_err",
8831 "tmld_ld_cid_mini_cache_err",
8832 "tmld_ld_long_message",
8835 #define tmld_int_attn_desc OSAL_NULL
8838 static const u16 tmld_int0_bb_a0_attn_idx[6] = {
8842 static struct attn_hw_reg tmld_int0_bb_a0 = {
8843 0, 6, tmld_int0_bb_a0_attn_idx, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184
8846 static struct attn_hw_reg *tmld_int_bb_a0_regs[1] = {
8850 static const u16 tmld_int0_bb_b0_attn_idx[6] = {
8854 static struct attn_hw_reg tmld_int0_bb_b0 = {
8855 0, 6, tmld_int0_bb_b0_attn_idx, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184
8858 static struct attn_hw_reg *tmld_int_bb_b0_regs[1] = {
8862 static const u16 tmld_int0_k2_attn_idx[6] = {
8866 static struct attn_hw_reg tmld_int0_k2 = {
8867 0, 6, tmld_int0_k2_attn_idx, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184
8870 static struct attn_hw_reg *tmld_int_k2_regs[1] = {
8875 static const char *tmld_prty_attn_desc[8] = {
8876 "tmld_mem006_i_ecc_rf_int",
8877 "tmld_mem002_i_ecc_rf_int",
8878 "tmld_mem003_i_mem_prty",
8879 "tmld_mem004_i_mem_prty",
8880 "tmld_mem007_i_mem_prty",
8881 "tmld_mem008_i_mem_prty",
8882 "tmld_mem005_i_mem_prty",
8883 "tmld_mem001_i_mem_prty",
8886 #define tmld_prty_attn_desc OSAL_NULL
8889 static const u16 tmld_prty1_bb_a0_attn_idx[8] = {
8890 0, 1, 2, 3, 4, 5, 6, 7,
8893 static struct attn_hw_reg tmld_prty1_bb_a0 = {
8894 0, 8, tmld_prty1_bb_a0_attn_idx, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204
8897 static struct attn_hw_reg *tmld_prty_bb_a0_regs[1] = {
8901 static const u16 tmld_prty1_bb_b0_attn_idx[8] = {
8902 0, 1, 2, 3, 4, 5, 6, 7,
8905 static struct attn_hw_reg tmld_prty1_bb_b0 = {
8906 0, 8, tmld_prty1_bb_b0_attn_idx, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204
8909 static struct attn_hw_reg *tmld_prty_bb_b0_regs[1] = {
8913 static const u16 tmld_prty1_k2_attn_idx[8] = {
8914 0, 1, 2, 3, 4, 5, 6, 7,
8917 static struct attn_hw_reg tmld_prty1_k2 = {
8918 0, 8, tmld_prty1_k2_attn_idx, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204
8921 static struct attn_hw_reg *tmld_prty_k2_regs[1] = {
8926 static const char *muld_int_attn_desc[6] = {
8927 "muld_address_error",
8929 "muld_ld_seg_msg_err",
8930 "muld_ld_tid_mini_cache_err",
8931 "muld_ld_cid_mini_cache_err",
8932 "muld_ld_long_message",
8935 #define muld_int_attn_desc OSAL_NULL
8938 static const u16 muld_int0_bb_a0_attn_idx[6] = {
8942 static struct attn_hw_reg muld_int0_bb_a0 = {
8943 0, 6, muld_int0_bb_a0_attn_idx, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184
8946 static struct attn_hw_reg *muld_int_bb_a0_regs[1] = {
8950 static const u16 muld_int0_bb_b0_attn_idx[6] = {
8954 static struct attn_hw_reg muld_int0_bb_b0 = {
8955 0, 6, muld_int0_bb_b0_attn_idx, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184
8958 static struct attn_hw_reg *muld_int_bb_b0_regs[1] = {
8962 static const u16 muld_int0_k2_attn_idx[6] = {
8966 static struct attn_hw_reg muld_int0_k2 = {
8967 0, 6, muld_int0_k2_attn_idx, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184
8970 static struct attn_hw_reg *muld_int_k2_regs[1] = {
8975 static const char *muld_prty_attn_desc[10] = {
8976 "muld_mem005_i_ecc_rf_int",
8977 "muld_mem001_i_ecc_rf_int",
8978 "muld_mem008_i_ecc_rf_int",
8979 "muld_mem007_i_ecc_rf_int",
8980 "muld_mem002_i_mem_prty",
8981 "muld_mem003_i_mem_prty",
8982 "muld_mem009_i_mem_prty",
8983 "muld_mem010_i_mem_prty",
8984 "muld_mem004_i_mem_prty",
8985 "muld_mem006_i_mem_prty",
8988 #define muld_prty_attn_desc OSAL_NULL
8991 static const u16 muld_prty1_bb_a0_attn_idx[10] = {
8992 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
8995 static struct attn_hw_reg muld_prty1_bb_a0 = {
8996 0, 10, muld_prty1_bb_a0_attn_idx, 0x4e0200, 0x4e020c, 0x4e0208,
9000 static struct attn_hw_reg *muld_prty_bb_a0_regs[1] = {
9004 static const u16 muld_prty1_bb_b0_attn_idx[10] = {
9005 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
9008 static struct attn_hw_reg muld_prty1_bb_b0 = {
9009 0, 10, muld_prty1_bb_b0_attn_idx, 0x4e0200, 0x4e020c, 0x4e0208,
9013 static struct attn_hw_reg *muld_prty_bb_b0_regs[1] = {
9017 static const u16 muld_prty1_k2_attn_idx[10] = {
9018 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
9021 static struct attn_hw_reg muld_prty1_k2 = {
9022 0, 10, muld_prty1_k2_attn_idx, 0x4e0200, 0x4e020c, 0x4e0208, 0x4e0204
9025 static struct attn_hw_reg *muld_prty_k2_regs[1] = {
9030 static const char *yuld_int_attn_desc[6] = {
9031 "yuld_address_error",
9033 "yuld_ld_seg_msg_err",
9034 "yuld_ld_tid_mini_cache_err",
9035 "yuld_ld_cid_mini_cache_err",
9036 "yuld_ld_long_message",
9039 #define yuld_int_attn_desc OSAL_NULL
9042 static const u16 yuld_int0_bb_a0_attn_idx[6] = {
9046 static struct attn_hw_reg yuld_int0_bb_a0 = {
9047 0, 6, yuld_int0_bb_a0_attn_idx, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184
9050 static struct attn_hw_reg *yuld_int_bb_a0_regs[1] = {
9054 static const u16 yuld_int0_bb_b0_attn_idx[6] = {
9058 static struct attn_hw_reg yuld_int0_bb_b0 = {
9059 0, 6, yuld_int0_bb_b0_attn_idx, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184
9062 static struct attn_hw_reg *yuld_int_bb_b0_regs[1] = {
9066 static const u16 yuld_int0_k2_attn_idx[6] = {
9070 static struct attn_hw_reg yuld_int0_k2 = {
9071 0, 6, yuld_int0_k2_attn_idx, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184
9074 static struct attn_hw_reg *yuld_int_k2_regs[1] = {
9079 static const char *yuld_prty_attn_desc[6] = {
9080 "yuld_mem001_i_mem_prty",
9081 "yuld_mem002_i_mem_prty",
9082 "yuld_mem005_i_mem_prty",
9083 "yuld_mem006_i_mem_prty",
9084 "yuld_mem004_i_mem_prty",
9085 "yuld_mem003_i_mem_prty",
9088 #define yuld_prty_attn_desc OSAL_NULL
9091 static const u16 yuld_prty1_bb_a0_attn_idx[6] = {
9095 static struct attn_hw_reg yuld_prty1_bb_a0 = {
9096 0, 6, yuld_prty1_bb_a0_attn_idx, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204
9099 static struct attn_hw_reg *yuld_prty_bb_a0_regs[1] = {
9103 static const u16 yuld_prty1_bb_b0_attn_idx[6] = {
9107 static struct attn_hw_reg yuld_prty1_bb_b0 = {
9108 0, 6, yuld_prty1_bb_b0_attn_idx, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204
9111 static struct attn_hw_reg *yuld_prty_bb_b0_regs[1] = {
9115 static const u16 yuld_prty1_k2_attn_idx[6] = {
9119 static struct attn_hw_reg yuld_prty1_k2 = {
9120 0, 6, yuld_prty1_k2_attn_idx, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204
9123 static struct attn_hw_reg *yuld_prty_k2_regs[1] = {
9128 static const char *xyld_int_attn_desc[6] = {
9129 "xyld_address_error",
9131 "xyld_ld_seg_msg_err",
9132 "xyld_ld_tid_mini_cache_err",
9133 "xyld_ld_cid_mini_cache_err",
9134 "xyld_ld_long_message",
9137 #define xyld_int_attn_desc OSAL_NULL
9140 static const u16 xyld_int0_bb_a0_attn_idx[6] = {
9144 static struct attn_hw_reg xyld_int0_bb_a0 = {
9145 0, 6, xyld_int0_bb_a0_attn_idx, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184
9148 static struct attn_hw_reg *xyld_int_bb_a0_regs[1] = {
9152 static const u16 xyld_int0_bb_b0_attn_idx[6] = {
9156 static struct attn_hw_reg xyld_int0_bb_b0 = {
9157 0, 6, xyld_int0_bb_b0_attn_idx, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184
9160 static struct attn_hw_reg *xyld_int_bb_b0_regs[1] = {
9164 static const u16 xyld_int0_k2_attn_idx[6] = {
9168 static struct attn_hw_reg xyld_int0_k2 = {
9169 0, 6, xyld_int0_k2_attn_idx, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184
9172 static struct attn_hw_reg *xyld_int_k2_regs[1] = {
9177 static const char *xyld_prty_attn_desc[9] = {
9178 "xyld_mem004_i_ecc_rf_int",
9179 "xyld_mem006_i_ecc_rf_int",
9180 "xyld_mem001_i_mem_prty",
9181 "xyld_mem002_i_mem_prty",
9182 "xyld_mem008_i_mem_prty",
9183 "xyld_mem009_i_mem_prty",
9184 "xyld_mem003_i_mem_prty",
9185 "xyld_mem005_i_mem_prty",
9186 "xyld_mem007_i_mem_prty",
9189 #define xyld_prty_attn_desc OSAL_NULL
9192 static const u16 xyld_prty1_bb_a0_attn_idx[9] = {
9193 0, 1, 2, 3, 4, 5, 6, 7, 8,
9196 static struct attn_hw_reg xyld_prty1_bb_a0 = {
9197 0, 9, xyld_prty1_bb_a0_attn_idx, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204
9200 static struct attn_hw_reg *xyld_prty_bb_a0_regs[1] = {
9204 static const u16 xyld_prty1_bb_b0_attn_idx[9] = {
9205 0, 1, 2, 3, 4, 5, 6, 7, 8,
9208 static struct attn_hw_reg xyld_prty1_bb_b0 = {
9209 0, 9, xyld_prty1_bb_b0_attn_idx, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204
9212 static struct attn_hw_reg *xyld_prty_bb_b0_regs[1] = {
9216 static const u16 xyld_prty1_k2_attn_idx[9] = {
9217 0, 1, 2, 3, 4, 5, 6, 7, 8,
9220 static struct attn_hw_reg xyld_prty1_k2 = {
9221 0, 9, xyld_prty1_k2_attn_idx, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204
9224 static struct attn_hw_reg *xyld_prty_k2_regs[1] = {
9229 static const char *prm_int_attn_desc[11] = {
9230 "prm_address_error",
9232 "prm_immed_fifo_error",
9233 "prm_ofst_pend_error",
9234 "prm_pad_pend_error",
9235 "prm_pbinp_pend_error",
9236 "prm_tag_pend_error",
9237 "prm_mstorm_eop_err",
9238 "prm_ustorm_eop_err",
9239 "prm_mstorm_que_err",
9240 "prm_ustorm_que_err",
9243 #define prm_int_attn_desc OSAL_NULL
9246 static const u16 prm_int0_bb_a0_attn_idx[11] = {
9247 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
9250 static struct attn_hw_reg prm_int0_bb_a0 = {
9251 0, 11, prm_int0_bb_a0_attn_idx, 0x230040, 0x23004c, 0x230048, 0x230044
9254 static struct attn_hw_reg *prm_int_bb_a0_regs[1] = {
9258 static const u16 prm_int0_bb_b0_attn_idx[11] = {
9259 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
9262 static struct attn_hw_reg prm_int0_bb_b0 = {
9263 0, 11, prm_int0_bb_b0_attn_idx, 0x230040, 0x23004c, 0x230048, 0x230044
9266 static struct attn_hw_reg *prm_int_bb_b0_regs[1] = {
9270 static const u16 prm_int0_k2_attn_idx[11] = {
9271 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
9274 static struct attn_hw_reg prm_int0_k2 = {
9275 0, 11, prm_int0_k2_attn_idx, 0x230040, 0x23004c, 0x230048, 0x230044
9278 static struct attn_hw_reg *prm_int_k2_regs[1] = {
9283 static const char *prm_prty_attn_desc[30] = {
9284 "prm_datapath_registers",
9285 "prm_mem012_i_ecc_rf_int",
9286 "prm_mem013_i_ecc_rf_int",
9287 "prm_mem014_i_ecc_rf_int",
9288 "prm_mem020_i_ecc_rf_int",
9289 "prm_mem004_i_mem_prty",
9290 "prm_mem024_i_mem_prty",
9291 "prm_mem016_i_mem_prty",
9292 "prm_mem017_i_mem_prty",
9293 "prm_mem008_i_mem_prty",
9294 "prm_mem009_i_mem_prty",
9295 "prm_mem010_i_mem_prty",
9296 "prm_mem015_i_mem_prty",
9297 "prm_mem011_i_mem_prty",
9298 "prm_mem003_i_mem_prty",
9299 "prm_mem002_i_mem_prty",
9300 "prm_mem005_i_mem_prty",
9301 "prm_mem023_i_mem_prty",
9302 "prm_mem006_i_mem_prty",
9303 "prm_mem007_i_mem_prty",
9304 "prm_mem001_i_mem_prty",
9305 "prm_mem022_i_mem_prty",
9306 "prm_mem021_i_mem_prty",
9307 "prm_mem019_i_mem_prty",
9308 "prm_mem015_i_ecc_rf_int",
9309 "prm_mem021_i_ecc_rf_int",
9310 "prm_mem025_i_mem_prty",
9311 "prm_mem018_i_mem_prty",
9312 "prm_mem012_i_mem_prty",
9313 "prm_mem020_i_mem_prty",
9316 #define prm_prty_attn_desc OSAL_NULL
9319 static const u16 prm_prty1_bb_a0_attn_idx[25] = {
9320 2, 3, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 24,
9324 static struct attn_hw_reg prm_prty1_bb_a0 = {
9325 0, 25, prm_prty1_bb_a0_attn_idx, 0x230200, 0x23020c, 0x230208, 0x230204
9328 static struct attn_hw_reg *prm_prty_bb_a0_regs[1] = {
9332 static const u16 prm_prty0_bb_b0_attn_idx[1] = {
9336 static struct attn_hw_reg prm_prty0_bb_b0 = {
9337 0, 1, prm_prty0_bb_b0_attn_idx, 0x230050, 0x23005c, 0x230058, 0x230054
9340 static const u16 prm_prty1_bb_b0_attn_idx[24] = {
9341 2, 3, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 24, 25,
9345 static struct attn_hw_reg prm_prty1_bb_b0 = {
9346 1, 24, prm_prty1_bb_b0_attn_idx, 0x230200, 0x23020c, 0x230208, 0x230204
9349 static struct attn_hw_reg *prm_prty_bb_b0_regs[2] = {
9350 &prm_prty0_bb_b0, &prm_prty1_bb_b0,
9353 static const u16 prm_prty0_k2_attn_idx[1] = {
9357 static struct attn_hw_reg prm_prty0_k2 = {
9358 0, 1, prm_prty0_k2_attn_idx, 0x230050, 0x23005c, 0x230058, 0x230054
9361 static const u16 prm_prty1_k2_attn_idx[23] = {
9362 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
9367 static struct attn_hw_reg prm_prty1_k2 = {
9368 1, 23, prm_prty1_k2_attn_idx, 0x230200, 0x23020c, 0x230208, 0x230204
9371 static struct attn_hw_reg *prm_prty_k2_regs[2] = {
9372 &prm_prty0_k2, &prm_prty1_k2,
9376 static const char *pbf_pb1_int_attn_desc[9] = {
9377 "pbf_pb1_address_error",
9378 "pbf_pb1_eop_error",
9379 "pbf_pb1_ififo_error",
9380 "pbf_pb1_pfifo_error",
9381 "pbf_pb1_db_buf_error",
9382 "pbf_pb1_th_exec_error",
9383 "pbf_pb1_tq_error_wr",
9384 "pbf_pb1_tq_error_rd_th",
9385 "pbf_pb1_tq_error_rd_ih",
9388 #define pbf_pb1_int_attn_desc OSAL_NULL
9391 static const u16 pbf_pb1_int0_bb_a0_attn_idx[9] = {
9392 0, 1, 2, 3, 4, 5, 6, 7, 8,
9395 static struct attn_hw_reg pbf_pb1_int0_bb_a0 = {
9396 0, 9, pbf_pb1_int0_bb_a0_attn_idx, 0xda0040, 0xda004c, 0xda0048,
9400 static struct attn_hw_reg *pbf_pb1_int_bb_a0_regs[1] = {
9401 &pbf_pb1_int0_bb_a0,
9404 static const u16 pbf_pb1_int0_bb_b0_attn_idx[9] = {
9405 0, 1, 2, 3, 4, 5, 6, 7, 8,
9408 static struct attn_hw_reg pbf_pb1_int0_bb_b0 = {
9409 0, 9, pbf_pb1_int0_bb_b0_attn_idx, 0xda0040, 0xda004c, 0xda0048,
9413 static struct attn_hw_reg *pbf_pb1_int_bb_b0_regs[1] = {
9414 &pbf_pb1_int0_bb_b0,
9417 static const u16 pbf_pb1_int0_k2_attn_idx[9] = {
9418 0, 1, 2, 3, 4, 5, 6, 7, 8,
9421 static struct attn_hw_reg pbf_pb1_int0_k2 = {
9422 0, 9, pbf_pb1_int0_k2_attn_idx, 0xda0040, 0xda004c, 0xda0048, 0xda0044
9425 static struct attn_hw_reg *pbf_pb1_int_k2_regs[1] = {
9430 static const char *pbf_pb1_prty_attn_desc[1] = {
9431 "pbf_pb1_datapath_registers",
9434 #define pbf_pb1_prty_attn_desc OSAL_NULL
9437 static const u16 pbf_pb1_prty0_bb_b0_attn_idx[1] = {
9441 static struct attn_hw_reg pbf_pb1_prty0_bb_b0 = {
9442 0, 1, pbf_pb1_prty0_bb_b0_attn_idx, 0xda0050, 0xda005c, 0xda0058,
9446 static struct attn_hw_reg *pbf_pb1_prty_bb_b0_regs[1] = {
9447 &pbf_pb1_prty0_bb_b0,
9450 static const u16 pbf_pb1_prty0_k2_attn_idx[1] = {
9454 static struct attn_hw_reg pbf_pb1_prty0_k2 = {
9455 0, 1, pbf_pb1_prty0_k2_attn_idx, 0xda0050, 0xda005c, 0xda0058, 0xda0054
9458 static struct attn_hw_reg *pbf_pb1_prty_k2_regs[1] = {
9463 static const char *pbf_pb2_int_attn_desc[9] = {
9464 "pbf_pb2_address_error",
9465 "pbf_pb2_eop_error",
9466 "pbf_pb2_ififo_error",
9467 "pbf_pb2_pfifo_error",
9468 "pbf_pb2_db_buf_error",
9469 "pbf_pb2_th_exec_error",
9470 "pbf_pb2_tq_error_wr",
9471 "pbf_pb2_tq_error_rd_th",
9472 "pbf_pb2_tq_error_rd_ih",
9475 #define pbf_pb2_int_attn_desc OSAL_NULL
9478 static const u16 pbf_pb2_int0_bb_a0_attn_idx[9] = {
9479 0, 1, 2, 3, 4, 5, 6, 7, 8,
9482 static struct attn_hw_reg pbf_pb2_int0_bb_a0 = {
9483 0, 9, pbf_pb2_int0_bb_a0_attn_idx, 0xda4040, 0xda404c, 0xda4048,
9487 static struct attn_hw_reg *pbf_pb2_int_bb_a0_regs[1] = {
9488 &pbf_pb2_int0_bb_a0,
9491 static const u16 pbf_pb2_int0_bb_b0_attn_idx[9] = {
9492 0, 1, 2, 3, 4, 5, 6, 7, 8,
9495 static struct attn_hw_reg pbf_pb2_int0_bb_b0 = {
9496 0, 9, pbf_pb2_int0_bb_b0_attn_idx, 0xda4040, 0xda404c, 0xda4048,
9500 static struct attn_hw_reg *pbf_pb2_int_bb_b0_regs[1] = {
9501 &pbf_pb2_int0_bb_b0,
9504 static const u16 pbf_pb2_int0_k2_attn_idx[9] = {
9505 0, 1, 2, 3, 4, 5, 6, 7, 8,
9508 static struct attn_hw_reg pbf_pb2_int0_k2 = {
9509 0, 9, pbf_pb2_int0_k2_attn_idx, 0xda4040, 0xda404c, 0xda4048, 0xda4044
9512 static struct attn_hw_reg *pbf_pb2_int_k2_regs[1] = {
9517 static const char *pbf_pb2_prty_attn_desc[1] = {
9518 "pbf_pb2_datapath_registers",
9521 #define pbf_pb2_prty_attn_desc OSAL_NULL
9524 static const u16 pbf_pb2_prty0_bb_b0_attn_idx[1] = {
9528 static struct attn_hw_reg pbf_pb2_prty0_bb_b0 = {
9529 0, 1, pbf_pb2_prty0_bb_b0_attn_idx, 0xda4050, 0xda405c, 0xda4058,
9533 static struct attn_hw_reg *pbf_pb2_prty_bb_b0_regs[1] = {
9534 &pbf_pb2_prty0_bb_b0,
9537 static const u16 pbf_pb2_prty0_k2_attn_idx[1] = {
9541 static struct attn_hw_reg pbf_pb2_prty0_k2 = {
9542 0, 1, pbf_pb2_prty0_k2_attn_idx, 0xda4050, 0xda405c, 0xda4058, 0xda4054
9545 static struct attn_hw_reg *pbf_pb2_prty_k2_regs[1] = {
9550 static const char *rpb_int_attn_desc[9] = {
9551 "rpb_address_error",
9556 "rpb_th_exec_error",
9558 "rpb_tq_error_rd_th",
9559 "rpb_tq_error_rd_ih",
9562 #define rpb_int_attn_desc OSAL_NULL
9565 static const u16 rpb_int0_bb_a0_attn_idx[9] = {
9566 0, 1, 2, 3, 4, 5, 6, 7, 8,
9569 static struct attn_hw_reg rpb_int0_bb_a0 = {
9570 0, 9, rpb_int0_bb_a0_attn_idx, 0x23c040, 0x23c04c, 0x23c048, 0x23c044
9573 static struct attn_hw_reg *rpb_int_bb_a0_regs[1] = {
9577 static const u16 rpb_int0_bb_b0_attn_idx[9] = {
9578 0, 1, 2, 3, 4, 5, 6, 7, 8,
9581 static struct attn_hw_reg rpb_int0_bb_b0 = {
9582 0, 9, rpb_int0_bb_b0_attn_idx, 0x23c040, 0x23c04c, 0x23c048, 0x23c044
9585 static struct attn_hw_reg *rpb_int_bb_b0_regs[1] = {
9589 static const u16 rpb_int0_k2_attn_idx[9] = {
9590 0, 1, 2, 3, 4, 5, 6, 7, 8,
9593 static struct attn_hw_reg rpb_int0_k2 = {
9594 0, 9, rpb_int0_k2_attn_idx, 0x23c040, 0x23c04c, 0x23c048, 0x23c044
9597 static struct attn_hw_reg *rpb_int_k2_regs[1] = {
9602 static const char *rpb_prty_attn_desc[1] = {
9603 "rpb_datapath_registers",
9606 #define rpb_prty_attn_desc OSAL_NULL
9609 static const u16 rpb_prty0_bb_b0_attn_idx[1] = {
9613 static struct attn_hw_reg rpb_prty0_bb_b0 = {
9614 0, 1, rpb_prty0_bb_b0_attn_idx, 0x23c050, 0x23c05c, 0x23c058, 0x23c054
9617 static struct attn_hw_reg *rpb_prty_bb_b0_regs[1] = {
9621 static const u16 rpb_prty0_k2_attn_idx[1] = {
9625 static struct attn_hw_reg rpb_prty0_k2 = {
9626 0, 1, rpb_prty0_k2_attn_idx, 0x23c050, 0x23c05c, 0x23c058, 0x23c054
9629 static struct attn_hw_reg *rpb_prty_k2_regs[1] = {
9634 static const char *btb_int_attn_desc[139] = {
9635 "btb_address_error",
9636 "btb_rc_pkt0_rls_error",
9638 "btb_rc_pkt0_len_error",
9640 "btb_rc_pkt0_protocol_error",
9641 "btb_rc_pkt1_rls_error",
9643 "btb_rc_pkt1_len_error",
9645 "btb_rc_pkt1_protocol_error",
9646 "btb_rc_pkt2_rls_error",
9648 "btb_rc_pkt2_len_error",
9650 "btb_rc_pkt2_protocol_error",
9651 "btb_rc_pkt3_rls_error",
9653 "btb_rc_pkt3_len_error",
9655 "btb_rc_pkt3_protocol_error",
9656 "btb_rc_sop_req_tc_port_error",
9658 "btb_wc0_protocol_error",
9661 "btb_ll_arb_calc_error",
9662 "btb_fc_alm_calc_error",
9663 "btb_wc0_inp_fifo_error",
9664 "btb_wc0_sop_fifo_error",
9665 "btb_wc0_len_fifo_error",
9666 "btb_wc0_eop_fifo_error",
9667 "btb_wc0_queue_fifo_error",
9668 "btb_wc0_free_point_fifo_error",
9669 "btb_wc0_next_point_fifo_error",
9670 "btb_wc0_strt_fifo_error",
9671 "btb_wc0_second_dscr_fifo_error",
9672 "btb_wc0_pkt_avail_fifo_error",
9673 "btb_wc0_notify_fifo_error",
9674 "btb_wc0_ll_req_fifo_error",
9675 "btb_wc0_ll_pa_cnt_error",
9676 "btb_wc0_bb_pa_cnt_error",
9677 "btb_wc_dup_upd_data_fifo_error",
9678 "btb_wc_dup_rsp_dscr_fifo_error",
9679 "btb_wc_dup_upd_point_fifo_error",
9680 "btb_wc_dup_pkt_avail_fifo_error",
9681 "btb_wc_dup_pkt_avail_cnt_error",
9682 "btb_rc_pkt0_side_fifo_error",
9683 "btb_rc_pkt0_req_fifo_error",
9684 "btb_rc_pkt0_blk_fifo_error",
9685 "btb_rc_pkt0_rls_left_fifo_error",
9686 "btb_rc_pkt0_strt_ptr_fifo_error",
9687 "btb_rc_pkt0_second_ptr_fifo_error",
9688 "btb_rc_pkt0_rsp_fifo_error",
9689 "btb_rc_pkt0_dscr_fifo_error",
9690 "btb_rc_pkt1_side_fifo_error",
9691 "btb_rc_pkt1_req_fifo_error",
9692 "btb_rc_pkt1_blk_fifo_error",
9693 "btb_rc_pkt1_rls_left_fifo_error",
9694 "btb_rc_pkt1_strt_ptr_fifo_error",
9695 "btb_rc_pkt1_second_ptr_fifo_error",
9696 "btb_rc_pkt1_rsp_fifo_error",
9697 "btb_rc_pkt1_dscr_fifo_error",
9698 "btb_rc_pkt2_side_fifo_error",
9699 "btb_rc_pkt2_req_fifo_error",
9700 "btb_rc_pkt2_blk_fifo_error",
9701 "btb_rc_pkt2_rls_left_fifo_error",
9702 "btb_rc_pkt2_strt_ptr_fifo_error",
9703 "btb_rc_pkt2_second_ptr_fifo_error",
9704 "btb_rc_pkt2_rsp_fifo_error",
9705 "btb_rc_pkt2_dscr_fifo_error",
9706 "btb_rc_pkt3_side_fifo_error",
9707 "btb_rc_pkt3_req_fifo_error",
9708 "btb_rc_pkt3_blk_fifo_error",
9709 "btb_rc_pkt3_rls_left_fifo_error",
9710 "btb_rc_pkt3_strt_ptr_fifo_error",
9711 "btb_rc_pkt3_second_ptr_fifo_error",
9712 "btb_rc_pkt3_rsp_fifo_error",
9713 "btb_rc_pkt3_dscr_fifo_error",
9714 "btb_rc_sop_queue_fifo_error",
9715 "btb_ll_arb_rls_fifo_error",
9716 "btb_ll_arb_prefetch_fifo_error",
9717 "btb_rc_pkt0_rls_fifo_error",
9718 "btb_rc_pkt1_rls_fifo_error",
9719 "btb_rc_pkt2_rls_fifo_error",
9720 "btb_rc_pkt3_rls_fifo_error",
9721 "btb_rc_pkt4_rls_fifo_error",
9722 "btb_rc_pkt5_rls_fifo_error",
9723 "btb_rc_pkt6_rls_fifo_error",
9724 "btb_rc_pkt7_rls_fifo_error",
9725 "btb_rc_pkt4_rls_error",
9726 "btb_rc_pkt4_len_error",
9727 "btb_rc_pkt4_protocol_error",
9728 "btb_rc_pkt4_side_fifo_error",
9729 "btb_rc_pkt4_req_fifo_error",
9730 "btb_rc_pkt4_blk_fifo_error",
9731 "btb_rc_pkt4_rls_left_fifo_error",
9732 "btb_rc_pkt4_strt_ptr_fifo_error",
9733 "btb_rc_pkt4_second_ptr_fifo_error",
9734 "btb_rc_pkt4_rsp_fifo_error",
9735 "btb_rc_pkt4_dscr_fifo_error",
9736 "btb_rc_pkt5_rls_error",
9737 "btb_rc_pkt5_len_error",
9738 "btb_rc_pkt5_protocol_error",
9739 "btb_rc_pkt5_side_fifo_error",
9740 "btb_rc_pkt5_req_fifo_error",
9741 "btb_rc_pkt5_blk_fifo_error",
9742 "btb_rc_pkt5_rls_left_fifo_error",
9743 "btb_rc_pkt5_strt_ptr_fifo_error",
9744 "btb_rc_pkt5_second_ptr_fifo_error",
9745 "btb_rc_pkt5_rsp_fifo_error",
9746 "btb_rc_pkt5_dscr_fifo_error",
9747 "btb_rc_pkt6_rls_error",
9748 "btb_rc_pkt6_len_error",
9749 "btb_rc_pkt6_protocol_error",
9750 "btb_rc_pkt6_side_fifo_error",
9751 "btb_rc_pkt6_req_fifo_error",
9752 "btb_rc_pkt6_blk_fifo_error",
9753 "btb_rc_pkt6_rls_left_fifo_error",
9754 "btb_rc_pkt6_strt_ptr_fifo_error",
9755 "btb_rc_pkt6_second_ptr_fifo_error",
9756 "btb_rc_pkt6_rsp_fifo_error",
9757 "btb_rc_pkt6_dscr_fifo_error",
9758 "btb_rc_pkt7_rls_error",
9759 "btb_rc_pkt7_len_error",
9760 "btb_rc_pkt7_protocol_error",
9761 "btb_rc_pkt7_side_fifo_error",
9762 "btb_rc_pkt7_req_fifo_error",
9763 "btb_rc_pkt7_blk_fifo_error",
9764 "btb_rc_pkt7_rls_left_fifo_error",
9765 "btb_rc_pkt7_strt_ptr_fifo_error",
9766 "btb_rc_pkt7_second_ptr_fifo_error",
9767 "btb_rc_pkt7_rsp_fifo_error",
9768 "btb_packet_available_sync_fifo_push_error",
9769 "btb_wc6_notify_fifo_error",
9770 "btb_wc9_queue_fifo_error",
9771 "btb_wc0_sync_fifo_push_error",
9772 "btb_rls_sync_fifo_push_error",
9773 "btb_rc_pkt7_dscr_fifo_error",
9776 #define btb_int_attn_desc OSAL_NULL
9779 static const u16 btb_int0_bb_a0_attn_idx[16] = {
9780 0, 1, 3, 5, 6, 8, 10, 11, 13, 15, 16, 18, 20, 21, 23, 25,
9783 static struct attn_hw_reg btb_int0_bb_a0 = {
9784 0, 16, btb_int0_bb_a0_attn_idx, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4
9787 static const u16 btb_int1_bb_a0_attn_idx[16] = {
9788 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
9791 static struct attn_hw_reg btb_int1_bb_a0 = {
9792 1, 16, btb_int1_bb_a0_attn_idx, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc
9795 static const u16 btb_int2_bb_a0_attn_idx[4] = {
9799 static struct attn_hw_reg btb_int2_bb_a0 = {
9800 2, 4, btb_int2_bb_a0_attn_idx, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4
9803 static const u16 btb_int3_bb_a0_attn_idx[32] = {
9804 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
9805 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
9808 static struct attn_hw_reg btb_int3_bb_a0 = {
9809 3, 32, btb_int3_bb_a0_attn_idx, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c
9812 static const u16 btb_int4_bb_a0_attn_idx[23] = {
9813 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
9814 96, 97, 98, 99, 100,
9817 static struct attn_hw_reg btb_int4_bb_a0 = {
9818 4, 23, btb_int4_bb_a0_attn_idx, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124
9821 static const u16 btb_int5_bb_a0_attn_idx[32] = {
9822 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114,
9824 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,
9829 static struct attn_hw_reg btb_int5_bb_a0 = {
9830 5, 32, btb_int5_bb_a0_attn_idx, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c
9833 static const u16 btb_int6_bb_a0_attn_idx[1] = {
9837 static struct attn_hw_reg btb_int6_bb_a0 = {
9838 6, 1, btb_int6_bb_a0_attn_idx, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154
9841 static const u16 btb_int8_bb_a0_attn_idx[1] = {
9845 static struct attn_hw_reg btb_int8_bb_a0 = {
9846 7, 1, btb_int8_bb_a0_attn_idx, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188
9849 static const u16 btb_int9_bb_a0_attn_idx[1] = {
9853 static struct attn_hw_reg btb_int9_bb_a0 = {
9854 8, 1, btb_int9_bb_a0_attn_idx, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0
9857 static const u16 btb_int10_bb_a0_attn_idx[1] = {
9861 static struct attn_hw_reg btb_int10_bb_a0 = {
9862 9, 1, btb_int10_bb_a0_attn_idx, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8
9865 static const u16 btb_int11_bb_a0_attn_idx[2] = {
9869 static struct attn_hw_reg btb_int11_bb_a0 = {
9870 10, 2, btb_int11_bb_a0_attn_idx, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0
9873 static struct attn_hw_reg *btb_int_bb_a0_regs[11] = {
9874 &btb_int0_bb_a0, &btb_int1_bb_a0, &btb_int2_bb_a0, &btb_int3_bb_a0,
9875 &btb_int4_bb_a0, &btb_int5_bb_a0, &btb_int6_bb_a0, &btb_int8_bb_a0,
9876 &btb_int9_bb_a0, &btb_int10_bb_a0,
9880 static const u16 btb_int0_bb_b0_attn_idx[16] = {
9881 0, 1, 3, 5, 6, 8, 10, 11, 13, 15, 16, 18, 20, 21, 23, 25,
9884 static struct attn_hw_reg btb_int0_bb_b0 = {
9885 0, 16, btb_int0_bb_b0_attn_idx, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4
9888 static const u16 btb_int1_bb_b0_attn_idx[16] = {
9889 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
9892 static struct attn_hw_reg btb_int1_bb_b0 = {
9893 1, 16, btb_int1_bb_b0_attn_idx, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc
9896 static const u16 btb_int2_bb_b0_attn_idx[4] = {
9900 static struct attn_hw_reg btb_int2_bb_b0 = {
9901 2, 4, btb_int2_bb_b0_attn_idx, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4
9904 static const u16 btb_int3_bb_b0_attn_idx[32] = {
9905 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
9906 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
9909 static struct attn_hw_reg btb_int3_bb_b0 = {
9910 3, 32, btb_int3_bb_b0_attn_idx, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c
9913 static const u16 btb_int4_bb_b0_attn_idx[23] = {
9914 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
9915 96, 97, 98, 99, 100,
9918 static struct attn_hw_reg btb_int4_bb_b0 = {
9919 4, 23, btb_int4_bb_b0_attn_idx, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124
9922 static const u16 btb_int5_bb_b0_attn_idx[32] = {
9923 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114,
9925 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,
9930 static struct attn_hw_reg btb_int5_bb_b0 = {
9931 5, 32, btb_int5_bb_b0_attn_idx, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c
9934 static const u16 btb_int6_bb_b0_attn_idx[1] = {
9938 static struct attn_hw_reg btb_int6_bb_b0 = {
9939 6, 1, btb_int6_bb_b0_attn_idx, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154
9942 static const u16 btb_int8_bb_b0_attn_idx[1] = {
9946 static struct attn_hw_reg btb_int8_bb_b0 = {
9947 7, 1, btb_int8_bb_b0_attn_idx, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188
9950 static const u16 btb_int9_bb_b0_attn_idx[1] = {
9954 static struct attn_hw_reg btb_int9_bb_b0 = {
9955 8, 1, btb_int9_bb_b0_attn_idx, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0
9958 static const u16 btb_int10_bb_b0_attn_idx[1] = {
9962 static struct attn_hw_reg btb_int10_bb_b0 = {
9963 9, 1, btb_int10_bb_b0_attn_idx, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8
9966 static const u16 btb_int11_bb_b0_attn_idx[2] = {
9970 static struct attn_hw_reg btb_int11_bb_b0 = {
9971 10, 2, btb_int11_bb_b0_attn_idx, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0
9974 static struct attn_hw_reg *btb_int_bb_b0_regs[11] = {
9975 &btb_int0_bb_b0, &btb_int1_bb_b0, &btb_int2_bb_b0, &btb_int3_bb_b0,
9976 &btb_int4_bb_b0, &btb_int5_bb_b0, &btb_int6_bb_b0, &btb_int8_bb_b0,
9977 &btb_int9_bb_b0, &btb_int10_bb_b0,
9981 static const u16 btb_int0_k2_attn_idx[16] = {
9982 0, 1, 3, 5, 6, 8, 10, 11, 13, 15, 16, 18, 20, 21, 23, 25,
9985 static struct attn_hw_reg btb_int0_k2 = {
9986 0, 16, btb_int0_k2_attn_idx, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4
9989 static const u16 btb_int1_k2_attn_idx[16] = {
9990 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
9993 static struct attn_hw_reg btb_int1_k2 = {
9994 1, 16, btb_int1_k2_attn_idx, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc
9997 static const u16 btb_int2_k2_attn_idx[4] = {
10001 static struct attn_hw_reg btb_int2_k2 = {
10002 2, 4, btb_int2_k2_attn_idx, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4
10005 static const u16 btb_int3_k2_attn_idx[32] = {
10006 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
10007 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
10010 static struct attn_hw_reg btb_int3_k2 = {
10011 3, 32, btb_int3_k2_attn_idx, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c
10014 static const u16 btb_int4_k2_attn_idx[23] = {
10015 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
10016 96, 97, 98, 99, 100,
10019 static struct attn_hw_reg btb_int4_k2 = {
10020 4, 23, btb_int4_k2_attn_idx, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124
10023 static const u16 btb_int5_k2_attn_idx[32] = {
10024 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114,
10026 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,
10031 static struct attn_hw_reg btb_int5_k2 = {
10032 5, 32, btb_int5_k2_attn_idx, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c
10035 static const u16 btb_int6_k2_attn_idx[1] = {
10039 static struct attn_hw_reg btb_int6_k2 = {
10040 6, 1, btb_int6_k2_attn_idx, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154
10043 static const u16 btb_int8_k2_attn_idx[1] = {
10047 static struct attn_hw_reg btb_int8_k2 = {
10048 7, 1, btb_int8_k2_attn_idx, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188
10051 static const u16 btb_int9_k2_attn_idx[1] = {
10055 static struct attn_hw_reg btb_int9_k2 = {
10056 8, 1, btb_int9_k2_attn_idx, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0
10059 static const u16 btb_int10_k2_attn_idx[1] = {
10063 static struct attn_hw_reg btb_int10_k2 = {
10064 9, 1, btb_int10_k2_attn_idx, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8
10067 static const u16 btb_int11_k2_attn_idx[2] = {
10071 static struct attn_hw_reg btb_int11_k2 = {
10072 10, 2, btb_int11_k2_attn_idx, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0
10075 static struct attn_hw_reg *btb_int_k2_regs[11] = {
10076 &btb_int0_k2, &btb_int1_k2, &btb_int2_k2, &btb_int3_k2, &btb_int4_k2,
10077 &btb_int5_k2, &btb_int6_k2, &btb_int8_k2, &btb_int9_k2, &btb_int10_k2,
10082 static const char *btb_prty_attn_desc[36] = {
10083 "btb_ll_bank0_mem_prty",
10084 "btb_ll_bank1_mem_prty",
10085 "btb_ll_bank2_mem_prty",
10086 "btb_ll_bank3_mem_prty",
10087 "btb_datapath_registers",
10088 "btb_mem001_i_ecc_rf_int",
10089 "btb_mem008_i_ecc_rf_int",
10090 "btb_mem009_i_ecc_rf_int",
10091 "btb_mem010_i_ecc_rf_int",
10092 "btb_mem011_i_ecc_rf_int",
10093 "btb_mem012_i_ecc_rf_int",
10094 "btb_mem013_i_ecc_rf_int",
10095 "btb_mem014_i_ecc_rf_int",
10096 "btb_mem015_i_ecc_rf_int",
10097 "btb_mem016_i_ecc_rf_int",
10098 "btb_mem002_i_ecc_rf_int",
10099 "btb_mem003_i_ecc_rf_int",
10100 "btb_mem004_i_ecc_rf_int",
10101 "btb_mem005_i_ecc_rf_int",
10102 "btb_mem006_i_ecc_rf_int",
10103 "btb_mem007_i_ecc_rf_int",
10104 "btb_mem033_i_mem_prty",
10105 "btb_mem035_i_mem_prty",
10106 "btb_mem034_i_mem_prty",
10107 "btb_mem032_i_mem_prty",
10108 "btb_mem031_i_mem_prty",
10109 "btb_mem021_i_mem_prty",
10110 "btb_mem022_i_mem_prty",
10111 "btb_mem023_i_mem_prty",
10112 "btb_mem024_i_mem_prty",
10113 "btb_mem025_i_mem_prty",
10114 "btb_mem026_i_mem_prty",
10115 "btb_mem027_i_mem_prty",
10116 "btb_mem028_i_mem_prty",
10117 "btb_mem030_i_mem_prty",
10118 "btb_mem029_i_mem_prty",
10121 #define btb_prty_attn_desc OSAL_NULL
10124 static const u16 btb_prty1_bb_a0_attn_idx[27] = {
10125 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 25, 26, 27,
10127 29, 30, 31, 32, 33, 34, 35,
10130 static struct attn_hw_reg btb_prty1_bb_a0 = {
10131 0, 27, btb_prty1_bb_a0_attn_idx, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404
10134 static struct attn_hw_reg *btb_prty_bb_a0_regs[1] = {
10138 static const u16 btb_prty0_bb_b0_attn_idx[5] = {
10142 static struct attn_hw_reg btb_prty0_bb_b0 = {
10143 0, 5, btb_prty0_bb_b0_attn_idx, 0xdb01dc, 0xdb01e8, 0xdb01e4, 0xdb01e0
10146 static const u16 btb_prty1_bb_b0_attn_idx[23] = {
10147 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 25, 30, 31,
10152 static struct attn_hw_reg btb_prty1_bb_b0 = {
10153 1, 23, btb_prty1_bb_b0_attn_idx, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404
10156 static struct attn_hw_reg *btb_prty_bb_b0_regs[2] = {
10157 &btb_prty0_bb_b0, &btb_prty1_bb_b0,
10160 static const u16 btb_prty0_k2_attn_idx[5] = {
10164 static struct attn_hw_reg btb_prty0_k2 = {
10165 0, 5, btb_prty0_k2_attn_idx, 0xdb01dc, 0xdb01e8, 0xdb01e4, 0xdb01e0
10168 static const u16 btb_prty1_k2_attn_idx[31] = {
10169 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
10171 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,
10174 static struct attn_hw_reg btb_prty1_k2 = {
10175 1, 31, btb_prty1_k2_attn_idx, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404
10178 static struct attn_hw_reg *btb_prty_k2_regs[2] = {
10179 &btb_prty0_k2, &btb_prty1_k2,
10183 static const char *pbf_int_attn_desc[1] = {
10184 "pbf_address_error",
10187 #define pbf_int_attn_desc OSAL_NULL
10190 static const u16 pbf_int0_bb_a0_attn_idx[1] = {
10194 static struct attn_hw_reg pbf_int0_bb_a0 = {
10195 0, 1, pbf_int0_bb_a0_attn_idx, 0xd80180, 0xd8018c, 0xd80188, 0xd80184
10198 static struct attn_hw_reg *pbf_int_bb_a0_regs[1] = {
10202 static const u16 pbf_int0_bb_b0_attn_idx[1] = {
10206 static struct attn_hw_reg pbf_int0_bb_b0 = {
10207 0, 1, pbf_int0_bb_b0_attn_idx, 0xd80180, 0xd8018c, 0xd80188, 0xd80184
10210 static struct attn_hw_reg *pbf_int_bb_b0_regs[1] = {
10214 static const u16 pbf_int0_k2_attn_idx[1] = {
10218 static struct attn_hw_reg pbf_int0_k2 = {
10219 0, 1, pbf_int0_k2_attn_idx, 0xd80180, 0xd8018c, 0xd80188, 0xd80184
10222 static struct attn_hw_reg *pbf_int_k2_regs[1] = {
10227 static const char *pbf_prty_attn_desc[59] = {
10228 "pbf_datapath_registers",
10229 "pbf_mem041_i_ecc_rf_int",
10230 "pbf_mem042_i_ecc_rf_int",
10231 "pbf_mem033_i_ecc_rf_int",
10232 "pbf_mem003_i_ecc_rf_int",
10233 "pbf_mem018_i_ecc_rf_int",
10234 "pbf_mem009_i_ecc_0_rf_int",
10235 "pbf_mem009_i_ecc_1_rf_int",
10236 "pbf_mem012_i_ecc_0_rf_int",
10237 "pbf_mem012_i_ecc_1_rf_int",
10238 "pbf_mem012_i_ecc_2_rf_int",
10239 "pbf_mem012_i_ecc_3_rf_int",
10240 "pbf_mem012_i_ecc_4_rf_int",
10241 "pbf_mem012_i_ecc_5_rf_int",
10242 "pbf_mem012_i_ecc_6_rf_int",
10243 "pbf_mem012_i_ecc_7_rf_int",
10244 "pbf_mem012_i_ecc_8_rf_int",
10245 "pbf_mem012_i_ecc_9_rf_int",
10246 "pbf_mem012_i_ecc_10_rf_int",
10247 "pbf_mem012_i_ecc_11_rf_int",
10248 "pbf_mem012_i_ecc_12_rf_int",
10249 "pbf_mem012_i_ecc_13_rf_int",
10250 "pbf_mem012_i_ecc_14_rf_int",
10251 "pbf_mem012_i_ecc_15_rf_int",
10252 "pbf_mem040_i_mem_prty",
10253 "pbf_mem039_i_mem_prty",
10254 "pbf_mem038_i_mem_prty",
10255 "pbf_mem034_i_mem_prty",
10256 "pbf_mem032_i_mem_prty",
10257 "pbf_mem031_i_mem_prty",
10258 "pbf_mem030_i_mem_prty",
10259 "pbf_mem029_i_mem_prty",
10260 "pbf_mem022_i_mem_prty",
10261 "pbf_mem023_i_mem_prty",
10262 "pbf_mem021_i_mem_prty",
10263 "pbf_mem020_i_mem_prty",
10264 "pbf_mem001_i_mem_prty",
10265 "pbf_mem002_i_mem_prty",
10266 "pbf_mem006_i_mem_prty",
10267 "pbf_mem007_i_mem_prty",
10268 "pbf_mem005_i_mem_prty",
10269 "pbf_mem004_i_mem_prty",
10270 "pbf_mem028_i_mem_prty",
10271 "pbf_mem026_i_mem_prty",
10272 "pbf_mem027_i_mem_prty",
10273 "pbf_mem019_i_mem_prty",
10274 "pbf_mem016_i_mem_prty",
10275 "pbf_mem017_i_mem_prty",
10276 "pbf_mem008_i_mem_prty",
10277 "pbf_mem011_i_mem_prty",
10278 "pbf_mem010_i_mem_prty",
10279 "pbf_mem024_i_mem_prty",
10280 "pbf_mem025_i_mem_prty",
10281 "pbf_mem037_i_mem_prty",
10282 "pbf_mem036_i_mem_prty",
10283 "pbf_mem035_i_mem_prty",
10284 "pbf_mem014_i_mem_prty",
10285 "pbf_mem015_i_mem_prty",
10286 "pbf_mem013_i_mem_prty",
10289 #define pbf_prty_attn_desc OSAL_NULL
10292 static const u16 pbf_prty1_bb_a0_attn_idx[31] = {
10293 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
10295 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
10298 static struct attn_hw_reg pbf_prty1_bb_a0 = {
10299 0, 31, pbf_prty1_bb_a0_attn_idx, 0xd80200, 0xd8020c, 0xd80208, 0xd80204
10302 static const u16 pbf_prty2_bb_a0_attn_idx[27] = {
10303 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
10304 50, 51, 52, 53, 54, 55, 56, 57, 58,
10307 static struct attn_hw_reg pbf_prty2_bb_a0 = {
10308 1, 27, pbf_prty2_bb_a0_attn_idx, 0xd80210, 0xd8021c, 0xd80218, 0xd80214
10311 static struct attn_hw_reg *pbf_prty_bb_a0_regs[2] = {
10312 &pbf_prty1_bb_a0, &pbf_prty2_bb_a0,
10315 static const u16 pbf_prty0_bb_b0_attn_idx[1] = {
10319 static struct attn_hw_reg pbf_prty0_bb_b0 = {
10320 0, 1, pbf_prty0_bb_b0_attn_idx, 0xd80190, 0xd8019c, 0xd80198, 0xd80194
10323 static const u16 pbf_prty1_bb_b0_attn_idx[31] = {
10324 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
10326 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
10329 static struct attn_hw_reg pbf_prty1_bb_b0 = {
10330 1, 31, pbf_prty1_bb_b0_attn_idx, 0xd80200, 0xd8020c, 0xd80208, 0xd80204
10333 static const u16 pbf_prty2_bb_b0_attn_idx[27] = {
10334 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
10335 50, 51, 52, 53, 54, 55, 56, 57, 58,
10338 static struct attn_hw_reg pbf_prty2_bb_b0 = {
10339 2, 27, pbf_prty2_bb_b0_attn_idx, 0xd80210, 0xd8021c, 0xd80218, 0xd80214
10342 static struct attn_hw_reg *pbf_prty_bb_b0_regs[3] = {
10343 &pbf_prty0_bb_b0, &pbf_prty1_bb_b0, &pbf_prty2_bb_b0,
10346 static const u16 pbf_prty0_k2_attn_idx[1] = {
10350 static struct attn_hw_reg pbf_prty0_k2 = {
10351 0, 1, pbf_prty0_k2_attn_idx, 0xd80190, 0xd8019c, 0xd80198, 0xd80194
10354 static const u16 pbf_prty1_k2_attn_idx[31] = {
10355 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
10357 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
10360 static struct attn_hw_reg pbf_prty1_k2 = {
10361 1, 31, pbf_prty1_k2_attn_idx, 0xd80200, 0xd8020c, 0xd80208, 0xd80204
10364 static const u16 pbf_prty2_k2_attn_idx[27] = {
10365 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
10366 50, 51, 52, 53, 54, 55, 56, 57, 58,
10369 static struct attn_hw_reg pbf_prty2_k2 = {
10370 2, 27, pbf_prty2_k2_attn_idx, 0xd80210, 0xd8021c, 0xd80218, 0xd80214
10373 static struct attn_hw_reg *pbf_prty_k2_regs[3] = {
10374 &pbf_prty0_k2, &pbf_prty1_k2, &pbf_prty2_k2,
10378 static const char *rdif_int_attn_desc[9] = {
10379 "rdif_address_error",
10380 "rdif_fatal_dix_err",
10381 "rdif_fatal_config_err",
10382 "rdif_cmd_fifo_err",
10383 "rdif_order_fifo_err",
10384 "rdif_rdata_fifo_err",
10385 "rdif_dif_stop_err",
10386 "rdif_partial_dif_w_eob",
10387 "rdif_l1_dirty_bit",
10390 #define rdif_int_attn_desc OSAL_NULL
10393 static const u16 rdif_int0_bb_a0_attn_idx[8] = {
10394 0, 1, 2, 3, 4, 5, 6, 7,
10397 static struct attn_hw_reg rdif_int0_bb_a0 = {
10398 0, 8, rdif_int0_bb_a0_attn_idx, 0x300180, 0x30018c, 0x300188, 0x300184
10401 static struct attn_hw_reg *rdif_int_bb_a0_regs[1] = {
10405 static const u16 rdif_int0_bb_b0_attn_idx[8] = {
10406 0, 1, 2, 3, 4, 5, 6, 7,
10409 static struct attn_hw_reg rdif_int0_bb_b0 = {
10410 0, 8, rdif_int0_bb_b0_attn_idx, 0x300180, 0x30018c, 0x300188, 0x300184
10413 static struct attn_hw_reg *rdif_int_bb_b0_regs[1] = {
10417 static const u16 rdif_int0_k2_attn_idx[9] = {
10418 0, 1, 2, 3, 4, 5, 6, 7, 8,
10421 static struct attn_hw_reg rdif_int0_k2 = {
10422 0, 9, rdif_int0_k2_attn_idx, 0x300180, 0x30018c, 0x300188, 0x300184
10425 static struct attn_hw_reg *rdif_int_k2_regs[1] = {
10430 static const char *rdif_prty_attn_desc[2] = {
10432 "rdif_datapath_registers",
10435 #define rdif_prty_attn_desc OSAL_NULL
10438 static const u16 rdif_prty0_bb_b0_attn_idx[1] = {
10442 static struct attn_hw_reg rdif_prty0_bb_b0 = {
10443 0, 1, rdif_prty0_bb_b0_attn_idx, 0x300190, 0x30019c, 0x300198, 0x300194
10446 static struct attn_hw_reg *rdif_prty_bb_b0_regs[1] = {
10450 static const u16 rdif_prty0_k2_attn_idx[1] = {
10454 static struct attn_hw_reg rdif_prty0_k2 = {
10455 0, 1, rdif_prty0_k2_attn_idx, 0x300190, 0x30019c, 0x300198, 0x300194
10458 static struct attn_hw_reg *rdif_prty_k2_regs[1] = {
10463 static const char *tdif_int_attn_desc[9] = {
10464 "tdif_address_error",
10465 "tdif_fatal_dix_err",
10466 "tdif_fatal_config_err",
10467 "tdif_cmd_fifo_err",
10468 "tdif_order_fifo_err",
10469 "tdif_rdata_fifo_err",
10470 "tdif_dif_stop_err",
10471 "tdif_partial_dif_w_eob",
10472 "tdif_l1_dirty_bit",
10475 #define tdif_int_attn_desc OSAL_NULL
10478 static const u16 tdif_int0_bb_a0_attn_idx[8] = {
10479 0, 1, 2, 3, 4, 5, 6, 7,
10482 static struct attn_hw_reg tdif_int0_bb_a0 = {
10483 0, 8, tdif_int0_bb_a0_attn_idx, 0x310180, 0x31018c, 0x310188, 0x310184
10486 static struct attn_hw_reg *tdif_int_bb_a0_regs[1] = {
10490 static const u16 tdif_int0_bb_b0_attn_idx[8] = {
10491 0, 1, 2, 3, 4, 5, 6, 7,
10494 static struct attn_hw_reg tdif_int0_bb_b0 = {
10495 0, 8, tdif_int0_bb_b0_attn_idx, 0x310180, 0x31018c, 0x310188, 0x310184
10498 static struct attn_hw_reg *tdif_int_bb_b0_regs[1] = {
10502 static const u16 tdif_int0_k2_attn_idx[9] = {
10503 0, 1, 2, 3, 4, 5, 6, 7, 8,
10506 static struct attn_hw_reg tdif_int0_k2 = {
10507 0, 9, tdif_int0_k2_attn_idx, 0x310180, 0x31018c, 0x310188, 0x310184
10510 static struct attn_hw_reg *tdif_int_k2_regs[1] = {
10515 static const char *tdif_prty_attn_desc[13] = {
10517 "tdif_datapath_registers",
10518 "tdif_mem005_i_ecc_rf_int",
10519 "tdif_mem009_i_ecc_rf_int",
10520 "tdif_mem010_i_ecc_rf_int",
10521 "tdif_mem011_i_ecc_rf_int",
10522 "tdif_mem001_i_mem_prty",
10523 "tdif_mem003_i_mem_prty",
10524 "tdif_mem002_i_mem_prty",
10525 "tdif_mem006_i_mem_prty",
10526 "tdif_mem007_i_mem_prty",
10527 "tdif_mem008_i_mem_prty",
10528 "tdif_mem004_i_mem_prty",
10531 #define tdif_prty_attn_desc OSAL_NULL
10534 static const u16 tdif_prty1_bb_a0_attn_idx[11] = {
10535 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
10538 static struct attn_hw_reg tdif_prty1_bb_a0 = {
10539 0, 11, tdif_prty1_bb_a0_attn_idx, 0x310200, 0x31020c, 0x310208,
10543 static struct attn_hw_reg *tdif_prty_bb_a0_regs[1] = {
10547 static const u16 tdif_prty0_bb_b0_attn_idx[1] = {
10551 static struct attn_hw_reg tdif_prty0_bb_b0 = {
10552 0, 1, tdif_prty0_bb_b0_attn_idx, 0x310190, 0x31019c, 0x310198, 0x310194
10555 static const u16 tdif_prty1_bb_b0_attn_idx[11] = {
10556 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
10559 static struct attn_hw_reg tdif_prty1_bb_b0 = {
10560 1, 11, tdif_prty1_bb_b0_attn_idx, 0x310200, 0x31020c, 0x310208,
10564 static struct attn_hw_reg *tdif_prty_bb_b0_regs[2] = {
10565 &tdif_prty0_bb_b0, &tdif_prty1_bb_b0,
10568 static const u16 tdif_prty0_k2_attn_idx[1] = {
10572 static struct attn_hw_reg tdif_prty0_k2 = {
10573 0, 1, tdif_prty0_k2_attn_idx, 0x310190, 0x31019c, 0x310198, 0x310194
10576 static const u16 tdif_prty1_k2_attn_idx[11] = {
10577 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
10580 static struct attn_hw_reg tdif_prty1_k2 = {
10581 1, 11, tdif_prty1_k2_attn_idx, 0x310200, 0x31020c, 0x310208, 0x310204
10584 static struct attn_hw_reg *tdif_prty_k2_regs[2] = {
10585 &tdif_prty0_k2, &tdif_prty1_k2,
10589 static const char *cdu_int_attn_desc[8] = {
10590 "cdu_address_error",
10591 "cdu_ccfc_ld_l1_num_error",
10592 "cdu_tcfc_ld_l1_num_error",
10593 "cdu_ccfc_wb_l1_num_error",
10594 "cdu_tcfc_wb_l1_num_error",
10595 "cdu_ccfc_cvld_error",
10596 "cdu_tcfc_cvld_error",
10597 "cdu_bvalid_error",
10600 #define cdu_int_attn_desc OSAL_NULL
10603 static const u16 cdu_int0_bb_a0_attn_idx[8] = {
10604 0, 1, 2, 3, 4, 5, 6, 7,
10607 static struct attn_hw_reg cdu_int0_bb_a0 = {
10608 0, 8, cdu_int0_bb_a0_attn_idx, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc
10611 static struct attn_hw_reg *cdu_int_bb_a0_regs[1] = {
10615 static const u16 cdu_int0_bb_b0_attn_idx[8] = {
10616 0, 1, 2, 3, 4, 5, 6, 7,
10619 static struct attn_hw_reg cdu_int0_bb_b0 = {
10620 0, 8, cdu_int0_bb_b0_attn_idx, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc
10623 static struct attn_hw_reg *cdu_int_bb_b0_regs[1] = {
10627 static const u16 cdu_int0_k2_attn_idx[8] = {
10628 0, 1, 2, 3, 4, 5, 6, 7,
10631 static struct attn_hw_reg cdu_int0_k2 = {
10632 0, 8, cdu_int0_k2_attn_idx, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc
10635 static struct attn_hw_reg *cdu_int_k2_regs[1] = {
10640 static const char *cdu_prty_attn_desc[5] = {
10641 "cdu_mem001_i_mem_prty",
10642 "cdu_mem004_i_mem_prty",
10643 "cdu_mem002_i_mem_prty",
10644 "cdu_mem005_i_mem_prty",
10645 "cdu_mem003_i_mem_prty",
10648 #define cdu_prty_attn_desc OSAL_NULL
10651 static const u16 cdu_prty1_bb_a0_attn_idx[5] = {
10655 static struct attn_hw_reg cdu_prty1_bb_a0 = {
10656 0, 5, cdu_prty1_bb_a0_attn_idx, 0x580200, 0x58020c, 0x580208, 0x580204
10659 static struct attn_hw_reg *cdu_prty_bb_a0_regs[1] = {
10663 static const u16 cdu_prty1_bb_b0_attn_idx[5] = {
10667 static struct attn_hw_reg cdu_prty1_bb_b0 = {
10668 0, 5, cdu_prty1_bb_b0_attn_idx, 0x580200, 0x58020c, 0x580208, 0x580204
10671 static struct attn_hw_reg *cdu_prty_bb_b0_regs[1] = {
10675 static const u16 cdu_prty1_k2_attn_idx[5] = {
10679 static struct attn_hw_reg cdu_prty1_k2 = {
10680 0, 5, cdu_prty1_k2_attn_idx, 0x580200, 0x58020c, 0x580208, 0x580204
10683 static struct attn_hw_reg *cdu_prty_k2_regs[1] = {
10688 static const char *ccfc_int_attn_desc[2] = {
10689 "ccfc_address_error",
10693 #define ccfc_int_attn_desc OSAL_NULL
10696 static const u16 ccfc_int0_bb_a0_attn_idx[2] = {
10700 static struct attn_hw_reg ccfc_int0_bb_a0 = {
10701 0, 2, ccfc_int0_bb_a0_attn_idx, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184
10704 static struct attn_hw_reg *ccfc_int_bb_a0_regs[1] = {
10708 static const u16 ccfc_int0_bb_b0_attn_idx[2] = {
10712 static struct attn_hw_reg ccfc_int0_bb_b0 = {
10713 0, 2, ccfc_int0_bb_b0_attn_idx, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184
10716 static struct attn_hw_reg *ccfc_int_bb_b0_regs[1] = {
10720 static const u16 ccfc_int0_k2_attn_idx[2] = {
10724 static struct attn_hw_reg ccfc_int0_k2 = {
10725 0, 2, ccfc_int0_k2_attn_idx, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184
10728 static struct attn_hw_reg *ccfc_int_k2_regs[1] = {
10733 static const char *ccfc_prty_attn_desc[10] = {
10734 "ccfc_mem001_i_ecc_rf_int",
10735 "ccfc_mem003_i_mem_prty",
10736 "ccfc_mem007_i_mem_prty",
10737 "ccfc_mem006_i_mem_prty",
10738 "ccfc_ccam_par_err",
10739 "ccfc_scam_par_err",
10740 "ccfc_lc_que_ram_porta_lsb_par_err",
10741 "ccfc_lc_que_ram_porta_msb_par_err",
10742 "ccfc_lc_que_ram_portb_lsb_par_err",
10743 "ccfc_lc_que_ram_portb_msb_par_err",
10746 #define ccfc_prty_attn_desc OSAL_NULL
10749 static const u16 ccfc_prty1_bb_a0_attn_idx[4] = {
10753 static struct attn_hw_reg ccfc_prty1_bb_a0 = {
10754 0, 4, ccfc_prty1_bb_a0_attn_idx, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204
10757 static const u16 ccfc_prty0_bb_a0_attn_idx[2] = {
10761 static struct attn_hw_reg ccfc_prty0_bb_a0 = {
10762 1, 2, ccfc_prty0_bb_a0_attn_idx, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8
10765 static struct attn_hw_reg *ccfc_prty_bb_a0_regs[2] = {
10766 &ccfc_prty1_bb_a0, &ccfc_prty0_bb_a0,
10769 static const u16 ccfc_prty1_bb_b0_attn_idx[2] = {
10773 static struct attn_hw_reg ccfc_prty1_bb_b0 = {
10774 0, 2, ccfc_prty1_bb_b0_attn_idx, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204
10777 static const u16 ccfc_prty0_bb_b0_attn_idx[6] = {
10781 static struct attn_hw_reg ccfc_prty0_bb_b0 = {
10782 1, 6, ccfc_prty0_bb_b0_attn_idx, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8
10785 static struct attn_hw_reg *ccfc_prty_bb_b0_regs[2] = {
10786 &ccfc_prty1_bb_b0, &ccfc_prty0_bb_b0,
10789 static const u16 ccfc_prty1_k2_attn_idx[2] = {
10793 static struct attn_hw_reg ccfc_prty1_k2 = {
10794 0, 2, ccfc_prty1_k2_attn_idx, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204
10797 static const u16 ccfc_prty0_k2_attn_idx[6] = {
10801 static struct attn_hw_reg ccfc_prty0_k2 = {
10802 1, 6, ccfc_prty0_k2_attn_idx, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8
10805 static struct attn_hw_reg *ccfc_prty_k2_regs[2] = {
10806 &ccfc_prty1_k2, &ccfc_prty0_k2,
10810 static const char *tcfc_int_attn_desc[2] = {
10811 "tcfc_address_error",
10815 #define tcfc_int_attn_desc OSAL_NULL
10818 static const u16 tcfc_int0_bb_a0_attn_idx[2] = {
10822 static struct attn_hw_reg tcfc_int0_bb_a0 = {
10823 0, 2, tcfc_int0_bb_a0_attn_idx, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184
10826 static struct attn_hw_reg *tcfc_int_bb_a0_regs[1] = {
10830 static const u16 tcfc_int0_bb_b0_attn_idx[2] = {
10834 static struct attn_hw_reg tcfc_int0_bb_b0 = {
10835 0, 2, tcfc_int0_bb_b0_attn_idx, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184
10838 static struct attn_hw_reg *tcfc_int_bb_b0_regs[1] = {
10842 static const u16 tcfc_int0_k2_attn_idx[2] = {
10846 static struct attn_hw_reg tcfc_int0_k2 = {
10847 0, 2, tcfc_int0_k2_attn_idx, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184
10850 static struct attn_hw_reg *tcfc_int_k2_regs[1] = {
10855 static const char *tcfc_prty_attn_desc[10] = {
10856 "tcfc_mem002_i_mem_prty",
10857 "tcfc_mem001_i_mem_prty",
10858 "tcfc_mem006_i_mem_prty",
10859 "tcfc_mem005_i_mem_prty",
10860 "tcfc_ccam_par_err",
10861 "tcfc_scam_par_err",
10862 "tcfc_lc_que_ram_porta_lsb_par_err",
10863 "tcfc_lc_que_ram_porta_msb_par_err",
10864 "tcfc_lc_que_ram_portb_lsb_par_err",
10865 "tcfc_lc_que_ram_portb_msb_par_err",
10868 #define tcfc_prty_attn_desc OSAL_NULL
10871 static const u16 tcfc_prty1_bb_a0_attn_idx[4] = {
10875 static struct attn_hw_reg tcfc_prty1_bb_a0 = {
10876 0, 4, tcfc_prty1_bb_a0_attn_idx, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204
10879 static const u16 tcfc_prty0_bb_a0_attn_idx[2] = {
10883 static struct attn_hw_reg tcfc_prty0_bb_a0 = {
10884 1, 2, tcfc_prty0_bb_a0_attn_idx, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8
10887 static struct attn_hw_reg *tcfc_prty_bb_a0_regs[2] = {
10888 &tcfc_prty1_bb_a0, &tcfc_prty0_bb_a0,
10891 static const u16 tcfc_prty1_bb_b0_attn_idx[2] = {
10895 static struct attn_hw_reg tcfc_prty1_bb_b0 = {
10896 0, 2, tcfc_prty1_bb_b0_attn_idx, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204
10899 static const u16 tcfc_prty0_bb_b0_attn_idx[6] = {
10903 static struct attn_hw_reg tcfc_prty0_bb_b0 = {
10904 1, 6, tcfc_prty0_bb_b0_attn_idx, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8
10907 static struct attn_hw_reg *tcfc_prty_bb_b0_regs[2] = {
10908 &tcfc_prty1_bb_b0, &tcfc_prty0_bb_b0,
10911 static const u16 tcfc_prty1_k2_attn_idx[2] = {
10915 static struct attn_hw_reg tcfc_prty1_k2 = {
10916 0, 2, tcfc_prty1_k2_attn_idx, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204
10919 static const u16 tcfc_prty0_k2_attn_idx[6] = {
10923 static struct attn_hw_reg tcfc_prty0_k2 = {
10924 1, 6, tcfc_prty0_k2_attn_idx, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8
10927 static struct attn_hw_reg *tcfc_prty_k2_regs[2] = {
10928 &tcfc_prty1_k2, &tcfc_prty0_k2,
10932 static const char *igu_int_attn_desc[11] = {
10933 "igu_address_error",
10934 "igu_ctrl_fifo_error_err",
10935 "igu_pxp_req_length_too_big",
10936 "igu_host_tries2access_prod_upd",
10937 "igu_vf_tries2acc_attn_cmd",
10938 "igu_mme_bigger_then_5",
10939 "igu_sb_index_is_not_valid",
10940 "igu_durin_int_read_with_simd_dis",
10941 "igu_cmd_fid_not_match",
10942 "igu_segment_access_invalid",
10943 "igu_attn_prod_acc",
10946 #define igu_int_attn_desc OSAL_NULL
10949 static const u16 igu_int0_bb_a0_attn_idx[11] = {
10950 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
10953 static struct attn_hw_reg igu_int0_bb_a0 = {
10954 0, 11, igu_int0_bb_a0_attn_idx, 0x180180, 0x18018c, 0x180188, 0x180184
10957 static struct attn_hw_reg *igu_int_bb_a0_regs[1] = {
10961 static const u16 igu_int0_bb_b0_attn_idx[11] = {
10962 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
10965 static struct attn_hw_reg igu_int0_bb_b0 = {
10966 0, 11, igu_int0_bb_b0_attn_idx, 0x180180, 0x18018c, 0x180188, 0x180184
10969 static struct attn_hw_reg *igu_int_bb_b0_regs[1] = {
10973 static const u16 igu_int0_k2_attn_idx[11] = {
10974 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
10977 static struct attn_hw_reg igu_int0_k2 = {
10978 0, 11, igu_int0_k2_attn_idx, 0x180180, 0x18018c, 0x180188, 0x180184
10981 static struct attn_hw_reg *igu_int_k2_regs[1] = {
10986 static const char *igu_prty_attn_desc[42] = {
10988 "igu_mem009_i_ecc_rf_int",
10989 "igu_mem015_i_mem_prty",
10990 "igu_mem016_i_mem_prty",
10991 "igu_mem017_i_mem_prty",
10992 "igu_mem018_i_mem_prty",
10993 "igu_mem019_i_mem_prty",
10994 "igu_mem001_i_mem_prty",
10995 "igu_mem002_i_mem_prty_0",
10996 "igu_mem002_i_mem_prty_1",
10997 "igu_mem004_i_mem_prty_0",
10998 "igu_mem004_i_mem_prty_1",
10999 "igu_mem004_i_mem_prty_2",
11000 "igu_mem003_i_mem_prty",
11001 "igu_mem005_i_mem_prty",
11002 "igu_mem006_i_mem_prty_0",
11003 "igu_mem006_i_mem_prty_1",
11004 "igu_mem008_i_mem_prty_0",
11005 "igu_mem008_i_mem_prty_1",
11006 "igu_mem008_i_mem_prty_2",
11007 "igu_mem007_i_mem_prty",
11008 "igu_mem010_i_mem_prty_0",
11009 "igu_mem010_i_mem_prty_1",
11010 "igu_mem012_i_mem_prty_0",
11011 "igu_mem012_i_mem_prty_1",
11012 "igu_mem012_i_mem_prty_2",
11013 "igu_mem011_i_mem_prty",
11014 "igu_mem013_i_mem_prty",
11015 "igu_mem014_i_mem_prty",
11016 "igu_mem020_i_mem_prty",
11017 "igu_mem003_i_mem_prty_0",
11018 "igu_mem003_i_mem_prty_1",
11019 "igu_mem003_i_mem_prty_2",
11020 "igu_mem002_i_mem_prty",
11021 "igu_mem007_i_mem_prty_0",
11022 "igu_mem007_i_mem_prty_1",
11023 "igu_mem007_i_mem_prty_2",
11024 "igu_mem006_i_mem_prty",
11025 "igu_mem010_i_mem_prty_2",
11026 "igu_mem010_i_mem_prty_3",
11027 "igu_mem013_i_mem_prty_0",
11028 "igu_mem013_i_mem_prty_1",
11031 #define igu_prty_attn_desc OSAL_NULL
11034 static const u16 igu_prty0_bb_a0_attn_idx[1] = {
11038 static struct attn_hw_reg igu_prty0_bb_a0 = {
11039 0, 1, igu_prty0_bb_a0_attn_idx, 0x180190, 0x18019c, 0x180198, 0x180194
11042 static const u16 igu_prty1_bb_a0_attn_idx[31] = {
11043 1, 3, 4, 5, 6, 7, 10, 11, 14, 17, 18, 21, 22, 23, 24, 25, 26, 28, 29,
11045 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
11048 static struct attn_hw_reg igu_prty1_bb_a0 = {
11049 1, 31, igu_prty1_bb_a0_attn_idx, 0x180200, 0x18020c, 0x180208, 0x180204
11052 static const u16 igu_prty2_bb_a0_attn_idx[1] = {
11056 static struct attn_hw_reg igu_prty2_bb_a0 = {
11057 2, 1, igu_prty2_bb_a0_attn_idx, 0x180210, 0x18021c, 0x180218, 0x180214
11060 static struct attn_hw_reg *igu_prty_bb_a0_regs[3] = {
11061 &igu_prty0_bb_a0, &igu_prty1_bb_a0, &igu_prty2_bb_a0,
11064 static const u16 igu_prty0_bb_b0_attn_idx[1] = {
11068 static struct attn_hw_reg igu_prty0_bb_b0 = {
11069 0, 1, igu_prty0_bb_b0_attn_idx, 0x180190, 0x18019c, 0x180198, 0x180194
11072 static const u16 igu_prty1_bb_b0_attn_idx[31] = {
11073 1, 3, 4, 5, 6, 7, 10, 11, 14, 17, 18, 21, 22, 23, 24, 25, 26, 28, 29,
11075 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
11078 static struct attn_hw_reg igu_prty1_bb_b0 = {
11079 1, 31, igu_prty1_bb_b0_attn_idx, 0x180200, 0x18020c, 0x180208, 0x180204
11082 static const u16 igu_prty2_bb_b0_attn_idx[1] = {
11086 static struct attn_hw_reg igu_prty2_bb_b0 = {
11087 2, 1, igu_prty2_bb_b0_attn_idx, 0x180210, 0x18021c, 0x180218, 0x180214
11090 static struct attn_hw_reg *igu_prty_bb_b0_regs[3] = {
11091 &igu_prty0_bb_b0, &igu_prty1_bb_b0, &igu_prty2_bb_b0,
11094 static const u16 igu_prty0_k2_attn_idx[1] = {
11098 static struct attn_hw_reg igu_prty0_k2 = {
11099 0, 1, igu_prty0_k2_attn_idx, 0x180190, 0x18019c, 0x180198, 0x180194
11102 static const u16 igu_prty1_k2_attn_idx[28] = {
11103 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
11105 22, 23, 24, 25, 26, 27, 28,
11108 static struct attn_hw_reg igu_prty1_k2 = {
11109 1, 28, igu_prty1_k2_attn_idx, 0x180200, 0x18020c, 0x180208, 0x180204
11112 static struct attn_hw_reg *igu_prty_k2_regs[2] = {
11113 &igu_prty0_k2, &igu_prty1_k2,
11117 static const char *cau_int_attn_desc[11] = {
11118 "cau_address_error",
11119 "cau_unauthorized_pxp_rd_cmd",
11120 "cau_unauthorized_pxp_length_cmd",
11121 "cau_pxp_sb_address_error",
11122 "cau_pxp_pi_number_error",
11123 "cau_cleanup_reg_sb_idx_error",
11124 "cau_fsm_invalid_line",
11125 "cau_cqe_fifo_err",
11126 "cau_igu_wdata_fifo_err",
11127 "cau_igu_req_fifo_err",
11128 "cau_igu_cmd_fifo_err",
11131 #define cau_int_attn_desc OSAL_NULL
11134 static const u16 cau_int0_bb_a0_attn_idx[11] = {
11135 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11138 static struct attn_hw_reg cau_int0_bb_a0 = {
11139 0, 11, cau_int0_bb_a0_attn_idx, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0
11142 static struct attn_hw_reg *cau_int_bb_a0_regs[1] = {
11146 static const u16 cau_int0_bb_b0_attn_idx[11] = {
11147 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11150 static struct attn_hw_reg cau_int0_bb_b0 = {
11151 0, 11, cau_int0_bb_b0_attn_idx, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0
11154 static struct attn_hw_reg *cau_int_bb_b0_regs[1] = {
11158 static const u16 cau_int0_k2_attn_idx[11] = {
11159 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11162 static struct attn_hw_reg cau_int0_k2 = {
11163 0, 11, cau_int0_k2_attn_idx, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0
11166 static struct attn_hw_reg *cau_int_k2_regs[1] = {
11171 static const char *cau_prty_attn_desc[15] = {
11172 "cau_mem006_i_ecc_rf_int",
11173 "cau_mem001_i_ecc_0_rf_int",
11174 "cau_mem001_i_ecc_1_rf_int",
11175 "cau_mem002_i_ecc_rf_int",
11176 "cau_mem004_i_ecc_rf_int",
11177 "cau_mem005_i_mem_prty",
11178 "cau_mem007_i_mem_prty",
11179 "cau_mem008_i_mem_prty",
11180 "cau_mem009_i_mem_prty",
11181 "cau_mem010_i_mem_prty",
11182 "cau_mem011_i_mem_prty",
11183 "cau_mem003_i_mem_prty_0",
11184 "cau_mem003_i_mem_prty_1",
11185 "cau_mem002_i_mem_prty",
11186 "cau_mem004_i_mem_prty",
11189 #define cau_prty_attn_desc OSAL_NULL
11192 static const u16 cau_prty1_bb_a0_attn_idx[13] = {
11193 0, 1, 2, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
11196 static struct attn_hw_reg cau_prty1_bb_a0 = {
11197 0, 13, cau_prty1_bb_a0_attn_idx, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204
11200 static struct attn_hw_reg *cau_prty_bb_a0_regs[1] = {
11204 static const u16 cau_prty1_bb_b0_attn_idx[13] = {
11205 0, 1, 2, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
11208 static struct attn_hw_reg cau_prty1_bb_b0 = {
11209 0, 13, cau_prty1_bb_b0_attn_idx, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204
11212 static struct attn_hw_reg *cau_prty_bb_b0_regs[1] = {
11216 static const u16 cau_prty1_k2_attn_idx[13] = {
11217 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
11220 static struct attn_hw_reg cau_prty1_k2 = {
11221 0, 13, cau_prty1_k2_attn_idx, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204
11224 static struct attn_hw_reg *cau_prty_k2_regs[1] = {
11229 static const char *umac_int_attn_desc[2] = {
11230 "umac_address_error",
11231 "umac_tx_overflow",
11234 #define umac_int_attn_desc OSAL_NULL
11237 static const u16 umac_int0_k2_attn_idx[2] = {
11241 static struct attn_hw_reg umac_int0_k2 = {
11242 0, 2, umac_int0_k2_attn_idx, 0x51180, 0x5118c, 0x51188, 0x51184
11245 static struct attn_hw_reg *umac_int_k2_regs[1] = {
11250 static const char *dbg_int_attn_desc[1] = {
11251 "dbg_address_error",
11254 #define dbg_int_attn_desc OSAL_NULL
11257 static const u16 dbg_int0_bb_a0_attn_idx[1] = {
11261 static struct attn_hw_reg dbg_int0_bb_a0 = {
11262 0, 1, dbg_int0_bb_a0_attn_idx, 0x10180, 0x1018c, 0x10188, 0x10184
11265 static struct attn_hw_reg *dbg_int_bb_a0_regs[1] = {
11269 static const u16 dbg_int0_bb_b0_attn_idx[1] = {
11273 static struct attn_hw_reg dbg_int0_bb_b0 = {
11274 0, 1, dbg_int0_bb_b0_attn_idx, 0x10180, 0x1018c, 0x10188, 0x10184
11277 static struct attn_hw_reg *dbg_int_bb_b0_regs[1] = {
11281 static const u16 dbg_int0_k2_attn_idx[1] = {
11285 static struct attn_hw_reg dbg_int0_k2 = {
11286 0, 1, dbg_int0_k2_attn_idx, 0x10180, 0x1018c, 0x10188, 0x10184
11289 static struct attn_hw_reg *dbg_int_k2_regs[1] = {
11294 static const char *dbg_prty_attn_desc[1] = {
11295 "dbg_mem001_i_mem_prty",
11298 #define dbg_prty_attn_desc OSAL_NULL
11301 static const u16 dbg_prty1_bb_a0_attn_idx[1] = {
11305 static struct attn_hw_reg dbg_prty1_bb_a0 = {
11306 0, 1, dbg_prty1_bb_a0_attn_idx, 0x10200, 0x1020c, 0x10208, 0x10204
11309 static struct attn_hw_reg *dbg_prty_bb_a0_regs[1] = {
11313 static const u16 dbg_prty1_bb_b0_attn_idx[1] = {
11317 static struct attn_hw_reg dbg_prty1_bb_b0 = {
11318 0, 1, dbg_prty1_bb_b0_attn_idx, 0x10200, 0x1020c, 0x10208, 0x10204
11321 static struct attn_hw_reg *dbg_prty_bb_b0_regs[1] = {
11325 static const u16 dbg_prty1_k2_attn_idx[1] = {
11329 static struct attn_hw_reg dbg_prty1_k2 = {
11330 0, 1, dbg_prty1_k2_attn_idx, 0x10200, 0x1020c, 0x10208, 0x10204
11333 static struct attn_hw_reg *dbg_prty_k2_regs[1] = {
11338 static const char *nig_int_attn_desc[196] = {
11339 "nig_address_error",
11340 "nig_debug_fifo_error",
11341 "nig_dorq_fifo_error",
11342 "nig_dbg_syncfifo_error_wr",
11343 "nig_dorq_syncfifo_error_wr",
11344 "nig_storm_syncfifo_error_wr",
11345 "nig_dbgmux_syncfifo_error_wr",
11346 "nig_msdm_syncfifo_error_wr",
11347 "nig_tsdm_syncfifo_error_wr",
11348 "nig_usdm_syncfifo_error_wr",
11349 "nig_xsdm_syncfifo_error_wr",
11350 "nig_ysdm_syncfifo_error_wr",
11351 "nig_tx_sopq0_error",
11352 "nig_tx_sopq1_error",
11353 "nig_tx_sopq2_error",
11354 "nig_tx_sopq3_error",
11355 "nig_tx_sopq4_error",
11356 "nig_tx_sopq5_error",
11357 "nig_tx_sopq6_error",
11358 "nig_tx_sopq7_error",
11359 "nig_tx_sopq8_error",
11360 "nig_tx_sopq9_error",
11361 "nig_tx_sopq10_error",
11362 "nig_tx_sopq11_error",
11363 "nig_tx_sopq12_error",
11364 "nig_tx_sopq13_error",
11365 "nig_tx_sopq14_error",
11366 "nig_tx_sopq15_error",
11367 "nig_lb_sopq0_error",
11368 "nig_lb_sopq1_error",
11369 "nig_lb_sopq2_error",
11370 "nig_lb_sopq3_error",
11371 "nig_lb_sopq4_error",
11372 "nig_lb_sopq5_error",
11373 "nig_lb_sopq6_error",
11374 "nig_lb_sopq7_error",
11375 "nig_lb_sopq8_error",
11376 "nig_lb_sopq9_error",
11377 "nig_lb_sopq10_error",
11378 "nig_lb_sopq11_error",
11379 "nig_lb_sopq12_error",
11380 "nig_lb_sopq13_error",
11381 "nig_lb_sopq14_error",
11382 "nig_lb_sopq15_error",
11383 "nig_p0_purelb_sopq_error",
11384 "nig_p0_rx_macfifo_error",
11385 "nig_p0_tx_macfifo_error",
11386 "nig_p0_tx_bmb_fifo_error",
11387 "nig_p0_lb_bmb_fifo_error",
11388 "nig_p0_tx_btb_fifo_error",
11389 "nig_p0_lb_btb_fifo_error",
11390 "nig_p0_rx_llh_dfifo_error",
11391 "nig_p0_tx_llh_dfifo_error",
11392 "nig_p0_lb_llh_dfifo_error",
11393 "nig_p0_rx_llh_hfifo_error",
11394 "nig_p0_tx_llh_hfifo_error",
11395 "nig_p0_lb_llh_hfifo_error",
11396 "nig_p0_rx_llh_rfifo_error",
11397 "nig_p0_tx_llh_rfifo_error",
11398 "nig_p0_lb_llh_rfifo_error",
11399 "nig_p0_storm_fifo_error",
11400 "nig_p0_storm_dscr_fifo_error",
11401 "nig_p0_tx_gnt_fifo_error",
11402 "nig_p0_lb_gnt_fifo_error",
11403 "nig_p0_tx_pause_too_long_int",
11404 "nig_p0_tc0_pause_too_long_int",
11405 "nig_p0_tc1_pause_too_long_int",
11406 "nig_p0_tc2_pause_too_long_int",
11407 "nig_p0_tc3_pause_too_long_int",
11408 "nig_p0_tc4_pause_too_long_int",
11409 "nig_p0_tc5_pause_too_long_int",
11410 "nig_p0_tc6_pause_too_long_int",
11411 "nig_p0_tc7_pause_too_long_int",
11412 "nig_p0_lb_tc0_pause_too_long_int",
11413 "nig_p0_lb_tc1_pause_too_long_int",
11414 "nig_p0_lb_tc2_pause_too_long_int",
11415 "nig_p0_lb_tc3_pause_too_long_int",
11416 "nig_p0_lb_tc4_pause_too_long_int",
11417 "nig_p0_lb_tc5_pause_too_long_int",
11418 "nig_p0_lb_tc6_pause_too_long_int",
11419 "nig_p0_lb_tc7_pause_too_long_int",
11420 "nig_p0_lb_tc8_pause_too_long_int",
11421 "nig_p1_purelb_sopq_error",
11422 "nig_p1_rx_macfifo_error",
11423 "nig_p1_tx_macfifo_error",
11424 "nig_p1_tx_bmb_fifo_error",
11425 "nig_p1_lb_bmb_fifo_error",
11426 "nig_p1_tx_btb_fifo_error",
11427 "nig_p1_lb_btb_fifo_error",
11428 "nig_p1_rx_llh_dfifo_error",
11429 "nig_p1_tx_llh_dfifo_error",
11430 "nig_p1_lb_llh_dfifo_error",
11431 "nig_p1_rx_llh_hfifo_error",
11432 "nig_p1_tx_llh_hfifo_error",
11433 "nig_p1_lb_llh_hfifo_error",
11434 "nig_p1_rx_llh_rfifo_error",
11435 "nig_p1_tx_llh_rfifo_error",
11436 "nig_p1_lb_llh_rfifo_error",
11437 "nig_p1_storm_fifo_error",
11438 "nig_p1_storm_dscr_fifo_error",
11439 "nig_p1_tx_gnt_fifo_error",
11440 "nig_p1_lb_gnt_fifo_error",
11441 "nig_p1_tx_pause_too_long_int",
11442 "nig_p1_tc0_pause_too_long_int",
11443 "nig_p1_tc1_pause_too_long_int",
11444 "nig_p1_tc2_pause_too_long_int",
11445 "nig_p1_tc3_pause_too_long_int",
11446 "nig_p1_tc4_pause_too_long_int",
11447 "nig_p1_tc5_pause_too_long_int",
11448 "nig_p1_tc6_pause_too_long_int",
11449 "nig_p1_tc7_pause_too_long_int",
11450 "nig_p1_lb_tc0_pause_too_long_int",
11451 "nig_p1_lb_tc1_pause_too_long_int",
11452 "nig_p1_lb_tc2_pause_too_long_int",
11453 "nig_p1_lb_tc3_pause_too_long_int",
11454 "nig_p1_lb_tc4_pause_too_long_int",
11455 "nig_p1_lb_tc5_pause_too_long_int",
11456 "nig_p1_lb_tc6_pause_too_long_int",
11457 "nig_p1_lb_tc7_pause_too_long_int",
11458 "nig_p1_lb_tc8_pause_too_long_int",
11459 "nig_p2_purelb_sopq_error",
11460 "nig_p2_rx_macfifo_error",
11461 "nig_p2_tx_macfifo_error",
11462 "nig_p2_tx_bmb_fifo_error",
11463 "nig_p2_lb_bmb_fifo_error",
11464 "nig_p2_tx_btb_fifo_error",
11465 "nig_p2_lb_btb_fifo_error",
11466 "nig_p2_rx_llh_dfifo_error",
11467 "nig_p2_tx_llh_dfifo_error",
11468 "nig_p2_lb_llh_dfifo_error",
11469 "nig_p2_rx_llh_hfifo_error",
11470 "nig_p2_tx_llh_hfifo_error",
11471 "nig_p2_lb_llh_hfifo_error",
11472 "nig_p2_rx_llh_rfifo_error",
11473 "nig_p2_tx_llh_rfifo_error",
11474 "nig_p2_lb_llh_rfifo_error",
11475 "nig_p2_storm_fifo_error",
11476 "nig_p2_storm_dscr_fifo_error",
11477 "nig_p2_tx_gnt_fifo_error",
11478 "nig_p2_lb_gnt_fifo_error",
11479 "nig_p2_tx_pause_too_long_int",
11480 "nig_p2_tc0_pause_too_long_int",
11481 "nig_p2_tc1_pause_too_long_int",
11482 "nig_p2_tc2_pause_too_long_int",
11483 "nig_p2_tc3_pause_too_long_int",
11484 "nig_p2_tc4_pause_too_long_int",
11485 "nig_p2_tc5_pause_too_long_int",
11486 "nig_p2_tc6_pause_too_long_int",
11487 "nig_p2_tc7_pause_too_long_int",
11488 "nig_p2_lb_tc0_pause_too_long_int",
11489 "nig_p2_lb_tc1_pause_too_long_int",
11490 "nig_p2_lb_tc2_pause_too_long_int",
11491 "nig_p2_lb_tc3_pause_too_long_int",
11492 "nig_p2_lb_tc4_pause_too_long_int",
11493 "nig_p2_lb_tc5_pause_too_long_int",
11494 "nig_p2_lb_tc6_pause_too_long_int",
11495 "nig_p2_lb_tc7_pause_too_long_int",
11496 "nig_p2_lb_tc8_pause_too_long_int",
11497 "nig_p3_purelb_sopq_error",
11498 "nig_p3_rx_macfifo_error",
11499 "nig_p3_tx_macfifo_error",
11500 "nig_p3_tx_bmb_fifo_error",
11501 "nig_p3_lb_bmb_fifo_error",
11502 "nig_p3_tx_btb_fifo_error",
11503 "nig_p3_lb_btb_fifo_error",
11504 "nig_p3_rx_llh_dfifo_error",
11505 "nig_p3_tx_llh_dfifo_error",
11506 "nig_p3_lb_llh_dfifo_error",
11507 "nig_p3_rx_llh_hfifo_error",
11508 "nig_p3_tx_llh_hfifo_error",
11509 "nig_p3_lb_llh_hfifo_error",
11510 "nig_p3_rx_llh_rfifo_error",
11511 "nig_p3_tx_llh_rfifo_error",
11512 "nig_p3_lb_llh_rfifo_error",
11513 "nig_p3_storm_fifo_error",
11514 "nig_p3_storm_dscr_fifo_error",
11515 "nig_p3_tx_gnt_fifo_error",
11516 "nig_p3_lb_gnt_fifo_error",
11517 "nig_p3_tx_pause_too_long_int",
11518 "nig_p3_tc0_pause_too_long_int",
11519 "nig_p3_tc1_pause_too_long_int",
11520 "nig_p3_tc2_pause_too_long_int",
11521 "nig_p3_tc3_pause_too_long_int",
11522 "nig_p3_tc4_pause_too_long_int",
11523 "nig_p3_tc5_pause_too_long_int",
11524 "nig_p3_tc6_pause_too_long_int",
11525 "nig_p3_tc7_pause_too_long_int",
11526 "nig_p3_lb_tc0_pause_too_long_int",
11527 "nig_p3_lb_tc1_pause_too_long_int",
11528 "nig_p3_lb_tc2_pause_too_long_int",
11529 "nig_p3_lb_tc3_pause_too_long_int",
11530 "nig_p3_lb_tc4_pause_too_long_int",
11531 "nig_p3_lb_tc5_pause_too_long_int",
11532 "nig_p3_lb_tc6_pause_too_long_int",
11533 "nig_p3_lb_tc7_pause_too_long_int",
11534 "nig_p3_lb_tc8_pause_too_long_int",
11537 #define nig_int_attn_desc OSAL_NULL
11540 static const u16 nig_int0_bb_a0_attn_idx[12] = {
11541 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
11544 static struct attn_hw_reg nig_int0_bb_a0 = {
11545 0, 12, nig_int0_bb_a0_attn_idx, 0x500040, 0x50004c, 0x500048, 0x500044
11548 static const u16 nig_int1_bb_a0_attn_idx[32] = {
11549 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
11550 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
11553 static struct attn_hw_reg nig_int1_bb_a0 = {
11554 1, 32, nig_int1_bb_a0_attn_idx, 0x500050, 0x50005c, 0x500058, 0x500054
11557 static const u16 nig_int2_bb_a0_attn_idx[20] = {
11558 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
11562 static struct attn_hw_reg nig_int2_bb_a0 = {
11563 2, 20, nig_int2_bb_a0_attn_idx, 0x500060, 0x50006c, 0x500068, 0x500064
11566 static const u16 nig_int3_bb_a0_attn_idx[18] = {
11567 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,
11570 static struct attn_hw_reg nig_int3_bb_a0 = {
11571 3, 18, nig_int3_bb_a0_attn_idx, 0x500070, 0x50007c, 0x500078, 0x500074
11574 static const u16 nig_int4_bb_a0_attn_idx[20] = {
11575 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,
11579 static struct attn_hw_reg nig_int4_bb_a0 = {
11580 4, 20, nig_int4_bb_a0_attn_idx, 0x500080, 0x50008c, 0x500088, 0x500084
11583 static const u16 nig_int5_bb_a0_attn_idx[18] = {
11584 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115,
11589 static struct attn_hw_reg nig_int5_bb_a0 = {
11590 5, 18, nig_int5_bb_a0_attn_idx, 0x500090, 0x50009c, 0x500098, 0x500094
11593 static struct attn_hw_reg *nig_int_bb_a0_regs[6] = {
11594 &nig_int0_bb_a0, &nig_int1_bb_a0, &nig_int2_bb_a0, &nig_int3_bb_a0,
11595 &nig_int4_bb_a0, &nig_int5_bb_a0,
11598 static const u16 nig_int0_bb_b0_attn_idx[12] = {
11599 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
11602 static struct attn_hw_reg nig_int0_bb_b0 = {
11603 0, 12, nig_int0_bb_b0_attn_idx, 0x500040, 0x50004c, 0x500048, 0x500044
11606 static const u16 nig_int1_bb_b0_attn_idx[32] = {
11607 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
11608 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
11611 static struct attn_hw_reg nig_int1_bb_b0 = {
11612 1, 32, nig_int1_bb_b0_attn_idx, 0x500050, 0x50005c, 0x500058, 0x500054
11615 static const u16 nig_int2_bb_b0_attn_idx[20] = {
11616 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
11620 static struct attn_hw_reg nig_int2_bb_b0 = {
11621 2, 20, nig_int2_bb_b0_attn_idx, 0x500060, 0x50006c, 0x500068, 0x500064
11624 static const u16 nig_int3_bb_b0_attn_idx[18] = {
11625 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,
11628 static struct attn_hw_reg nig_int3_bb_b0 = {
11629 3, 18, nig_int3_bb_b0_attn_idx, 0x500070, 0x50007c, 0x500078, 0x500074
11632 static const u16 nig_int4_bb_b0_attn_idx[20] = {
11633 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,
11637 static struct attn_hw_reg nig_int4_bb_b0 = {
11638 4, 20, nig_int4_bb_b0_attn_idx, 0x500080, 0x50008c, 0x500088, 0x500084
11641 static const u16 nig_int5_bb_b0_attn_idx[18] = {
11642 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115,
11647 static struct attn_hw_reg nig_int5_bb_b0 = {
11648 5, 18, nig_int5_bb_b0_attn_idx, 0x500090, 0x50009c, 0x500098, 0x500094
11651 static struct attn_hw_reg *nig_int_bb_b0_regs[6] = {
11652 &nig_int0_bb_b0, &nig_int1_bb_b0, &nig_int2_bb_b0, &nig_int3_bb_b0,
11653 &nig_int4_bb_b0, &nig_int5_bb_b0,
11656 static const u16 nig_int0_k2_attn_idx[12] = {
11657 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
11660 static struct attn_hw_reg nig_int0_k2 = {
11661 0, 12, nig_int0_k2_attn_idx, 0x500040, 0x50004c, 0x500048, 0x500044
11664 static const u16 nig_int1_k2_attn_idx[32] = {
11665 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
11666 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
11669 static struct attn_hw_reg nig_int1_k2 = {
11670 1, 32, nig_int1_k2_attn_idx, 0x500050, 0x50005c, 0x500058, 0x500054
11673 static const u16 nig_int2_k2_attn_idx[20] = {
11674 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
11678 static struct attn_hw_reg nig_int2_k2 = {
11679 2, 20, nig_int2_k2_attn_idx, 0x500060, 0x50006c, 0x500068, 0x500064
11682 static const u16 nig_int3_k2_attn_idx[18] = {
11683 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,
11686 static struct attn_hw_reg nig_int3_k2 = {
11687 3, 18, nig_int3_k2_attn_idx, 0x500070, 0x50007c, 0x500078, 0x500074
11690 static const u16 nig_int4_k2_attn_idx[20] = {
11691 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,
11695 static struct attn_hw_reg nig_int4_k2 = {
11696 4, 20, nig_int4_k2_attn_idx, 0x500080, 0x50008c, 0x500088, 0x500084
11699 static const u16 nig_int5_k2_attn_idx[18] = {
11700 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115,
11705 static struct attn_hw_reg nig_int5_k2 = {
11706 5, 18, nig_int5_k2_attn_idx, 0x500090, 0x50009c, 0x500098, 0x500094
11709 static const u16 nig_int6_k2_attn_idx[20] = {
11710 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,
11712 135, 136, 137, 138, 139,
11715 static struct attn_hw_reg nig_int6_k2 = {
11716 6, 20, nig_int6_k2_attn_idx, 0x5000a0, 0x5000ac, 0x5000a8, 0x5000a4
11719 static const u16 nig_int7_k2_attn_idx[18] = {
11720 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,
11725 static struct attn_hw_reg nig_int7_k2 = {
11726 7, 18, nig_int7_k2_attn_idx, 0x5000b0, 0x5000bc, 0x5000b8, 0x5000b4
11729 static const u16 nig_int8_k2_attn_idx[20] = {
11730 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171,
11732 173, 174, 175, 176, 177,
11735 static struct attn_hw_reg nig_int8_k2 = {
11736 8, 20, nig_int8_k2_attn_idx, 0x5000c0, 0x5000cc, 0x5000c8, 0x5000c4
11739 static const u16 nig_int9_k2_attn_idx[18] = {
11740 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191,
11745 static struct attn_hw_reg nig_int9_k2 = {
11746 9, 18, nig_int9_k2_attn_idx, 0x5000d0, 0x5000dc, 0x5000d8, 0x5000d4
11749 static struct attn_hw_reg *nig_int_k2_regs[10] = {
11750 &nig_int0_k2, &nig_int1_k2, &nig_int2_k2, &nig_int3_k2, &nig_int4_k2,
11751 &nig_int5_k2, &nig_int6_k2, &nig_int7_k2, &nig_int8_k2, &nig_int9_k2,
11755 static const char *nig_prty_attn_desc[113] = {
11756 "nig_datapath_parity_error",
11757 "nig_mem107_i_mem_prty",
11758 "nig_mem103_i_mem_prty",
11759 "nig_mem104_i_mem_prty",
11760 "nig_mem105_i_mem_prty",
11761 "nig_mem106_i_mem_prty",
11762 "nig_mem072_i_mem_prty",
11763 "nig_mem071_i_mem_prty",
11764 "nig_mem074_i_mem_prty",
11765 "nig_mem073_i_mem_prty",
11766 "nig_mem076_i_mem_prty",
11767 "nig_mem075_i_mem_prty",
11768 "nig_mem078_i_mem_prty",
11769 "nig_mem077_i_mem_prty",
11770 "nig_mem055_i_mem_prty",
11771 "nig_mem062_i_mem_prty",
11772 "nig_mem063_i_mem_prty",
11773 "nig_mem064_i_mem_prty",
11774 "nig_mem065_i_mem_prty",
11775 "nig_mem066_i_mem_prty",
11776 "nig_mem067_i_mem_prty",
11777 "nig_mem068_i_mem_prty",
11778 "nig_mem069_i_mem_prty",
11779 "nig_mem070_i_mem_prty",
11780 "nig_mem056_i_mem_prty",
11781 "nig_mem057_i_mem_prty",
11782 "nig_mem058_i_mem_prty",
11783 "nig_mem059_i_mem_prty",
11784 "nig_mem060_i_mem_prty",
11785 "nig_mem061_i_mem_prty",
11786 "nig_mem035_i_mem_prty",
11787 "nig_mem046_i_mem_prty",
11788 "nig_mem051_i_mem_prty",
11789 "nig_mem052_i_mem_prty",
11790 "nig_mem090_i_mem_prty",
11791 "nig_mem089_i_mem_prty",
11792 "nig_mem092_i_mem_prty",
11793 "nig_mem091_i_mem_prty",
11794 "nig_mem109_i_mem_prty",
11795 "nig_mem110_i_mem_prty",
11796 "nig_mem001_i_mem_prty",
11797 "nig_mem008_i_mem_prty",
11798 "nig_mem009_i_mem_prty",
11799 "nig_mem010_i_mem_prty",
11800 "nig_mem011_i_mem_prty",
11801 "nig_mem012_i_mem_prty",
11802 "nig_mem013_i_mem_prty",
11803 "nig_mem014_i_mem_prty",
11804 "nig_mem015_i_mem_prty",
11805 "nig_mem016_i_mem_prty",
11806 "nig_mem002_i_mem_prty",
11807 "nig_mem003_i_mem_prty",
11808 "nig_mem004_i_mem_prty",
11809 "nig_mem005_i_mem_prty",
11810 "nig_mem006_i_mem_prty",
11811 "nig_mem007_i_mem_prty",
11812 "nig_mem080_i_mem_prty",
11813 "nig_mem081_i_mem_prty",
11814 "nig_mem082_i_mem_prty",
11815 "nig_mem083_i_mem_prty",
11816 "nig_mem048_i_mem_prty",
11817 "nig_mem049_i_mem_prty",
11818 "nig_mem102_i_mem_prty",
11819 "nig_mem087_i_mem_prty",
11820 "nig_mem086_i_mem_prty",
11821 "nig_mem088_i_mem_prty",
11822 "nig_mem079_i_mem_prty",
11823 "nig_mem047_i_mem_prty",
11824 "nig_mem050_i_mem_prty",
11825 "nig_mem053_i_mem_prty",
11826 "nig_mem054_i_mem_prty",
11827 "nig_mem036_i_mem_prty",
11828 "nig_mem037_i_mem_prty",
11829 "nig_mem038_i_mem_prty",
11830 "nig_mem039_i_mem_prty",
11831 "nig_mem040_i_mem_prty",
11832 "nig_mem041_i_mem_prty",
11833 "nig_mem042_i_mem_prty",
11834 "nig_mem043_i_mem_prty",
11835 "nig_mem044_i_mem_prty",
11836 "nig_mem045_i_mem_prty",
11837 "nig_mem093_i_mem_prty",
11838 "nig_mem094_i_mem_prty",
11839 "nig_mem027_i_mem_prty",
11840 "nig_mem028_i_mem_prty",
11841 "nig_mem029_i_mem_prty",
11842 "nig_mem030_i_mem_prty",
11843 "nig_mem017_i_mem_prty",
11844 "nig_mem018_i_mem_prty",
11845 "nig_mem095_i_mem_prty",
11846 "nig_mem084_i_mem_prty",
11847 "nig_mem085_i_mem_prty",
11848 "nig_mem099_i_mem_prty",
11849 "nig_mem100_i_mem_prty",
11850 "nig_mem096_i_mem_prty",
11851 "nig_mem097_i_mem_prty",
11852 "nig_mem098_i_mem_prty",
11853 "nig_mem031_i_mem_prty",
11854 "nig_mem032_i_mem_prty",
11855 "nig_mem033_i_mem_prty",
11856 "nig_mem034_i_mem_prty",
11857 "nig_mem019_i_mem_prty",
11858 "nig_mem020_i_mem_prty",
11859 "nig_mem021_i_mem_prty",
11860 "nig_mem022_i_mem_prty",
11861 "nig_mem101_i_mem_prty",
11862 "nig_mem023_i_mem_prty",
11863 "nig_mem024_i_mem_prty",
11864 "nig_mem025_i_mem_prty",
11865 "nig_mem026_i_mem_prty",
11866 "nig_mem108_i_mem_prty",
11867 "nig_mem031_ext_i_mem_prty",
11868 "nig_mem034_ext_i_mem_prty",
11871 #define nig_prty_attn_desc OSAL_NULL
11874 static const u16 nig_prty1_bb_a0_attn_idx[31] = {
11875 1, 2, 5, 12, 13, 23, 35, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
11876 52, 53, 54, 55, 56, 60, 61, 62, 63, 64, 65, 66,
11879 static struct attn_hw_reg nig_prty1_bb_a0 = {
11880 0, 31, nig_prty1_bb_a0_attn_idx, 0x500200, 0x50020c, 0x500208, 0x500204
11883 static const u16 nig_prty2_bb_a0_attn_idx[31] = {
11884 33, 69, 70, 90, 91, 8, 11, 10, 14, 17, 18, 19, 20, 21, 22, 7, 6, 24, 25,
11885 26, 27, 28, 29, 15, 16, 57, 58, 59, 9, 94, 95,
11888 static struct attn_hw_reg nig_prty2_bb_a0 = {
11889 1, 31, nig_prty2_bb_a0_attn_idx, 0x500210, 0x50021c, 0x500218, 0x500214
11892 static const u16 nig_prty3_bb_a0_attn_idx[31] = {
11893 96, 97, 98, 103, 104, 92, 93, 105, 106, 107, 108, 109, 80, 31, 67, 83,
11895 3, 68, 85, 86, 89, 77, 78, 79, 4, 32, 36, 81, 82, 87,
11898 static struct attn_hw_reg nig_prty3_bb_a0 = {
11899 2, 31, nig_prty3_bb_a0_attn_idx, 0x500220, 0x50022c, 0x500228, 0x500224
11902 static const u16 nig_prty4_bb_a0_attn_idx[14] = {
11903 88, 101, 102, 75, 71, 74, 76, 73, 72, 34, 37, 99, 30, 100,
11906 static struct attn_hw_reg nig_prty4_bb_a0 = {
11907 3, 14, nig_prty4_bb_a0_attn_idx, 0x500230, 0x50023c, 0x500238, 0x500234
11910 static struct attn_hw_reg *nig_prty_bb_a0_regs[4] = {
11911 &nig_prty1_bb_a0, &nig_prty2_bb_a0, &nig_prty3_bb_a0, &nig_prty4_bb_a0,
11914 static const u16 nig_prty0_bb_b0_attn_idx[1] = {
11918 static struct attn_hw_reg nig_prty0_bb_b0 = {
11919 0, 1, nig_prty0_bb_b0_attn_idx, 0x5000a0, 0x5000ac, 0x5000a8, 0x5000a4
11922 static const u16 nig_prty1_bb_b0_attn_idx[31] = {
11923 4, 5, 9, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
11924 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
11927 static struct attn_hw_reg nig_prty1_bb_b0 = {
11928 1, 31, nig_prty1_bb_b0_attn_idx, 0x500200, 0x50020c, 0x500208, 0x500204
11931 static const u16 nig_prty2_bb_b0_attn_idx[31] = {
11932 90, 91, 64, 63, 65, 8, 11, 10, 13, 12, 66, 14, 17, 18, 19, 20, 21, 22,
11934 7, 6, 24, 25, 26, 27, 28, 29, 15, 16, 92, 93,
11937 static struct attn_hw_reg nig_prty2_bb_b0 = {
11938 2, 31, nig_prty2_bb_b0_attn_idx, 0x500210, 0x50021c, 0x500218, 0x500214
11941 static const u16 nig_prty3_bb_b0_attn_idx[31] = {
11942 94, 95, 96, 97, 99, 100, 103, 104, 105, 62, 108, 109, 80, 31, 1, 67, 60,
11943 69, 83, 84, 2, 3, 110, 61, 68, 70, 85, 86, 111, 112, 89,
11946 static struct attn_hw_reg nig_prty3_bb_b0 = {
11947 3, 31, nig_prty3_bb_b0_attn_idx, 0x500220, 0x50022c, 0x500228, 0x500224
11950 static const u16 nig_prty4_bb_b0_attn_idx[17] = {
11951 106, 107, 87, 88, 81, 82, 101, 102, 75, 71, 74, 76, 77, 78, 79, 73, 72,
11954 static struct attn_hw_reg nig_prty4_bb_b0 = {
11955 4, 17, nig_prty4_bb_b0_attn_idx, 0x500230, 0x50023c, 0x500238, 0x500234
11958 static struct attn_hw_reg *nig_prty_bb_b0_regs[5] = {
11959 &nig_prty0_bb_b0, &nig_prty1_bb_b0, &nig_prty2_bb_b0, &nig_prty3_bb_b0,
11963 static const u16 nig_prty0_k2_attn_idx[1] = {
11967 static struct attn_hw_reg nig_prty0_k2 = {
11968 0, 1, nig_prty0_k2_attn_idx, 0x5000e0, 0x5000ec, 0x5000e8, 0x5000e4
11971 static const u16 nig_prty1_k2_attn_idx[31] = {
11972 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
11974 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
11977 static struct attn_hw_reg nig_prty1_k2 = {
11978 1, 31, nig_prty1_k2_attn_idx, 0x500200, 0x50020c, 0x500208, 0x500204
11981 static const u16 nig_prty2_k2_attn_idx[31] = {
11982 67, 60, 61, 68, 32, 33, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
11983 37, 36, 81, 82, 83, 84, 85, 86, 48, 49, 87, 88, 89,
11986 static struct attn_hw_reg nig_prty2_k2 = {
11987 2, 31, nig_prty2_k2_attn_idx, 0x500210, 0x50021c, 0x500218, 0x500214
11990 static const u16 nig_prty3_k2_attn_idx[31] = {
11991 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 92, 93, 105, 62, 106,
11992 107, 108, 109, 59, 90, 91, 64, 55, 41, 42, 43, 63, 65, 35, 34,
11995 static struct attn_hw_reg nig_prty3_k2 = {
11996 3, 31, nig_prty3_k2_attn_idx, 0x500220, 0x50022c, 0x500228, 0x500224
11999 static const u16 nig_prty4_k2_attn_idx[14] = {
12000 44, 45, 46, 47, 40, 50, 66, 56, 57, 58, 51, 52, 53, 54,
12003 static struct attn_hw_reg nig_prty4_k2 = {
12004 4, 14, nig_prty4_k2_attn_idx, 0x500230, 0x50023c, 0x500238, 0x500234
12007 static struct attn_hw_reg *nig_prty_k2_regs[5] = {
12008 &nig_prty0_k2, &nig_prty1_k2, &nig_prty2_k2, &nig_prty3_k2,
12013 static const char *wol_int_attn_desc[1] = {
12014 "wol_address_error",
12017 #define wol_int_attn_desc OSAL_NULL
12020 static const u16 wol_int0_k2_attn_idx[1] = {
12024 static struct attn_hw_reg wol_int0_k2 = {
12025 0, 1, wol_int0_k2_attn_idx, 0x600040, 0x60004c, 0x600048, 0x600044
12028 static struct attn_hw_reg *wol_int_k2_regs[1] = {
12033 static const char *wol_prty_attn_desc[24] = {
12034 "wol_mem017_i_mem_prty",
12035 "wol_mem018_i_mem_prty",
12036 "wol_mem019_i_mem_prty",
12037 "wol_mem020_i_mem_prty",
12038 "wol_mem021_i_mem_prty",
12039 "wol_mem022_i_mem_prty",
12040 "wol_mem023_i_mem_prty",
12041 "wol_mem024_i_mem_prty",
12042 "wol_mem001_i_mem_prty",
12043 "wol_mem008_i_mem_prty",
12044 "wol_mem009_i_mem_prty",
12045 "wol_mem010_i_mem_prty",
12046 "wol_mem011_i_mem_prty",
12047 "wol_mem012_i_mem_prty",
12048 "wol_mem013_i_mem_prty",
12049 "wol_mem014_i_mem_prty",
12050 "wol_mem015_i_mem_prty",
12051 "wol_mem016_i_mem_prty",
12052 "wol_mem002_i_mem_prty",
12053 "wol_mem003_i_mem_prty",
12054 "wol_mem004_i_mem_prty",
12055 "wol_mem005_i_mem_prty",
12056 "wol_mem006_i_mem_prty",
12057 "wol_mem007_i_mem_prty",
12060 #define wol_prty_attn_desc OSAL_NULL
12063 static const u16 wol_prty1_k2_attn_idx[24] = {
12064 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
12069 static struct attn_hw_reg wol_prty1_k2 = {
12070 0, 24, wol_prty1_k2_attn_idx, 0x600200, 0x60020c, 0x600208, 0x600204
12073 static struct attn_hw_reg *wol_prty_k2_regs[1] = {
12078 static const char *bmbn_int_attn_desc[1] = {
12079 "bmbn_address_error",
12082 #define bmbn_int_attn_desc OSAL_NULL
12085 static const u16 bmbn_int0_k2_attn_idx[1] = {
12089 static struct attn_hw_reg bmbn_int0_k2 = {
12090 0, 1, bmbn_int0_k2_attn_idx, 0x610040, 0x61004c, 0x610048, 0x610044
12093 static struct attn_hw_reg *bmbn_int_k2_regs[1] = {
12098 static const char *ipc_int_attn_desc[14] = {
12099 "ipc_address_error",
12101 "ipc_vmain_por_assert",
12102 "ipc_vmain_por_deassert",
12103 "ipc_perst_assert",
12104 "ipc_perst_deassert",
12105 "ipc_otp_ecc_ded_0",
12106 "ipc_otp_ecc_ded_1",
12107 "ipc_otp_ecc_ded_2",
12108 "ipc_otp_ecc_ded_3",
12109 "ipc_otp_ecc_ded_4",
12110 "ipc_otp_ecc_ded_5",
12111 "ipc_otp_ecc_ded_6",
12112 "ipc_otp_ecc_ded_7",
12115 #define ipc_int_attn_desc OSAL_NULL
12118 static const u16 ipc_int0_bb_a0_attn_idx[5] = {
12122 static struct attn_hw_reg ipc_int0_bb_a0 = {
12123 0, 5, ipc_int0_bb_a0_attn_idx, 0x2050c, 0x20518, 0x20514, 0x20510
12126 static struct attn_hw_reg *ipc_int_bb_a0_regs[1] = {
12130 static const u16 ipc_int0_bb_b0_attn_idx[13] = {
12131 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
12134 static struct attn_hw_reg ipc_int0_bb_b0 = {
12135 0, 13, ipc_int0_bb_b0_attn_idx, 0x2050c, 0x20518, 0x20514, 0x20510
12138 static struct attn_hw_reg *ipc_int_bb_b0_regs[1] = {
12142 static const u16 ipc_int0_k2_attn_idx[5] = {
12146 static struct attn_hw_reg ipc_int0_k2 = {
12147 0, 5, ipc_int0_k2_attn_idx, 0x202dc, 0x202e8, 0x202e4, 0x202e0
12150 static struct attn_hw_reg *ipc_int_k2_regs[1] = {
12155 static const char *ipc_prty_attn_desc[1] = {
12156 "ipc_fake_par_err",
12159 #define ipc_prty_attn_desc OSAL_NULL
12162 static const u16 ipc_prty0_bb_a0_attn_idx[1] = {
12166 static struct attn_hw_reg ipc_prty0_bb_a0 = {
12167 0, 1, ipc_prty0_bb_a0_attn_idx, 0x2051c, 0x20528, 0x20524, 0x20520
12170 static struct attn_hw_reg *ipc_prty_bb_a0_regs[1] = {
12174 static const u16 ipc_prty0_bb_b0_attn_idx[1] = {
12178 static struct attn_hw_reg ipc_prty0_bb_b0 = {
12179 0, 1, ipc_prty0_bb_b0_attn_idx, 0x2051c, 0x20528, 0x20524, 0x20520
12182 static struct attn_hw_reg *ipc_prty_bb_b0_regs[1] = {
12187 static const char *nwm_int_attn_desc[18] = {
12188 "nwm_address_error",
12189 "nwm_tx_overflow_0",
12190 "nwm_tx_underflow_0",
12191 "nwm_tx_overflow_1",
12192 "nwm_tx_underflow_1",
12193 "nwm_tx_overflow_2",
12194 "nwm_tx_underflow_2",
12195 "nwm_tx_overflow_3",
12196 "nwm_tx_underflow_3",
12208 #define nwm_int_attn_desc OSAL_NULL
12211 static const u16 nwm_int0_k2_attn_idx[17] = {
12212 0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17,
12215 static struct attn_hw_reg nwm_int0_k2 = {
12216 0, 17, nwm_int0_k2_attn_idx, 0x800004, 0x800010, 0x80000c, 0x800008
12219 static struct attn_hw_reg *nwm_int_k2_regs[1] = {
12224 static const char *nwm_prty_attn_desc[72] = {
12225 "nwm_mem020_i_mem_prty",
12226 "nwm_mem028_i_mem_prty",
12227 "nwm_mem036_i_mem_prty",
12228 "nwm_mem044_i_mem_prty",
12229 "nwm_mem023_i_mem_prty",
12230 "nwm_mem031_i_mem_prty",
12231 "nwm_mem039_i_mem_prty",
12232 "nwm_mem047_i_mem_prty",
12233 "nwm_mem024_i_mem_prty",
12234 "nwm_mem032_i_mem_prty",
12235 "nwm_mem040_i_mem_prty",
12236 "nwm_mem048_i_mem_prty",
12237 "nwm_mem018_i_mem_prty",
12238 "nwm_mem026_i_mem_prty",
12239 "nwm_mem034_i_mem_prty",
12240 "nwm_mem042_i_mem_prty",
12241 "nwm_mem017_i_mem_prty",
12242 "nwm_mem025_i_mem_prty",
12243 "nwm_mem033_i_mem_prty",
12244 "nwm_mem041_i_mem_prty",
12245 "nwm_mem021_i_mem_prty",
12246 "nwm_mem029_i_mem_prty",
12247 "nwm_mem037_i_mem_prty",
12248 "nwm_mem045_i_mem_prty",
12249 "nwm_mem019_i_mem_prty",
12250 "nwm_mem027_i_mem_prty",
12251 "nwm_mem035_i_mem_prty",
12252 "nwm_mem043_i_mem_prty",
12253 "nwm_mem022_i_mem_prty",
12254 "nwm_mem030_i_mem_prty",
12255 "nwm_mem038_i_mem_prty",
12256 "nwm_mem046_i_mem_prty",
12257 "nwm_mem057_i_mem_prty",
12258 "nwm_mem059_i_mem_prty",
12259 "nwm_mem061_i_mem_prty",
12260 "nwm_mem063_i_mem_prty",
12261 "nwm_mem058_i_mem_prty",
12262 "nwm_mem060_i_mem_prty",
12263 "nwm_mem062_i_mem_prty",
12264 "nwm_mem064_i_mem_prty",
12265 "nwm_mem009_i_mem_prty",
12266 "nwm_mem010_i_mem_prty",
12267 "nwm_mem011_i_mem_prty",
12268 "nwm_mem012_i_mem_prty",
12269 "nwm_mem013_i_mem_prty",
12270 "nwm_mem014_i_mem_prty",
12271 "nwm_mem015_i_mem_prty",
12272 "nwm_mem016_i_mem_prty",
12273 "nwm_mem001_i_mem_prty",
12274 "nwm_mem002_i_mem_prty",
12275 "nwm_mem003_i_mem_prty",
12276 "nwm_mem004_i_mem_prty",
12277 "nwm_mem005_i_mem_prty",
12278 "nwm_mem006_i_mem_prty",
12279 "nwm_mem007_i_mem_prty",
12280 "nwm_mem008_i_mem_prty",
12281 "nwm_mem049_i_mem_prty",
12282 "nwm_mem053_i_mem_prty",
12283 "nwm_mem050_i_mem_prty",
12284 "nwm_mem054_i_mem_prty",
12285 "nwm_mem051_i_mem_prty",
12286 "nwm_mem055_i_mem_prty",
12287 "nwm_mem052_i_mem_prty",
12288 "nwm_mem056_i_mem_prty",
12289 "nwm_mem066_i_mem_prty",
12290 "nwm_mem068_i_mem_prty",
12291 "nwm_mem070_i_mem_prty",
12292 "nwm_mem072_i_mem_prty",
12293 "nwm_mem065_i_mem_prty",
12294 "nwm_mem067_i_mem_prty",
12295 "nwm_mem069_i_mem_prty",
12296 "nwm_mem071_i_mem_prty",
12299 #define nwm_prty_attn_desc OSAL_NULL
12302 static const u16 nwm_prty1_k2_attn_idx[31] = {
12303 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
12305 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
12308 static struct attn_hw_reg nwm_prty1_k2 = {
12309 0, 31, nwm_prty1_k2_attn_idx, 0x800200, 0x80020c, 0x800208, 0x800204
12312 static const u16 nwm_prty2_k2_attn_idx[31] = {
12313 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
12314 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
12317 static struct attn_hw_reg nwm_prty2_k2 = {
12318 1, 31, nwm_prty2_k2_attn_idx, 0x800210, 0x80021c, 0x800218, 0x800214
12321 static const u16 nwm_prty3_k2_attn_idx[10] = {
12322 62, 63, 64, 65, 66, 67, 68, 69, 70, 71,
12325 static struct attn_hw_reg nwm_prty3_k2 = {
12326 2, 10, nwm_prty3_k2_attn_idx, 0x800220, 0x80022c, 0x800228, 0x800224
12329 static struct attn_hw_reg *nwm_prty_k2_regs[3] = {
12330 &nwm_prty1_k2, &nwm_prty2_k2, &nwm_prty3_k2,
12334 static const char *nws_int_attn_desc[38] = {
12335 "nws_address_error",
12336 "nws_ln0_an_resolve_50g_cr2",
12337 "nws_ln0_an_resolve_50g_kr2",
12338 "nws_ln0_an_resolve_40g_cr4",
12339 "nws_ln0_an_resolve_40g_kr4",
12340 "nws_ln0_an_resolve_25g_gr",
12341 "nws_ln0_an_resolve_25g_cr",
12342 "nws_ln0_an_resolve_25g_kr",
12343 "nws_ln0_an_resolve_10g_kr",
12344 "nws_ln0_an_resolve_1g_kx",
12346 "nws_ln1_an_resolve_50g_cr2",
12347 "nws_ln1_an_resolve_50g_kr2",
12348 "nws_ln1_an_resolve_40g_cr4",
12349 "nws_ln1_an_resolve_40g_kr4",
12350 "nws_ln1_an_resolve_25g_gr",
12351 "nws_ln1_an_resolve_25g_cr",
12352 "nws_ln1_an_resolve_25g_kr",
12353 "nws_ln1_an_resolve_10g_kr",
12354 "nws_ln1_an_resolve_1g_kx",
12355 "nws_ln2_an_resolve_50g_cr2",
12356 "nws_ln2_an_resolve_50g_kr2",
12357 "nws_ln2_an_resolve_40g_cr4",
12358 "nws_ln2_an_resolve_40g_kr4",
12359 "nws_ln2_an_resolve_25g_gr",
12360 "nws_ln2_an_resolve_25g_cr",
12361 "nws_ln2_an_resolve_25g_kr",
12362 "nws_ln2_an_resolve_10g_kr",
12363 "nws_ln2_an_resolve_1g_kx",
12364 "nws_ln3_an_resolve_50g_cr2",
12365 "nws_ln3_an_resolve_50g_kr2",
12366 "nws_ln3_an_resolve_40g_cr4",
12367 "nws_ln3_an_resolve_40g_kr4",
12368 "nws_ln3_an_resolve_25g_gr",
12369 "nws_ln3_an_resolve_25g_cr",
12370 "nws_ln3_an_resolve_25g_kr",
12371 "nws_ln3_an_resolve_10g_kr",
12372 "nws_ln3_an_resolve_1g_kx",
12375 #define nws_int_attn_desc OSAL_NULL
12378 static const u16 nws_int0_k2_attn_idx[10] = {
12379 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
12382 static struct attn_hw_reg nws_int0_k2 = {
12383 0, 10, nws_int0_k2_attn_idx, 0x700180, 0x70018c, 0x700188, 0x700184
12386 static const u16 nws_int1_k2_attn_idx[9] = {
12387 11, 12, 13, 14, 15, 16, 17, 18, 19,
12390 static struct attn_hw_reg nws_int1_k2 = {
12391 1, 9, nws_int1_k2_attn_idx, 0x700190, 0x70019c, 0x700198, 0x700194
12394 static const u16 nws_int2_k2_attn_idx[9] = {
12395 20, 21, 22, 23, 24, 25, 26, 27, 28,
12398 static struct attn_hw_reg nws_int2_k2 = {
12399 2, 9, nws_int2_k2_attn_idx, 0x7001a0, 0x7001ac, 0x7001a8, 0x7001a4
12402 static const u16 nws_int3_k2_attn_idx[9] = {
12403 29, 30, 31, 32, 33, 34, 35, 36, 37,
12406 static struct attn_hw_reg nws_int3_k2 = {
12407 3, 9, nws_int3_k2_attn_idx, 0x7001b0, 0x7001bc, 0x7001b8, 0x7001b4
12410 static struct attn_hw_reg *nws_int_k2_regs[4] = {
12411 &nws_int0_k2, &nws_int1_k2, &nws_int2_k2, &nws_int3_k2,
12415 static const char *nws_prty_attn_desc[4] = {
12416 "nws_mem003_i_mem_prty",
12417 "nws_mem001_i_mem_prty",
12418 "nws_mem004_i_mem_prty",
12419 "nws_mem002_i_mem_prty",
12422 #define nws_prty_attn_desc OSAL_NULL
12425 static const u16 nws_prty1_k2_attn_idx[4] = {
12429 static struct attn_hw_reg nws_prty1_k2 = {
12430 0, 4, nws_prty1_k2_attn_idx, 0x700200, 0x70020c, 0x700208, 0x700204
12433 static struct attn_hw_reg *nws_prty_k2_regs[1] = {
12438 static const char *ms_int_attn_desc[1] = {
12439 "ms_address_error",
12442 #define ms_int_attn_desc OSAL_NULL
12445 static const u16 ms_int0_k2_attn_idx[1] = {
12449 static struct attn_hw_reg ms_int0_k2 = {
12450 0, 1, ms_int0_k2_attn_idx, 0x6a0180, 0x6a018c, 0x6a0188, 0x6a0184
12453 static struct attn_hw_reg *ms_int_k2_regs[1] = {
12457 static struct attn_hw_block attn_blocks[] = {
12458 {"grc", grc_int_attn_desc, grc_prty_attn_desc, {
12460 grc_int_bb_a0_regs,
12461 grc_prty_bb_a0_regs},
12463 grc_int_bb_b0_regs,
12464 grc_prty_bb_b0_regs},
12465 {1, 1, grc_int_k2_regs,
12466 grc_prty_k2_regs} } },
12467 {"miscs", miscs_int_attn_desc, miscs_prty_attn_desc, {
12470 miscs_int_bb_a0_regs,
12474 miscs_int_bb_b0_regs,
12476 miscs_prty_bb_b0_regs},
12481 miscs_prty_k2_regs } } },
12482 {"misc", misc_int_attn_desc, OSAL_NULL, {
12483 {1, 0, misc_int_bb_a0_regs,
12485 {1, 0, misc_int_bb_b0_regs,
12487 {1, 0, misc_int_k2_regs,
12489 {"dbu", OSAL_NULL, OSAL_NULL, {
12490 {0, 0, OSAL_NULL, OSAL_NULL},
12491 {0, 0, OSAL_NULL, OSAL_NULL},
12492 {0, 0, OSAL_NULL, OSAL_NULL } } },
12493 {"pglue_b", pglue_b_int_attn_desc, pglue_b_prty_attn_desc, {
12496 pglue_b_int_bb_a0_regs,
12498 pglue_b_prty_bb_a0_regs},
12501 pglue_b_int_bb_b0_regs,
12503 pglue_b_prty_bb_b0_regs},
12506 pglue_b_int_k2_regs,
12508 pglue_b_prty_k2_regs } } },
12509 {"cnig", cnig_int_attn_desc, cnig_prty_attn_desc, {
12511 cnig_int_bb_a0_regs,
12514 cnig_int_bb_b0_regs,
12516 cnig_prty_bb_b0_regs},
12520 cnig_prty_k2_regs } } },
12521 {"cpmu", cpmu_int_attn_desc, OSAL_NULL, {
12522 {1, 0, cpmu_int_bb_a0_regs,
12524 {1, 0, cpmu_int_bb_b0_regs,
12526 {1, 0, cpmu_int_k2_regs,
12528 {"ncsi", ncsi_int_attn_desc, ncsi_prty_attn_desc, {
12530 ncsi_int_bb_a0_regs,
12532 ncsi_prty_bb_a0_regs},
12534 ncsi_int_bb_b0_regs,
12536 ncsi_prty_bb_b0_regs},
12540 ncsi_prty_k2_regs } } },
12541 {"opte", OSAL_NULL, opte_prty_attn_desc, {
12543 opte_prty_bb_a0_regs},
12545 opte_prty_bb_b0_regs},
12547 opte_prty_k2_regs } } },
12548 {"bmb", bmb_int_attn_desc, bmb_prty_attn_desc, {
12550 bmb_int_bb_a0_regs,
12551 bmb_prty_bb_a0_regs},
12553 bmb_int_bb_b0_regs,
12554 bmb_prty_bb_b0_regs},
12555 {12, 3, bmb_int_k2_regs,
12556 bmb_prty_k2_regs } } },
12557 {"pcie", pcie_int_attn_desc, pcie_prty_attn_desc, {
12560 pcie_prty_bb_a0_regs},
12563 pcie_prty_bb_b0_regs},
12567 pcie_prty_k2_regs } } },
12568 {"mcp", OSAL_NULL, OSAL_NULL, {
12569 {0, 0, OSAL_NULL, OSAL_NULL},
12570 {0, 0, OSAL_NULL, OSAL_NULL},
12571 {0, 0, OSAL_NULL, OSAL_NULL } } },
12572 {"mcp2", OSAL_NULL, mcp2_prty_attn_desc, {
12574 mcp2_prty_bb_a0_regs},
12576 mcp2_prty_bb_b0_regs},
12578 mcp2_prty_k2_regs } } },
12579 {"pswhst", pswhst_int_attn_desc, pswhst_prty_attn_desc, {
12582 pswhst_int_bb_a0_regs,
12584 pswhst_prty_bb_a0_regs},
12587 pswhst_int_bb_b0_regs,
12589 pswhst_prty_bb_b0_regs},
12592 pswhst_int_k2_regs,
12594 pswhst_prty_k2_regs } } },
12595 {"pswhst2", pswhst2_int_attn_desc, pswhst2_prty_attn_desc, {
12598 pswhst2_int_bb_a0_regs,
12602 pswhst2_int_bb_b0_regs,
12604 pswhst2_prty_bb_b0_regs},
12607 pswhst2_int_k2_regs,
12609 pswhst2_prty_k2_regs } } },
12610 {"pswrd", pswrd_int_attn_desc, pswrd_prty_attn_desc, {
12613 pswrd_int_bb_a0_regs,
12617 pswrd_int_bb_b0_regs,
12619 pswrd_prty_bb_b0_regs},
12624 pswrd_prty_k2_regs } } },
12625 {"pswrd2", pswrd2_int_attn_desc, pswrd2_prty_attn_desc, {
12628 pswrd2_int_bb_a0_regs,
12630 pswrd2_prty_bb_a0_regs},
12633 pswrd2_int_bb_b0_regs,
12635 pswrd2_prty_bb_b0_regs},
12638 pswrd2_int_k2_regs,
12640 pswrd2_prty_k2_regs } } },
12641 {"pswwr", pswwr_int_attn_desc, pswwr_prty_attn_desc, {
12644 pswwr_int_bb_a0_regs,
12648 pswwr_int_bb_b0_regs,
12650 pswwr_prty_bb_b0_regs},
12655 pswwr_prty_k2_regs } } },
12656 {"pswwr2", pswwr2_int_attn_desc, pswwr2_prty_attn_desc, {
12659 pswwr2_int_bb_a0_regs,
12661 pswwr2_prty_bb_a0_regs},
12664 pswwr2_int_bb_b0_regs,
12666 pswwr2_prty_bb_b0_regs},
12669 pswwr2_int_k2_regs,
12671 pswwr2_prty_k2_regs } } },
12672 {"pswrq", pswrq_int_attn_desc, pswrq_prty_attn_desc, {
12675 pswrq_int_bb_a0_regs,
12679 pswrq_int_bb_b0_regs,
12681 pswrq_prty_bb_b0_regs},
12686 pswrq_prty_k2_regs } } },
12687 {"pswrq2", pswrq2_int_attn_desc, pswrq2_prty_attn_desc, {
12690 pswrq2_int_bb_a0_regs,
12692 pswrq2_prty_bb_a0_regs},
12695 pswrq2_int_bb_b0_regs,
12697 pswrq2_prty_bb_b0_regs},
12700 pswrq2_int_k2_regs,
12702 pswrq2_prty_k2_regs } } },
12703 {"pglcs", pglcs_int_attn_desc, OSAL_NULL, {
12704 {1, 0, pglcs_int_bb_a0_regs,
12706 {1, 0, pglcs_int_bb_b0_regs,
12708 {1, 0, pglcs_int_k2_regs,
12710 {"dmae", dmae_int_attn_desc, dmae_prty_attn_desc, {
12712 dmae_int_bb_a0_regs,
12714 dmae_prty_bb_a0_regs},
12716 dmae_int_bb_b0_regs,
12718 dmae_prty_bb_b0_regs},
12722 dmae_prty_k2_regs } } },
12723 {"ptu", ptu_int_attn_desc, ptu_prty_attn_desc, {
12725 ptu_int_bb_a0_regs,
12726 ptu_prty_bb_a0_regs},
12728 ptu_int_bb_b0_regs,
12729 ptu_prty_bb_b0_regs},
12730 {1, 1, ptu_int_k2_regs,
12731 ptu_prty_k2_regs } } },
12732 {"tcm", tcm_int_attn_desc, tcm_prty_attn_desc, {
12734 tcm_int_bb_a0_regs,
12735 tcm_prty_bb_a0_regs},
12737 tcm_int_bb_b0_regs,
12738 tcm_prty_bb_b0_regs},
12739 {3, 2, tcm_int_k2_regs,
12740 tcm_prty_k2_regs } } },
12741 {"mcm", mcm_int_attn_desc, mcm_prty_attn_desc, {
12743 mcm_int_bb_a0_regs,
12744 mcm_prty_bb_a0_regs},
12746 mcm_int_bb_b0_regs,
12747 mcm_prty_bb_b0_regs},
12748 {3, 2, mcm_int_k2_regs,
12749 mcm_prty_k2_regs } } },
12750 {"ucm", ucm_int_attn_desc, ucm_prty_attn_desc, {
12752 ucm_int_bb_a0_regs,
12753 ucm_prty_bb_a0_regs},
12755 ucm_int_bb_b0_regs,
12756 ucm_prty_bb_b0_regs},
12757 {3, 2, ucm_int_k2_regs,
12758 ucm_prty_k2_regs } } },
12759 {"xcm", xcm_int_attn_desc, xcm_prty_attn_desc, {
12761 xcm_int_bb_a0_regs,
12762 xcm_prty_bb_a0_regs},
12764 xcm_int_bb_b0_regs,
12765 xcm_prty_bb_b0_regs},
12766 {3, 2, xcm_int_k2_regs,
12767 xcm_prty_k2_regs } } },
12768 {"ycm", ycm_int_attn_desc, ycm_prty_attn_desc, {
12770 ycm_int_bb_a0_regs,
12771 ycm_prty_bb_a0_regs},
12773 ycm_int_bb_b0_regs,
12774 ycm_prty_bb_b0_regs},
12775 {3, 2, ycm_int_k2_regs,
12776 ycm_prty_k2_regs } } },
12777 {"pcm", pcm_int_attn_desc, pcm_prty_attn_desc, {
12779 pcm_int_bb_a0_regs,
12780 pcm_prty_bb_a0_regs},
12782 pcm_int_bb_b0_regs,
12783 pcm_prty_bb_b0_regs},
12784 {3, 1, pcm_int_k2_regs,
12785 pcm_prty_k2_regs } } },
12786 {"qm", qm_int_attn_desc, qm_prty_attn_desc, {
12787 {1, 4, qm_int_bb_a0_regs,
12788 qm_prty_bb_a0_regs},
12789 {1, 4, qm_int_bb_b0_regs,
12790 qm_prty_bb_b0_regs},
12791 {1, 4, qm_int_k2_regs,
12792 qm_prty_k2_regs } } },
12793 {"tm", tm_int_attn_desc, tm_prty_attn_desc, {
12794 {2, 1, tm_int_bb_a0_regs,
12795 tm_prty_bb_a0_regs},
12796 {2, 1, tm_int_bb_b0_regs,
12797 tm_prty_bb_b0_regs},
12798 {2, 1, tm_int_k2_regs,
12799 tm_prty_k2_regs } } },
12800 {"dorq", dorq_int_attn_desc, dorq_prty_attn_desc, {
12802 dorq_int_bb_a0_regs,
12804 dorq_prty_bb_a0_regs},
12806 dorq_int_bb_b0_regs,
12808 dorq_prty_bb_b0_regs},
12812 dorq_prty_k2_regs } } },
12813 {"brb", brb_int_attn_desc, brb_prty_attn_desc, {
12815 brb_int_bb_a0_regs,
12816 brb_prty_bb_a0_regs},
12818 brb_int_bb_b0_regs,
12819 brb_prty_bb_b0_regs},
12820 {12, 3, brb_int_k2_regs,
12821 brb_prty_k2_regs } } },
12822 {"src", src_int_attn_desc, OSAL_NULL, {
12823 {1, 0, src_int_bb_a0_regs,
12825 {1, 0, src_int_bb_b0_regs,
12827 {1, 0, src_int_k2_regs,
12829 {"prs", prs_int_attn_desc, prs_prty_attn_desc, {
12831 prs_int_bb_a0_regs,
12832 prs_prty_bb_a0_regs},
12834 prs_int_bb_b0_regs,
12835 prs_prty_bb_b0_regs},
12836 {1, 3, prs_int_k2_regs,
12837 prs_prty_k2_regs } } },
12838 {"tsdm", tsdm_int_attn_desc, tsdm_prty_attn_desc, {
12840 tsdm_int_bb_a0_regs,
12842 tsdm_prty_bb_a0_regs},
12844 tsdm_int_bb_b0_regs,
12846 tsdm_prty_bb_b0_regs},
12850 tsdm_prty_k2_regs } } },
12851 {"msdm", msdm_int_attn_desc, msdm_prty_attn_desc, {
12853 msdm_int_bb_a0_regs,
12855 msdm_prty_bb_a0_regs},
12857 msdm_int_bb_b0_regs,
12859 msdm_prty_bb_b0_regs},
12863 msdm_prty_k2_regs } } },
12864 {"usdm", usdm_int_attn_desc, usdm_prty_attn_desc, {
12866 usdm_int_bb_a0_regs,
12868 usdm_prty_bb_a0_regs},
12870 usdm_int_bb_b0_regs,
12872 usdm_prty_bb_b0_regs},
12876 usdm_prty_k2_regs } } },
12877 {"xsdm", xsdm_int_attn_desc, xsdm_prty_attn_desc, {
12879 xsdm_int_bb_a0_regs,
12881 xsdm_prty_bb_a0_regs},
12883 xsdm_int_bb_b0_regs,
12885 xsdm_prty_bb_b0_regs},
12889 xsdm_prty_k2_regs } } },
12890 {"ysdm", ysdm_int_attn_desc, ysdm_prty_attn_desc, {
12892 ysdm_int_bb_a0_regs,
12894 ysdm_prty_bb_a0_regs},
12896 ysdm_int_bb_b0_regs,
12898 ysdm_prty_bb_b0_regs},
12902 ysdm_prty_k2_regs } } },
12903 {"psdm", psdm_int_attn_desc, psdm_prty_attn_desc, {
12905 psdm_int_bb_a0_regs,
12907 psdm_prty_bb_a0_regs},
12909 psdm_int_bb_b0_regs,
12911 psdm_prty_bb_b0_regs},
12915 psdm_prty_k2_regs } } },
12916 {"tsem", tsem_int_attn_desc, tsem_prty_attn_desc, {
12918 tsem_int_bb_a0_regs,
12920 tsem_prty_bb_a0_regs},
12922 tsem_int_bb_b0_regs,
12924 tsem_prty_bb_b0_regs},
12928 tsem_prty_k2_regs } } },
12929 {"msem", msem_int_attn_desc, msem_prty_attn_desc, {
12931 msem_int_bb_a0_regs,
12933 msem_prty_bb_a0_regs},
12935 msem_int_bb_b0_regs,
12937 msem_prty_bb_b0_regs},
12941 msem_prty_k2_regs } } },
12942 {"usem", usem_int_attn_desc, usem_prty_attn_desc, {
12944 usem_int_bb_a0_regs,
12946 usem_prty_bb_a0_regs},
12948 usem_int_bb_b0_regs,
12950 usem_prty_bb_b0_regs},
12954 usem_prty_k2_regs } } },
12955 {"xsem", xsem_int_attn_desc, xsem_prty_attn_desc, {
12957 xsem_int_bb_a0_regs,
12959 xsem_prty_bb_a0_regs},
12961 xsem_int_bb_b0_regs,
12963 xsem_prty_bb_b0_regs},
12967 xsem_prty_k2_regs } } },
12968 {"ysem", ysem_int_attn_desc, ysem_prty_attn_desc, {
12970 ysem_int_bb_a0_regs,
12972 ysem_prty_bb_a0_regs},
12974 ysem_int_bb_b0_regs,
12976 ysem_prty_bb_b0_regs},
12980 ysem_prty_k2_regs } } },
12981 {"psem", psem_int_attn_desc, psem_prty_attn_desc, {
12983 psem_int_bb_a0_regs,
12985 psem_prty_bb_a0_regs},
12987 psem_int_bb_b0_regs,
12989 psem_prty_bb_b0_regs},
12993 psem_prty_k2_regs } } },
12994 {"rss", rss_int_attn_desc, rss_prty_attn_desc, {
12996 rss_int_bb_a0_regs,
12997 rss_prty_bb_a0_regs},
12999 rss_int_bb_b0_regs,
13000 rss_prty_bb_b0_regs},
13001 {1, 1, rss_int_k2_regs,
13002 rss_prty_k2_regs } } },
13003 {"tmld", tmld_int_attn_desc, tmld_prty_attn_desc, {
13005 tmld_int_bb_a0_regs,
13007 tmld_prty_bb_a0_regs},
13009 tmld_int_bb_b0_regs,
13011 tmld_prty_bb_b0_regs},
13015 tmld_prty_k2_regs } } },
13016 {"muld", muld_int_attn_desc, muld_prty_attn_desc, {
13018 muld_int_bb_a0_regs,
13020 muld_prty_bb_a0_regs},
13022 muld_int_bb_b0_regs,
13024 muld_prty_bb_b0_regs},
13028 muld_prty_k2_regs } } },
13029 {"yuld", yuld_int_attn_desc, yuld_prty_attn_desc, {
13031 yuld_int_bb_a0_regs,
13033 yuld_prty_bb_a0_regs},
13035 yuld_int_bb_b0_regs,
13037 yuld_prty_bb_b0_regs},
13041 yuld_prty_k2_regs } } },
13042 {"xyld", xyld_int_attn_desc, xyld_prty_attn_desc, {
13044 xyld_int_bb_a0_regs,
13046 xyld_prty_bb_a0_regs},
13048 xyld_int_bb_b0_regs,
13050 xyld_prty_bb_b0_regs},
13054 xyld_prty_k2_regs } } },
13055 {"prm", prm_int_attn_desc, prm_prty_attn_desc, {
13057 prm_int_bb_a0_regs,
13058 prm_prty_bb_a0_regs},
13060 prm_int_bb_b0_regs,
13061 prm_prty_bb_b0_regs},
13062 {1, 2, prm_int_k2_regs,
13063 prm_prty_k2_regs } } },
13064 {"pbf_pb1", pbf_pb1_int_attn_desc, pbf_pb1_prty_attn_desc, {
13067 pbf_pb1_int_bb_a0_regs,
13071 pbf_pb1_int_bb_b0_regs,
13073 pbf_pb1_prty_bb_b0_regs},
13076 pbf_pb1_int_k2_regs,
13078 pbf_pb1_prty_k2_regs } } },
13079 {"pbf_pb2", pbf_pb2_int_attn_desc, pbf_pb2_prty_attn_desc, {
13082 pbf_pb2_int_bb_a0_regs,
13086 pbf_pb2_int_bb_b0_regs,
13088 pbf_pb2_prty_bb_b0_regs},
13091 pbf_pb2_int_k2_regs,
13093 pbf_pb2_prty_k2_regs } } },
13094 {"rpb", rpb_int_attn_desc, rpb_prty_attn_desc, {
13096 rpb_int_bb_a0_regs,
13099 rpb_int_bb_b0_regs,
13100 rpb_prty_bb_b0_regs},
13101 {1, 1, rpb_int_k2_regs,
13102 rpb_prty_k2_regs } } },
13103 {"btb", btb_int_attn_desc, btb_prty_attn_desc, {
13105 btb_int_bb_a0_regs,
13106 btb_prty_bb_a0_regs},
13108 btb_int_bb_b0_regs,
13109 btb_prty_bb_b0_regs},
13110 {11, 2, btb_int_k2_regs,
13111 btb_prty_k2_regs } } },
13112 {"pbf", pbf_int_attn_desc, pbf_prty_attn_desc, {
13114 pbf_int_bb_a0_regs,
13115 pbf_prty_bb_a0_regs},
13117 pbf_int_bb_b0_regs,
13118 pbf_prty_bb_b0_regs},
13119 {1, 3, pbf_int_k2_regs,
13120 pbf_prty_k2_regs } } },
13121 {"rdif", rdif_int_attn_desc, rdif_prty_attn_desc, {
13123 rdif_int_bb_a0_regs,
13126 rdif_int_bb_b0_regs,
13128 rdif_prty_bb_b0_regs},
13132 rdif_prty_k2_regs } } },
13133 {"tdif", tdif_int_attn_desc, tdif_prty_attn_desc, {
13135 tdif_int_bb_a0_regs,
13137 tdif_prty_bb_a0_regs},
13139 tdif_int_bb_b0_regs,
13141 tdif_prty_bb_b0_regs},
13145 tdif_prty_k2_regs } } },
13146 {"cdu", cdu_int_attn_desc, cdu_prty_attn_desc, {
13148 cdu_int_bb_a0_regs,
13149 cdu_prty_bb_a0_regs},
13151 cdu_int_bb_b0_regs,
13152 cdu_prty_bb_b0_regs},
13153 {1, 1, cdu_int_k2_regs,
13154 cdu_prty_k2_regs } } },
13155 {"ccfc", ccfc_int_attn_desc, ccfc_prty_attn_desc, {
13157 ccfc_int_bb_a0_regs,
13159 ccfc_prty_bb_a0_regs},
13161 ccfc_int_bb_b0_regs,
13163 ccfc_prty_bb_b0_regs},
13167 ccfc_prty_k2_regs } } },
13168 {"tcfc", tcfc_int_attn_desc, tcfc_prty_attn_desc, {
13170 tcfc_int_bb_a0_regs,
13172 tcfc_prty_bb_a0_regs},
13174 tcfc_int_bb_b0_regs,
13176 tcfc_prty_bb_b0_regs},
13180 tcfc_prty_k2_regs } } },
13181 {"igu", igu_int_attn_desc, igu_prty_attn_desc, {
13183 igu_int_bb_a0_regs,
13184 igu_prty_bb_a0_regs},
13186 igu_int_bb_b0_regs,
13187 igu_prty_bb_b0_regs},
13188 {1, 2, igu_int_k2_regs,
13189 igu_prty_k2_regs } } },
13190 {"cau", cau_int_attn_desc, cau_prty_attn_desc, {
13192 cau_int_bb_a0_regs,
13193 cau_prty_bb_a0_regs},
13195 cau_int_bb_b0_regs,
13196 cau_prty_bb_b0_regs},
13197 {1, 1, cau_int_k2_regs,
13198 cau_prty_k2_regs } } },
13199 {"umac", umac_int_attn_desc, OSAL_NULL, {
13200 {0, 0, OSAL_NULL, OSAL_NULL},
13201 {0, 0, OSAL_NULL, OSAL_NULL},
13202 {1, 0, umac_int_k2_regs,
13204 {"xmac", OSAL_NULL, OSAL_NULL, {
13205 {0, 0, OSAL_NULL, OSAL_NULL},
13206 {0, 0, OSAL_NULL, OSAL_NULL},
13207 {0, 0, OSAL_NULL, OSAL_NULL } } },
13208 {"dbg", dbg_int_attn_desc, dbg_prty_attn_desc, {
13210 dbg_int_bb_a0_regs,
13211 dbg_prty_bb_a0_regs},
13213 dbg_int_bb_b0_regs,
13214 dbg_prty_bb_b0_regs},
13215 {1, 1, dbg_int_k2_regs,
13216 dbg_prty_k2_regs } } },
13217 {"nig", nig_int_attn_desc, nig_prty_attn_desc, {
13219 nig_int_bb_a0_regs,
13220 nig_prty_bb_a0_regs},
13222 nig_int_bb_b0_regs,
13223 nig_prty_bb_b0_regs},
13224 {10, 5, nig_int_k2_regs,
13225 nig_prty_k2_regs } } },
13226 {"wol", wol_int_attn_desc, wol_prty_attn_desc, {
13231 {1, 1, wol_int_k2_regs,
13232 wol_prty_k2_regs } } },
13233 {"bmbn", bmbn_int_attn_desc, OSAL_NULL, {
13234 {0, 0, OSAL_NULL, OSAL_NULL},
13235 {0, 0, OSAL_NULL, OSAL_NULL},
13236 {1, 0, bmbn_int_k2_regs,
13238 {"ipc", ipc_int_attn_desc, ipc_prty_attn_desc, {
13240 ipc_int_bb_a0_regs,
13241 ipc_prty_bb_a0_regs},
13243 ipc_int_bb_b0_regs,
13244 ipc_prty_bb_b0_regs},
13245 {1, 0, ipc_int_k2_regs,
13247 {"nwm", nwm_int_attn_desc, nwm_prty_attn_desc, {
13252 {1, 3, nwm_int_k2_regs,
13253 nwm_prty_k2_regs } } },
13254 {"nws", nws_int_attn_desc, nws_prty_attn_desc, {
13259 {4, 1, nws_int_k2_regs,
13260 nws_prty_k2_regs } } },
13261 {"ms", ms_int_attn_desc, OSAL_NULL, {
13262 {0, 0, OSAL_NULL, OSAL_NULL},
13263 {0, 0, OSAL_NULL, OSAL_NULL},
13264 {1, 0, ms_int_k2_regs,
13266 {"phy_pcie", OSAL_NULL, OSAL_NULL, {
13267 {0, 0, OSAL_NULL, OSAL_NULL},
13268 {0, 0, OSAL_NULL, OSAL_NULL},
13269 {0, 0, OSAL_NULL, OSAL_NULL } } },
13270 {"misc_aeu", OSAL_NULL, OSAL_NULL, {
13271 {0, 0, OSAL_NULL, OSAL_NULL},
13272 {0, 0, OSAL_NULL, OSAL_NULL},
13273 {0, 0, OSAL_NULL, OSAL_NULL } } },
13274 {"bar0_map", OSAL_NULL, OSAL_NULL, {
13275 {0, 0, OSAL_NULL, OSAL_NULL},
13276 {0, 0, OSAL_NULL, OSAL_NULL},
13277 {0, 0, OSAL_NULL, OSAL_NULL } } },
13280 #define NUM_INT_REGS 423
13281 #define NUM_PRTY_REGS 378
13283 #endif /* __PREVENT_INT_ATTN__ */
13285 #endif /* __ATTN_VALUES_H__ */