2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_hsi_common.h"
12 #include "ecore_hsi_eth.h"
13 #include "ecore_rt_defs.h"
14 #include "ecore_status.h"
16 #include "ecore_init_ops.h"
17 #include "ecore_init_fw_funcs.h"
18 #include "ecore_cxt.h"
20 #include "ecore_dev_api.h"
22 /* Max number of connection types in HW (DQ/CDU etc.) */
23 #define MAX_CONN_TYPES PROTOCOLID_COMMON
24 #define NUM_TASK_TYPES 2
25 #define NUM_TASK_PF_SEGMENTS 4
26 #define NUM_TASK_VF_SEGMENTS 1
28 /* Doorbell-Queue constants */
29 #define DQ_RANGE_SHIFT 4
30 #define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT)
32 /* Searcher constants */
33 #define SRC_MIN_NUM_ELEMS 256
35 /* Timers constants */
37 #define TM_ALIGN (1 << TM_SHIFT)
38 #define TM_ELEM_SIZE 4
41 /* If for some reason, HW P size is modified to be less than 32K,
42 * special handling needs to be made for CDU initialization
44 #define ILT_DEFAULT_HW_P_SIZE 3
46 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
47 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
49 /* ILT entry structure */
50 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
51 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
52 #define ILT_ENTRY_VALID_MASK 0x1ULL
53 #define ILT_ENTRY_VALID_SHIFT 52
54 #define ILT_ENTRY_IN_REGS 2
55 #define ILT_REG_SIZE_IN_BYTES 4
57 /* connection context union */
59 struct core_conn_context core_ctx;
60 struct eth_conn_context eth_ctx;
68 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
69 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
71 #define CONN_CXT_SIZE(p_hwfn) \
72 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
74 /* PF per protocl configuration object */
75 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
76 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
78 struct ecore_tid_seg {
84 struct ecore_conn_type_cfg {
88 struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
91 /* ILT Client configuration,
92 * Per connection type (protocol) resources (cids, tis, vf cids etc.)
93 * 1 - for connection context (CDUC) and for each task context we need two
94 * values, for regular task context and for force load memory
96 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
97 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
99 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
100 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS)
111 struct ilt_cfg_pair {
116 struct ecore_ilt_cli_blk {
117 u32 total_size; /* 0 means not active */
118 u32 real_size_in_page;
120 u32 dynamic_line_cnt;
123 struct ecore_ilt_client_cfg {
127 struct ilt_cfg_pair first;
128 struct ilt_cfg_pair last;
129 struct ilt_cfg_pair p_size;
131 /* ILT client blocks for PF */
132 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
135 /* ILT client blocks for VFs */
136 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
142 * Protocol acquired CID lists
143 * PF start line in ILT
145 struct ecore_dma_mem {
151 #define MAP_WORD_SIZE sizeof(unsigned long)
152 #define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8)
154 struct ecore_cid_acquired_map {
157 unsigned long *cid_map;
160 struct ecore_cxt_mngr {
161 /* Per protocl configuration */
162 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
164 /* computed ILT structure */
165 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
167 /* Task type sizes */
168 u32 task_type_size[NUM_TASK_TYPES];
170 /* total number of VFs for this hwfn -
171 * ALL VFs are symmetric in terms of HW resources
176 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
178 /* ILT shadow table */
179 struct ecore_dma_mem *ilt_shadow;
183 struct ecore_dma_mem *t2;
189 /* check if resources/configuration is required according to protocol type */
190 static OSAL_INLINE bool src_proto(enum protocol_type type)
192 return type == PROTOCOLID_TOE;
195 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
197 return type == PROTOCOLID_TOE;
200 /* counts the iids for the CDU/CDUC ILT client configuration */
201 struct ecore_cdu_iids {
206 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
207 struct ecore_cdu_iids *iids)
211 for (type = 0; type < MAX_CONN_TYPES; type++) {
212 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
213 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
217 /* counts the iids for the Searcher block configuration */
218 struct ecore_src_iids {
223 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
224 struct ecore_src_iids *iids)
228 for (i = 0; i < MAX_CONN_TYPES; i++) {
232 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
233 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
237 /* counts the iids for the Timers block configuration */
238 struct ecore_tm_iids {
240 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
246 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
247 struct ecore_tm_iids *iids)
251 for (i = 0; i < MAX_CONN_TYPES; i++) {
252 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
254 if (tm_cid_proto(i)) {
255 iids->pf_cids += p_cfg->cid_count;
256 iids->per_vf_cids += p_cfg->cids_per_vf;
260 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
261 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
262 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
264 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
265 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
266 iids->pf_tids_total += iids->pf_tids[j];
270 void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids)
272 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
273 struct ecore_tid_seg *segs;
274 u32 vf_cids = 0, type, j;
277 for (type = 0; type < MAX_CONN_TYPES; type++) {
278 iids->cids += p_mngr->conn_cfg[type].cid_count;
279 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
281 segs = p_mngr->conn_cfg[type].tid_seg;
282 /* for each segment there is at most one
283 * protocol for which count is not 0.
285 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
286 iids->tids += segs[j].count;
288 /* The last array elelment is for the VFs. As for PF
289 * segments there can be only one protocol for
290 * which this value is not 0.
292 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
295 iids->vf_cids += vf_cids * p_mngr->vf_count;
296 iids->tids += vf_tids * p_mngr->vf_count;
298 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
299 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
300 iids->cids, iids->vf_cids, iids->tids, vf_tids);
303 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
306 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
309 /* Find the protocol with tid count > 0 for this segment.
310 * Note: there can only be one and this is already validated.
312 for (i = 0; i < MAX_CONN_TYPES; i++) {
313 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
314 return &p_cfg->conn_cfg[i].tid_seg[seg];
319 /* set the iids (cid/tid) count per protocol */
320 void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
321 enum protocol_type type,
322 u32 cid_count, u32 vf_cid_cnt)
324 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
325 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
327 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
328 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
331 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
332 enum protocol_type type, u32 *vf_cid)
335 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
337 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
340 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
341 enum protocol_type type)
343 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
346 static u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
347 enum protocol_type type)
352 for (i = 0; i < TASK_SEGMENTS; i++)
353 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
358 static OSAL_INLINE void
359 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
360 enum protocol_type proto,
361 u8 seg, u8 seg_type, u32 count, bool has_fl)
363 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
364 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
366 p_seg->count = count;
367 p_seg->has_fl_mem = has_fl;
368 p_seg->type = seg_type;
371 /* the *p_line parameter must be either 0 for the first invocation or the
372 * value returned in the previous invocation.
374 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
375 struct ecore_ilt_cli_blk *p_blk,
377 u32 total_size, u32 elem_size)
379 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
381 /* verfiy called once for each block */
382 if (p_blk->total_size)
385 p_blk->total_size = total_size;
386 p_blk->real_size_in_page = 0;
388 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
389 p_blk->start_line = start_line;
392 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
393 struct ecore_ilt_client_cfg *p_cli,
394 struct ecore_ilt_cli_blk *p_blk,
395 u32 *p_line, enum ilt_clients client_id)
397 if (!p_blk->total_size)
401 p_cli->first.val = *p_line;
403 p_cli->active = true;
404 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
405 p_cli->last.val = *p_line - 1;
407 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
408 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
409 client_id, p_cli->first.val, p_cli->last.val,
410 p_blk->total_size, p_blk->real_size_in_page,
414 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
415 enum ilt_clients ilt_client)
417 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
418 struct ecore_ilt_client_cfg *p_cli;
419 u32 lines_to_skip = 0;
422 /* TBD MK: ILT code should be simplified once PROTO enum is changed */
424 if (ilt_client == ILT_CLI_CDUC) {
425 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
427 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
428 (u32)CONN_CXT_SIZE(p_hwfn);
430 lines_to_skip = cid_count / cxts_per_p;
433 return lines_to_skip;
436 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
438 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
439 u32 curr_line, total, i, task_size, line;
440 struct ecore_ilt_client_cfg *p_cli;
441 struct ecore_ilt_cli_blk *p_blk;
442 struct ecore_cdu_iids cdu_iids;
443 struct ecore_src_iids src_iids;
444 struct ecore_qm_iids qm_iids;
445 struct ecore_tm_iids tm_iids;
446 struct ecore_tid_seg *p_seg;
448 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
449 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
450 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
451 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
453 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
455 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
456 "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
457 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
460 p_cli = &p_mngr->clients[ILT_CLI_CDUC];
462 curr_line = p_mngr->pf_start_line;
465 p_cli->pf_total_lines = 0;
467 /* get the counters for the CDUC,CDUC and QM clients */
468 ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
470 p_blk = &p_cli->pf_blks[CDUC_BLK];
472 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
474 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
475 total, CONN_CXT_SIZE(p_hwfn));
477 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
478 p_cli->pf_total_lines = curr_line - p_blk->start_line;
480 p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
484 p_blk = &p_cli->vf_blks[CDUC_BLK];
485 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
487 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
488 total, CONN_CXT_SIZE(p_hwfn));
490 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
491 p_cli->vf_total_lines = curr_line - p_blk->start_line;
493 for (i = 1; i < p_mngr->vf_count; i++)
494 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
498 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
499 p_cli->first.val = curr_line;
501 /* first the 'working' task memory */
502 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
503 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
504 if (!p_seg || p_seg->count == 0)
507 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
508 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
509 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
510 p_mngr->task_type_size[p_seg->type]);
512 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
516 /* next the 'init' task memory (forced load memory) */
517 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
518 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
519 if (!p_seg || p_seg->count == 0)
522 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
524 if (!p_seg->has_fl_mem) {
525 /* The segment is active (total size pf 'working'
526 * memory is > 0) but has no FL (forced-load, Init)
529 * 1. The total-size in the corrsponding FL block of
530 * the ILT client is set to 0 - No ILT line are
531 * provisioned and no ILT memory allocated.
533 * 2. The start-line of said block is set to the
534 * start line of the matching working memory
535 * block in the ILT client. This is later used to
536 * configure the CDU segment offset registers and
537 * results in an FL command for TIDs of this
538 * segment behaves as regular load commands
539 * (loading TIDs from the working memory).
541 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
543 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
546 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
548 ecore_ilt_cli_blk_fill(p_cli, p_blk,
550 p_mngr->task_type_size[p_seg->type]);
552 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
555 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
558 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
559 if (p_seg && p_seg->count) {
560 /* Stricly speaking we need to iterate over all VF
561 * task segment types, but a VF has only 1 segment
564 /* 'working' memory */
565 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
567 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
568 ecore_ilt_cli_blk_fill(p_cli, p_blk,
570 p_mngr->task_type_size[p_seg->type]);
572 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
576 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
577 if (!p_seg->has_fl_mem) {
578 /* see comment above */
579 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
580 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
582 task_size = p_mngr->task_type_size[p_seg->type];
583 ecore_ilt_cli_blk_fill(p_cli, p_blk,
584 curr_line, total, task_size);
585 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
588 p_cli->vf_total_lines = curr_line -
589 p_cli->vf_blks[0].start_line;
591 /* Now for the rest of the VFs */
592 for (i = 1; i < p_mngr->vf_count; i++) {
593 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
594 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
597 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
598 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
604 p_cli = &p_mngr->clients[ILT_CLI_QM];
605 p_blk = &p_cli->pf_blks[0];
607 ecore_cxt_qm_iids(p_hwfn, &qm_iids);
608 total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
609 qm_iids.vf_cids, qm_iids.tids,
610 p_hwfn->qm_info.num_pqs,
611 p_hwfn->qm_info.num_vf_pqs);
613 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
614 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
615 " num_vf_pqs=%d, memory_size=%d)\n",
616 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
617 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
619 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
622 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
623 p_cli->pf_total_lines = curr_line - p_blk->start_line;
626 p_cli = &p_mngr->clients[ILT_CLI_SRC];
627 ecore_cxt_src_iids(p_mngr, &src_iids);
629 /* Both the PF and VFs searcher connections are stored in the per PF
630 * database. Thus sum the PF searcher cids and all the VFs searcher
633 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
635 u32 local_max = OSAL_MAX_T(u32, total,
638 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
640 p_blk = &p_cli->pf_blks[0];
641 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
642 total * sizeof(struct src_ent),
643 sizeof(struct src_ent));
645 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
647 p_cli->pf_total_lines = curr_line - p_blk->start_line;
651 p_cli = &p_mngr->clients[ILT_CLI_TM];
652 ecore_cxt_tm_iids(p_mngr, &tm_iids);
653 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
655 p_blk = &p_cli->pf_blks[0];
656 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
657 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
659 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
661 p_cli->pf_total_lines = curr_line - p_blk->start_line;
665 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
667 p_blk = &p_cli->vf_blks[0];
668 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
669 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
671 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
673 p_cli->pf_total_lines = curr_line - p_blk->start_line;
675 for (i = 1; i < p_mngr->vf_count; i++) {
676 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
681 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
682 RESC_NUM(p_hwfn, ECORE_ILT)) {
683 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
684 curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
688 return ECORE_SUCCESS;
691 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
693 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
699 for (i = 0; i < p_mngr->t2_num_pages; i++)
700 if (p_mngr->t2[i].p_virt)
701 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
702 p_mngr->t2[i].p_virt,
703 p_mngr->t2[i].p_phys,
706 OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
707 p_mngr->t2 = OSAL_NULL;
710 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
712 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
713 u32 conn_num, total_size, ent_per_page, psz, i;
714 struct ecore_ilt_client_cfg *p_src;
715 struct ecore_src_iids src_iids;
716 struct ecore_dma_mem *p_t2;
717 enum _ecore_status_t rc;
719 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
721 /* if the SRC ILT client is inactive - there are no connection
722 * requiring the searcer, leave.
724 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
726 return ECORE_SUCCESS;
728 ecore_cxt_src_iids(p_mngr, &src_iids);
729 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
730 total_size = conn_num * sizeof(struct src_ent);
732 /* use the same page size as the SRC ILT client */
733 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
734 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
737 p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
738 p_mngr->t2_num_pages *
739 sizeof(struct ecore_dma_mem));
741 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
746 /* allocate t2 pages */
747 for (i = 0; i < p_mngr->t2_num_pages; i++) {
748 u32 size = OSAL_MIN_T(u32, total_size, psz);
749 void **p_virt = &p_mngr->t2[i].p_virt;
751 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
752 &p_mngr->t2[i].p_phys, size);
753 if (!p_mngr->t2[i].p_virt) {
757 OSAL_MEM_ZERO(*p_virt, size);
758 p_mngr->t2[i].size = size;
762 /* Set the t2 pointers */
764 /* entries per page - must be a power of two */
765 ent_per_page = psz / sizeof(struct src_ent);
767 p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
769 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
770 p_mngr->last_free = (u64)p_t2->p_phys +
771 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
773 for (i = 0; i < p_mngr->t2_num_pages; i++) {
774 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
775 struct src_ent *entries = p_mngr->t2[i].p_virt;
776 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
779 for (j = 0; j < ent_num - 1; j++) {
780 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
781 entries[j].next = OSAL_CPU_TO_BE64(val);
784 if (i < p_mngr->t2_num_pages - 1)
785 val = (u64)p_mngr->t2[i + 1].p_phys;
788 entries[j].next = OSAL_CPU_TO_BE64(val);
790 conn_num -= ent_per_page;
793 return ECORE_SUCCESS;
796 ecore_cxt_src_t2_free(p_hwfn);
800 /* Total number of ILT lines used by this PF */
801 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
806 for (i = 0; i < ILT_CLI_MAX; i++)
807 if (!ilt_clients[i].active)
810 size += (ilt_clients[i].last.val -
811 ilt_clients[i].first.val + 1);
816 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
818 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
819 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
822 ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
824 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
825 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
828 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
830 p_dma->p_phys, p_dma->size);
831 p_dma->p_virt = OSAL_NULL;
833 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
836 static enum _ecore_status_t
837 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
838 struct ecore_ilt_cli_blk *p_blk,
839 enum ilt_clients ilt_client, u32 start_line_offset)
841 struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
842 u32 lines, line, sz_left, lines_to_skip = 0;
844 /* Special handling for RoCE that supports dynamic allocation */
845 if (ilt_client == ILT_CLI_CDUT)
846 return ECORE_SUCCESS;
848 lines_to_skip = p_blk->dynamic_line_cnt;
850 if (!p_blk->total_size)
851 return ECORE_SUCCESS;
853 sz_left = p_blk->total_size;
854 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
855 line = p_blk->start_line + start_line_offset -
856 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
858 for (; lines; lines--) {
863 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
866 #define ILT_BLOCK_ALIGN_SIZE 0x1000
867 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
869 ILT_BLOCK_ALIGN_SIZE);
872 OSAL_MEM_ZERO(p_virt, size);
874 ilt_shadow[line].p_phys = p_phys;
875 ilt_shadow[line].p_virt = p_virt;
876 ilt_shadow[line].size = size;
878 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
879 "ILT shadow: Line [%d] Physical 0x%" PRIx64
880 " Virtual %p Size %d\n",
881 line, (u64)p_phys, p_virt, size);
887 return ECORE_SUCCESS;
890 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
892 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
893 struct ecore_ilt_client_cfg *clients = p_mngr->clients;
894 struct ecore_ilt_cli_blk *p_blk;
895 enum _ecore_status_t rc;
898 size = ecore_cxt_ilt_shadow_size(clients);
899 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
900 size * sizeof(struct ecore_dma_mem));
902 if (!p_mngr->ilt_shadow) {
903 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt shadow table");
905 goto ilt_shadow_fail;
908 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
909 "Allocated 0x%x bytes for ilt shadow\n",
910 (u32)(size * sizeof(struct ecore_dma_mem)));
912 for (i = 0; i < ILT_CLI_MAX; i++)
913 if (!clients[i].active) {
916 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
917 p_blk = &clients[i].pf_blks[j];
918 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
919 if (rc != ECORE_SUCCESS)
920 goto ilt_shadow_fail;
922 for (k = 0; k < p_mngr->vf_count; k++) {
923 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
924 u32 lines = clients[i].vf_total_lines * k;
926 p_blk = &clients[i].vf_blks[j];
927 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
929 if (rc != ECORE_SUCCESS)
930 goto ilt_shadow_fail;
935 return ECORE_SUCCESS;
938 ecore_ilt_shadow_free(p_hwfn);
942 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
944 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
947 for (type = 0; type < MAX_CONN_TYPES; type++) {
948 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
949 p_mngr->acquired[type].max_count = 0;
950 p_mngr->acquired[type].start_cid = 0;
954 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
956 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
960 for (type = 0; type < MAX_CONN_TYPES; type++) {
961 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
967 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD);
968 p_mngr->acquired[type].cid_map = OSAL_ZALLOC(p_hwfn->p_dev,
970 if (!p_mngr->acquired[type].cid_map)
973 p_mngr->acquired[type].max_count = cid_cnt;
974 p_mngr->acquired[type].start_cid = start_cid;
976 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
978 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
979 "Type %08x start: %08x count %08x\n",
980 type, p_mngr->acquired[type].start_cid,
981 p_mngr->acquired[type].max_count);
982 start_cid += cid_cnt;
985 return ECORE_SUCCESS;
988 ecore_cid_map_free(p_hwfn);
992 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
994 struct ecore_cxt_mngr *p_mngr;
997 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
999 DP_NOTICE(p_hwfn, true,
1000 "Failed to allocate `struct ecore_cxt_mngr'\n");
1004 /* Initialize ILT client registers */
1005 p_mngr->clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1006 p_mngr->clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1007 p_mngr->clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1009 p_mngr->clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1010 p_mngr->clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1011 p_mngr->clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1013 p_mngr->clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1014 p_mngr->clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1015 p_mngr->clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1017 p_mngr->clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1018 p_mngr->clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1019 p_mngr->clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1021 p_mngr->clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1022 p_mngr->clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1023 p_mngr->clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1025 /* default ILT page size for all clients is 32K */
1026 for (i = 0; i < ILT_CLI_MAX; i++)
1027 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1029 /* Initialize task sizes */
1030 p_mngr->task_type_size[0] = 512; /* @DPDK */
1031 p_mngr->task_type_size[1] = 128; /* @DPDK */
1033 p_mngr->vf_count = p_hwfn->p_dev->sriov_info.total_vfs;
1034 /* Set the cxt mangr pointer priori to further allocations */
1035 p_hwfn->p_cxt_mngr = p_mngr;
1037 return ECORE_SUCCESS;
1040 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1042 enum _ecore_status_t rc;
1044 /* Allocate the ILT shadow table */
1045 rc = ecore_ilt_shadow_alloc(p_hwfn);
1047 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1048 goto tables_alloc_fail;
1051 /* Allocate the T2 table */
1052 rc = ecore_cxt_src_t2_alloc(p_hwfn);
1054 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1055 goto tables_alloc_fail;
1058 /* Allocate and initialize the acquired cids bitmaps */
1059 rc = ecore_cid_map_alloc(p_hwfn);
1061 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1062 goto tables_alloc_fail;
1065 return ECORE_SUCCESS;
1068 ecore_cxt_mngr_free(p_hwfn);
1072 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1074 if (!p_hwfn->p_cxt_mngr)
1077 ecore_cid_map_free(p_hwfn);
1078 ecore_cxt_src_t2_free(p_hwfn);
1079 ecore_ilt_shadow_free(p_hwfn);
1080 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1082 p_hwfn->p_cxt_mngr = OSAL_NULL;
1085 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1087 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1090 /* Reset acquired cids */
1091 for (type = 0; type < MAX_CONN_TYPES; type++) {
1092 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1098 for (i = 0; i < DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD); i++)
1099 p_mngr->acquired[type].cid_map[i] = 0;
1103 /* HW initialization helper (per Block, per phase) */
1106 #define CDUC_CXT_SIZE_SHIFT \
1107 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1109 #define CDUC_CXT_SIZE_MASK \
1110 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1112 #define CDUC_BLOCK_WASTE_SHIFT \
1113 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1115 #define CDUC_BLOCK_WASTE_MASK \
1116 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1118 #define CDUC_NCIB_SHIFT \
1119 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1121 #define CDUC_NCIB_MASK \
1122 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1124 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1125 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1127 #define CDUT_TYPE0_CXT_SIZE_MASK \
1128 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1129 CDUT_TYPE0_CXT_SIZE_SHIFT)
1131 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1132 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1134 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1135 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1136 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1138 #define CDUT_TYPE0_NCIB_SHIFT \
1139 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1141 #define CDUT_TYPE0_NCIB_MASK \
1142 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1143 CDUT_TYPE0_NCIB_SHIFT)
1145 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1146 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1148 #define CDUT_TYPE1_CXT_SIZE_MASK \
1149 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1150 CDUT_TYPE1_CXT_SIZE_SHIFT)
1152 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1153 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1155 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1156 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1157 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1159 #define CDUT_TYPE1_NCIB_SHIFT \
1160 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1162 #define CDUT_TYPE1_NCIB_MASK \
1163 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1164 CDUT_TYPE1_NCIB_SHIFT)
1166 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1168 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1170 /* CDUC - connection configuration */
1171 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1172 cxt_size = CONN_CXT_SIZE(p_hwfn);
1173 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1174 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1176 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1177 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1178 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1179 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1181 /* CDUT - type-0 tasks configuration */
1182 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1183 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1184 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1185 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1187 /* cxt size and block-waste are multipes of 8 */
1189 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1190 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1191 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1192 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1194 /* CDUT - type-1 tasks configuration */
1195 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1196 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1197 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1199 /* cxt size and block-waste are multipes of 8 */
1201 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1202 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1203 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1204 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1208 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1209 #define CDU_SEG_REG_TYPE_MASK 0x1
1210 #define CDU_SEG_REG_OFFSET_SHIFT 0
1211 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1213 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1215 struct ecore_ilt_client_cfg *p_cli;
1216 struct ecore_tid_seg *p_seg;
1217 u32 cdu_seg_params, offset;
1220 static const u32 rt_type_offset_arr[] = {
1221 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1222 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1223 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1224 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1227 static const u32 rt_type_offset_fl_arr[] = {
1228 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1229 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1230 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1231 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1234 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1236 /* There are initializations only for CDUT during pf Phase */
1237 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1239 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1243 /* Note: start_line is already adjusted for the CDU
1244 * segment register granularity, so we just need to
1245 * divide. Adjustment is implicit as we assume ILT
1246 * Page size is larger than 32K!
1248 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1249 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1250 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1253 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1254 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1255 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1257 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1258 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1259 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1262 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1263 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1264 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1268 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1270 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1271 struct ecore_qm_iids iids;
1273 OSAL_MEM_ZERO(&iids, sizeof(iids));
1274 ecore_cxt_qm_iids(p_hwfn, &iids);
1276 ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1277 p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1278 p_hwfn->first_on_engine,
1279 iids.cids, iids.vf_cids, iids.tids,
1281 qm_info->num_pqs - qm_info->num_vf_pqs,
1282 qm_info->num_vf_pqs,
1283 qm_info->start_vport,
1284 qm_info->num_vports, qm_info->pf_wfq,
1285 qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1286 p_hwfn->qm_info.qm_vport_params);
1290 static enum _ecore_status_t ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1292 union ecore_qm_pq_params pq_params;
1295 /* XCM pure-LB queue */
1296 OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
1297 pq_params.core.tc = LB_TC;
1298 pq = ecore_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
1299 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq);
1301 return ECORE_SUCCESS;
1305 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1307 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1308 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1310 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1311 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1313 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1314 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1316 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1317 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1319 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1320 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1322 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1323 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1325 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1326 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1328 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1329 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1331 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1332 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1334 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1335 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1337 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1338 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1340 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1341 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1343 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1344 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1346 /* Connection types 6 & 7 are not in use, yet they must be configured
1347 * as the highest possible connection. Not configuring them means the
1348 * defaults will be used, and with a large number of cids a bug may
1349 * occur, if the defaults will be smaller than dq_pf_max_cid /
1352 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1353 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1355 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1356 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1359 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1361 struct ecore_ilt_client_cfg *ilt_clients;
1364 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1365 for (i = 0; i < ILT_CLI_MAX; i++)
1366 if (!ilt_clients[i].active) {
1369 STORE_RT_REG(p_hwfn,
1370 ilt_clients[i].first.reg,
1371 ilt_clients[i].first.val);
1372 STORE_RT_REG(p_hwfn,
1373 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1374 STORE_RT_REG(p_hwfn,
1375 ilt_clients[i].p_size.reg,
1376 ilt_clients[i].p_size.val);
1380 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1382 struct ecore_ilt_client_cfg *p_cli;
1385 /* For simplicty we set the 'block' to be an ILT page */
1386 STORE_RT_REG(p_hwfn,
1387 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1388 p_hwfn->hw_info.first_vf_in_pf);
1389 STORE_RT_REG(p_hwfn,
1390 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1391 p_hwfn->hw_info.first_vf_in_pf +
1392 p_hwfn->p_dev->sriov_info.total_vfs);
1394 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1395 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1396 if (p_cli->active) {
1397 STORE_RT_REG(p_hwfn,
1398 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1400 STORE_RT_REG(p_hwfn,
1401 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1402 p_cli->pf_total_lines);
1403 STORE_RT_REG(p_hwfn,
1404 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1405 p_cli->vf_total_lines);
1408 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1409 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1410 if (p_cli->active) {
1411 STORE_RT_REG(p_hwfn,
1412 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1414 STORE_RT_REG(p_hwfn,
1415 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1416 p_cli->pf_total_lines);
1417 STORE_RT_REG(p_hwfn,
1418 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1419 p_cli->vf_total_lines);
1422 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1423 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1424 if (p_cli->active) {
1425 STORE_RT_REG(p_hwfn,
1426 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1427 STORE_RT_REG(p_hwfn,
1428 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1429 p_cli->pf_total_lines);
1430 STORE_RT_REG(p_hwfn,
1431 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1432 p_cli->vf_total_lines);
1436 /* ILT (PSWRQ2) PF */
1437 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1439 struct ecore_ilt_client_cfg *clients;
1440 struct ecore_cxt_mngr *p_mngr;
1441 struct ecore_dma_mem *p_shdw;
1442 u32 line, rt_offst, i;
1444 ecore_ilt_bounds_init(p_hwfn);
1445 ecore_ilt_vf_bounds_init(p_hwfn);
1447 p_mngr = p_hwfn->p_cxt_mngr;
1448 p_shdw = p_mngr->ilt_shadow;
1449 clients = p_hwfn->p_cxt_mngr->clients;
1451 for (i = 0; i < ILT_CLI_MAX; i++)
1452 if (!clients[i].active) {
1455 /* Client's 1st val and RT array are absolute, ILT shadows'
1456 * lines are relative.
1458 line = clients[i].first.val - p_mngr->pf_start_line;
1459 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1460 clients[i].first.val * ILT_ENTRY_IN_REGS;
1462 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1463 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1464 u64 ilt_hw_entry = 0;
1466 /** p_virt could be OSAL_NULL incase of dynamic
1469 if (p_shdw[line].p_virt != OSAL_NULL) {
1470 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1471 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1472 (p_shdw[line].p_phys >> 12));
1474 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1475 "Setting RT[0x%08x] from"
1476 " ILT[0x%08x] [Client is %d] to"
1477 " Physical addr: 0x%" PRIx64 "\n",
1479 (u64)(p_shdw[line].p_phys >> 12));
1482 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1487 /* SRC (Searcher) PF */
1488 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1490 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1491 u32 rounded_conn_num, conn_num, conn_max;
1492 struct ecore_src_iids src_iids;
1494 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1495 ecore_cxt_src_iids(p_mngr, &src_iids);
1496 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1500 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1501 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1503 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1504 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1505 OSAL_LOG2(rounded_conn_num));
1507 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1508 p_hwfn->p_cxt_mngr->first_free);
1509 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1510 p_hwfn->p_cxt_mngr->last_free);
1514 #define TM_CFG_NUM_IDS_SHIFT 0
1515 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1516 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1517 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1518 #define TM_CFG_PARENT_PF_SHIFT 25
1519 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1521 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1522 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1524 #define TM_CFG_TID_OFFSET_SHIFT 30
1525 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1526 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1527 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1529 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1531 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1532 u32 active_seg_mask = 0, tm_offset, rt_reg;
1533 struct ecore_tm_iids tm_iids;
1537 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1538 ecore_cxt_tm_iids(p_mngr, &tm_iids);
1540 /* @@@TBD No pre-scan for now */
1542 /* Note: We assume consecutive VFs for a PF */
1543 for (i = 0; i < p_mngr->vf_count; i++) {
1545 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1546 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1547 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1548 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1550 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1551 (sizeof(cfg_word) / sizeof(u32)) *
1552 (p_hwfn->hw_info.first_vf_in_pf + i);
1553 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1557 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1558 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1559 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1560 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1562 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1563 (sizeof(cfg_word) / sizeof(u32)) *
1564 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1565 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1568 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1569 tm_iids.pf_cids ? 0x1 : 0x0);
1571 /* @@@TBD how to enable the scan for the VFs */
1573 tm_offset = tm_iids.per_vf_cids;
1575 /* Note: We assume consecutive VFs for a PF */
1576 for (i = 0; i < p_mngr->vf_count; i++) {
1578 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1579 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1580 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1581 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1582 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1584 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1585 (sizeof(cfg_word) / sizeof(u32)) *
1586 (p_hwfn->hw_info.first_vf_in_pf + i);
1588 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1591 tm_offset = tm_iids.pf_cids;
1592 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1594 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1595 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1596 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1597 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1598 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1600 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1601 (sizeof(cfg_word) / sizeof(u32)) *
1602 (NUM_OF_VFS(p_hwfn->p_dev) +
1603 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1605 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1606 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1608 tm_offset += tm_iids.pf_tids[i];
1611 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1613 /* @@@TBD how to enable the scan for the VFs */
1616 static void ecore_prs_init_common(struct ecore_hwfn *p_hwfn)
1620 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1622 /* CDU configuration */
1623 ecore_cdu_init_common(p_hwfn);
1624 ecore_prs_init_common(p_hwfn);
1627 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1629 ecore_qm_init_pf(p_hwfn);
1630 ecore_cm_init_pf(p_hwfn);
1631 ecore_dq_init_pf(p_hwfn);
1632 ecore_cdu_init_pf(p_hwfn);
1633 ecore_ilt_init_pf(p_hwfn);
1634 ecore_src_init_pf(p_hwfn);
1635 ecore_tm_init_pf(p_hwfn);
1638 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1639 enum protocol_type type, u32 *p_cid)
1641 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1644 if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1645 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1649 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_mngr->acquired[type].cid_map,
1650 p_mngr->acquired[type].max_count);
1652 if (rel_cid >= p_mngr->acquired[type].max_count) {
1653 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d",
1655 return ECORE_NORESOURCES;
1658 OSAL_SET_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1660 *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1662 return ECORE_SUCCESS;
1665 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1666 u32 cid, enum protocol_type *p_type)
1668 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1669 struct ecore_cid_acquired_map *p_map;
1670 enum protocol_type p;
1673 /* Iterate over protocols and find matching cid range */
1674 for (p = 0; p < MAX_CONN_TYPES; p++) {
1675 p_map = &p_mngr->acquired[p];
1677 if (!p_map->cid_map)
1679 if (cid >= p_map->start_cid &&
1680 cid < p_map->start_cid + p_map->max_count) {
1686 if (p == MAX_CONN_TYPES) {
1687 DP_NOTICE(p_hwfn, true, "Invalid CID %d", cid);
1690 rel_cid = cid - p_map->start_cid;
1691 if (!OSAL_TEST_BIT(rel_cid, p_map->cid_map)) {
1692 DP_NOTICE(p_hwfn, true, "CID %d not acquired", cid);
1698 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1700 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1701 enum protocol_type type;
1705 /* Test acquired and find matching per-protocol map */
1706 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, &type);
1711 rel_cid = cid - p_mngr->acquired[type].start_cid;
1712 OSAL_CLEAR_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1715 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1716 struct ecore_cxt_info *p_info)
1718 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1719 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1720 enum protocol_type type;
1723 /* Test acquired and find matching per-protocol map */
1724 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1729 /* set the protocl type */
1730 p_info->type = type;
1732 /* compute context virtual pointer */
1733 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1735 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1736 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1737 line = p_info->iid / cxts_per_p;
1739 /* Make sure context is allocated (dynamic allocation) */
1740 if (!p_mngr->ilt_shadow[line].p_virt)
1743 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1744 p_info->iid % cxts_per_p * conn_cxt_size;
1746 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1747 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1748 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1750 return ECORE_SUCCESS;
1753 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1755 /* Set the number of required CORE connections */
1756 u32 core_cids = 1; /* SPQ */
1758 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1760 switch (p_hwfn->hw_info.personality) {
1763 struct ecore_eth_pf_params *p_params =
1764 &p_hwfn->pf_params.eth_pf_params;
1766 ecore_cxt_set_proto_cid_count(p_hwfn,
1768 p_params->num_cons, 1); /* FIXME VF count... */
1776 return ECORE_SUCCESS;
1779 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
1780 struct ecore_tid_mem *p_info)
1782 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1783 u32 proto, seg, total_lines, i, shadow_line;
1784 struct ecore_ilt_client_cfg *p_cli;
1785 struct ecore_ilt_cli_blk *p_fl_seg;
1786 struct ecore_tid_seg *p_seg_info;
1788 /* Verify the personality */
1789 switch (p_hwfn->hw_info.personality) {
1794 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1798 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1799 if (!p_seg_info->has_fl_mem)
1802 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1803 total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1804 p_fl_seg->real_size_in_page);
1806 for (i = 0; i < total_lines; i++) {
1807 shadow_line = i + p_fl_seg->start_line -
1808 p_hwfn->p_cxt_mngr->pf_start_line;
1809 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1811 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1812 p_fl_seg->real_size_in_page;
1813 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1814 p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1817 return ECORE_SUCCESS;
1820 /* This function is very RoCE oriented, if another protocol in the future
1821 * will want this feature we'll need to modify the function to be more generic
1823 static enum _ecore_status_t
1824 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
1825 enum ecore_cxt_elem_type elem_type,
1826 u32 start_iid, u32 count)
1828 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
1829 u32 start_line, end_line, shadow_start_line, shadow_end_line;
1830 struct ecore_ilt_client_cfg *p_cli;
1831 struct ecore_ilt_cli_blk *p_blk;
1832 u32 end_iid = start_iid + count;
1833 struct ecore_ptt *p_ptt;
1834 u64 ilt_hw_entry = 0;
1837 if (elem_type == ECORE_ELEM_CXT) {
1838 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1839 elem_size = CONN_CXT_SIZE(p_hwfn);
1840 p_blk = &p_cli->pf_blks[CDUC_BLK];
1843 /* Calculate line in ilt */
1844 hw_p_size = p_cli->p_size.val;
1845 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1846 start_line = p_blk->start_line + (start_iid / elems_per_p);
1847 end_line = p_blk->start_line + (end_iid / elems_per_p);
1848 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
1851 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
1852 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
1854 p_ptt = ecore_ptt_acquire(p_hwfn);
1856 DP_NOTICE(p_hwfn, false,
1857 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
1858 return ECORE_TIMEOUT;
1861 for (i = shadow_start_line; i < shadow_end_line; i++) {
1862 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
1865 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1866 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
1867 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
1868 p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
1870 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
1871 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
1872 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
1874 /* compute absolute offset */
1875 reg_offset = PSWRQ2_REG_ILT_MEMORY +
1876 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
1879 ecore_wr(p_hwfn, p_ptt, reg_offset, U64_LO(ilt_hw_entry));
1880 ecore_wr(p_hwfn, p_ptt, reg_offset + ILT_REG_SIZE_IN_BYTES,
1881 U64_HI(ilt_hw_entry));
1884 ecore_ptt_release(p_hwfn, p_ptt);
1886 return ECORE_SUCCESS;
1889 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
1890 enum protocol_type proto)
1892 enum _ecore_status_t rc;
1895 /* Free Connection CXT */
1896 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
1897 ecore_cxt_get_proto_cid_start(p_hwfn,
1899 ecore_cxt_get_proto_cid_count(p_hwfn,
1907 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
1908 ecore_cxt_get_proto_tid_count(p_hwfn,
1914 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
1916 u8 ctx_type, void **pp_task_ctx)
1918 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1919 struct ecore_ilt_client_cfg *p_cli;
1920 struct ecore_ilt_cli_blk *p_seg;
1921 struct ecore_tid_seg *p_seg_info;
1924 u32 tid_size, ilt_idx;
1925 u32 num_tids_per_block;
1927 /* Verify the personality */
1928 switch (p_hwfn->hw_info.personality) {
1933 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1937 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1939 if (ctx_type == ECORE_CTX_WORKING_MEM) {
1940 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
1941 } else if (ctx_type == ECORE_CTX_FL_MEM) {
1942 if (!p_seg_info->has_fl_mem)
1944 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1948 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
1949 tid_size = p_mngr->task_type_size[p_seg_info->type];
1950 num_tids_per_block = p_seg->real_size_in_page / tid_size;
1952 if (total_lines < tid / num_tids_per_block)
1955 ilt_idx = tid / num_tids_per_block + p_seg->start_line -
1956 p_mngr->pf_start_line;
1957 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
1958 (tid % num_tids_per_block) * tid_size;
1960 return ECORE_SUCCESS;