2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "common_hsi.h"
12 #include "ecore_hsi_common.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_status.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_init_fw_funcs.h"
19 #include "ecore_cxt.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
23 #include "ecore_mcp.h"
25 /* Max number of connection types in HW (DQ/CDU etc.) */
26 #define MAX_CONN_TYPES PROTOCOLID_COMMON
27 #define NUM_TASK_TYPES 2
28 #define NUM_TASK_PF_SEGMENTS 4
29 #define NUM_TASK_VF_SEGMENTS 1
31 /* Doorbell-Queue constants */
32 #define DQ_RANGE_SHIFT 4
33 #define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT)
35 /* Searcher constants */
36 #define SRC_MIN_NUM_ELEMS 256
38 /* Timers constants */
40 #define TM_ALIGN (1 << TM_SHIFT)
41 #define TM_ELEM_SIZE 4
44 /* If for some reason, HW P size is modified to be less than 32K,
45 * special handling needs to be made for CDU initialization
47 #define ILT_DEFAULT_HW_P_SIZE 3
49 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
50 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
52 /* ILT entry structure */
53 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
54 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
55 #define ILT_ENTRY_VALID_MASK 0x1ULL
56 #define ILT_ENTRY_VALID_SHIFT 52
57 #define ILT_ENTRY_IN_REGS 2
58 #define ILT_REG_SIZE_IN_BYTES 4
60 /* connection context union */
62 struct core_conn_context core_ctx;
63 struct eth_conn_context eth_ctx;
66 /* TYPE-0 task context - iSCSI, FCOE */
67 union type0_task_context {
70 /* TYPE-1 task context - ROCE */
71 union type1_task_context {
79 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
80 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
82 #define CONN_CXT_SIZE(p_hwfn) \
83 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
85 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
87 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
88 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
90 /* Alignment is inherent to the type1_task_context structure */
91 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
93 /* PF per protocl configuration object */
94 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
95 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
97 struct ecore_tid_seg {
103 struct ecore_conn_type_cfg {
106 struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
109 /* ILT Client configuration,
110 * Per connection type (protocol) resources (cids, tis, vf cids etc.)
111 * 1 - for connection context (CDUC) and for each task context we need two
112 * values, for regular task context and for force load memory
114 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
115 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
118 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
119 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS)
131 struct ilt_cfg_pair {
136 struct ecore_ilt_cli_blk {
137 u32 total_size; /* 0 means not active */
138 u32 real_size_in_page;
140 u32 dynamic_line_cnt;
143 struct ecore_ilt_client_cfg {
147 struct ilt_cfg_pair first;
148 struct ilt_cfg_pair last;
149 struct ilt_cfg_pair p_size;
151 /* ILT client blocks for PF */
152 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
155 /* ILT client blocks for VFs */
156 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
162 * Protocol acquired CID lists
163 * PF start line in ILT
165 struct ecore_dma_mem {
171 #define MAP_WORD_SIZE sizeof(unsigned long)
172 #define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8)
174 struct ecore_cid_acquired_map {
177 unsigned long *cid_map;
180 struct ecore_cxt_mngr {
181 /* Per protocl configuration */
182 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
184 /* computed ILT structure */
185 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
187 /* Task type sizes */
188 u32 task_type_size[NUM_TASK_TYPES];
190 /* total number of VFs for this hwfn -
191 * ALL VFs are symmetric in terms of HW resources
195 /* total number of SRQ's for this hwfn */
199 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
200 /* TBD - do we want this allocated to reserve space? */
201 struct ecore_cid_acquired_map
202 acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS];
204 /* ILT shadow table */
205 struct ecore_dma_mem *ilt_shadow;
208 /* Mutex for a dynamic ILT allocation */
212 struct ecore_dma_mem *t2;
218 /* check if resources/configuration is required according to protocol type */
219 static OSAL_INLINE bool src_proto(enum protocol_type type)
221 return type == PROTOCOLID_TOE;
224 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
226 return type == PROTOCOLID_TOE;
229 static bool tm_tid_proto(enum protocol_type type)
231 return type == PROTOCOLID_FCOE;
234 /* counts the iids for the CDU/CDUC ILT client configuration */
235 struct ecore_cdu_iids {
240 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
241 struct ecore_cdu_iids *iids)
245 for (type = 0; type < MAX_CONN_TYPES; type++) {
246 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
247 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
251 /* counts the iids for the Searcher block configuration */
252 struct ecore_src_iids {
257 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
258 struct ecore_src_iids *iids)
262 for (i = 0; i < MAX_CONN_TYPES; i++) {
266 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
267 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
271 /* counts the iids for the Timers block configuration */
272 struct ecore_tm_iids {
274 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
280 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
281 struct ecore_tm_iids *iids)
283 bool tm_vf_required = false;
284 bool tm_required = false;
287 for (i = 0; i < MAX_CONN_TYPES; i++) {
288 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
290 if (tm_cid_proto(i) || tm_required) {
291 if (p_cfg->cid_count)
294 iids->pf_cids += p_cfg->cid_count;
297 if (tm_cid_proto(i) || tm_vf_required) {
298 if (p_cfg->cids_per_vf)
299 tm_vf_required = true;
303 if (tm_tid_proto(i)) {
304 struct ecore_tid_seg *segs = p_cfg->tid_seg;
306 /* for each segment there is at most one
307 * protocol for which count is not 0.
309 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
310 iids->pf_tids[j] += segs[j].count;
312 /* The last array elelment is for the VFs. As for PF
313 * segments there can be only one protocol for
314 * which this value is not 0.
316 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
320 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
321 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
322 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
324 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
325 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
326 iids->pf_tids_total += iids->pf_tids[j];
330 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
331 struct ecore_qm_iids *iids)
333 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
334 struct ecore_tid_seg *segs;
335 u32 vf_cids = 0, type, j;
338 for (type = 0; type < MAX_CONN_TYPES; type++) {
339 iids->cids += p_mngr->conn_cfg[type].cid_count;
340 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
342 segs = p_mngr->conn_cfg[type].tid_seg;
343 /* for each segment there is at most one
344 * protocol for which count is not 0.
346 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
347 iids->tids += segs[j].count;
349 /* The last array elelment is for the VFs. As for PF
350 * segments there can be only one protocol for
351 * which this value is not 0.
353 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
356 iids->vf_cids += vf_cids * p_mngr->vf_count;
357 iids->tids += vf_tids * p_mngr->vf_count;
359 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
360 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
361 iids->cids, iids->vf_cids, iids->tids, vf_tids);
364 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
367 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
370 /* Find the protocol with tid count > 0 for this segment.
371 * Note: there can only be one and this is already validated.
373 for (i = 0; i < MAX_CONN_TYPES; i++) {
374 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
375 return &p_cfg->conn_cfg[i].tid_seg[seg];
380 /* set the iids (cid/tid) count per protocol */
381 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
382 enum protocol_type type,
383 u32 cid_count, u32 vf_cid_cnt)
385 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
386 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
388 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
389 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
392 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
393 enum protocol_type type, u32 *vf_cid)
396 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
398 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
401 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
402 enum protocol_type type)
404 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
407 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
408 enum protocol_type type)
413 for (i = 0; i < TASK_SEGMENTS; i++)
414 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
419 static OSAL_INLINE void
420 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
421 enum protocol_type proto,
422 u8 seg, u8 seg_type, u32 count, bool has_fl)
424 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
425 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
427 p_seg->count = count;
428 p_seg->has_fl_mem = has_fl;
429 p_seg->type = seg_type;
432 /* the *p_line parameter must be either 0 for the first invocation or the
433 * value returned in the previous invocation.
435 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
436 struct ecore_ilt_cli_blk *p_blk,
438 u32 total_size, u32 elem_size)
440 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
442 /* verify that it's called once for each block */
443 if (p_blk->total_size)
446 p_blk->total_size = total_size;
447 p_blk->real_size_in_page = 0;
449 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
450 p_blk->start_line = start_line;
453 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
454 struct ecore_ilt_client_cfg *p_cli,
455 struct ecore_ilt_cli_blk *p_blk,
456 u32 *p_line, enum ilt_clients client_id)
458 if (!p_blk->total_size)
462 p_cli->first.val = *p_line;
464 p_cli->active = true;
465 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
466 p_cli->last.val = *p_line - 1;
468 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
469 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
470 " [Real %08x] Start line %d\n",
471 client_id, p_cli->first.val, p_cli->last.val,
472 p_blk->total_size, p_blk->real_size_in_page,
476 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
477 enum ilt_clients ilt_client)
479 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
480 struct ecore_ilt_client_cfg *p_cli;
481 u32 lines_to_skip = 0;
484 /* TBD MK: ILT code should be simplified once PROTO enum is changed */
486 if (ilt_client == ILT_CLI_CDUC) {
487 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
489 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
490 (u32)CONN_CXT_SIZE(p_hwfn);
492 lines_to_skip = cid_count / cxts_per_p;
495 return lines_to_skip;
498 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
500 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
501 u32 curr_line, total, i, task_size, line;
502 struct ecore_ilt_client_cfg *p_cli;
503 struct ecore_ilt_cli_blk *p_blk;
504 struct ecore_cdu_iids cdu_iids;
505 struct ecore_src_iids src_iids;
506 struct ecore_qm_iids qm_iids;
507 struct ecore_tm_iids tm_iids;
508 struct ecore_tid_seg *p_seg;
510 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
511 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
512 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
513 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
515 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
517 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
518 "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
519 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
522 p_cli = &p_mngr->clients[ILT_CLI_CDUC];
524 curr_line = p_mngr->pf_start_line;
527 p_cli->pf_total_lines = 0;
529 /* get the counters for the CDUC,CDUC and QM clients */
530 ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
532 p_blk = &p_cli->pf_blks[CDUC_BLK];
534 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
536 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
537 total, CONN_CXT_SIZE(p_hwfn));
539 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
540 p_cli->pf_total_lines = curr_line - p_blk->start_line;
542 p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
546 p_blk = &p_cli->vf_blks[CDUC_BLK];
547 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
549 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
550 total, CONN_CXT_SIZE(p_hwfn));
552 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
553 p_cli->vf_total_lines = curr_line - p_blk->start_line;
555 for (i = 1; i < p_mngr->vf_count; i++)
556 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
560 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
561 p_cli->first.val = curr_line;
563 /* first the 'working' task memory */
564 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
565 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
566 if (!p_seg || p_seg->count == 0)
569 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
570 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
571 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
572 p_mngr->task_type_size[p_seg->type]);
574 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
578 /* next the 'init' task memory (forced load memory) */
579 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
580 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
581 if (!p_seg || p_seg->count == 0)
584 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
586 if (!p_seg->has_fl_mem) {
587 /* The segment is active (total size pf 'working'
588 * memory is > 0) but has no FL (forced-load, Init)
591 * 1. The total-size in the corrsponding FL block of
592 * the ILT client is set to 0 - No ILT line are
593 * provisioned and no ILT memory allocated.
595 * 2. The start-line of said block is set to the
596 * start line of the matching working memory
597 * block in the ILT client. This is later used to
598 * configure the CDU segment offset registers and
599 * results in an FL command for TIDs of this
600 * segment behaves as regular load commands
601 * (loading TIDs from the working memory).
603 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
605 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
608 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
610 ecore_ilt_cli_blk_fill(p_cli, p_blk,
612 p_mngr->task_type_size[p_seg->type]);
614 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
617 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
620 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
621 if (p_seg && p_seg->count) {
622 /* Stricly speaking we need to iterate over all VF
623 * task segment types, but a VF has only 1 segment
626 /* 'working' memory */
627 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
629 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
630 ecore_ilt_cli_blk_fill(p_cli, p_blk,
632 p_mngr->task_type_size[p_seg->type]);
634 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
638 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
639 if (!p_seg->has_fl_mem) {
640 /* see comment above */
641 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
642 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
644 task_size = p_mngr->task_type_size[p_seg->type];
645 ecore_ilt_cli_blk_fill(p_cli, p_blk,
646 curr_line, total, task_size);
647 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
650 p_cli->vf_total_lines = curr_line -
651 p_cli->vf_blks[0].start_line;
653 /* Now for the rest of the VFs */
654 for (i = 1; i < p_mngr->vf_count; i++) {
655 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
656 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
659 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
660 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
666 p_cli = &p_mngr->clients[ILT_CLI_QM];
667 p_blk = &p_cli->pf_blks[0];
669 ecore_cxt_qm_iids(p_hwfn, &qm_iids);
670 total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
671 qm_iids.vf_cids, qm_iids.tids,
672 p_hwfn->qm_info.num_pqs,
673 p_hwfn->qm_info.num_vf_pqs);
675 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
676 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
677 " num_vf_pqs=%d, memory_size=%d)\n",
678 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
679 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
681 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
684 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
685 p_cli->pf_total_lines = curr_line - p_blk->start_line;
688 p_cli = &p_mngr->clients[ILT_CLI_SRC];
689 ecore_cxt_src_iids(p_mngr, &src_iids);
691 /* Both the PF and VFs searcher connections are stored in the per PF
692 * database. Thus sum the PF searcher cids and all the VFs searcher
695 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
697 u32 local_max = OSAL_MAX_T(u32, total,
700 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
702 p_blk = &p_cli->pf_blks[0];
703 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
704 total * sizeof(struct src_ent),
705 sizeof(struct src_ent));
707 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
709 p_cli->pf_total_lines = curr_line - p_blk->start_line;
713 p_cli = &p_mngr->clients[ILT_CLI_TM];
714 ecore_cxt_tm_iids(p_mngr, &tm_iids);
715 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
717 p_blk = &p_cli->pf_blks[0];
718 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
719 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
721 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
723 p_cli->pf_total_lines = curr_line - p_blk->start_line;
727 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
729 p_blk = &p_cli->vf_blks[0];
730 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
731 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
733 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
736 p_cli->vf_total_lines = curr_line - p_blk->start_line;
737 for (i = 1; i < p_mngr->vf_count; i++) {
738 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
743 /* TSDM (SRQ CONTEXT) */
744 total = ecore_cxt_get_srq_count(p_hwfn);
747 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
748 p_blk = &p_cli->pf_blks[SRQ_BLK];
749 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
750 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
752 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
754 p_cli->pf_total_lines = curr_line - p_blk->start_line;
757 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
758 RESC_NUM(p_hwfn, ECORE_ILT)) {
759 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
760 curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
764 return ECORE_SUCCESS;
767 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
769 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
775 for (i = 0; i < p_mngr->t2_num_pages; i++)
776 if (p_mngr->t2[i].p_virt)
777 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
778 p_mngr->t2[i].p_virt,
779 p_mngr->t2[i].p_phys,
782 OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
785 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
787 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
788 u32 conn_num, total_size, ent_per_page, psz, i;
789 struct ecore_ilt_client_cfg *p_src;
790 struct ecore_src_iids src_iids;
791 struct ecore_dma_mem *p_t2;
792 enum _ecore_status_t rc;
794 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
796 /* if the SRC ILT client is inactive - there are no connection
797 * requiring the searcer, leave.
799 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
801 return ECORE_SUCCESS;
803 ecore_cxt_src_iids(p_mngr, &src_iids);
804 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
805 total_size = conn_num * sizeof(struct src_ent);
807 /* use the same page size as the SRC ILT client */
808 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
809 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
812 p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
813 p_mngr->t2_num_pages *
814 sizeof(struct ecore_dma_mem));
816 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
821 /* allocate t2 pages */
822 for (i = 0; i < p_mngr->t2_num_pages; i++) {
823 u32 size = OSAL_MIN_T(u32, total_size, psz);
824 void **p_virt = &p_mngr->t2[i].p_virt;
826 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
827 &p_mngr->t2[i].p_phys, size);
828 if (!p_mngr->t2[i].p_virt) {
832 OSAL_MEM_ZERO(*p_virt, size);
833 p_mngr->t2[i].size = size;
837 /* Set the t2 pointers */
839 /* entries per page - must be a power of two */
840 ent_per_page = psz / sizeof(struct src_ent);
842 p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
844 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
845 p_mngr->last_free = (u64)p_t2->p_phys +
846 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
848 for (i = 0; i < p_mngr->t2_num_pages; i++) {
849 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
850 struct src_ent *entries = p_mngr->t2[i].p_virt;
851 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
854 for (j = 0; j < ent_num - 1; j++) {
855 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
856 entries[j].next = OSAL_CPU_TO_BE64(val);
859 if (i < p_mngr->t2_num_pages - 1)
860 val = (u64)p_mngr->t2[i + 1].p_phys;
863 entries[j].next = OSAL_CPU_TO_BE64(val);
868 return ECORE_SUCCESS;
871 ecore_cxt_src_t2_free(p_hwfn);
875 #define for_each_ilt_valid_client(pos, clients) \
876 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
877 if (!clients[pos].active) { \
882 /* Total number of ILT lines used by this PF */
883 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
888 for_each_ilt_valid_client(i, ilt_clients)
889 size += (ilt_clients[i].last.val -
890 ilt_clients[i].first.val + 1);
895 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
897 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
898 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
901 ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
903 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
904 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
907 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
909 p_dma->p_phys, p_dma->size);
910 p_dma->p_virt = OSAL_NULL;
912 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
915 static enum _ecore_status_t
916 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
917 struct ecore_ilt_cli_blk *p_blk,
918 enum ilt_clients ilt_client, u32 start_line_offset)
920 struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
921 u32 lines, line, sz_left, lines_to_skip = 0;
923 /* Special handling for RoCE that supports dynamic allocation */
924 if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
925 return ECORE_SUCCESS;
927 lines_to_skip = p_blk->dynamic_line_cnt;
929 if (!p_blk->total_size)
930 return ECORE_SUCCESS;
932 sz_left = p_blk->total_size;
933 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
934 line = p_blk->start_line + start_line_offset -
935 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
937 for (; lines; lines--) {
942 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
945 #define ILT_BLOCK_ALIGN_SIZE 0x1000
946 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
948 ILT_BLOCK_ALIGN_SIZE);
951 OSAL_MEM_ZERO(p_virt, size);
953 ilt_shadow[line].p_phys = p_phys;
954 ilt_shadow[line].p_virt = p_virt;
955 ilt_shadow[line].size = size;
957 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
958 "ILT shadow: Line [%d] Physical 0x%lx"
959 " Virtual %p Size %d\n",
960 line, (unsigned long)p_phys, p_virt, size);
966 return ECORE_SUCCESS;
969 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
971 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
972 struct ecore_ilt_client_cfg *clients = p_mngr->clients;
973 struct ecore_ilt_cli_blk *p_blk;
975 enum _ecore_status_t rc;
977 size = ecore_cxt_ilt_shadow_size(clients);
978 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
979 size * sizeof(struct ecore_dma_mem));
981 if (!p_mngr->ilt_shadow) {
982 DP_NOTICE(p_hwfn, true,
983 "Failed to allocate ilt shadow table\n");
985 goto ilt_shadow_fail;
988 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
989 "Allocated 0x%x bytes for ilt shadow\n",
990 (u32)(size * sizeof(struct ecore_dma_mem)));
992 for_each_ilt_valid_client(i, clients) {
993 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
994 p_blk = &clients[i].pf_blks[j];
995 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
996 if (rc != ECORE_SUCCESS)
997 goto ilt_shadow_fail;
999 for (k = 0; k < p_mngr->vf_count; k++) {
1000 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1001 u32 lines = clients[i].vf_total_lines * k;
1003 p_blk = &clients[i].vf_blks[j];
1004 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1006 if (rc != ECORE_SUCCESS)
1007 goto ilt_shadow_fail;
1012 return ECORE_SUCCESS;
1015 ecore_ilt_shadow_free(p_hwfn);
1019 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1021 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1024 for (type = 0; type < MAX_CONN_TYPES; type++) {
1025 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1026 p_mngr->acquired[type].max_count = 0;
1027 p_mngr->acquired[type].start_cid = 0;
1029 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1030 OSAL_FREE(p_hwfn->p_dev,
1031 p_mngr->acquired_vf[type][vf].cid_map);
1032 p_mngr->acquired_vf[type][vf].max_count = 0;
1033 p_mngr->acquired_vf[type][vf].start_cid = 0;
1038 static enum _ecore_status_t
1039 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1040 u32 cid_start, u32 cid_count,
1041 struct ecore_cid_acquired_map *p_map)
1046 return ECORE_SUCCESS;
1048 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1049 p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1050 if (p_map->cid_map == OSAL_NULL)
1053 p_map->max_count = cid_count;
1054 p_map->start_cid = cid_start;
1056 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1057 "Type %08x start: %08x count %08x\n",
1058 type, p_map->start_cid, p_map->max_count);
1060 return ECORE_SUCCESS;
1063 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1065 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1066 u32 start_cid = 0, vf_start_cid = 0;
1069 for (type = 0; type < MAX_CONN_TYPES; type++) {
1070 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1071 struct ecore_cid_acquired_map *p_map;
1073 /* Handle PF maps */
1074 p_map = &p_mngr->acquired[type];
1075 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1076 p_cfg->cid_count, p_map))
1079 /* Handle VF maps */
1080 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1081 p_map = &p_mngr->acquired_vf[type][vf];
1082 if (ecore_cid_map_alloc_single(p_hwfn, type,
1089 start_cid += p_cfg->cid_count;
1090 vf_start_cid += p_cfg->cids_per_vf;
1093 return ECORE_SUCCESS;
1096 ecore_cid_map_free(p_hwfn);
1100 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1102 struct ecore_ilt_client_cfg *clients;
1103 struct ecore_cxt_mngr *p_mngr;
1106 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1108 DP_NOTICE(p_hwfn, true,
1109 "Failed to allocate `struct ecore_cxt_mngr'\n");
1113 /* Initialize ILT client registers */
1114 clients = p_mngr->clients;
1115 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1116 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1117 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1119 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1120 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1121 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1123 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1124 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1125 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1127 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1128 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1129 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1131 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1132 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1133 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1135 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1136 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1137 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1139 /* default ILT page size for all clients is 32K */
1140 for (i = 0; i < ILT_CLI_MAX; i++)
1141 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1143 /* due to removal of ISCSI/FCoE files union type0_task_context
1144 * task_type_size will be 0. So hardcoded for now.
1146 p_mngr->task_type_size[0] = 512; /* @DPDK */
1147 p_mngr->task_type_size[1] = 128; /* @DPDK */
1149 if (p_hwfn->p_dev->p_iov_info)
1150 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1152 /* Initialize the dynamic ILT allocation mutex */
1153 OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1154 OSAL_MUTEX_INIT(&p_mngr->mutex);
1156 /* Set the cxt mangr pointer priori to further allocations */
1157 p_hwfn->p_cxt_mngr = p_mngr;
1159 return ECORE_SUCCESS;
1162 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1164 enum _ecore_status_t rc;
1166 /* Allocate the ILT shadow table */
1167 rc = ecore_ilt_shadow_alloc(p_hwfn);
1169 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1170 goto tables_alloc_fail;
1173 /* Allocate the T2 table */
1174 rc = ecore_cxt_src_t2_alloc(p_hwfn);
1176 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1177 goto tables_alloc_fail;
1180 /* Allocate and initialize the acquired cids bitmaps */
1181 rc = ecore_cid_map_alloc(p_hwfn);
1183 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1184 goto tables_alloc_fail;
1187 return ECORE_SUCCESS;
1190 ecore_cxt_mngr_free(p_hwfn);
1194 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1196 if (!p_hwfn->p_cxt_mngr)
1199 ecore_cid_map_free(p_hwfn);
1200 ecore_cxt_src_t2_free(p_hwfn);
1201 ecore_ilt_shadow_free(p_hwfn);
1202 OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1203 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1206 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1208 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1209 struct ecore_cid_acquired_map *p_map;
1210 struct ecore_conn_type_cfg *p_cfg;
1214 /* Reset acquired cids */
1215 for (type = 0; type < MAX_CONN_TYPES; type++) {
1218 p_cfg = &p_mngr->conn_cfg[type];
1219 if (p_cfg->cid_count) {
1220 p_map = &p_mngr->acquired[type];
1221 len = DIV_ROUND_UP(p_map->max_count,
1222 BITS_PER_MAP_WORD) *
1224 OSAL_MEM_ZERO(p_map->cid_map, len);
1227 if (!p_cfg->cids_per_vf)
1230 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1231 p_map = &p_mngr->acquired_vf[type][vf];
1232 len = DIV_ROUND_UP(p_map->max_count,
1233 BITS_PER_MAP_WORD) *
1235 OSAL_MEM_ZERO(p_map->cid_map, len);
1240 /* HW initialization helper (per Block, per phase) */
1243 #define CDUC_CXT_SIZE_SHIFT \
1244 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1246 #define CDUC_CXT_SIZE_MASK \
1247 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1249 #define CDUC_BLOCK_WASTE_SHIFT \
1250 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1252 #define CDUC_BLOCK_WASTE_MASK \
1253 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1255 #define CDUC_NCIB_SHIFT \
1256 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1258 #define CDUC_NCIB_MASK \
1259 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1261 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1262 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1264 #define CDUT_TYPE0_CXT_SIZE_MASK \
1265 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1266 CDUT_TYPE0_CXT_SIZE_SHIFT)
1268 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1269 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1271 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1272 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1273 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1275 #define CDUT_TYPE0_NCIB_SHIFT \
1276 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1278 #define CDUT_TYPE0_NCIB_MASK \
1279 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1280 CDUT_TYPE0_NCIB_SHIFT)
1282 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1283 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1285 #define CDUT_TYPE1_CXT_SIZE_MASK \
1286 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1287 CDUT_TYPE1_CXT_SIZE_SHIFT)
1289 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1290 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1292 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1293 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1294 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1296 #define CDUT_TYPE1_NCIB_SHIFT \
1297 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1299 #define CDUT_TYPE1_NCIB_MASK \
1300 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1301 CDUT_TYPE1_NCIB_SHIFT)
1303 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1305 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1307 /* CDUC - connection configuration */
1308 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1309 cxt_size = CONN_CXT_SIZE(p_hwfn);
1310 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1311 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1313 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1314 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1315 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1316 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1318 /* CDUT - type-0 tasks configuration */
1319 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1320 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1321 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1322 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1324 /* cxt size and block-waste are multipes of 8 */
1326 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1327 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1328 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1329 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1331 /* CDUT - type-1 tasks configuration */
1332 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1333 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1334 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1336 /* cxt size and block-waste are multipes of 8 */
1338 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1339 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1340 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1341 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1345 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1346 #define CDU_SEG_REG_TYPE_MASK 0x1
1347 #define CDU_SEG_REG_OFFSET_SHIFT 0
1348 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1350 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1352 struct ecore_ilt_client_cfg *p_cli;
1353 struct ecore_tid_seg *p_seg;
1354 u32 cdu_seg_params, offset;
1357 static const u32 rt_type_offset_arr[] = {
1358 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1359 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1360 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1361 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1364 static const u32 rt_type_offset_fl_arr[] = {
1365 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1366 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1367 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1368 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1371 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1373 /* There are initializations only for CDUT during pf Phase */
1374 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1376 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1380 /* Note: start_line is already adjusted for the CDU
1381 * segment register granularity, so we just need to
1382 * divide. Adjustment is implicit as we assume ILT
1383 * Page size is larger than 32K!
1385 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1386 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1387 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1390 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1391 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1392 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1394 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1395 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1396 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1399 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1400 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1401 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1405 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1407 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1408 struct ecore_qm_iids iids;
1410 OSAL_MEM_ZERO(&iids, sizeof(iids));
1411 ecore_cxt_qm_iids(p_hwfn, &iids);
1413 ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1414 p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1415 p_hwfn->first_on_engine,
1416 iids.cids, iids.vf_cids, iids.tids,
1418 qm_info->num_pqs - qm_info->num_vf_pqs,
1419 qm_info->num_vf_pqs,
1420 qm_info->start_vport,
1421 qm_info->num_vports, qm_info->pf_wfq,
1422 qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1423 p_hwfn->qm_info.qm_vport_params);
1427 void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1429 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1430 ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1434 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1436 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1437 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1439 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1440 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1442 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1443 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1445 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1446 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1448 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1449 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1451 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1452 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1454 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1455 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1457 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1458 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1460 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1461 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1463 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1464 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1466 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1467 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1469 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1470 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1472 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1473 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1475 /* Connection types 6 & 7 are not in use, yet they must be configured
1476 * as the highest possible connection. Not configuring them means the
1477 * defaults will be used, and with a large number of cids a bug may
1478 * occur, if the defaults will be smaller than dq_pf_max_cid /
1481 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1482 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1484 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1485 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1488 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1490 struct ecore_ilt_client_cfg *ilt_clients;
1493 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1494 for_each_ilt_valid_client(i, ilt_clients) {
1495 STORE_RT_REG(p_hwfn,
1496 ilt_clients[i].first.reg,
1497 ilt_clients[i].first.val);
1498 STORE_RT_REG(p_hwfn,
1499 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1500 STORE_RT_REG(p_hwfn,
1501 ilt_clients[i].p_size.reg,
1502 ilt_clients[i].p_size.val);
1506 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1508 struct ecore_ilt_client_cfg *p_cli;
1511 /* For simplicty we set the 'block' to be an ILT page */
1512 if (p_hwfn->p_dev->p_iov_info) {
1513 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1515 STORE_RT_REG(p_hwfn,
1516 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1517 p_iov->first_vf_in_pf);
1518 STORE_RT_REG(p_hwfn,
1519 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1520 p_iov->first_vf_in_pf + p_iov->total_vfs);
1523 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1524 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1525 if (p_cli->active) {
1526 STORE_RT_REG(p_hwfn,
1527 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1529 STORE_RT_REG(p_hwfn,
1530 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1531 p_cli->pf_total_lines);
1532 STORE_RT_REG(p_hwfn,
1533 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1534 p_cli->vf_total_lines);
1537 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1538 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1539 if (p_cli->active) {
1540 STORE_RT_REG(p_hwfn,
1541 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1543 STORE_RT_REG(p_hwfn,
1544 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1545 p_cli->pf_total_lines);
1546 STORE_RT_REG(p_hwfn,
1547 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1548 p_cli->vf_total_lines);
1551 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1552 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1553 if (p_cli->active) {
1554 STORE_RT_REG(p_hwfn,
1555 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1556 STORE_RT_REG(p_hwfn,
1557 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1558 p_cli->pf_total_lines);
1559 STORE_RT_REG(p_hwfn,
1560 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1561 p_cli->vf_total_lines);
1565 /* ILT (PSWRQ2) PF */
1566 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1568 struct ecore_ilt_client_cfg *clients;
1569 struct ecore_cxt_mngr *p_mngr;
1570 struct ecore_dma_mem *p_shdw;
1571 u32 line, rt_offst, i;
1573 ecore_ilt_bounds_init(p_hwfn);
1574 ecore_ilt_vf_bounds_init(p_hwfn);
1576 p_mngr = p_hwfn->p_cxt_mngr;
1577 p_shdw = p_mngr->ilt_shadow;
1578 clients = p_hwfn->p_cxt_mngr->clients;
1580 for_each_ilt_valid_client(i, clients) {
1581 /* Client's 1st val and RT array are absolute, ILT shadows'
1582 * lines are relative.
1584 line = clients[i].first.val - p_mngr->pf_start_line;
1585 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1586 clients[i].first.val * ILT_ENTRY_IN_REGS;
1588 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1589 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1590 u64 ilt_hw_entry = 0;
1592 /** p_virt could be OSAL_NULL incase of dynamic
1595 if (p_shdw[line].p_virt != OSAL_NULL) {
1596 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1597 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1598 (p_shdw[line].p_phys >> 12));
1600 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1601 "Setting RT[0x%08x] from"
1602 " ILT[0x%08x] [Client is %d] to"
1603 " Physical addr: 0x%lx\n",
1605 (unsigned long)(p_shdw[line].
1609 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1614 /* SRC (Searcher) PF */
1615 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1617 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1618 u32 rounded_conn_num, conn_num, conn_max;
1619 struct ecore_src_iids src_iids;
1621 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1622 ecore_cxt_src_iids(p_mngr, &src_iids);
1623 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1627 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1628 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1630 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1631 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1632 OSAL_LOG2(rounded_conn_num));
1634 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1635 p_hwfn->p_cxt_mngr->first_free);
1636 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1637 p_hwfn->p_cxt_mngr->last_free);
1641 #define TM_CFG_NUM_IDS_SHIFT 0
1642 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1643 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1644 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1645 #define TM_CFG_PARENT_PF_SHIFT 25
1646 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1648 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1649 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1651 #define TM_CFG_TID_OFFSET_SHIFT 30
1652 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1653 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1654 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1656 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1658 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1659 u32 active_seg_mask = 0, tm_offset, rt_reg;
1660 struct ecore_tm_iids tm_iids;
1664 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1665 ecore_cxt_tm_iids(p_mngr, &tm_iids);
1667 /* @@@TBD No pre-scan for now */
1669 /* Note: We assume consecutive VFs for a PF */
1670 for (i = 0; i < p_mngr->vf_count; i++) {
1672 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1673 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1674 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1675 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1677 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1678 (sizeof(cfg_word) / sizeof(u32)) *
1679 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1680 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1684 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1685 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1686 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1687 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1689 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1690 (sizeof(cfg_word) / sizeof(u32)) *
1691 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1692 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1695 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1696 tm_iids.pf_cids ? 0x1 : 0x0);
1698 /* @@@TBD how to enable the scan for the VFs */
1700 tm_offset = tm_iids.per_vf_cids;
1702 /* Note: We assume consecutive VFs for a PF */
1703 for (i = 0; i < p_mngr->vf_count; i++) {
1705 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1706 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1707 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1708 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1709 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1711 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1712 (sizeof(cfg_word) / sizeof(u32)) *
1713 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1715 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1718 tm_offset = tm_iids.pf_cids;
1719 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1721 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1722 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1723 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1724 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1725 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1727 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1728 (sizeof(cfg_word) / sizeof(u32)) *
1729 (NUM_OF_VFS(p_hwfn->p_dev) +
1730 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1732 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1733 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1735 tm_offset += tm_iids.pf_tids[i];
1738 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1740 /* @@@TBD how to enable the scan for the VFs */
1743 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1745 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1746 struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1747 struct ecore_tid_seg *p_tid;
1749 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1750 if (!p_fcoe->cid_count)
1753 p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1754 STORE_RT_REG_AGG(p_hwfn,
1755 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1759 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1761 /* CDU configuration */
1762 ecore_cdu_init_common(p_hwfn);
1765 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1767 ecore_qm_init_pf(p_hwfn);
1768 ecore_cm_init_pf(p_hwfn);
1769 ecore_dq_init_pf(p_hwfn);
1770 ecore_cdu_init_pf(p_hwfn);
1771 ecore_ilt_init_pf(p_hwfn);
1772 ecore_src_init_pf(p_hwfn);
1773 ecore_tm_init_pf(p_hwfn);
1774 ecore_prs_init_pf(p_hwfn);
1777 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1778 enum protocol_type type,
1779 u32 *p_cid, u8 vfid)
1781 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1782 struct ecore_cid_acquired_map *p_map;
1785 if (type >= MAX_CONN_TYPES) {
1786 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1790 if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) {
1791 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1795 /* Determine the right map to take this CID from */
1796 if (vfid == ECORE_CXT_PF_CID)
1797 p_map = &p_mngr->acquired[type];
1799 p_map = &p_mngr->acquired_vf[type][vfid];
1801 if (p_map->cid_map == OSAL_NULL) {
1802 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1806 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1809 if (rel_cid >= p_map->max_count) {
1810 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1812 return ECORE_NORESOURCES;
1815 OSAL_SET_BIT(rel_cid, p_map->cid_map);
1817 *p_cid = rel_cid + p_map->start_cid;
1819 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1820 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1821 *p_cid, rel_cid, vfid, type);
1823 return ECORE_SUCCESS;
1826 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1827 enum protocol_type type,
1830 return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
1833 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1835 enum protocol_type *p_type,
1836 struct ecore_cid_acquired_map **pp_map)
1838 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1841 /* Iterate over protocols and find matching cid range */
1842 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1843 if (vfid == ECORE_CXT_PF_CID)
1844 *pp_map = &p_mngr->acquired[*p_type];
1846 *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1848 if (!((*pp_map)->cid_map))
1850 if (cid >= (*pp_map)->start_cid &&
1851 cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
1855 if (*p_type == MAX_CONN_TYPES) {
1856 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
1860 rel_cid = cid - (*pp_map)->start_cid;
1861 if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
1862 DP_NOTICE(p_hwfn, true,
1863 "CID %d [vifd %02x] not acquired", cid, vfid);
1869 *p_type = MAX_CONN_TYPES;
1870 *pp_map = OSAL_NULL;
1874 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
1876 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1877 enum protocol_type type;
1881 if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) {
1882 DP_NOTICE(p_hwfn, true,
1883 "Trying to return incorrect CID belonging to VF %02x\n",
1888 /* Test acquired and find matching per-protocol map */
1889 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
1895 rel_cid = cid - p_map->start_cid;
1896 OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
1898 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1899 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
1900 cid, rel_cid, vfid, type);
1903 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1905 _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
1908 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1909 struct ecore_cxt_info *p_info)
1911 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1912 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1913 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1914 enum protocol_type type;
1917 /* Test acquired and find matching per-protocol map */
1918 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
1925 /* set the protocl type */
1926 p_info->type = type;
1928 /* compute context virtual pointer */
1929 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1931 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1932 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1933 line = p_info->iid / cxts_per_p;
1935 /* Make sure context is allocated (dynamic allocation) */
1936 if (!p_mngr->ilt_shadow[line].p_virt)
1939 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1940 p_info->iid % cxts_per_p * conn_cxt_size;
1942 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1943 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1944 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1946 return ECORE_SUCCESS;
1949 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
1951 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1953 p_mgr->srq_count = num_srqs;
1956 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
1958 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1960 return p_mgr->srq_count;
1963 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1965 /* Set the number of required CORE connections */
1966 u32 core_cids = 1; /* SPQ */
1968 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1970 switch (p_hwfn->hw_info.personality) {
1973 struct ecore_eth_pf_params *p_params =
1974 &p_hwfn->pf_params.eth_pf_params;
1976 /* TODO - we probably want to add VF number to the PF
1978 * As of now, allocates 16 * 2 per-VF [to retain regular
1981 ecore_cxt_set_proto_cid_count(p_hwfn,
1983 p_params->num_cons, 32);
1991 return ECORE_SUCCESS;
1994 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
1995 struct ecore_tid_mem *p_info)
1997 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1998 u32 proto, seg, total_lines, i, shadow_line;
1999 struct ecore_ilt_client_cfg *p_cli;
2000 struct ecore_ilt_cli_blk *p_fl_seg;
2001 struct ecore_tid_seg *p_seg_info;
2003 /* Verify the personality */
2004 switch (p_hwfn->hw_info.personality) {
2009 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2013 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2014 if (!p_seg_info->has_fl_mem)
2017 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2018 total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
2019 p_fl_seg->real_size_in_page);
2021 for (i = 0; i < total_lines; i++) {
2022 shadow_line = i + p_fl_seg->start_line -
2023 p_hwfn->p_cxt_mngr->pf_start_line;
2024 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
2026 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
2027 p_fl_seg->real_size_in_page;
2028 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
2029 p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
2032 return ECORE_SUCCESS;
2035 /* This function is very RoCE oriented, if another protocol in the future
2036 * will want this feature we'll need to modify the function to be more generic
2038 enum _ecore_status_t
2039 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2040 enum ecore_cxt_elem_type elem_type,
2043 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2044 struct ecore_ilt_client_cfg *p_cli;
2045 struct ecore_ilt_cli_blk *p_blk;
2046 struct ecore_ptt *p_ptt;
2050 enum _ecore_status_t rc = ECORE_SUCCESS;
2052 switch (elem_type) {
2053 case ECORE_ELEM_CXT:
2054 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2055 elem_size = CONN_CXT_SIZE(p_hwfn);
2056 p_blk = &p_cli->pf_blks[CDUC_BLK];
2058 case ECORE_ELEM_SRQ:
2059 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2060 elem_size = SRQ_CXT_SIZE;
2061 p_blk = &p_cli->pf_blks[SRQ_BLK];
2063 case ECORE_ELEM_TASK:
2064 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2065 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2066 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2069 DP_NOTICE(p_hwfn, false,
2070 "ECORE_INVALID elem type = %d", elem_type);
2074 /* Calculate line in ilt */
2075 hw_p_size = p_cli->p_size.val;
2076 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2077 line = p_blk->start_line + (iid / elems_per_p);
2078 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2080 /* If line is already allocated, do nothing, otherwise allocate it and
2081 * write it to the PSWRQ2 registers.
2082 * This section can be run in parallel from different contexts and thus
2083 * a mutex protection is needed.
2086 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2088 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2091 p_ptt = ecore_ptt_acquire(p_hwfn);
2093 DP_NOTICE(p_hwfn, false,
2094 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2099 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2101 p_blk->real_size_in_page);
2106 OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2108 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2109 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2110 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2111 p_blk->real_size_in_page;
2113 /* compute absolute offset */
2114 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2115 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2118 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2119 SET_FIELD(ilt_hw_entry,
2121 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2123 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2125 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2126 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2129 if (elem_type == ECORE_ELEM_CXT) {
2130 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2133 /* Update the relevant register in the parser */
2134 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2135 last_cid_allocated - 1);
2137 if (!p_hwfn->b_rdma_enabled_in_prs) {
2138 /* Enable RoCE search */
2139 ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2140 p_hwfn->b_rdma_enabled_in_prs = true;
2145 ecore_ptt_release(p_hwfn, p_ptt);
2147 OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2152 /* This function is very RoCE oriented, if another protocol in the future
2153 * will want this feature we'll need to modify the function to be more generic
2155 static enum _ecore_status_t
2156 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2157 enum ecore_cxt_elem_type elem_type,
2158 u32 start_iid, u32 count)
2160 u32 start_line, end_line, shadow_start_line, shadow_end_line;
2161 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2162 struct ecore_ilt_client_cfg *p_cli;
2163 struct ecore_ilt_cli_blk *p_blk;
2164 u32 end_iid = start_iid + count;
2165 struct ecore_ptt *p_ptt;
2166 u64 ilt_hw_entry = 0;
2169 switch (elem_type) {
2170 case ECORE_ELEM_CXT:
2171 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2172 elem_size = CONN_CXT_SIZE(p_hwfn);
2173 p_blk = &p_cli->pf_blks[CDUC_BLK];
2175 case ECORE_ELEM_SRQ:
2176 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2177 elem_size = SRQ_CXT_SIZE;
2178 p_blk = &p_cli->pf_blks[SRQ_BLK];
2180 case ECORE_ELEM_TASK:
2181 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2182 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2183 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2186 DP_NOTICE(p_hwfn, false,
2187 "ECORE_INVALID elem type = %d", elem_type);
2191 /* Calculate line in ilt */
2192 hw_p_size = p_cli->p_size.val;
2193 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2194 start_line = p_blk->start_line + (start_iid / elems_per_p);
2195 end_line = p_blk->start_line + (end_iid / elems_per_p);
2196 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2199 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2200 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2202 p_ptt = ecore_ptt_acquire(p_hwfn);
2204 DP_NOTICE(p_hwfn, false,
2205 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2206 return ECORE_TIMEOUT;
2209 for (i = shadow_start_line; i < shadow_end_line; i++) {
2210 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2213 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2214 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2215 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2216 p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2218 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2219 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2220 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2222 /* compute absolute offset */
2223 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2224 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2227 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2230 ecore_dmae_host2grc(p_hwfn, p_ptt,
2231 (u64)(osal_uintptr_t)&ilt_hw_entry,
2233 sizeof(ilt_hw_entry) / sizeof(u32),
2237 ecore_ptt_release(p_hwfn, p_ptt);
2239 return ECORE_SUCCESS;
2242 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2243 enum protocol_type proto)
2245 enum _ecore_status_t rc;
2248 /* Free Connection CXT */
2249 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2250 ecore_cxt_get_proto_cid_start(p_hwfn,
2252 ecore_cxt_get_proto_cid_count(p_hwfn,
2260 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2261 ecore_cxt_get_proto_tid_count(p_hwfn,
2267 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2268 ecore_cxt_get_srq_count(p_hwfn));
2273 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
2275 u8 ctx_type, void **pp_task_ctx)
2277 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2278 struct ecore_ilt_client_cfg *p_cli;
2279 struct ecore_ilt_cli_blk *p_seg;
2280 struct ecore_tid_seg *p_seg_info;
2283 u32 tid_size, ilt_idx;
2284 u32 num_tids_per_block;
2286 /* Verify the personality */
2287 switch (p_hwfn->hw_info.personality) {
2292 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2296 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2298 if (ctx_type == ECORE_CTX_WORKING_MEM) {
2299 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2300 } else if (ctx_type == ECORE_CTX_FL_MEM) {
2301 if (!p_seg_info->has_fl_mem)
2303 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2307 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2308 tid_size = p_mngr->task_type_size[p_seg_info->type];
2309 num_tids_per_block = p_seg->real_size_in_page / tid_size;
2311 if (total_lines < tid / num_tids_per_block)
2314 ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2315 p_mngr->pf_start_line;
2316 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2317 (tid % num_tids_per_block) * tid_size;
2319 return ECORE_SUCCESS;