2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_hsi_common.h"
12 #include "ecore_hsi_eth.h"
13 #include "ecore_rt_defs.h"
14 #include "ecore_status.h"
16 #include "ecore_init_ops.h"
17 #include "ecore_init_fw_funcs.h"
18 #include "ecore_cxt.h"
20 #include "ecore_dev_api.h"
21 #include "ecore_sriov.h"
23 /* Max number of connection types in HW (DQ/CDU etc.) */
24 #define MAX_CONN_TYPES PROTOCOLID_COMMON
25 #define NUM_TASK_TYPES 2
26 #define NUM_TASK_PF_SEGMENTS 4
27 #define NUM_TASK_VF_SEGMENTS 1
29 /* Doorbell-Queue constants */
30 #define DQ_RANGE_SHIFT 4
31 #define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT)
33 /* Searcher constants */
34 #define SRC_MIN_NUM_ELEMS 256
36 /* Timers constants */
38 #define TM_ALIGN (1 << TM_SHIFT)
39 #define TM_ELEM_SIZE 4
42 /* If for some reason, HW P size is modified to be less than 32K,
43 * special handling needs to be made for CDU initialization
45 #define ILT_DEFAULT_HW_P_SIZE 3
47 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
48 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
50 /* ILT entry structure */
51 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
52 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
53 #define ILT_ENTRY_VALID_MASK 0x1ULL
54 #define ILT_ENTRY_VALID_SHIFT 52
55 #define ILT_ENTRY_IN_REGS 2
56 #define ILT_REG_SIZE_IN_BYTES 4
58 /* connection context union */
60 struct core_conn_context core_ctx;
61 struct eth_conn_context eth_ctx;
64 /* TYPE-0 task context - iSCSI, FCOE */
65 union type0_task_context {
68 /* TYPE-1 task context - ROCE */
69 union type1_task_context {
77 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
78 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
80 #define CONN_CXT_SIZE(p_hwfn) \
81 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
83 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
85 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
86 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
88 /* Alignment is inherent to the type1_task_context structure */
89 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
91 /* PF per protocl configuration object */
92 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
93 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
95 struct ecore_tid_seg {
101 struct ecore_conn_type_cfg {
105 struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
108 /* ILT Client configuration,
109 * Per connection type (protocol) resources (cids, tis, vf cids etc.)
110 * 1 - for connection context (CDUC) and for each task context we need two
111 * values, for regular task context and for force load memory
113 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
114 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
117 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
118 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS)
130 struct ilt_cfg_pair {
135 struct ecore_ilt_cli_blk {
136 u32 total_size; /* 0 means not active */
137 u32 real_size_in_page;
139 u32 dynamic_line_cnt;
142 struct ecore_ilt_client_cfg {
146 struct ilt_cfg_pair first;
147 struct ilt_cfg_pair last;
148 struct ilt_cfg_pair p_size;
150 /* ILT client blocks for PF */
151 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
154 /* ILT client blocks for VFs */
155 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
161 * Protocol acquired CID lists
162 * PF start line in ILT
164 struct ecore_dma_mem {
170 #define MAP_WORD_SIZE sizeof(unsigned long)
171 #define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8)
173 struct ecore_cid_acquired_map {
176 unsigned long *cid_map;
179 struct ecore_cxt_mngr {
180 /* Per protocl configuration */
181 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
183 /* computed ILT structure */
184 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
186 /* Task type sizes */
187 u32 task_type_size[NUM_TASK_TYPES];
189 /* total number of VFs for this hwfn -
190 * ALL VFs are symmetric in terms of HW resources
194 /* total number of SRQ's for this hwfn */
198 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
200 /* ILT shadow table */
201 struct ecore_dma_mem *ilt_shadow;
204 /* Mutex for a dynamic ILT allocation */
208 struct ecore_dma_mem *t2;
214 /* check if resources/configuration is required according to protocol type */
215 static OSAL_INLINE bool src_proto(enum protocol_type type)
217 return type == PROTOCOLID_TOE;
220 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
222 return type == PROTOCOLID_TOE;
225 static bool tm_tid_proto(enum protocol_type type)
227 return type == PROTOCOLID_FCOE;
230 /* counts the iids for the CDU/CDUC ILT client configuration */
231 struct ecore_cdu_iids {
236 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
237 struct ecore_cdu_iids *iids)
241 for (type = 0; type < MAX_CONN_TYPES; type++) {
242 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
243 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
247 /* counts the iids for the Searcher block configuration */
248 struct ecore_src_iids {
253 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
254 struct ecore_src_iids *iids)
258 for (i = 0; i < MAX_CONN_TYPES; i++) {
262 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
263 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
267 /* counts the iids for the Timers block configuration */
268 struct ecore_tm_iids {
270 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
276 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
277 struct ecore_tm_iids *iids)
279 bool tm_vf_required = false;
280 bool tm_required = false;
283 for (i = 0; i < MAX_CONN_TYPES; i++) {
284 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
286 if (tm_cid_proto(i) || tm_required) {
287 if (p_cfg->cid_count)
290 iids->pf_cids += p_cfg->cid_count;
293 if (tm_cid_proto(i) || tm_vf_required) {
294 if (p_cfg->cids_per_vf)
295 tm_vf_required = true;
299 if (tm_tid_proto(i)) {
300 struct ecore_tid_seg *segs = p_cfg->tid_seg;
302 /* for each segment there is at most one
303 * protocol for which count is not 0.
305 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
306 iids->pf_tids[j] += segs[j].count;
308 /* The last array elelment is for the VFs. As for PF
309 * segments there can be only one protocol for
310 * which this value is not 0.
312 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
316 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
317 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
318 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
320 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
321 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
322 iids->pf_tids_total += iids->pf_tids[j];
326 void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids)
328 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
329 struct ecore_tid_seg *segs;
330 u32 vf_cids = 0, type, j;
333 for (type = 0; type < MAX_CONN_TYPES; type++) {
334 iids->cids += p_mngr->conn_cfg[type].cid_count;
335 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
337 segs = p_mngr->conn_cfg[type].tid_seg;
338 /* for each segment there is at most one
339 * protocol for which count is not 0.
341 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
342 iids->tids += segs[j].count;
344 /* The last array elelment is for the VFs. As for PF
345 * segments there can be only one protocol for
346 * which this value is not 0.
348 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
351 iids->vf_cids += vf_cids * p_mngr->vf_count;
352 iids->tids += vf_tids * p_mngr->vf_count;
354 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
355 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
356 iids->cids, iids->vf_cids, iids->tids, vf_tids);
359 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
362 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
365 /* Find the protocol with tid count > 0 for this segment.
366 * Note: there can only be one and this is already validated.
368 for (i = 0; i < MAX_CONN_TYPES; i++) {
369 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
370 return &p_cfg->conn_cfg[i].tid_seg[seg];
375 /* set the iids (cid/tid) count per protocol */
376 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
377 enum protocol_type type,
378 u32 cid_count, u32 vf_cid_cnt)
380 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
381 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
383 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
384 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
387 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
388 enum protocol_type type, u32 *vf_cid)
391 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
393 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
396 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
397 enum protocol_type type)
399 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
402 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
403 enum protocol_type type)
408 for (i = 0; i < TASK_SEGMENTS; i++)
409 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
414 static OSAL_INLINE void
415 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
416 enum protocol_type proto,
417 u8 seg, u8 seg_type, u32 count, bool has_fl)
419 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
420 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
422 p_seg->count = count;
423 p_seg->has_fl_mem = has_fl;
424 p_seg->type = seg_type;
427 /* the *p_line parameter must be either 0 for the first invocation or the
428 * value returned in the previous invocation.
430 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
431 struct ecore_ilt_cli_blk *p_blk,
433 u32 total_size, u32 elem_size)
435 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
437 /* verify that it's called once for each block */
438 if (p_blk->total_size)
441 p_blk->total_size = total_size;
442 p_blk->real_size_in_page = 0;
444 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
445 p_blk->start_line = start_line;
448 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
449 struct ecore_ilt_client_cfg *p_cli,
450 struct ecore_ilt_cli_blk *p_blk,
451 u32 *p_line, enum ilt_clients client_id)
453 if (!p_blk->total_size)
457 p_cli->first.val = *p_line;
459 p_cli->active = true;
460 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
461 p_cli->last.val = *p_line - 1;
463 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
464 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
465 " [Real %08x] Start line %d\n",
466 client_id, p_cli->first.val, p_cli->last.val,
467 p_blk->total_size, p_blk->real_size_in_page,
471 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
472 enum ilt_clients ilt_client)
474 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
475 struct ecore_ilt_client_cfg *p_cli;
476 u32 lines_to_skip = 0;
479 /* TBD MK: ILT code should be simplified once PROTO enum is changed */
481 if (ilt_client == ILT_CLI_CDUC) {
482 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
484 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
485 (u32)CONN_CXT_SIZE(p_hwfn);
487 lines_to_skip = cid_count / cxts_per_p;
490 return lines_to_skip;
493 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
495 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
496 u32 curr_line, total, i, task_size, line;
497 struct ecore_ilt_client_cfg *p_cli;
498 struct ecore_ilt_cli_blk *p_blk;
499 struct ecore_cdu_iids cdu_iids;
500 struct ecore_src_iids src_iids;
501 struct ecore_qm_iids qm_iids;
502 struct ecore_tm_iids tm_iids;
503 struct ecore_tid_seg *p_seg;
505 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
506 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
507 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
508 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
510 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
512 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
513 "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
514 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
517 p_cli = &p_mngr->clients[ILT_CLI_CDUC];
519 curr_line = p_mngr->pf_start_line;
522 p_cli->pf_total_lines = 0;
524 /* get the counters for the CDUC,CDUC and QM clients */
525 ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
527 p_blk = &p_cli->pf_blks[CDUC_BLK];
529 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
531 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
532 total, CONN_CXT_SIZE(p_hwfn));
534 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
535 p_cli->pf_total_lines = curr_line - p_blk->start_line;
537 p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
541 p_blk = &p_cli->vf_blks[CDUC_BLK];
542 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
544 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
545 total, CONN_CXT_SIZE(p_hwfn));
547 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
548 p_cli->vf_total_lines = curr_line - p_blk->start_line;
550 for (i = 1; i < p_mngr->vf_count; i++)
551 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
555 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
556 p_cli->first.val = curr_line;
558 /* first the 'working' task memory */
559 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
560 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
561 if (!p_seg || p_seg->count == 0)
564 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
565 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
566 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
567 p_mngr->task_type_size[p_seg->type]);
569 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
573 /* next the 'init' task memory (forced load memory) */
574 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
575 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
576 if (!p_seg || p_seg->count == 0)
579 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
581 if (!p_seg->has_fl_mem) {
582 /* The segment is active (total size pf 'working'
583 * memory is > 0) but has no FL (forced-load, Init)
586 * 1. The total-size in the corrsponding FL block of
587 * the ILT client is set to 0 - No ILT line are
588 * provisioned and no ILT memory allocated.
590 * 2. The start-line of said block is set to the
591 * start line of the matching working memory
592 * block in the ILT client. This is later used to
593 * configure the CDU segment offset registers and
594 * results in an FL command for TIDs of this
595 * segment behaves as regular load commands
596 * (loading TIDs from the working memory).
598 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
600 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
603 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
605 ecore_ilt_cli_blk_fill(p_cli, p_blk,
607 p_mngr->task_type_size[p_seg->type]);
609 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
612 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
615 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
616 if (p_seg && p_seg->count) {
617 /* Stricly speaking we need to iterate over all VF
618 * task segment types, but a VF has only 1 segment
621 /* 'working' memory */
622 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
624 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
625 ecore_ilt_cli_blk_fill(p_cli, p_blk,
627 p_mngr->task_type_size[p_seg->type]);
629 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
633 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
634 if (!p_seg->has_fl_mem) {
635 /* see comment above */
636 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
637 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
639 task_size = p_mngr->task_type_size[p_seg->type];
640 ecore_ilt_cli_blk_fill(p_cli, p_blk,
641 curr_line, total, task_size);
642 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
645 p_cli->vf_total_lines = curr_line -
646 p_cli->vf_blks[0].start_line;
648 /* Now for the rest of the VFs */
649 for (i = 1; i < p_mngr->vf_count; i++) {
650 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
651 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
654 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
655 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
661 p_cli = &p_mngr->clients[ILT_CLI_QM];
662 p_blk = &p_cli->pf_blks[0];
664 ecore_cxt_qm_iids(p_hwfn, &qm_iids);
665 total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
666 qm_iids.vf_cids, qm_iids.tids,
667 p_hwfn->qm_info.num_pqs,
668 p_hwfn->qm_info.num_vf_pqs);
670 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
671 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
672 " num_vf_pqs=%d, memory_size=%d)\n",
673 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
674 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
676 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
679 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
680 p_cli->pf_total_lines = curr_line - p_blk->start_line;
683 p_cli = &p_mngr->clients[ILT_CLI_SRC];
684 ecore_cxt_src_iids(p_mngr, &src_iids);
686 /* Both the PF and VFs searcher connections are stored in the per PF
687 * database. Thus sum the PF searcher cids and all the VFs searcher
690 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
692 u32 local_max = OSAL_MAX_T(u32, total,
695 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
697 p_blk = &p_cli->pf_blks[0];
698 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
699 total * sizeof(struct src_ent),
700 sizeof(struct src_ent));
702 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
704 p_cli->pf_total_lines = curr_line - p_blk->start_line;
708 p_cli = &p_mngr->clients[ILT_CLI_TM];
709 ecore_cxt_tm_iids(p_mngr, &tm_iids);
710 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
712 p_blk = &p_cli->pf_blks[0];
713 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
714 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
716 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
718 p_cli->pf_total_lines = curr_line - p_blk->start_line;
722 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
724 p_blk = &p_cli->vf_blks[0];
725 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
726 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
728 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
731 p_cli->vf_total_lines = curr_line - p_blk->start_line;
732 for (i = 1; i < p_mngr->vf_count; i++) {
733 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
738 /* TSDM (SRQ CONTEXT) */
739 total = ecore_cxt_get_srq_count(p_hwfn);
742 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
743 p_blk = &p_cli->pf_blks[SRQ_BLK];
744 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
745 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
747 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
749 p_cli->pf_total_lines = curr_line - p_blk->start_line;
752 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
753 RESC_NUM(p_hwfn, ECORE_ILT)) {
754 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
755 curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
759 return ECORE_SUCCESS;
762 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
764 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
770 for (i = 0; i < p_mngr->t2_num_pages; i++)
771 if (p_mngr->t2[i].p_virt)
772 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
773 p_mngr->t2[i].p_virt,
774 p_mngr->t2[i].p_phys,
777 OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
780 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
782 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
783 u32 conn_num, total_size, ent_per_page, psz, i;
784 struct ecore_ilt_client_cfg *p_src;
785 struct ecore_src_iids src_iids;
786 struct ecore_dma_mem *p_t2;
787 enum _ecore_status_t rc;
789 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
791 /* if the SRC ILT client is inactive - there are no connection
792 * requiring the searcer, leave.
794 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
796 return ECORE_SUCCESS;
798 ecore_cxt_src_iids(p_mngr, &src_iids);
799 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
800 total_size = conn_num * sizeof(struct src_ent);
802 /* use the same page size as the SRC ILT client */
803 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
804 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
807 p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
808 p_mngr->t2_num_pages *
809 sizeof(struct ecore_dma_mem));
811 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
816 /* allocate t2 pages */
817 for (i = 0; i < p_mngr->t2_num_pages; i++) {
818 u32 size = OSAL_MIN_T(u32, total_size, psz);
819 void **p_virt = &p_mngr->t2[i].p_virt;
821 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
822 &p_mngr->t2[i].p_phys, size);
823 if (!p_mngr->t2[i].p_virt) {
827 OSAL_MEM_ZERO(*p_virt, size);
828 p_mngr->t2[i].size = size;
832 /* Set the t2 pointers */
834 /* entries per page - must be a power of two */
835 ent_per_page = psz / sizeof(struct src_ent);
837 p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
839 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
840 p_mngr->last_free = (u64)p_t2->p_phys +
841 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
843 for (i = 0; i < p_mngr->t2_num_pages; i++) {
844 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
845 struct src_ent *entries = p_mngr->t2[i].p_virt;
846 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
849 for (j = 0; j < ent_num - 1; j++) {
850 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
851 entries[j].next = OSAL_CPU_TO_BE64(val);
854 if (i < p_mngr->t2_num_pages - 1)
855 val = (u64)p_mngr->t2[i + 1].p_phys;
858 entries[j].next = OSAL_CPU_TO_BE64(val);
863 return ECORE_SUCCESS;
866 ecore_cxt_src_t2_free(p_hwfn);
870 #define for_each_ilt_valid_client(pos, clients) \
871 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
872 if (!clients[pos].active) { \
877 /* Total number of ILT lines used by this PF */
878 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
883 for_each_ilt_valid_client(i, ilt_clients)
884 size += (ilt_clients[i].last.val -
885 ilt_clients[i].first.val + 1);
890 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
892 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
893 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
896 ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
898 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
899 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
902 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
904 p_dma->p_phys, p_dma->size);
905 p_dma->p_virt = OSAL_NULL;
907 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
910 static enum _ecore_status_t
911 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
912 struct ecore_ilt_cli_blk *p_blk,
913 enum ilt_clients ilt_client, u32 start_line_offset)
915 struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
916 u32 lines, line, sz_left, lines_to_skip = 0;
918 /* Special handling for RoCE that supports dynamic allocation */
919 if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
920 return ECORE_SUCCESS;
922 lines_to_skip = p_blk->dynamic_line_cnt;
924 if (!p_blk->total_size)
925 return ECORE_SUCCESS;
927 sz_left = p_blk->total_size;
928 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
929 line = p_blk->start_line + start_line_offset -
930 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
932 for (; lines; lines--) {
937 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
940 #define ILT_BLOCK_ALIGN_SIZE 0x1000
941 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
943 ILT_BLOCK_ALIGN_SIZE);
946 OSAL_MEM_ZERO(p_virt, size);
948 ilt_shadow[line].p_phys = p_phys;
949 ilt_shadow[line].p_virt = p_virt;
950 ilt_shadow[line].size = size;
952 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
953 "ILT shadow: Line [%d] Physical 0x%lx"
954 " Virtual %p Size %d\n",
955 line, (unsigned long)p_phys, p_virt, size);
961 return ECORE_SUCCESS;
964 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
966 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
967 struct ecore_ilt_client_cfg *clients = p_mngr->clients;
968 struct ecore_ilt_cli_blk *p_blk;
970 enum _ecore_status_t rc;
972 size = ecore_cxt_ilt_shadow_size(clients);
973 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
974 size * sizeof(struct ecore_dma_mem));
976 if (!p_mngr->ilt_shadow) {
977 DP_NOTICE(p_hwfn, true,
978 "Failed to allocate ilt shadow table\n");
980 goto ilt_shadow_fail;
983 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
984 "Allocated 0x%x bytes for ilt shadow\n",
985 (u32)(size * sizeof(struct ecore_dma_mem)));
987 for_each_ilt_valid_client(i, clients) {
988 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
989 p_blk = &clients[i].pf_blks[j];
990 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
991 if (rc != ECORE_SUCCESS)
992 goto ilt_shadow_fail;
994 for (k = 0; k < p_mngr->vf_count; k++) {
995 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
996 u32 lines = clients[i].vf_total_lines * k;
998 p_blk = &clients[i].vf_blks[j];
999 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1001 if (rc != ECORE_SUCCESS)
1002 goto ilt_shadow_fail;
1007 return ECORE_SUCCESS;
1010 ecore_ilt_shadow_free(p_hwfn);
1014 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1016 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1019 for (type = 0; type < MAX_CONN_TYPES; type++) {
1020 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1021 p_mngr->acquired[type].max_count = 0;
1022 p_mngr->acquired[type].start_cid = 0;
1026 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1028 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1032 for (type = 0; type < MAX_CONN_TYPES; type++) {
1033 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1039 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD);
1040 p_mngr->acquired[type].cid_map = OSAL_ZALLOC(p_hwfn->p_dev,
1042 if (!p_mngr->acquired[type].cid_map)
1045 p_mngr->acquired[type].max_count = cid_cnt;
1046 p_mngr->acquired[type].start_cid = start_cid;
1048 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1050 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1051 "Type %08x start: %08x count %08x\n",
1052 type, p_mngr->acquired[type].start_cid,
1053 p_mngr->acquired[type].max_count);
1054 start_cid += cid_cnt;
1057 return ECORE_SUCCESS;
1060 ecore_cid_map_free(p_hwfn);
1064 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1066 struct ecore_ilt_client_cfg *clients;
1067 struct ecore_cxt_mngr *p_mngr;
1070 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1072 DP_NOTICE(p_hwfn, true,
1073 "Failed to allocate `struct ecore_cxt_mngr'\n");
1077 /* Initialize ILT client registers */
1078 clients = p_mngr->clients;
1079 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1080 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1081 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1083 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1084 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1085 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1087 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1088 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1089 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1091 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1092 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1093 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1095 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1096 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1097 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1099 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1100 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1101 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1103 /* default ILT page size for all clients is 32K */
1104 for (i = 0; i < ILT_CLI_MAX; i++)
1105 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1107 /* due to removal of ISCSI/FCoE files union type0_task_context
1108 * task_type_size will be 0. So hardcoded for now.
1110 p_mngr->task_type_size[0] = 512; /* @DPDK */
1111 p_mngr->task_type_size[1] = 128; /* @DPDK */
1113 if (p_hwfn->p_dev->p_iov_info)
1114 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1116 /* Initialize the dynamic ILT allocation mutex */
1117 OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1118 OSAL_MUTEX_INIT(&p_mngr->mutex);
1120 /* Set the cxt mangr pointer priori to further allocations */
1121 p_hwfn->p_cxt_mngr = p_mngr;
1123 return ECORE_SUCCESS;
1126 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1128 enum _ecore_status_t rc;
1130 /* Allocate the ILT shadow table */
1131 rc = ecore_ilt_shadow_alloc(p_hwfn);
1133 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1134 goto tables_alloc_fail;
1137 /* Allocate the T2 table */
1138 rc = ecore_cxt_src_t2_alloc(p_hwfn);
1140 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1141 goto tables_alloc_fail;
1144 /* Allocate and initialize the acquired cids bitmaps */
1145 rc = ecore_cid_map_alloc(p_hwfn);
1147 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1148 goto tables_alloc_fail;
1151 return ECORE_SUCCESS;
1154 ecore_cxt_mngr_free(p_hwfn);
1158 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1160 if (!p_hwfn->p_cxt_mngr)
1163 ecore_cid_map_free(p_hwfn);
1164 ecore_cxt_src_t2_free(p_hwfn);
1165 ecore_ilt_shadow_free(p_hwfn);
1166 OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1167 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1170 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1172 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1175 /* Reset acquired cids */
1176 for (type = 0; type < MAX_CONN_TYPES; type++) {
1177 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1183 for (i = 0; i < DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD); i++)
1184 p_mngr->acquired[type].cid_map[i] = 0;
1188 /* HW initialization helper (per Block, per phase) */
1191 #define CDUC_CXT_SIZE_SHIFT \
1192 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1194 #define CDUC_CXT_SIZE_MASK \
1195 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1197 #define CDUC_BLOCK_WASTE_SHIFT \
1198 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1200 #define CDUC_BLOCK_WASTE_MASK \
1201 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1203 #define CDUC_NCIB_SHIFT \
1204 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1206 #define CDUC_NCIB_MASK \
1207 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1209 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1210 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1212 #define CDUT_TYPE0_CXT_SIZE_MASK \
1213 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1214 CDUT_TYPE0_CXT_SIZE_SHIFT)
1216 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1217 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1219 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1220 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1221 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1223 #define CDUT_TYPE0_NCIB_SHIFT \
1224 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1226 #define CDUT_TYPE0_NCIB_MASK \
1227 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1228 CDUT_TYPE0_NCIB_SHIFT)
1230 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1231 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1233 #define CDUT_TYPE1_CXT_SIZE_MASK \
1234 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1235 CDUT_TYPE1_CXT_SIZE_SHIFT)
1237 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1238 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1240 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1241 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1242 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1244 #define CDUT_TYPE1_NCIB_SHIFT \
1245 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1247 #define CDUT_TYPE1_NCIB_MASK \
1248 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1249 CDUT_TYPE1_NCIB_SHIFT)
1251 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1253 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1255 /* CDUC - connection configuration */
1256 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1257 cxt_size = CONN_CXT_SIZE(p_hwfn);
1258 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1259 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1261 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1262 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1263 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1264 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1266 /* CDUT - type-0 tasks configuration */
1267 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1268 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1269 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1270 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1272 /* cxt size and block-waste are multipes of 8 */
1274 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1275 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1276 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1277 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1279 /* CDUT - type-1 tasks configuration */
1280 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1281 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1282 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1284 /* cxt size and block-waste are multipes of 8 */
1286 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1287 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1288 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1289 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1293 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1294 #define CDU_SEG_REG_TYPE_MASK 0x1
1295 #define CDU_SEG_REG_OFFSET_SHIFT 0
1296 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1298 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1300 struct ecore_ilt_client_cfg *p_cli;
1301 struct ecore_tid_seg *p_seg;
1302 u32 cdu_seg_params, offset;
1305 static const u32 rt_type_offset_arr[] = {
1306 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1307 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1308 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1309 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1312 static const u32 rt_type_offset_fl_arr[] = {
1313 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1314 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1315 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1316 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1319 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1321 /* There are initializations only for CDUT during pf Phase */
1322 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1324 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1328 /* Note: start_line is already adjusted for the CDU
1329 * segment register granularity, so we just need to
1330 * divide. Adjustment is implicit as we assume ILT
1331 * Page size is larger than 32K!
1333 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1334 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1335 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1338 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1339 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1340 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1342 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1343 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1344 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1347 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1348 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1349 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1353 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1355 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1356 struct ecore_qm_iids iids;
1358 OSAL_MEM_ZERO(&iids, sizeof(iids));
1359 ecore_cxt_qm_iids(p_hwfn, &iids);
1361 ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1362 p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1363 p_hwfn->first_on_engine,
1364 iids.cids, iids.vf_cids, iids.tids,
1366 qm_info->num_pqs - qm_info->num_vf_pqs,
1367 qm_info->num_vf_pqs,
1368 qm_info->start_vport,
1369 qm_info->num_vports, qm_info->pf_wfq,
1370 qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1371 p_hwfn->qm_info.qm_vport_params);
1375 static enum _ecore_status_t ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1377 union ecore_qm_pq_params pq_params;
1380 /* XCM pure-LB queue */
1381 OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
1382 pq_params.core.tc = LB_TC;
1383 pq = ecore_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
1384 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq);
1386 return ECORE_SUCCESS;
1390 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1392 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1393 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1395 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1396 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1398 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1399 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1401 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1402 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1404 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1405 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1407 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1408 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1410 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1411 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1413 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1414 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1416 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1417 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1419 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1420 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1422 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1423 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1425 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1426 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1428 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1429 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1431 /* Connection types 6 & 7 are not in use, yet they must be configured
1432 * as the highest possible connection. Not configuring them means the
1433 * defaults will be used, and with a large number of cids a bug may
1434 * occur, if the defaults will be smaller than dq_pf_max_cid /
1437 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1438 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1440 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1441 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1444 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1446 struct ecore_ilt_client_cfg *ilt_clients;
1449 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1450 for_each_ilt_valid_client(i, ilt_clients) {
1451 STORE_RT_REG(p_hwfn,
1452 ilt_clients[i].first.reg,
1453 ilt_clients[i].first.val);
1454 STORE_RT_REG(p_hwfn,
1455 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1456 STORE_RT_REG(p_hwfn,
1457 ilt_clients[i].p_size.reg,
1458 ilt_clients[i].p_size.val);
1462 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1464 struct ecore_ilt_client_cfg *p_cli;
1467 /* For simplicty we set the 'block' to be an ILT page */
1468 if (p_hwfn->p_dev->p_iov_info) {
1469 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1471 STORE_RT_REG(p_hwfn,
1472 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1473 p_iov->first_vf_in_pf);
1474 STORE_RT_REG(p_hwfn,
1475 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1476 p_iov->first_vf_in_pf + p_iov->total_vfs);
1479 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1480 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1481 if (p_cli->active) {
1482 STORE_RT_REG(p_hwfn,
1483 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1485 STORE_RT_REG(p_hwfn,
1486 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1487 p_cli->pf_total_lines);
1488 STORE_RT_REG(p_hwfn,
1489 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1490 p_cli->vf_total_lines);
1493 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1494 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1495 if (p_cli->active) {
1496 STORE_RT_REG(p_hwfn,
1497 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1499 STORE_RT_REG(p_hwfn,
1500 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1501 p_cli->pf_total_lines);
1502 STORE_RT_REG(p_hwfn,
1503 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1504 p_cli->vf_total_lines);
1507 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1508 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1509 if (p_cli->active) {
1510 STORE_RT_REG(p_hwfn,
1511 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1512 STORE_RT_REG(p_hwfn,
1513 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1514 p_cli->pf_total_lines);
1515 STORE_RT_REG(p_hwfn,
1516 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1517 p_cli->vf_total_lines);
1521 /* ILT (PSWRQ2) PF */
1522 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1524 struct ecore_ilt_client_cfg *clients;
1525 struct ecore_cxt_mngr *p_mngr;
1526 struct ecore_dma_mem *p_shdw;
1527 u32 line, rt_offst, i;
1529 ecore_ilt_bounds_init(p_hwfn);
1530 ecore_ilt_vf_bounds_init(p_hwfn);
1532 p_mngr = p_hwfn->p_cxt_mngr;
1533 p_shdw = p_mngr->ilt_shadow;
1534 clients = p_hwfn->p_cxt_mngr->clients;
1536 for_each_ilt_valid_client(i, clients) {
1537 /* Client's 1st val and RT array are absolute, ILT shadows'
1538 * lines are relative.
1540 line = clients[i].first.val - p_mngr->pf_start_line;
1541 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1542 clients[i].first.val * ILT_ENTRY_IN_REGS;
1544 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1545 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1546 u64 ilt_hw_entry = 0;
1548 /** p_virt could be OSAL_NULL incase of dynamic
1551 if (p_shdw[line].p_virt != OSAL_NULL) {
1552 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1553 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1554 (p_shdw[line].p_phys >> 12));
1556 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1557 "Setting RT[0x%08x] from"
1558 " ILT[0x%08x] [Client is %d] to"
1559 " Physical addr: 0x%lx\n",
1561 (unsigned long)(p_shdw[line].
1565 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1570 /* SRC (Searcher) PF */
1571 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1573 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1574 u32 rounded_conn_num, conn_num, conn_max;
1575 struct ecore_src_iids src_iids;
1577 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1578 ecore_cxt_src_iids(p_mngr, &src_iids);
1579 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1583 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1584 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1586 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1587 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1588 OSAL_LOG2(rounded_conn_num));
1590 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1591 p_hwfn->p_cxt_mngr->first_free);
1592 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1593 p_hwfn->p_cxt_mngr->last_free);
1597 #define TM_CFG_NUM_IDS_SHIFT 0
1598 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1599 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1600 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1601 #define TM_CFG_PARENT_PF_SHIFT 25
1602 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1604 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1605 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1607 #define TM_CFG_TID_OFFSET_SHIFT 30
1608 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1609 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1610 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1612 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1614 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1615 u32 active_seg_mask = 0, tm_offset, rt_reg;
1616 struct ecore_tm_iids tm_iids;
1620 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1621 ecore_cxt_tm_iids(p_mngr, &tm_iids);
1623 /* @@@TBD No pre-scan for now */
1625 /* Note: We assume consecutive VFs for a PF */
1626 for (i = 0; i < p_mngr->vf_count; i++) {
1628 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1629 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1630 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1631 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1633 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1634 (sizeof(cfg_word) / sizeof(u32)) *
1635 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1636 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1640 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1641 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1642 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1643 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1645 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1646 (sizeof(cfg_word) / sizeof(u32)) *
1647 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1648 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1651 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1652 tm_iids.pf_cids ? 0x1 : 0x0);
1654 /* @@@TBD how to enable the scan for the VFs */
1656 tm_offset = tm_iids.per_vf_cids;
1658 /* Note: We assume consecutive VFs for a PF */
1659 for (i = 0; i < p_mngr->vf_count; i++) {
1661 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1662 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1663 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1664 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1665 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1667 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1668 (sizeof(cfg_word) / sizeof(u32)) *
1669 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1671 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1674 tm_offset = tm_iids.pf_cids;
1675 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1677 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1678 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1679 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1680 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1681 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1683 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1684 (sizeof(cfg_word) / sizeof(u32)) *
1685 (NUM_OF_VFS(p_hwfn->p_dev) +
1686 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1688 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1689 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1691 tm_offset += tm_iids.pf_tids[i];
1694 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1696 /* @@@TBD how to enable the scan for the VFs */
1699 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1701 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1702 struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1703 struct ecore_tid_seg *p_tid;
1705 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1706 if (!p_fcoe->cid_count)
1709 p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1710 STORE_RT_REG_AGG(p_hwfn,
1711 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1715 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1717 /* CDU configuration */
1718 ecore_cdu_init_common(p_hwfn);
1721 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1723 ecore_qm_init_pf(p_hwfn);
1724 ecore_cm_init_pf(p_hwfn);
1725 ecore_dq_init_pf(p_hwfn);
1726 ecore_cdu_init_pf(p_hwfn);
1727 ecore_ilt_init_pf(p_hwfn);
1728 ecore_src_init_pf(p_hwfn);
1729 ecore_tm_init_pf(p_hwfn);
1730 ecore_prs_init_pf(p_hwfn);
1733 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1734 enum protocol_type type, u32 *p_cid)
1736 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1739 if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1740 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1744 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_mngr->acquired[type].cid_map,
1745 p_mngr->acquired[type].max_count);
1747 if (rel_cid >= p_mngr->acquired[type].max_count) {
1748 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1750 return ECORE_NORESOURCES;
1753 OSAL_SET_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1755 *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1757 return ECORE_SUCCESS;
1760 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1761 u32 cid, enum protocol_type *p_type)
1763 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1764 struct ecore_cid_acquired_map *p_map;
1765 enum protocol_type p;
1768 /* Iterate over protocols and find matching cid range */
1769 for (p = 0; p < MAX_CONN_TYPES; p++) {
1770 p_map = &p_mngr->acquired[p];
1772 if (!p_map->cid_map)
1774 if (cid >= p_map->start_cid &&
1775 cid < p_map->start_cid + p_map->max_count) {
1781 if (p == MAX_CONN_TYPES) {
1782 DP_NOTICE(p_hwfn, true, "Invalid CID %d", cid);
1785 rel_cid = cid - p_map->start_cid;
1786 if (!OSAL_TEST_BIT(rel_cid, p_map->cid_map)) {
1787 DP_NOTICE(p_hwfn, true, "CID %d not acquired", cid);
1793 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1795 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1796 enum protocol_type type;
1800 /* Test acquired and find matching per-protocol map */
1801 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, &type);
1806 rel_cid = cid - p_mngr->acquired[type].start_cid;
1807 OSAL_CLEAR_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1810 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1811 struct ecore_cxt_info *p_info)
1813 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1814 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1815 enum protocol_type type;
1818 /* Test acquired and find matching per-protocol map */
1819 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1824 /* set the protocl type */
1825 p_info->type = type;
1827 /* compute context virtual pointer */
1828 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1830 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1831 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1832 line = p_info->iid / cxts_per_p;
1834 /* Make sure context is allocated (dynamic allocation) */
1835 if (!p_mngr->ilt_shadow[line].p_virt)
1838 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1839 p_info->iid % cxts_per_p * conn_cxt_size;
1841 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1842 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1843 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1845 return ECORE_SUCCESS;
1848 void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
1850 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1852 p_mgr->srq_count = num_srqs;
1855 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
1857 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1859 return p_mgr->srq_count;
1862 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1864 /* Set the number of required CORE connections */
1865 u32 core_cids = 1; /* SPQ */
1867 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1869 switch (p_hwfn->hw_info.personality) {
1872 struct ecore_eth_pf_params *p_params =
1873 &p_hwfn->pf_params.eth_pf_params;
1875 ecore_cxt_set_proto_cid_count(p_hwfn,
1877 p_params->num_cons, 1); /* FIXME VF count... */
1885 return ECORE_SUCCESS;
1888 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
1889 struct ecore_tid_mem *p_info)
1891 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1892 u32 proto, seg, total_lines, i, shadow_line;
1893 struct ecore_ilt_client_cfg *p_cli;
1894 struct ecore_ilt_cli_blk *p_fl_seg;
1895 struct ecore_tid_seg *p_seg_info;
1897 /* Verify the personality */
1898 switch (p_hwfn->hw_info.personality) {
1903 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1907 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1908 if (!p_seg_info->has_fl_mem)
1911 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1912 total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1913 p_fl_seg->real_size_in_page);
1915 for (i = 0; i < total_lines; i++) {
1916 shadow_line = i + p_fl_seg->start_line -
1917 p_hwfn->p_cxt_mngr->pf_start_line;
1918 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1920 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1921 p_fl_seg->real_size_in_page;
1922 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1923 p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1926 return ECORE_SUCCESS;
1929 /* This function is very RoCE oriented, if another protocol in the future
1930 * will want this feature we'll need to modify the function to be more generic
1932 enum _ecore_status_t
1933 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
1934 enum ecore_cxt_elem_type elem_type,
1937 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
1938 struct ecore_ilt_client_cfg *p_cli;
1939 struct ecore_ilt_cli_blk *p_blk;
1940 struct ecore_ptt *p_ptt;
1944 enum _ecore_status_t rc = ECORE_SUCCESS;
1946 switch (elem_type) {
1947 case ECORE_ELEM_CXT:
1948 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1949 elem_size = CONN_CXT_SIZE(p_hwfn);
1950 p_blk = &p_cli->pf_blks[CDUC_BLK];
1952 case ECORE_ELEM_SRQ:
1953 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
1954 elem_size = SRQ_CXT_SIZE;
1955 p_blk = &p_cli->pf_blks[SRQ_BLK];
1957 case ECORE_ELEM_TASK:
1958 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1959 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
1960 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
1963 DP_NOTICE(p_hwfn, false,
1964 "ECORE_INVALID elem type = %d", elem_type);
1968 /* Calculate line in ilt */
1969 hw_p_size = p_cli->p_size.val;
1970 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1971 line = p_blk->start_line + (iid / elems_per_p);
1972 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
1974 /* If line is already allocated, do nothing, otherwise allocate it and
1975 * write it to the PSWRQ2 registers.
1976 * This section can be run in parallel from different contexts and thus
1977 * a mutex protection is needed.
1980 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
1982 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
1985 p_ptt = ecore_ptt_acquire(p_hwfn);
1987 DP_NOTICE(p_hwfn, false,
1988 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
1993 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1995 p_blk->real_size_in_page);
2000 OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2002 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2003 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2004 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2005 p_blk->real_size_in_page;
2007 /* compute absolute offset */
2008 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2009 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2012 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2013 SET_FIELD(ilt_hw_entry,
2015 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2017 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2019 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2020 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2023 if (elem_type == ECORE_ELEM_CXT) {
2024 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2027 /* Update the relevant register in the parser */
2028 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2029 last_cid_allocated - 1);
2031 if (!p_hwfn->b_rdma_enabled_in_prs) {
2032 /* Enable RoCE search */
2033 ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2034 p_hwfn->b_rdma_enabled_in_prs = true;
2039 ecore_ptt_release(p_hwfn, p_ptt);
2041 OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2046 /* This function is very RoCE oriented, if another protocol in the future
2047 * will want this feature we'll need to modify the function to be more generic
2049 static enum _ecore_status_t
2050 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2051 enum ecore_cxt_elem_type elem_type,
2052 u32 start_iid, u32 count)
2054 u32 start_line, end_line, shadow_start_line, shadow_end_line;
2055 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2056 struct ecore_ilt_client_cfg *p_cli;
2057 struct ecore_ilt_cli_blk *p_blk;
2058 u32 end_iid = start_iid + count;
2059 struct ecore_ptt *p_ptt;
2060 u64 ilt_hw_entry = 0;
2063 switch (elem_type) {
2064 case ECORE_ELEM_CXT:
2065 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2066 elem_size = CONN_CXT_SIZE(p_hwfn);
2067 p_blk = &p_cli->pf_blks[CDUC_BLK];
2069 case ECORE_ELEM_SRQ:
2070 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2071 elem_size = SRQ_CXT_SIZE;
2072 p_blk = &p_cli->pf_blks[SRQ_BLK];
2074 case ECORE_ELEM_TASK:
2075 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2076 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2077 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2080 DP_NOTICE(p_hwfn, false,
2081 "ECORE_INVALID elem type = %d", elem_type);
2085 /* Calculate line in ilt */
2086 hw_p_size = p_cli->p_size.val;
2087 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2088 start_line = p_blk->start_line + (start_iid / elems_per_p);
2089 end_line = p_blk->start_line + (end_iid / elems_per_p);
2090 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2093 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2094 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2096 p_ptt = ecore_ptt_acquire(p_hwfn);
2098 DP_NOTICE(p_hwfn, false,
2099 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2100 return ECORE_TIMEOUT;
2103 for (i = shadow_start_line; i < shadow_end_line; i++) {
2104 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2107 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2108 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2109 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2110 p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2112 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2113 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2114 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2116 /* compute absolute offset */
2117 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2118 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2121 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2124 ecore_dmae_host2grc(p_hwfn, p_ptt,
2125 (u64)(osal_uintptr_t)&ilt_hw_entry,
2127 sizeof(ilt_hw_entry) / sizeof(u32),
2131 ecore_ptt_release(p_hwfn, p_ptt);
2133 return ECORE_SUCCESS;
2136 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2137 enum protocol_type proto)
2139 enum _ecore_status_t rc;
2142 /* Free Connection CXT */
2143 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2144 ecore_cxt_get_proto_cid_start(p_hwfn,
2146 ecore_cxt_get_proto_cid_count(p_hwfn,
2154 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2155 ecore_cxt_get_proto_tid_count(p_hwfn,
2161 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2162 ecore_cxt_get_srq_count(p_hwfn));
2167 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
2169 u8 ctx_type, void **pp_task_ctx)
2171 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2172 struct ecore_ilt_client_cfg *p_cli;
2173 struct ecore_ilt_cli_blk *p_seg;
2174 struct ecore_tid_seg *p_seg_info;
2177 u32 tid_size, ilt_idx;
2178 u32 num_tids_per_block;
2180 /* Verify the personality */
2181 switch (p_hwfn->hw_info.personality) {
2186 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2190 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2192 if (ctx_type == ECORE_CTX_WORKING_MEM) {
2193 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2194 } else if (ctx_type == ECORE_CTX_FL_MEM) {
2195 if (!p_seg_info->has_fl_mem)
2197 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2201 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2202 tid_size = p_mngr->task_type_size[p_seg_info->type];
2203 num_tids_per_block = p_seg->real_size_in_page / tid_size;
2205 if (total_lines < tid / num_tids_per_block)
2208 ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2209 p_mngr->pf_start_line;
2210 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2211 (tid % num_tids_per_block) * tid_size;
2213 return ECORE_SUCCESS;