2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "common_hsi.h"
12 #include "ecore_hsi_common.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_status.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_init_fw_funcs.h"
19 #include "ecore_cxt.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
23 #include "ecore_mcp.h"
25 /* Max number of connection types in HW (DQ/CDU etc.) */
26 #define MAX_CONN_TYPES PROTOCOLID_COMMON
27 #define NUM_TASK_TYPES 2
28 #define NUM_TASK_PF_SEGMENTS 4
29 #define NUM_TASK_VF_SEGMENTS 1
31 /* Doorbell-Queue constants */
32 #define DQ_RANGE_SHIFT 4
33 #define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT)
35 /* Searcher constants */
36 #define SRC_MIN_NUM_ELEMS 256
38 /* Timers constants */
40 #define TM_ALIGN (1 << TM_SHIFT)
41 #define TM_ELEM_SIZE 4
44 #define ILT_DEFAULT_HW_P_SIZE 4
46 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
47 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
49 /* ILT entry structure */
50 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
51 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
52 #define ILT_ENTRY_VALID_MASK 0x1ULL
53 #define ILT_ENTRY_VALID_SHIFT 52
54 #define ILT_ENTRY_IN_REGS 2
55 #define ILT_REG_SIZE_IN_BYTES 4
57 /* connection context union */
59 struct e4_core_conn_context core_ctx;
60 struct e4_eth_conn_context eth_ctx;
63 /* TYPE-0 task context - iSCSI, FCOE */
64 union type0_task_context {
67 /* TYPE-1 task context - ROCE */
68 union type1_task_context {
69 struct regpair reserved; /* @DPDK */
77 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
78 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
80 #define CONN_CXT_SIZE(p_hwfn) \
81 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
83 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
85 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
86 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
88 /* Alignment is inherent to the type1_task_context structure */
89 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
91 /* PF per protocl configuration object */
92 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
93 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
95 struct ecore_tid_seg {
101 struct ecore_conn_type_cfg {
104 struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
107 /* ILT Client configuration,
108 * Per connection type (protocol) resources (cids, tis, vf cids etc.)
109 * 1 - for connection context (CDUC) and for each task context we need two
110 * values, for regular task context and for force load memory
112 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
113 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
116 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
117 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS)
129 struct ilt_cfg_pair {
134 struct ecore_ilt_cli_blk {
135 u32 total_size; /* 0 means not active */
136 u32 real_size_in_page;
138 u32 dynamic_line_cnt;
141 struct ecore_ilt_client_cfg {
145 struct ilt_cfg_pair first;
146 struct ilt_cfg_pair last;
147 struct ilt_cfg_pair p_size;
149 /* ILT client blocks for PF */
150 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
153 /* ILT client blocks for VFs */
154 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
160 * Protocol acquired CID lists
161 * PF start line in ILT
163 struct ecore_dma_mem {
169 #define MAP_WORD_SIZE sizeof(unsigned long)
170 #define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8)
172 struct ecore_cid_acquired_map {
175 unsigned long *cid_map;
178 struct ecore_cxt_mngr {
179 /* Per protocl configuration */
180 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
182 /* computed ILT structure */
183 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
185 /* Task type sizes */
186 u32 task_type_size[NUM_TASK_TYPES];
188 /* total number of VFs for this hwfn -
189 * ALL VFs are symmetric in terms of HW resources
194 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
195 /* TBD - do we want this allocated to reserve space? */
196 struct ecore_cid_acquired_map
197 acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS];
199 /* ILT shadow table */
200 struct ecore_dma_mem *ilt_shadow;
203 /* Mutex for a dynamic ILT allocation */
207 struct ecore_dma_mem *t2;
212 /* The infrastructure originally was very generic and context/task
213 * oriented - per connection-type we would set how many of those
214 * are needed, and later when determining how much memory we're
215 * needing for a given block we'd iterate over all the relevant
217 * But since then we've had some additional resources, some of which
218 * require memory which is indepent of the general context/task
219 * scheme. We add those here explicitly per-feature.
222 /* total number of SRQ's for this hwfn */
225 /* Maximal number of L2 steering filters */
228 /* TODO - VF arfs filters ? */
231 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
233 return type == PROTOCOLID_TOE;
236 static bool tm_tid_proto(enum protocol_type type)
238 return type == PROTOCOLID_FCOE;
241 /* counts the iids for the CDU/CDUC ILT client configuration */
242 struct ecore_cdu_iids {
247 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
248 struct ecore_cdu_iids *iids)
252 for (type = 0; type < MAX_CONN_TYPES; type++) {
253 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
254 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
258 /* counts the iids for the Searcher block configuration */
259 struct ecore_src_iids {
264 static void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
265 struct ecore_src_iids *iids)
269 for (i = 0; i < MAX_CONN_TYPES; i++) {
270 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
271 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
274 /* Add L2 filtering filters in addition */
275 iids->pf_cids += p_mngr->arfs_count;
278 /* counts the iids for the Timers block configuration */
279 struct ecore_tm_iids {
281 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
287 static void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
288 struct ecore_tm_iids *iids)
290 bool tm_vf_required = false;
291 bool tm_required = false;
294 for (i = 0; i < MAX_CONN_TYPES; i++) {
295 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
297 if (tm_cid_proto(i) || tm_required) {
298 if (p_cfg->cid_count)
301 iids->pf_cids += p_cfg->cid_count;
304 if (tm_cid_proto(i) || tm_vf_required) {
305 if (p_cfg->cids_per_vf)
306 tm_vf_required = true;
310 if (tm_tid_proto(i)) {
311 struct ecore_tid_seg *segs = p_cfg->tid_seg;
313 /* for each segment there is at most one
314 * protocol for which count is not 0.
316 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
317 iids->pf_tids[j] += segs[j].count;
319 /* The last array elelment is for the VFs. As for PF
320 * segments there can be only one protocol for
321 * which this value is not 0.
323 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
327 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
328 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
329 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
331 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
332 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
333 iids->pf_tids_total += iids->pf_tids[j];
337 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
338 struct ecore_qm_iids *iids)
340 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
341 struct ecore_tid_seg *segs;
342 u32 vf_cids = 0, type, j;
345 for (type = 0; type < MAX_CONN_TYPES; type++) {
346 iids->cids += p_mngr->conn_cfg[type].cid_count;
347 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
349 segs = p_mngr->conn_cfg[type].tid_seg;
350 /* for each segment there is at most one
351 * protocol for which count is not 0.
353 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
354 iids->tids += segs[j].count;
356 /* The last array elelment is for the VFs. As for PF
357 * segments there can be only one protocol for
358 * which this value is not 0.
360 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
363 iids->vf_cids += vf_cids * p_mngr->vf_count;
364 iids->tids += vf_tids * p_mngr->vf_count;
366 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
367 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
368 iids->cids, iids->vf_cids, iids->tids, vf_tids);
371 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
374 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
377 /* Find the protocol with tid count > 0 for this segment.
378 * Note: there can only be one and this is already validated.
380 for (i = 0; i < MAX_CONN_TYPES; i++) {
381 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
382 return &p_cfg->conn_cfg[i].tid_seg[seg];
387 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
389 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
391 p_mgr->srq_count = num_srqs;
394 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
396 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
398 return p_mgr->srq_count;
401 /* set the iids (cid/tid) count per protocol */
402 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
403 enum protocol_type type,
404 u32 cid_count, u32 vf_cid_cnt)
406 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
407 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
409 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
410 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
413 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
414 enum protocol_type type, u32 *vf_cid)
417 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
419 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
422 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
423 enum protocol_type type)
425 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
428 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
429 enum protocol_type type)
434 for (i = 0; i < TASK_SEGMENTS; i++)
435 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
440 static OSAL_INLINE void
441 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
442 enum protocol_type proto,
443 u8 seg, u8 seg_type, u32 count, bool has_fl)
445 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
446 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
448 p_seg->count = count;
449 p_seg->has_fl_mem = has_fl;
450 p_seg->type = seg_type;
453 /* the *p_line parameter must be either 0 for the first invocation or the
454 * value returned in the previous invocation.
456 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
457 struct ecore_ilt_cli_blk *p_blk,
459 u32 total_size, u32 elem_size)
461 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
463 /* verify that it's called once for each block */
464 if (p_blk->total_size)
467 p_blk->total_size = total_size;
468 p_blk->real_size_in_page = 0;
470 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
471 p_blk->start_line = start_line;
474 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
475 struct ecore_ilt_client_cfg *p_cli,
476 struct ecore_ilt_cli_blk *p_blk,
477 u32 *p_line, enum ilt_clients client_id)
479 if (!p_blk->total_size)
483 p_cli->first.val = *p_line;
485 p_cli->active = true;
486 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
487 p_cli->last.val = *p_line - 1;
489 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
490 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
491 " [Real %08x] Start line %d\n",
492 client_id, p_cli->first.val, p_cli->last.val,
493 p_blk->total_size, p_blk->real_size_in_page,
497 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
498 enum ilt_clients ilt_client)
500 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
501 struct ecore_ilt_client_cfg *p_cli;
502 u32 lines_to_skip = 0;
505 /* TBD MK: ILT code should be simplified once PROTO enum is changed */
507 if (ilt_client == ILT_CLI_CDUC) {
508 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
510 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
511 (u32)CONN_CXT_SIZE(p_hwfn);
513 lines_to_skip = cid_count / cxts_per_p;
516 return lines_to_skip;
519 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
521 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
522 u32 curr_line, total, i, task_size, line;
523 struct ecore_ilt_client_cfg *p_cli;
524 struct ecore_ilt_cli_blk *p_blk;
525 struct ecore_cdu_iids cdu_iids;
526 struct ecore_src_iids src_iids;
527 struct ecore_qm_iids qm_iids;
528 struct ecore_tm_iids tm_iids;
529 struct ecore_tid_seg *p_seg;
531 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
532 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
533 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
534 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
536 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
538 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
539 "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
540 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
543 p_cli = &p_mngr->clients[ILT_CLI_CDUC];
545 curr_line = p_mngr->pf_start_line;
548 p_cli->pf_total_lines = 0;
550 /* get the counters for the CDUC,CDUC and QM clients */
551 ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
553 p_blk = &p_cli->pf_blks[CDUC_BLK];
555 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
557 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
558 total, CONN_CXT_SIZE(p_hwfn));
560 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
561 p_cli->pf_total_lines = curr_line - p_blk->start_line;
563 p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
567 p_blk = &p_cli->vf_blks[CDUC_BLK];
568 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
570 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
571 total, CONN_CXT_SIZE(p_hwfn));
573 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
574 p_cli->vf_total_lines = curr_line - p_blk->start_line;
576 for (i = 1; i < p_mngr->vf_count; i++)
577 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
581 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
582 p_cli->first.val = curr_line;
584 /* first the 'working' task memory */
585 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
586 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
587 if (!p_seg || p_seg->count == 0)
590 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
591 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
592 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
593 p_mngr->task_type_size[p_seg->type]);
595 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
599 /* next the 'init' task memory (forced load memory) */
600 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
601 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
602 if (!p_seg || p_seg->count == 0)
605 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
607 if (!p_seg->has_fl_mem) {
608 /* The segment is active (total size pf 'working'
609 * memory is > 0) but has no FL (forced-load, Init)
612 * 1. The total-size in the corrsponding FL block of
613 * the ILT client is set to 0 - No ILT line are
614 * provisioned and no ILT memory allocated.
616 * 2. The start-line of said block is set to the
617 * start line of the matching working memory
618 * block in the ILT client. This is later used to
619 * configure the CDU segment offset registers and
620 * results in an FL command for TIDs of this
621 * segment behaves as regular load commands
622 * (loading TIDs from the working memory).
624 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
626 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
629 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
631 ecore_ilt_cli_blk_fill(p_cli, p_blk,
633 p_mngr->task_type_size[p_seg->type]);
635 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
638 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
641 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
642 if (p_seg && p_seg->count) {
643 /* Stricly speaking we need to iterate over all VF
644 * task segment types, but a VF has only 1 segment
647 /* 'working' memory */
648 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
650 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
651 ecore_ilt_cli_blk_fill(p_cli, p_blk,
653 p_mngr->task_type_size[p_seg->type]);
655 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
659 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
660 if (!p_seg->has_fl_mem) {
661 /* see comment above */
662 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
663 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
665 task_size = p_mngr->task_type_size[p_seg->type];
666 ecore_ilt_cli_blk_fill(p_cli, p_blk,
667 curr_line, total, task_size);
668 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
671 p_cli->vf_total_lines = curr_line -
672 p_cli->vf_blks[0].start_line;
674 /* Now for the rest of the VFs */
675 for (i = 1; i < p_mngr->vf_count; i++) {
676 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
677 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
680 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
681 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
687 p_cli = &p_mngr->clients[ILT_CLI_QM];
688 p_blk = &p_cli->pf_blks[0];
690 ecore_cxt_qm_iids(p_hwfn, &qm_iids);
691 total = ecore_qm_pf_mem_size(qm_iids.cids,
692 qm_iids.vf_cids, qm_iids.tids,
693 p_hwfn->qm_info.num_pqs,
694 p_hwfn->qm_info.num_vf_pqs);
696 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
697 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
698 " num_vf_pqs=%d, memory_size=%d)\n",
699 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
700 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
702 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
705 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
706 p_cli->pf_total_lines = curr_line - p_blk->start_line;
709 p_cli = &p_mngr->clients[ILT_CLI_SRC];
710 ecore_cxt_src_iids(p_mngr, &src_iids);
712 /* Both the PF and VFs searcher connections are stored in the per PF
713 * database. Thus sum the PF searcher cids and all the VFs searcher
716 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
718 u32 local_max = OSAL_MAX_T(u32, total,
721 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
723 p_blk = &p_cli->pf_blks[0];
724 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
725 total * sizeof(struct src_ent),
726 sizeof(struct src_ent));
728 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
730 p_cli->pf_total_lines = curr_line - p_blk->start_line;
734 p_cli = &p_mngr->clients[ILT_CLI_TM];
735 ecore_cxt_tm_iids(p_mngr, &tm_iids);
736 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
738 p_blk = &p_cli->pf_blks[0];
739 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
740 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
742 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
744 p_cli->pf_total_lines = curr_line - p_blk->start_line;
748 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
750 p_blk = &p_cli->vf_blks[0];
751 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
752 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
754 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
757 p_cli->vf_total_lines = curr_line - p_blk->start_line;
758 for (i = 1; i < p_mngr->vf_count; i++) {
759 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
764 /* TSDM (SRQ CONTEXT) */
765 total = ecore_cxt_get_srq_count(p_hwfn);
768 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
769 p_blk = &p_cli->pf_blks[SRQ_BLK];
770 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
771 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
773 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
775 p_cli->pf_total_lines = curr_line - p_blk->start_line;
778 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
779 RESC_NUM(p_hwfn, ECORE_ILT)) {
780 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
781 curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
785 return ECORE_SUCCESS;
788 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
790 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
796 for (i = 0; i < p_mngr->t2_num_pages; i++)
797 if (p_mngr->t2[i].p_virt)
798 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
799 p_mngr->t2[i].p_virt,
800 p_mngr->t2[i].p_phys,
803 OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
806 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
808 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
809 u32 conn_num, total_size, ent_per_page, psz, i;
810 struct ecore_ilt_client_cfg *p_src;
811 struct ecore_src_iids src_iids;
812 struct ecore_dma_mem *p_t2;
813 enum _ecore_status_t rc;
815 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
817 /* if the SRC ILT client is inactive - there are no connection
818 * requiring the searcer, leave.
820 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
822 return ECORE_SUCCESS;
824 ecore_cxt_src_iids(p_mngr, &src_iids);
825 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
826 total_size = conn_num * sizeof(struct src_ent);
828 /* use the same page size as the SRC ILT client */
829 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
830 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
833 p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
834 p_mngr->t2_num_pages *
835 sizeof(struct ecore_dma_mem));
837 DP_NOTICE(p_hwfn, false, "Failed to allocate t2 table\n");
842 /* allocate t2 pages */
843 for (i = 0; i < p_mngr->t2_num_pages; i++) {
844 u32 size = OSAL_MIN_T(u32, total_size, psz);
845 void **p_virt = &p_mngr->t2[i].p_virt;
847 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
848 &p_mngr->t2[i].p_phys, size);
849 if (!p_mngr->t2[i].p_virt) {
853 OSAL_MEM_ZERO(*p_virt, size);
854 p_mngr->t2[i].size = size;
858 /* Set the t2 pointers */
860 /* entries per page - must be a power of two */
861 ent_per_page = psz / sizeof(struct src_ent);
863 p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
865 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
866 p_mngr->last_free = (u64)p_t2->p_phys +
867 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
869 for (i = 0; i < p_mngr->t2_num_pages; i++) {
870 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
871 struct src_ent *entries = p_mngr->t2[i].p_virt;
872 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
875 for (j = 0; j < ent_num - 1; j++) {
876 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
877 entries[j].next = OSAL_CPU_TO_BE64(val);
880 if (i < p_mngr->t2_num_pages - 1)
881 val = (u64)p_mngr->t2[i + 1].p_phys;
884 entries[j].next = OSAL_CPU_TO_BE64(val);
889 return ECORE_SUCCESS;
892 ecore_cxt_src_t2_free(p_hwfn);
896 #define for_each_ilt_valid_client(pos, clients) \
897 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
898 if (!clients[pos].active) { \
903 /* Total number of ILT lines used by this PF */
904 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
909 for_each_ilt_valid_client(i, ilt_clients)
910 size += (ilt_clients[i].last.val -
911 ilt_clients[i].first.val + 1);
916 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
918 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
919 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
922 if (p_mngr->ilt_shadow == OSAL_NULL)
925 ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
927 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
928 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
931 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
933 p_dma->p_phys, p_dma->size);
934 p_dma->p_virt = OSAL_NULL;
936 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
937 p_mngr->ilt_shadow = OSAL_NULL;
940 static enum _ecore_status_t
941 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
942 struct ecore_ilt_cli_blk *p_blk,
943 enum ilt_clients ilt_client, u32 start_line_offset)
945 struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
946 u32 lines, line, sz_left, lines_to_skip = 0;
948 /* Special handling for RoCE that supports dynamic allocation */
949 if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
950 return ECORE_SUCCESS;
952 lines_to_skip = p_blk->dynamic_line_cnt;
954 if (!p_blk->total_size)
955 return ECORE_SUCCESS;
957 sz_left = p_blk->total_size;
958 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
959 line = p_blk->start_line + start_line_offset -
960 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
962 for (; lines; lines--) {
967 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
970 #define ILT_BLOCK_ALIGN_SIZE 0x1000
971 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
973 ILT_BLOCK_ALIGN_SIZE);
976 OSAL_MEM_ZERO(p_virt, size);
978 ilt_shadow[line].p_phys = p_phys;
979 ilt_shadow[line].p_virt = p_virt;
980 ilt_shadow[line].size = size;
982 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
983 "ILT shadow: Line [%d] Physical 0x%lx"
984 " Virtual %p Size %d\n",
985 line, (unsigned long)p_phys, p_virt, size);
991 return ECORE_SUCCESS;
994 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
996 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
997 struct ecore_ilt_client_cfg *clients = p_mngr->clients;
998 struct ecore_ilt_cli_blk *p_blk;
1000 enum _ecore_status_t rc;
1002 size = ecore_cxt_ilt_shadow_size(clients);
1003 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1004 size * sizeof(struct ecore_dma_mem));
1006 if (!p_mngr->ilt_shadow) {
1007 DP_NOTICE(p_hwfn, false, "Failed to allocate ilt shadow table\n");
1009 goto ilt_shadow_fail;
1012 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1013 "Allocated 0x%x bytes for ilt shadow\n",
1014 (u32)(size * sizeof(struct ecore_dma_mem)));
1016 for_each_ilt_valid_client(i, clients) {
1017 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1018 p_blk = &clients[i].pf_blks[j];
1019 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1020 if (rc != ECORE_SUCCESS)
1021 goto ilt_shadow_fail;
1023 for (k = 0; k < p_mngr->vf_count; k++) {
1024 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1025 u32 lines = clients[i].vf_total_lines * k;
1027 p_blk = &clients[i].vf_blks[j];
1028 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1030 if (rc != ECORE_SUCCESS)
1031 goto ilt_shadow_fail;
1036 return ECORE_SUCCESS;
1039 ecore_ilt_shadow_free(p_hwfn);
1043 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1045 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1048 for (type = 0; type < MAX_CONN_TYPES; type++) {
1049 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1050 p_mngr->acquired[type].cid_map = OSAL_NULL;
1051 p_mngr->acquired[type].max_count = 0;
1052 p_mngr->acquired[type].start_cid = 0;
1054 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1055 OSAL_FREE(p_hwfn->p_dev,
1056 p_mngr->acquired_vf[type][vf].cid_map);
1057 p_mngr->acquired_vf[type][vf].cid_map = OSAL_NULL;
1058 p_mngr->acquired_vf[type][vf].max_count = 0;
1059 p_mngr->acquired_vf[type][vf].start_cid = 0;
1064 static enum _ecore_status_t
1065 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1066 u32 cid_start, u32 cid_count,
1067 struct ecore_cid_acquired_map *p_map)
1072 return ECORE_SUCCESS;
1074 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1075 p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1076 if (p_map->cid_map == OSAL_NULL)
1079 p_map->max_count = cid_count;
1080 p_map->start_cid = cid_start;
1082 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1083 "Type %08x start: %08x count %08x\n",
1084 type, p_map->start_cid, p_map->max_count);
1086 return ECORE_SUCCESS;
1089 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1091 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1092 u32 start_cid = 0, vf_start_cid = 0;
1095 for (type = 0; type < MAX_CONN_TYPES; type++) {
1096 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1097 struct ecore_cid_acquired_map *p_map;
1099 /* Handle PF maps */
1100 p_map = &p_mngr->acquired[type];
1101 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1102 p_cfg->cid_count, p_map))
1105 /* Handle VF maps */
1106 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1107 p_map = &p_mngr->acquired_vf[type][vf];
1108 if (ecore_cid_map_alloc_single(p_hwfn, type,
1115 start_cid += p_cfg->cid_count;
1116 vf_start_cid += p_cfg->cids_per_vf;
1119 return ECORE_SUCCESS;
1122 ecore_cid_map_free(p_hwfn);
1126 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1128 struct ecore_ilt_client_cfg *clients;
1129 struct ecore_cxt_mngr *p_mngr;
1132 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1134 DP_NOTICE(p_hwfn, false, "Failed to allocate `struct ecore_cxt_mngr'\n");
1138 /* Initialize ILT client registers */
1139 clients = p_mngr->clients;
1140 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1141 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1142 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1144 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1145 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1146 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1148 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1149 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1150 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1152 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1153 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1154 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1156 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1157 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1158 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1160 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1161 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1162 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1164 /* default ILT page size for all clients is 64K */
1165 for (i = 0; i < ILT_CLI_MAX; i++)
1166 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1168 /* due to removal of ISCSI/FCoE files union type0_task_context
1169 * task_type_size will be 0. So hardcoded for now.
1171 p_mngr->task_type_size[0] = 512; /* @DPDK */
1172 p_mngr->task_type_size[1] = 128; /* @DPDK */
1174 if (p_hwfn->p_dev->p_iov_info)
1175 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1177 /* Initialize the dynamic ILT allocation mutex */
1178 #ifdef CONFIG_ECORE_LOCK_ALLOC
1179 OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1181 OSAL_MUTEX_INIT(&p_mngr->mutex);
1183 /* Set the cxt mangr pointer priori to further allocations */
1184 p_hwfn->p_cxt_mngr = p_mngr;
1186 return ECORE_SUCCESS;
1189 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1191 enum _ecore_status_t rc;
1193 /* Allocate the ILT shadow table */
1194 rc = ecore_ilt_shadow_alloc(p_hwfn);
1196 DP_NOTICE(p_hwfn, false, "Failed to allocate ilt memory\n");
1197 goto tables_alloc_fail;
1200 /* Allocate the T2 table */
1201 rc = ecore_cxt_src_t2_alloc(p_hwfn);
1203 DP_NOTICE(p_hwfn, false, "Failed to allocate T2 memory\n");
1204 goto tables_alloc_fail;
1207 /* Allocate and initialize the acquired cids bitmaps */
1208 rc = ecore_cid_map_alloc(p_hwfn);
1210 DP_NOTICE(p_hwfn, false, "Failed to allocate cid maps\n");
1211 goto tables_alloc_fail;
1214 return ECORE_SUCCESS;
1217 ecore_cxt_mngr_free(p_hwfn);
1221 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1223 if (!p_hwfn->p_cxt_mngr)
1226 ecore_cid_map_free(p_hwfn);
1227 ecore_cxt_src_t2_free(p_hwfn);
1228 ecore_ilt_shadow_free(p_hwfn);
1229 #ifdef CONFIG_ECORE_LOCK_ALLOC
1230 OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1232 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1235 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1237 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1238 struct ecore_cid_acquired_map *p_map;
1239 struct ecore_conn_type_cfg *p_cfg;
1243 /* Reset acquired cids */
1244 for (type = 0; type < MAX_CONN_TYPES; type++) {
1247 p_cfg = &p_mngr->conn_cfg[type];
1248 if (p_cfg->cid_count) {
1249 p_map = &p_mngr->acquired[type];
1250 len = DIV_ROUND_UP(p_map->max_count,
1251 BITS_PER_MAP_WORD) *
1253 OSAL_MEM_ZERO(p_map->cid_map, len);
1256 if (!p_cfg->cids_per_vf)
1259 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1260 p_map = &p_mngr->acquired_vf[type][vf];
1261 len = DIV_ROUND_UP(p_map->max_count,
1262 BITS_PER_MAP_WORD) *
1264 OSAL_MEM_ZERO(p_map->cid_map, len);
1269 /* HW initialization helper (per Block, per phase) */
1272 #define CDUC_CXT_SIZE_SHIFT \
1273 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1275 #define CDUC_CXT_SIZE_MASK \
1276 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1278 #define CDUC_BLOCK_WASTE_SHIFT \
1279 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1281 #define CDUC_BLOCK_WASTE_MASK \
1282 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1284 #define CDUC_NCIB_SHIFT \
1285 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1287 #define CDUC_NCIB_MASK \
1288 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1290 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1291 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1293 #define CDUT_TYPE0_CXT_SIZE_MASK \
1294 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1295 CDUT_TYPE0_CXT_SIZE_SHIFT)
1297 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1298 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1300 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1301 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1302 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1304 #define CDUT_TYPE0_NCIB_SHIFT \
1305 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1307 #define CDUT_TYPE0_NCIB_MASK \
1308 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1309 CDUT_TYPE0_NCIB_SHIFT)
1311 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1312 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1314 #define CDUT_TYPE1_CXT_SIZE_MASK \
1315 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1316 CDUT_TYPE1_CXT_SIZE_SHIFT)
1318 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1319 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1321 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1322 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1323 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1325 #define CDUT_TYPE1_NCIB_SHIFT \
1326 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1328 #define CDUT_TYPE1_NCIB_MASK \
1329 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1330 CDUT_TYPE1_NCIB_SHIFT)
1332 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1334 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1336 /* CDUC - connection configuration */
1337 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1338 cxt_size = CONN_CXT_SIZE(p_hwfn);
1339 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1340 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1342 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1343 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1344 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1345 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1347 /* CDUT - type-0 tasks configuration */
1348 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1349 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1350 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1351 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1353 /* cxt size and block-waste are multipes of 8 */
1355 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1356 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1357 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1358 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1360 /* CDUT - type-1 tasks configuration */
1361 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1362 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1363 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1365 /* cxt size and block-waste are multipes of 8 */
1367 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1368 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1369 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1370 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1374 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1375 #define CDU_SEG_REG_TYPE_MASK 0x1
1376 #define CDU_SEG_REG_OFFSET_SHIFT 0
1377 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1379 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1381 struct ecore_ilt_client_cfg *p_cli;
1382 struct ecore_tid_seg *p_seg;
1383 u32 cdu_seg_params, offset;
1386 static const u32 rt_type_offset_arr[] = {
1387 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1388 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1389 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1390 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1393 static const u32 rt_type_offset_fl_arr[] = {
1394 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1395 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1396 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1397 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1400 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1402 /* There are initializations only for CDUT during pf Phase */
1403 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1405 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1409 /* Note: start_line is already adjusted for the CDU
1410 * segment register granularity, so we just need to
1411 * divide. Adjustment is implicit as we assume ILT
1412 * Page size is larger than 32K!
1414 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1415 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1416 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1419 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1420 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1421 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1423 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1424 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1425 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1428 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1429 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1430 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1434 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1437 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1438 struct ecore_mcp_link_state *p_link;
1439 struct ecore_qm_iids iids;
1441 OSAL_MEM_ZERO(&iids, sizeof(iids));
1442 ecore_cxt_qm_iids(p_hwfn, &iids);
1444 p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output;
1446 ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1447 qm_info->max_phys_tcs_per_port,
1449 iids.cids, iids.vf_cids, iids.tids,
1451 qm_info->num_pqs - qm_info->num_vf_pqs,
1452 qm_info->num_vf_pqs,
1453 qm_info->start_vport,
1454 qm_info->num_vports, qm_info->pf_wfq,
1455 qm_info->pf_rl, p_link->speed,
1456 p_hwfn->qm_info.qm_pq_params,
1457 p_hwfn->qm_info.qm_vport_params);
1461 static void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1463 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1464 ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1468 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1470 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1471 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1473 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1474 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1476 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1477 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1479 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1480 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1482 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1483 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1485 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1486 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1488 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1489 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1491 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1492 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1494 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1495 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1497 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1498 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1500 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1501 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1503 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1504 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1506 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1507 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1509 /* Connection types 6 & 7 are not in use, yet they must be configured
1510 * as the highest possible connection. Not configuring them means the
1511 * defaults will be used, and with a large number of cids a bug may
1512 * occur, if the defaults will be smaller than dq_pf_max_cid /
1515 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1516 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1518 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1519 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1522 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1524 struct ecore_ilt_client_cfg *ilt_clients;
1527 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1528 for_each_ilt_valid_client(i, ilt_clients) {
1529 STORE_RT_REG(p_hwfn,
1530 ilt_clients[i].first.reg,
1531 ilt_clients[i].first.val);
1532 STORE_RT_REG(p_hwfn,
1533 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1534 STORE_RT_REG(p_hwfn,
1535 ilt_clients[i].p_size.reg,
1536 ilt_clients[i].p_size.val);
1540 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1542 struct ecore_ilt_client_cfg *p_cli;
1545 /* For simplicty we set the 'block' to be an ILT page */
1546 if (p_hwfn->p_dev->p_iov_info) {
1547 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1549 STORE_RT_REG(p_hwfn,
1550 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1551 p_iov->first_vf_in_pf);
1552 STORE_RT_REG(p_hwfn,
1553 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1554 p_iov->first_vf_in_pf + p_iov->total_vfs);
1557 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1558 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1559 if (p_cli->active) {
1560 STORE_RT_REG(p_hwfn,
1561 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1563 STORE_RT_REG(p_hwfn,
1564 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1565 p_cli->pf_total_lines);
1566 STORE_RT_REG(p_hwfn,
1567 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1568 p_cli->vf_total_lines);
1571 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1572 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1573 if (p_cli->active) {
1574 STORE_RT_REG(p_hwfn,
1575 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1577 STORE_RT_REG(p_hwfn,
1578 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1579 p_cli->pf_total_lines);
1580 STORE_RT_REG(p_hwfn,
1581 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1582 p_cli->vf_total_lines);
1585 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1586 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1587 if (p_cli->active) {
1588 STORE_RT_REG(p_hwfn,
1589 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1590 STORE_RT_REG(p_hwfn,
1591 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1592 p_cli->pf_total_lines);
1593 STORE_RT_REG(p_hwfn,
1594 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1595 p_cli->vf_total_lines);
1599 /* ILT (PSWRQ2) PF */
1600 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1602 struct ecore_ilt_client_cfg *clients;
1603 struct ecore_cxt_mngr *p_mngr;
1604 struct ecore_dma_mem *p_shdw;
1605 u32 line, rt_offst, i;
1607 ecore_ilt_bounds_init(p_hwfn);
1608 ecore_ilt_vf_bounds_init(p_hwfn);
1610 p_mngr = p_hwfn->p_cxt_mngr;
1611 p_shdw = p_mngr->ilt_shadow;
1612 clients = p_hwfn->p_cxt_mngr->clients;
1614 for_each_ilt_valid_client(i, clients) {
1615 /* Client's 1st val and RT array are absolute, ILT shadows'
1616 * lines are relative.
1618 line = clients[i].first.val - p_mngr->pf_start_line;
1619 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1620 clients[i].first.val * ILT_ENTRY_IN_REGS;
1622 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1623 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1624 u64 ilt_hw_entry = 0;
1626 /** p_virt could be OSAL_NULL incase of dynamic
1629 if (p_shdw[line].p_virt != OSAL_NULL) {
1630 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1631 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1632 (p_shdw[line].p_phys >> 12));
1634 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1635 "Setting RT[0x%08x] from"
1636 " ILT[0x%08x] [Client is %d] to"
1637 " Physical addr: 0x%lx\n",
1639 (unsigned long)(p_shdw[line].
1643 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1648 /* SRC (Searcher) PF */
1649 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1651 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1652 u32 rounded_conn_num, conn_num, conn_max;
1653 struct ecore_src_iids src_iids;
1655 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1656 ecore_cxt_src_iids(p_mngr, &src_iids);
1657 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1661 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1662 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1664 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1665 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1666 OSAL_LOG2(rounded_conn_num));
1668 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1669 p_hwfn->p_cxt_mngr->first_free);
1670 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1671 p_hwfn->p_cxt_mngr->last_free);
1672 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1673 "Configured SEARCHER for 0x%08x connections\n",
1678 #define TM_CFG_NUM_IDS_SHIFT 0
1679 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1680 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1681 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1682 #define TM_CFG_PARENT_PF_SHIFT 25
1683 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1685 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1686 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1688 #define TM_CFG_TID_OFFSET_SHIFT 30
1689 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1690 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1691 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1693 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1695 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1696 u32 active_seg_mask = 0, tm_offset, rt_reg;
1697 struct ecore_tm_iids tm_iids;
1701 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1702 ecore_cxt_tm_iids(p_mngr, &tm_iids);
1704 /* @@@TBD No pre-scan for now */
1706 /* Note: We assume consecutive VFs for a PF */
1707 for (i = 0; i < p_mngr->vf_count; i++) {
1709 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1710 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1711 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1712 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1714 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1715 (sizeof(cfg_word) / sizeof(u32)) *
1716 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1717 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1721 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1722 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1723 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1724 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1726 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1727 (sizeof(cfg_word) / sizeof(u32)) *
1728 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1729 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1732 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1733 tm_iids.pf_cids ? 0x1 : 0x0);
1735 /* @@@TBD how to enable the scan for the VFs */
1737 tm_offset = tm_iids.per_vf_cids;
1739 /* Note: We assume consecutive VFs for a PF */
1740 for (i = 0; i < p_mngr->vf_count; i++) {
1742 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1743 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1744 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1745 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1746 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1748 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1749 (sizeof(cfg_word) / sizeof(u32)) *
1750 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1752 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1755 tm_offset = tm_iids.pf_cids;
1756 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1758 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1759 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1760 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1761 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1762 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1764 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1765 (sizeof(cfg_word) / sizeof(u32)) *
1766 (NUM_OF_VFS(p_hwfn->p_dev) +
1767 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1769 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1770 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1772 tm_offset += tm_iids.pf_tids[i];
1775 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1777 /* @@@TBD how to enable the scan for the VFs */
1780 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1782 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1783 struct ecore_conn_type_cfg *p_fcoe;
1784 struct ecore_tid_seg *p_tid;
1786 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1788 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1789 if (!p_fcoe->cid_count)
1792 p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1793 STORE_RT_REG_AGG(p_hwfn,
1794 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1798 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1800 /* CDU configuration */
1801 ecore_cdu_init_common(p_hwfn);
1804 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1806 ecore_qm_init_pf(p_hwfn, p_ptt, true);
1807 ecore_cm_init_pf(p_hwfn);
1808 ecore_dq_init_pf(p_hwfn);
1809 ecore_cdu_init_pf(p_hwfn);
1810 ecore_ilt_init_pf(p_hwfn);
1811 ecore_src_init_pf(p_hwfn);
1812 ecore_tm_init_pf(p_hwfn);
1813 ecore_prs_init_pf(p_hwfn);
1816 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1817 enum protocol_type type,
1818 u32 *p_cid, u8 vfid)
1820 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1821 struct ecore_cid_acquired_map *p_map;
1824 if (type >= MAX_CONN_TYPES) {
1825 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1829 if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) {
1830 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1834 /* Determine the right map to take this CID from */
1835 if (vfid == ECORE_CXT_PF_CID)
1836 p_map = &p_mngr->acquired[type];
1838 p_map = &p_mngr->acquired_vf[type][vfid];
1840 if (p_map->cid_map == OSAL_NULL) {
1841 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1845 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1848 if (rel_cid >= p_map->max_count) {
1849 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1851 return ECORE_NORESOURCES;
1854 OSAL_SET_BIT(rel_cid, p_map->cid_map);
1856 *p_cid = rel_cid + p_map->start_cid;
1858 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1859 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1860 *p_cid, rel_cid, vfid, type);
1862 return ECORE_SUCCESS;
1865 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1866 enum protocol_type type,
1869 return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
1872 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1874 enum protocol_type *p_type,
1875 struct ecore_cid_acquired_map **pp_map)
1877 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1880 /* Iterate over protocols and find matching cid range */
1881 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1882 if (vfid == ECORE_CXT_PF_CID)
1883 *pp_map = &p_mngr->acquired[*p_type];
1885 *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1887 if (!((*pp_map)->cid_map))
1889 if (cid >= (*pp_map)->start_cid &&
1890 cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
1894 if (*p_type == MAX_CONN_TYPES) {
1895 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
1899 rel_cid = cid - (*pp_map)->start_cid;
1900 if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
1901 DP_NOTICE(p_hwfn, true,
1902 "CID %d [vifd %02x] not acquired", cid, vfid);
1908 *p_type = MAX_CONN_TYPES;
1909 *pp_map = OSAL_NULL;
1913 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
1915 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1916 enum protocol_type type;
1920 if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) {
1921 DP_NOTICE(p_hwfn, true,
1922 "Trying to return incorrect CID belonging to VF %02x\n",
1927 /* Test acquired and find matching per-protocol map */
1928 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
1934 rel_cid = cid - p_map->start_cid;
1935 OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
1937 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1938 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
1939 cid, rel_cid, vfid, type);
1942 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1944 _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
1947 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1948 struct ecore_cxt_info *p_info)
1950 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1951 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1952 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1953 enum protocol_type type;
1956 /* Test acquired and find matching per-protocol map */
1957 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
1964 /* set the protocl type */
1965 p_info->type = type;
1967 /* compute context virtual pointer */
1968 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1970 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1971 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1972 line = p_info->iid / cxts_per_p;
1974 /* Make sure context is allocated (dynamic allocation) */
1975 if (!p_mngr->ilt_shadow[line].p_virt)
1978 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1979 p_info->iid % cxts_per_p * conn_cxt_size;
1981 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1982 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1983 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1985 return ECORE_SUCCESS;
1988 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1990 /* Set the number of required CORE connections */
1991 u32 core_cids = 1; /* SPQ */
1993 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1995 switch (p_hwfn->hw_info.personality) {
2000 struct ecore_eth_pf_params *p_params =
2001 &p_hwfn->pf_params.eth_pf_params;
2003 if (!p_params->num_vf_cons)
2004 p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT;
2005 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2007 p_params->num_vf_cons);
2009 count = p_params->num_arfs_filters;
2011 if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS,
2012 &p_hwfn->p_dev->mf_bits))
2013 p_hwfn->p_cxt_mngr->arfs_count = count;
2021 return ECORE_SUCCESS;
2024 /* This function is very RoCE oriented, if another protocol in the future
2025 * will want this feature we'll need to modify the function to be more generic
2027 enum _ecore_status_t
2028 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2029 enum ecore_cxt_elem_type elem_type,
2032 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2033 struct ecore_ilt_client_cfg *p_cli;
2034 struct ecore_ilt_cli_blk *p_blk;
2035 struct ecore_ptt *p_ptt;
2039 enum _ecore_status_t rc = ECORE_SUCCESS;
2041 switch (elem_type) {
2042 case ECORE_ELEM_CXT:
2043 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2044 elem_size = CONN_CXT_SIZE(p_hwfn);
2045 p_blk = &p_cli->pf_blks[CDUC_BLK];
2047 case ECORE_ELEM_SRQ:
2048 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2049 elem_size = SRQ_CXT_SIZE;
2050 p_blk = &p_cli->pf_blks[SRQ_BLK];
2052 case ECORE_ELEM_TASK:
2053 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2054 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2055 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2058 DP_NOTICE(p_hwfn, false,
2059 "ECORE_INVALID elem type = %d", elem_type);
2063 /* Calculate line in ilt */
2064 hw_p_size = p_cli->p_size.val;
2065 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2066 line = p_blk->start_line + (iid / elems_per_p);
2067 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2069 /* If line is already allocated, do nothing, otherwise allocate it and
2070 * write it to the PSWRQ2 registers.
2071 * This section can be run in parallel from different contexts and thus
2072 * a mutex protection is needed.
2075 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2077 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2080 p_ptt = ecore_ptt_acquire(p_hwfn);
2082 DP_NOTICE(p_hwfn, false,
2083 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2088 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2090 p_blk->real_size_in_page);
2095 OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2097 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2098 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2099 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2100 p_blk->real_size_in_page;
2102 /* compute absolute offset */
2103 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2104 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2107 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2108 SET_FIELD(ilt_hw_entry,
2110 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2112 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2114 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2115 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2118 if (elem_type == ECORE_ELEM_CXT) {
2119 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2122 /* Update the relevant register in the parser */
2123 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2124 last_cid_allocated - 1);
2126 if (!p_hwfn->b_rdma_enabled_in_prs) {
2127 /* Enable RoCE search */
2128 ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2129 p_hwfn->b_rdma_enabled_in_prs = true;
2134 ecore_ptt_release(p_hwfn, p_ptt);
2136 OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2141 /* This function is very RoCE oriented, if another protocol in the future
2142 * will want this feature we'll need to modify the function to be more generic
2144 static enum _ecore_status_t
2145 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2146 enum ecore_cxt_elem_type elem_type,
2147 u32 start_iid, u32 count)
2149 u32 start_line, end_line, shadow_start_line, shadow_end_line;
2150 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2151 struct ecore_ilt_client_cfg *p_cli;
2152 struct ecore_ilt_cli_blk *p_blk;
2153 u32 end_iid = start_iid + count;
2154 struct ecore_ptt *p_ptt;
2155 u64 ilt_hw_entry = 0;
2158 switch (elem_type) {
2159 case ECORE_ELEM_CXT:
2160 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2161 elem_size = CONN_CXT_SIZE(p_hwfn);
2162 p_blk = &p_cli->pf_blks[CDUC_BLK];
2164 case ECORE_ELEM_SRQ:
2165 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2166 elem_size = SRQ_CXT_SIZE;
2167 p_blk = &p_cli->pf_blks[SRQ_BLK];
2169 case ECORE_ELEM_TASK:
2170 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2171 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2172 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2175 DP_NOTICE(p_hwfn, false,
2176 "ECORE_INVALID elem type = %d", elem_type);
2180 /* Calculate line in ilt */
2181 hw_p_size = p_cli->p_size.val;
2182 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2183 start_line = p_blk->start_line + (start_iid / elems_per_p);
2184 end_line = p_blk->start_line + (end_iid / elems_per_p);
2185 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2188 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2189 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2191 p_ptt = ecore_ptt_acquire(p_hwfn);
2193 DP_NOTICE(p_hwfn, false,
2194 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2195 return ECORE_TIMEOUT;
2198 for (i = shadow_start_line; i < shadow_end_line; i++) {
2199 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2202 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2203 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2204 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2205 p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2207 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2208 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2209 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2211 /* compute absolute offset */
2212 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2213 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2216 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2219 ecore_dmae_host2grc(p_hwfn, p_ptt,
2220 (u64)(osal_uintptr_t)&ilt_hw_entry,
2222 sizeof(ilt_hw_entry) / sizeof(u32),
2226 ecore_ptt_release(p_hwfn, p_ptt);
2228 return ECORE_SUCCESS;