2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_hsi_common.h"
12 #include "ecore_hsi_eth.h"
13 #include "ecore_rt_defs.h"
14 #include "ecore_status.h"
16 #include "ecore_init_ops.h"
17 #include "ecore_init_fw_funcs.h"
18 #include "ecore_cxt.h"
20 #include "ecore_dev_api.h"
21 #include "ecore_sriov.h"
23 /* Max number of connection types in HW (DQ/CDU etc.) */
24 #define MAX_CONN_TYPES PROTOCOLID_COMMON
25 #define NUM_TASK_TYPES 2
26 #define NUM_TASK_PF_SEGMENTS 4
27 #define NUM_TASK_VF_SEGMENTS 1
29 /* Doorbell-Queue constants */
30 #define DQ_RANGE_SHIFT 4
31 #define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT)
33 /* Searcher constants */
34 #define SRC_MIN_NUM_ELEMS 256
36 /* Timers constants */
38 #define TM_ALIGN (1 << TM_SHIFT)
39 #define TM_ELEM_SIZE 4
42 /* If for some reason, HW P size is modified to be less than 32K,
43 * special handling needs to be made for CDU initialization
45 #define ILT_DEFAULT_HW_P_SIZE 3
47 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
48 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
50 /* ILT entry structure */
51 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
52 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
53 #define ILT_ENTRY_VALID_MASK 0x1ULL
54 #define ILT_ENTRY_VALID_SHIFT 52
55 #define ILT_ENTRY_IN_REGS 2
56 #define ILT_REG_SIZE_IN_BYTES 4
58 /* connection context union */
60 struct core_conn_context core_ctx;
61 struct eth_conn_context eth_ctx;
64 /* TYPE-0 task context - iSCSI, FCOE */
65 union type0_task_context {
68 /* TYPE-1 task context - ROCE */
69 union type1_task_context {
77 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
78 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
80 #define CONN_CXT_SIZE(p_hwfn) \
81 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
83 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
85 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
86 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
88 /* Alignment is inherent to the type1_task_context structure */
89 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
91 /* PF per protocl configuration object */
92 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
93 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
95 struct ecore_tid_seg {
101 struct ecore_conn_type_cfg {
105 struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
108 /* ILT Client configuration,
109 * Per connection type (protocol) resources (cids, tis, vf cids etc.)
110 * 1 - for connection context (CDUC) and for each task context we need two
111 * values, for regular task context and for force load memory
113 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
114 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
117 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
118 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS)
130 struct ilt_cfg_pair {
135 struct ecore_ilt_cli_blk {
136 u32 total_size; /* 0 means not active */
137 u32 real_size_in_page;
139 u32 dynamic_line_cnt;
142 struct ecore_ilt_client_cfg {
146 struct ilt_cfg_pair first;
147 struct ilt_cfg_pair last;
148 struct ilt_cfg_pair p_size;
150 /* ILT client blocks for PF */
151 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
154 /* ILT client blocks for VFs */
155 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
161 * Protocol acquired CID lists
162 * PF start line in ILT
164 struct ecore_dma_mem {
170 #define MAP_WORD_SIZE sizeof(unsigned long)
171 #define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8)
173 struct ecore_cid_acquired_map {
176 unsigned long *cid_map;
179 struct ecore_cxt_mngr {
180 /* Per protocl configuration */
181 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
183 /* computed ILT structure */
184 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
186 /* Task type sizes */
187 u32 task_type_size[NUM_TASK_TYPES];
189 /* total number of VFs for this hwfn -
190 * ALL VFs are symmetric in terms of HW resources
194 /* total number of SRQ's for this hwfn */
198 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
200 /* ILT shadow table */
201 struct ecore_dma_mem *ilt_shadow;
204 /* Mutex for a dynamic ILT allocation */
208 struct ecore_dma_mem *t2;
214 /* check if resources/configuration is required according to protocol type */
215 static OSAL_INLINE bool src_proto(enum protocol_type type)
217 return type == PROTOCOLID_TOE;
220 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
222 return type == PROTOCOLID_TOE;
225 static bool tm_tid_proto(enum protocol_type type)
227 return type == PROTOCOLID_FCOE;
230 /* counts the iids for the CDU/CDUC ILT client configuration */
231 struct ecore_cdu_iids {
236 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
237 struct ecore_cdu_iids *iids)
241 for (type = 0; type < MAX_CONN_TYPES; type++) {
242 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
243 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
247 /* counts the iids for the Searcher block configuration */
248 struct ecore_src_iids {
253 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
254 struct ecore_src_iids *iids)
258 for (i = 0; i < MAX_CONN_TYPES; i++) {
262 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
263 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
267 /* counts the iids for the Timers block configuration */
268 struct ecore_tm_iids {
270 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
276 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
277 struct ecore_tm_iids *iids)
281 for (i = 0; i < MAX_CONN_TYPES; i++) {
282 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
284 if (tm_cid_proto(i)) {
285 iids->pf_cids += p_cfg->cid_count;
286 iids->per_vf_cids += p_cfg->cids_per_vf;
289 if (tm_tid_proto(i)) {
290 struct ecore_tid_seg *segs = p_cfg->tid_seg;
292 /* for each segment there is at most one
293 * protocol for which count is not 0.
295 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
296 iids->pf_tids[j] += segs[j].count;
298 /* The last array elelment is for the VFs. As for PF
299 * segments there can be only one protocol for
300 * which this value is not 0.
302 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
306 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
307 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
308 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
310 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
311 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
312 iids->pf_tids_total += iids->pf_tids[j];
316 void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids)
318 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
319 struct ecore_tid_seg *segs;
320 u32 vf_cids = 0, type, j;
323 for (type = 0; type < MAX_CONN_TYPES; type++) {
324 iids->cids += p_mngr->conn_cfg[type].cid_count;
325 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
327 segs = p_mngr->conn_cfg[type].tid_seg;
328 /* for each segment there is at most one
329 * protocol for which count is not 0.
331 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
332 iids->tids += segs[j].count;
334 /* The last array elelment is for the VFs. As for PF
335 * segments there can be only one protocol for
336 * which this value is not 0.
338 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
341 iids->vf_cids += vf_cids * p_mngr->vf_count;
342 iids->tids += vf_tids * p_mngr->vf_count;
344 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
345 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
346 iids->cids, iids->vf_cids, iids->tids, vf_tids);
349 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
352 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
355 /* Find the protocol with tid count > 0 for this segment.
356 * Note: there can only be one and this is already validated.
358 for (i = 0; i < MAX_CONN_TYPES; i++) {
359 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
360 return &p_cfg->conn_cfg[i].tid_seg[seg];
365 /* set the iids (cid/tid) count per protocol */
366 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
367 enum protocol_type type,
368 u32 cid_count, u32 vf_cid_cnt)
370 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
371 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
373 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
374 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
377 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
378 enum protocol_type type, u32 *vf_cid)
381 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
383 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
386 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
387 enum protocol_type type)
389 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
392 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
393 enum protocol_type type)
398 for (i = 0; i < TASK_SEGMENTS; i++)
399 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
404 static OSAL_INLINE void
405 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
406 enum protocol_type proto,
407 u8 seg, u8 seg_type, u32 count, bool has_fl)
409 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
410 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
412 p_seg->count = count;
413 p_seg->has_fl_mem = has_fl;
414 p_seg->type = seg_type;
417 /* the *p_line parameter must be either 0 for the first invocation or the
418 * value returned in the previous invocation.
420 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
421 struct ecore_ilt_cli_blk *p_blk,
423 u32 total_size, u32 elem_size)
425 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
427 /* verify that it's called once for each block */
428 if (p_blk->total_size)
431 p_blk->total_size = total_size;
432 p_blk->real_size_in_page = 0;
434 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
435 p_blk->start_line = start_line;
438 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
439 struct ecore_ilt_client_cfg *p_cli,
440 struct ecore_ilt_cli_blk *p_blk,
441 u32 *p_line, enum ilt_clients client_id)
443 if (!p_blk->total_size)
447 p_cli->first.val = *p_line;
449 p_cli->active = true;
450 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
451 p_cli->last.val = *p_line - 1;
453 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
454 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
455 " [Real %08x] Start line %d\n",
456 client_id, p_cli->first.val, p_cli->last.val,
457 p_blk->total_size, p_blk->real_size_in_page,
461 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
462 enum ilt_clients ilt_client)
464 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
465 struct ecore_ilt_client_cfg *p_cli;
466 u32 lines_to_skip = 0;
469 /* TBD MK: ILT code should be simplified once PROTO enum is changed */
471 if (ilt_client == ILT_CLI_CDUC) {
472 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
474 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
475 (u32)CONN_CXT_SIZE(p_hwfn);
477 lines_to_skip = cid_count / cxts_per_p;
480 return lines_to_skip;
483 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
485 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
486 u32 curr_line, total, i, task_size, line;
487 struct ecore_ilt_client_cfg *p_cli;
488 struct ecore_ilt_cli_blk *p_blk;
489 struct ecore_cdu_iids cdu_iids;
490 struct ecore_src_iids src_iids;
491 struct ecore_qm_iids qm_iids;
492 struct ecore_tm_iids tm_iids;
493 struct ecore_tid_seg *p_seg;
495 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
496 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
497 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
498 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
500 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
502 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
503 "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
504 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
507 p_cli = &p_mngr->clients[ILT_CLI_CDUC];
509 curr_line = p_mngr->pf_start_line;
512 p_cli->pf_total_lines = 0;
514 /* get the counters for the CDUC,CDUC and QM clients */
515 ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
517 p_blk = &p_cli->pf_blks[CDUC_BLK];
519 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
521 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
522 total, CONN_CXT_SIZE(p_hwfn));
524 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
525 p_cli->pf_total_lines = curr_line - p_blk->start_line;
527 p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
531 p_blk = &p_cli->vf_blks[CDUC_BLK];
532 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
534 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
535 total, CONN_CXT_SIZE(p_hwfn));
537 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
538 p_cli->vf_total_lines = curr_line - p_blk->start_line;
540 for (i = 1; i < p_mngr->vf_count; i++)
541 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
545 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
546 p_cli->first.val = curr_line;
548 /* first the 'working' task memory */
549 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
550 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
551 if (!p_seg || p_seg->count == 0)
554 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
555 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
556 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
557 p_mngr->task_type_size[p_seg->type]);
559 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
563 /* next the 'init' task memory (forced load memory) */
564 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
565 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
566 if (!p_seg || p_seg->count == 0)
569 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
571 if (!p_seg->has_fl_mem) {
572 /* The segment is active (total size pf 'working'
573 * memory is > 0) but has no FL (forced-load, Init)
576 * 1. The total-size in the corrsponding FL block of
577 * the ILT client is set to 0 - No ILT line are
578 * provisioned and no ILT memory allocated.
580 * 2. The start-line of said block is set to the
581 * start line of the matching working memory
582 * block in the ILT client. This is later used to
583 * configure the CDU segment offset registers and
584 * results in an FL command for TIDs of this
585 * segment behaves as regular load commands
586 * (loading TIDs from the working memory).
588 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
590 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
593 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
595 ecore_ilt_cli_blk_fill(p_cli, p_blk,
597 p_mngr->task_type_size[p_seg->type]);
599 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
602 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
605 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
606 if (p_seg && p_seg->count) {
607 /* Stricly speaking we need to iterate over all VF
608 * task segment types, but a VF has only 1 segment
611 /* 'working' memory */
612 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
614 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
615 ecore_ilt_cli_blk_fill(p_cli, p_blk,
617 p_mngr->task_type_size[p_seg->type]);
619 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
623 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
624 if (!p_seg->has_fl_mem) {
625 /* see comment above */
626 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
627 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
629 task_size = p_mngr->task_type_size[p_seg->type];
630 ecore_ilt_cli_blk_fill(p_cli, p_blk,
631 curr_line, total, task_size);
632 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
635 p_cli->vf_total_lines = curr_line -
636 p_cli->vf_blks[0].start_line;
638 /* Now for the rest of the VFs */
639 for (i = 1; i < p_mngr->vf_count; i++) {
640 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
641 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
644 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
645 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
651 p_cli = &p_mngr->clients[ILT_CLI_QM];
652 p_blk = &p_cli->pf_blks[0];
654 ecore_cxt_qm_iids(p_hwfn, &qm_iids);
655 total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
656 qm_iids.vf_cids, qm_iids.tids,
657 p_hwfn->qm_info.num_pqs,
658 p_hwfn->qm_info.num_vf_pqs);
660 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
661 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
662 " num_vf_pqs=%d, memory_size=%d)\n",
663 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
664 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
666 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
669 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
670 p_cli->pf_total_lines = curr_line - p_blk->start_line;
673 p_cli = &p_mngr->clients[ILT_CLI_SRC];
674 ecore_cxt_src_iids(p_mngr, &src_iids);
676 /* Both the PF and VFs searcher connections are stored in the per PF
677 * database. Thus sum the PF searcher cids and all the VFs searcher
680 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
682 u32 local_max = OSAL_MAX_T(u32, total,
685 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
687 p_blk = &p_cli->pf_blks[0];
688 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
689 total * sizeof(struct src_ent),
690 sizeof(struct src_ent));
692 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
694 p_cli->pf_total_lines = curr_line - p_blk->start_line;
698 p_cli = &p_mngr->clients[ILT_CLI_TM];
699 ecore_cxt_tm_iids(p_mngr, &tm_iids);
700 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
702 p_blk = &p_cli->pf_blks[0];
703 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
704 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
706 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
708 p_cli->pf_total_lines = curr_line - p_blk->start_line;
712 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
714 p_blk = &p_cli->vf_blks[0];
715 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
716 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
718 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
721 for (i = 1; i < p_mngr->vf_count; i++) {
722 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
726 p_cli->vf_total_lines = curr_line - p_blk->start_line;
729 /* TSDM (SRQ CONTEXT) */
730 total = ecore_cxt_get_srq_count(p_hwfn);
733 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
734 p_blk = &p_cli->pf_blks[SRQ_BLK];
735 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
736 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
738 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
740 p_cli->pf_total_lines = curr_line - p_blk->start_line;
743 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
744 RESC_NUM(p_hwfn, ECORE_ILT)) {
745 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
746 curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
750 return ECORE_SUCCESS;
753 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
755 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
761 for (i = 0; i < p_mngr->t2_num_pages; i++)
762 if (p_mngr->t2[i].p_virt)
763 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
764 p_mngr->t2[i].p_virt,
765 p_mngr->t2[i].p_phys,
768 OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
769 p_mngr->t2 = OSAL_NULL;
772 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
774 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
775 u32 conn_num, total_size, ent_per_page, psz, i;
776 struct ecore_ilt_client_cfg *p_src;
777 struct ecore_src_iids src_iids;
778 struct ecore_dma_mem *p_t2;
779 enum _ecore_status_t rc;
781 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
783 /* if the SRC ILT client is inactive - there are no connection
784 * requiring the searcer, leave.
786 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
788 return ECORE_SUCCESS;
790 ecore_cxt_src_iids(p_mngr, &src_iids);
791 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
792 total_size = conn_num * sizeof(struct src_ent);
794 /* use the same page size as the SRC ILT client */
795 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
796 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
799 p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
800 p_mngr->t2_num_pages *
801 sizeof(struct ecore_dma_mem));
803 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
808 /* allocate t2 pages */
809 for (i = 0; i < p_mngr->t2_num_pages; i++) {
810 u32 size = OSAL_MIN_T(u32, total_size, psz);
811 void **p_virt = &p_mngr->t2[i].p_virt;
813 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
814 &p_mngr->t2[i].p_phys, size);
815 if (!p_mngr->t2[i].p_virt) {
819 OSAL_MEM_ZERO(*p_virt, size);
820 p_mngr->t2[i].size = size;
824 /* Set the t2 pointers */
826 /* entries per page - must be a power of two */
827 ent_per_page = psz / sizeof(struct src_ent);
829 p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
831 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
832 p_mngr->last_free = (u64)p_t2->p_phys +
833 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
835 for (i = 0; i < p_mngr->t2_num_pages; i++) {
836 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
837 struct src_ent *entries = p_mngr->t2[i].p_virt;
838 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
841 for (j = 0; j < ent_num - 1; j++) {
842 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
843 entries[j].next = OSAL_CPU_TO_BE64(val);
846 if (i < p_mngr->t2_num_pages - 1)
847 val = (u64)p_mngr->t2[i + 1].p_phys;
850 entries[j].next = OSAL_CPU_TO_BE64(val);
855 return ECORE_SUCCESS;
858 ecore_cxt_src_t2_free(p_hwfn);
862 #define for_each_ilt_valid_client(pos, clients) \
863 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
864 if (!clients[pos].active) { \
869 /* Total number of ILT lines used by this PF */
870 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
875 for_each_ilt_valid_client(i, ilt_clients)
876 size += (ilt_clients[i].last.val -
877 ilt_clients[i].first.val + 1);
882 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
884 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
885 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
888 ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
890 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
891 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
894 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
896 p_dma->p_phys, p_dma->size);
897 p_dma->p_virt = OSAL_NULL;
899 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
902 static enum _ecore_status_t
903 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
904 struct ecore_ilt_cli_blk *p_blk,
905 enum ilt_clients ilt_client, u32 start_line_offset)
907 struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
908 u32 lines, line, sz_left, lines_to_skip = 0;
910 /* Special handling for RoCE that supports dynamic allocation */
911 if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
912 return ECORE_SUCCESS;
914 lines_to_skip = p_blk->dynamic_line_cnt;
916 if (!p_blk->total_size)
917 return ECORE_SUCCESS;
919 sz_left = p_blk->total_size;
920 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
921 line = p_blk->start_line + start_line_offset -
922 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
924 for (; lines; lines--) {
929 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
932 #define ILT_BLOCK_ALIGN_SIZE 0x1000
933 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
935 ILT_BLOCK_ALIGN_SIZE);
938 OSAL_MEM_ZERO(p_virt, size);
940 ilt_shadow[line].p_phys = p_phys;
941 ilt_shadow[line].p_virt = p_virt;
942 ilt_shadow[line].size = size;
944 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
945 "ILT shadow: Line [%d] Physical 0x%lx"
946 " Virtual %p Size %d\n",
947 line, (unsigned long)p_phys, p_virt, size);
953 return ECORE_SUCCESS;
956 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
958 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
959 struct ecore_ilt_client_cfg *clients = p_mngr->clients;
960 struct ecore_ilt_cli_blk *p_blk;
962 enum _ecore_status_t rc;
964 size = ecore_cxt_ilt_shadow_size(clients);
965 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
966 size * sizeof(struct ecore_dma_mem));
968 if (!p_mngr->ilt_shadow) {
969 DP_NOTICE(p_hwfn, true,
970 "Failed to allocate ilt shadow table\n");
972 goto ilt_shadow_fail;
975 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
976 "Allocated 0x%x bytes for ilt shadow\n",
977 (u32)(size * sizeof(struct ecore_dma_mem)));
979 for_each_ilt_valid_client(i, clients) {
980 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
981 p_blk = &clients[i].pf_blks[j];
982 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
983 if (rc != ECORE_SUCCESS)
984 goto ilt_shadow_fail;
986 for (k = 0; k < p_mngr->vf_count; k++) {
987 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
988 u32 lines = clients[i].vf_total_lines * k;
990 p_blk = &clients[i].vf_blks[j];
991 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
993 if (rc != ECORE_SUCCESS)
994 goto ilt_shadow_fail;
999 return ECORE_SUCCESS;
1002 ecore_ilt_shadow_free(p_hwfn);
1006 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1008 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1011 for (type = 0; type < MAX_CONN_TYPES; type++) {
1012 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1013 p_mngr->acquired[type].max_count = 0;
1014 p_mngr->acquired[type].start_cid = 0;
1018 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1020 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1024 for (type = 0; type < MAX_CONN_TYPES; type++) {
1025 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1031 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD);
1032 p_mngr->acquired[type].cid_map = OSAL_ZALLOC(p_hwfn->p_dev,
1034 if (!p_mngr->acquired[type].cid_map)
1037 p_mngr->acquired[type].max_count = cid_cnt;
1038 p_mngr->acquired[type].start_cid = start_cid;
1040 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1042 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1043 "Type %08x start: %08x count %08x\n",
1044 type, p_mngr->acquired[type].start_cid,
1045 p_mngr->acquired[type].max_count);
1046 start_cid += cid_cnt;
1049 return ECORE_SUCCESS;
1052 ecore_cid_map_free(p_hwfn);
1056 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1058 struct ecore_ilt_client_cfg *clients;
1059 struct ecore_cxt_mngr *p_mngr;
1062 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1064 DP_NOTICE(p_hwfn, true,
1065 "Failed to allocate `struct ecore_cxt_mngr'\n");
1069 /* Initialize ILT client registers */
1070 clients = p_mngr->clients;
1071 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1072 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1073 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1075 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1076 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1077 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1079 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1080 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1081 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1083 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1084 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1085 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1087 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1088 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1089 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1091 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1092 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1093 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1095 /* default ILT page size for all clients is 32K */
1096 for (i = 0; i < ILT_CLI_MAX; i++)
1097 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1099 /* due to removal of ISCSI/FCoE files union type0_task_context
1100 * task_type_size will be 0. So hardcoded for now.
1102 p_mngr->task_type_size[0] = 512; /* @DPDK */
1103 p_mngr->task_type_size[1] = 128; /* @DPDK */
1105 if (p_hwfn->p_dev->p_iov_info)
1106 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1108 /* Initialize the dynamic ILT allocation mutex */
1109 OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1110 OSAL_MUTEX_INIT(&p_mngr->mutex);
1112 /* Set the cxt mangr pointer priori to further allocations */
1113 p_hwfn->p_cxt_mngr = p_mngr;
1115 return ECORE_SUCCESS;
1118 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1120 enum _ecore_status_t rc;
1122 /* Allocate the ILT shadow table */
1123 rc = ecore_ilt_shadow_alloc(p_hwfn);
1125 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1126 goto tables_alloc_fail;
1129 /* Allocate the T2 table */
1130 rc = ecore_cxt_src_t2_alloc(p_hwfn);
1132 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1133 goto tables_alloc_fail;
1136 /* Allocate and initialize the acquired cids bitmaps */
1137 rc = ecore_cid_map_alloc(p_hwfn);
1139 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1140 goto tables_alloc_fail;
1143 return ECORE_SUCCESS;
1146 ecore_cxt_mngr_free(p_hwfn);
1150 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1152 if (!p_hwfn->p_cxt_mngr)
1155 ecore_cid_map_free(p_hwfn);
1156 ecore_cxt_src_t2_free(p_hwfn);
1157 ecore_ilt_shadow_free(p_hwfn);
1158 OSAL_MUTEX_DEALLOC(&p_mngr->mutex);
1159 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1161 p_hwfn->p_cxt_mngr = OSAL_NULL;
1164 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1166 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1169 /* Reset acquired cids */
1170 for (type = 0; type < MAX_CONN_TYPES; type++) {
1171 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1177 for (i = 0; i < DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD); i++)
1178 p_mngr->acquired[type].cid_map[i] = 0;
1182 /* HW initialization helper (per Block, per phase) */
1185 #define CDUC_CXT_SIZE_SHIFT \
1186 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1188 #define CDUC_CXT_SIZE_MASK \
1189 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1191 #define CDUC_BLOCK_WASTE_SHIFT \
1192 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1194 #define CDUC_BLOCK_WASTE_MASK \
1195 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1197 #define CDUC_NCIB_SHIFT \
1198 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1200 #define CDUC_NCIB_MASK \
1201 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1203 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1204 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1206 #define CDUT_TYPE0_CXT_SIZE_MASK \
1207 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1208 CDUT_TYPE0_CXT_SIZE_SHIFT)
1210 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1211 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1213 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1214 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1215 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1217 #define CDUT_TYPE0_NCIB_SHIFT \
1218 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1220 #define CDUT_TYPE0_NCIB_MASK \
1221 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1222 CDUT_TYPE0_NCIB_SHIFT)
1224 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1225 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1227 #define CDUT_TYPE1_CXT_SIZE_MASK \
1228 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1229 CDUT_TYPE1_CXT_SIZE_SHIFT)
1231 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1232 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1234 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1235 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1236 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1238 #define CDUT_TYPE1_NCIB_SHIFT \
1239 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1241 #define CDUT_TYPE1_NCIB_MASK \
1242 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1243 CDUT_TYPE1_NCIB_SHIFT)
1245 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1247 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1249 /* CDUC - connection configuration */
1250 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1251 cxt_size = CONN_CXT_SIZE(p_hwfn);
1252 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1253 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1255 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1256 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1257 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1258 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1260 /* CDUT - type-0 tasks configuration */
1261 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1262 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1263 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1264 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1266 /* cxt size and block-waste are multipes of 8 */
1268 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1269 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1270 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1271 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1273 /* CDUT - type-1 tasks configuration */
1274 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1275 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1276 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1278 /* cxt size and block-waste are multipes of 8 */
1280 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1281 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1282 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1283 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1287 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1288 #define CDU_SEG_REG_TYPE_MASK 0x1
1289 #define CDU_SEG_REG_OFFSET_SHIFT 0
1290 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1292 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1294 struct ecore_ilt_client_cfg *p_cli;
1295 struct ecore_tid_seg *p_seg;
1296 u32 cdu_seg_params, offset;
1299 static const u32 rt_type_offset_arr[] = {
1300 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1301 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1302 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1303 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1306 static const u32 rt_type_offset_fl_arr[] = {
1307 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1308 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1309 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1310 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1313 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1315 /* There are initializations only for CDUT during pf Phase */
1316 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1318 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1322 /* Note: start_line is already adjusted for the CDU
1323 * segment register granularity, so we just need to
1324 * divide. Adjustment is implicit as we assume ILT
1325 * Page size is larger than 32K!
1327 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1328 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1329 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1332 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1333 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1334 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1336 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1337 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1338 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1341 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1342 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1343 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1347 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1349 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1350 struct ecore_qm_iids iids;
1352 OSAL_MEM_ZERO(&iids, sizeof(iids));
1353 ecore_cxt_qm_iids(p_hwfn, &iids);
1355 ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1356 p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1357 p_hwfn->first_on_engine,
1358 iids.cids, iids.vf_cids, iids.tids,
1360 qm_info->num_pqs - qm_info->num_vf_pqs,
1361 qm_info->num_vf_pqs,
1362 qm_info->start_vport,
1363 qm_info->num_vports, qm_info->pf_wfq,
1364 qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1365 p_hwfn->qm_info.qm_vport_params);
1369 static enum _ecore_status_t ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1371 union ecore_qm_pq_params pq_params;
1374 /* XCM pure-LB queue */
1375 OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
1376 pq_params.core.tc = LB_TC;
1377 pq = ecore_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
1378 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq);
1380 return ECORE_SUCCESS;
1384 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1386 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1387 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1389 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1390 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1392 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1393 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1395 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1396 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1398 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1399 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1401 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1402 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1404 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1405 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1407 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1408 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1410 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1411 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1413 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1414 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1416 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1417 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1419 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1420 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1422 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1423 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1425 /* Connection types 6 & 7 are not in use, yet they must be configured
1426 * as the highest possible connection. Not configuring them means the
1427 * defaults will be used, and with a large number of cids a bug may
1428 * occur, if the defaults will be smaller than dq_pf_max_cid /
1431 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1432 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1434 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1435 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1438 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1440 struct ecore_ilt_client_cfg *ilt_clients;
1443 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1444 for_each_ilt_valid_client(i, ilt_clients) {
1445 STORE_RT_REG(p_hwfn,
1446 ilt_clients[i].first.reg,
1447 ilt_clients[i].first.val);
1448 STORE_RT_REG(p_hwfn,
1449 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1450 STORE_RT_REG(p_hwfn,
1451 ilt_clients[i].p_size.reg,
1452 ilt_clients[i].p_size.val);
1456 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1458 struct ecore_ilt_client_cfg *p_cli;
1461 /* For simplicty we set the 'block' to be an ILT page */
1462 if (p_hwfn->p_dev->p_iov_info) {
1463 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1465 STORE_RT_REG(p_hwfn,
1466 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1467 p_iov->first_vf_in_pf);
1468 STORE_RT_REG(p_hwfn,
1469 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1470 p_iov->first_vf_in_pf + p_iov->total_vfs);
1473 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1474 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1475 if (p_cli->active) {
1476 STORE_RT_REG(p_hwfn,
1477 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1479 STORE_RT_REG(p_hwfn,
1480 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1481 p_cli->pf_total_lines);
1482 STORE_RT_REG(p_hwfn,
1483 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1484 p_cli->vf_total_lines);
1487 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1488 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1489 if (p_cli->active) {
1490 STORE_RT_REG(p_hwfn,
1491 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1493 STORE_RT_REG(p_hwfn,
1494 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1495 p_cli->pf_total_lines);
1496 STORE_RT_REG(p_hwfn,
1497 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1498 p_cli->vf_total_lines);
1501 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1502 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1503 if (p_cli->active) {
1504 STORE_RT_REG(p_hwfn,
1505 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1506 STORE_RT_REG(p_hwfn,
1507 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1508 p_cli->pf_total_lines);
1509 STORE_RT_REG(p_hwfn,
1510 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1511 p_cli->vf_total_lines);
1515 /* ILT (PSWRQ2) PF */
1516 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1518 struct ecore_ilt_client_cfg *clients;
1519 struct ecore_cxt_mngr *p_mngr;
1520 struct ecore_dma_mem *p_shdw;
1521 u32 line, rt_offst, i;
1523 ecore_ilt_bounds_init(p_hwfn);
1524 ecore_ilt_vf_bounds_init(p_hwfn);
1526 p_mngr = p_hwfn->p_cxt_mngr;
1527 p_shdw = p_mngr->ilt_shadow;
1528 clients = p_hwfn->p_cxt_mngr->clients;
1530 for_each_ilt_valid_client(i, clients) {
1531 /* Client's 1st val and RT array are absolute, ILT shadows'
1532 * lines are relative.
1534 line = clients[i].first.val - p_mngr->pf_start_line;
1535 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1536 clients[i].first.val * ILT_ENTRY_IN_REGS;
1538 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1539 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1540 u64 ilt_hw_entry = 0;
1542 /** p_virt could be OSAL_NULL incase of dynamic
1545 if (p_shdw[line].p_virt != OSAL_NULL) {
1546 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1547 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1548 (p_shdw[line].p_phys >> 12));
1550 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1551 "Setting RT[0x%08x] from"
1552 " ILT[0x%08x] [Client is %d] to"
1553 " Physical addr: 0x%lx\n",
1555 (unsigned long)(p_shdw[line].
1559 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1564 /* SRC (Searcher) PF */
1565 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1567 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1568 u32 rounded_conn_num, conn_num, conn_max;
1569 struct ecore_src_iids src_iids;
1571 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1572 ecore_cxt_src_iids(p_mngr, &src_iids);
1573 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1577 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1578 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1580 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1581 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1582 OSAL_LOG2(rounded_conn_num));
1584 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1585 p_hwfn->p_cxt_mngr->first_free);
1586 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1587 p_hwfn->p_cxt_mngr->last_free);
1591 #define TM_CFG_NUM_IDS_SHIFT 0
1592 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1593 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1594 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1595 #define TM_CFG_PARENT_PF_SHIFT 25
1596 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1598 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1599 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1601 #define TM_CFG_TID_OFFSET_SHIFT 30
1602 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1603 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1604 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1606 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1608 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1609 u32 active_seg_mask = 0, tm_offset, rt_reg;
1610 struct ecore_tm_iids tm_iids;
1614 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1615 ecore_cxt_tm_iids(p_mngr, &tm_iids);
1617 /* @@@TBD No pre-scan for now */
1619 /* Note: We assume consecutive VFs for a PF */
1620 for (i = 0; i < p_mngr->vf_count; i++) {
1622 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1623 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1624 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1625 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1627 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1628 (sizeof(cfg_word) / sizeof(u32)) *
1629 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1630 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1634 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1635 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1636 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1637 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1639 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1640 (sizeof(cfg_word) / sizeof(u32)) *
1641 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1642 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1645 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1646 tm_iids.pf_cids ? 0x1 : 0x0);
1648 /* @@@TBD how to enable the scan for the VFs */
1650 tm_offset = tm_iids.per_vf_cids;
1652 /* Note: We assume consecutive VFs for a PF */
1653 for (i = 0; i < p_mngr->vf_count; i++) {
1655 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1656 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1657 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1658 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1659 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1661 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1662 (sizeof(cfg_word) / sizeof(u32)) *
1663 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1665 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1668 tm_offset = tm_iids.pf_cids;
1669 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1671 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1672 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1673 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1674 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1675 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1677 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1678 (sizeof(cfg_word) / sizeof(u32)) *
1679 (NUM_OF_VFS(p_hwfn->p_dev) +
1680 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1682 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1683 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1685 tm_offset += tm_iids.pf_tids[i];
1688 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1690 /* @@@TBD how to enable the scan for the VFs */
1693 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1695 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1696 struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1697 struct ecore_tid_seg *p_tid;
1699 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1700 if (!p_fcoe->cid_count)
1703 p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1704 STORE_RT_REG_AGG(p_hwfn,
1705 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1709 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1711 /* CDU configuration */
1712 ecore_cdu_init_common(p_hwfn);
1715 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1717 ecore_qm_init_pf(p_hwfn);
1718 ecore_cm_init_pf(p_hwfn);
1719 ecore_dq_init_pf(p_hwfn);
1720 ecore_cdu_init_pf(p_hwfn);
1721 ecore_ilt_init_pf(p_hwfn);
1722 ecore_src_init_pf(p_hwfn);
1723 ecore_tm_init_pf(p_hwfn);
1724 ecore_prs_init_pf(p_hwfn);
1727 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1728 enum protocol_type type, u32 *p_cid)
1730 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1733 if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1734 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1738 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_mngr->acquired[type].cid_map,
1739 p_mngr->acquired[type].max_count);
1741 if (rel_cid >= p_mngr->acquired[type].max_count) {
1742 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1744 return ECORE_NORESOURCES;
1747 OSAL_SET_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1749 *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1751 return ECORE_SUCCESS;
1754 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1755 u32 cid, enum protocol_type *p_type)
1757 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1758 struct ecore_cid_acquired_map *p_map;
1759 enum protocol_type p;
1762 /* Iterate over protocols and find matching cid range */
1763 for (p = 0; p < MAX_CONN_TYPES; p++) {
1764 p_map = &p_mngr->acquired[p];
1766 if (!p_map->cid_map)
1768 if (cid >= p_map->start_cid &&
1769 cid < p_map->start_cid + p_map->max_count) {
1775 if (p == MAX_CONN_TYPES) {
1776 DP_NOTICE(p_hwfn, true, "Invalid CID %d", cid);
1779 rel_cid = cid - p_map->start_cid;
1780 if (!OSAL_TEST_BIT(rel_cid, p_map->cid_map)) {
1781 DP_NOTICE(p_hwfn, true, "CID %d not acquired", cid);
1787 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1789 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1790 enum protocol_type type;
1794 /* Test acquired and find matching per-protocol map */
1795 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, &type);
1800 rel_cid = cid - p_mngr->acquired[type].start_cid;
1801 OSAL_CLEAR_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1804 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1805 struct ecore_cxt_info *p_info)
1807 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1808 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1809 enum protocol_type type;
1812 /* Test acquired and find matching per-protocol map */
1813 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1818 /* set the protocl type */
1819 p_info->type = type;
1821 /* compute context virtual pointer */
1822 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1824 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1825 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1826 line = p_info->iid / cxts_per_p;
1828 /* Make sure context is allocated (dynamic allocation) */
1829 if (!p_mngr->ilt_shadow[line].p_virt)
1832 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1833 p_info->iid % cxts_per_p * conn_cxt_size;
1835 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1836 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1837 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1839 return ECORE_SUCCESS;
1842 void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
1844 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1846 p_mgr->srq_count = num_srqs;
1849 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
1851 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1853 return p_mgr->srq_count;
1856 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1858 /* Set the number of required CORE connections */
1859 u32 core_cids = 1; /* SPQ */
1861 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1863 switch (p_hwfn->hw_info.personality) {
1866 struct ecore_eth_pf_params *p_params =
1867 &p_hwfn->pf_params.eth_pf_params;
1869 ecore_cxt_set_proto_cid_count(p_hwfn,
1871 p_params->num_cons, 1); /* FIXME VF count... */
1879 return ECORE_SUCCESS;
1882 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
1883 struct ecore_tid_mem *p_info)
1885 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1886 u32 proto, seg, total_lines, i, shadow_line;
1887 struct ecore_ilt_client_cfg *p_cli;
1888 struct ecore_ilt_cli_blk *p_fl_seg;
1889 struct ecore_tid_seg *p_seg_info;
1891 /* Verify the personality */
1892 switch (p_hwfn->hw_info.personality) {
1897 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1901 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1902 if (!p_seg_info->has_fl_mem)
1905 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1906 total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1907 p_fl_seg->real_size_in_page);
1909 for (i = 0; i < total_lines; i++) {
1910 shadow_line = i + p_fl_seg->start_line -
1911 p_hwfn->p_cxt_mngr->pf_start_line;
1912 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1914 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1915 p_fl_seg->real_size_in_page;
1916 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1917 p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1920 return ECORE_SUCCESS;
1923 /* This function is very RoCE oriented, if another protocol in the future
1924 * will want this feature we'll need to modify the function to be more generic
1926 enum _ecore_status_t
1927 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
1928 enum ecore_cxt_elem_type elem_type,
1931 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
1932 struct ecore_ilt_client_cfg *p_cli;
1933 struct ecore_ilt_cli_blk *p_blk;
1934 struct ecore_ptt *p_ptt;
1938 enum _ecore_status_t rc = ECORE_SUCCESS;
1940 switch (elem_type) {
1941 case ECORE_ELEM_CXT:
1942 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1943 elem_size = CONN_CXT_SIZE(p_hwfn);
1944 p_blk = &p_cli->pf_blks[CDUC_BLK];
1946 case ECORE_ELEM_SRQ:
1947 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
1948 elem_size = SRQ_CXT_SIZE;
1949 p_blk = &p_cli->pf_blks[SRQ_BLK];
1951 case ECORE_ELEM_TASK:
1952 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1953 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
1954 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
1957 DP_NOTICE(p_hwfn, false,
1958 "ECORE_INVALID elem type = %d", elem_type);
1962 /* Calculate line in ilt */
1963 hw_p_size = p_cli->p_size.val;
1964 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1965 line = p_blk->start_line + (iid / elems_per_p);
1966 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
1968 /* If line is already allocated, do nothing, otherwise allocate it and
1969 * write it to the PSWRQ2 registers.
1970 * This section can be run in parallel from different contexts and thus
1971 * a mutex protection is needed.
1974 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
1976 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
1979 p_ptt = ecore_ptt_acquire(p_hwfn);
1981 DP_NOTICE(p_hwfn, false,
1982 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
1987 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1989 p_blk->real_size_in_page);
1994 OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
1996 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
1997 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
1998 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
1999 p_blk->real_size_in_page;
2001 /* compute absolute offset */
2002 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2003 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2006 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2007 SET_FIELD(ilt_hw_entry,
2009 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2011 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2013 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2014 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2017 if (elem_type == ECORE_ELEM_CXT) {
2018 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2021 /* Update the relevant register in the parser */
2022 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2023 last_cid_allocated - 1);
2025 if (!p_hwfn->b_rdma_enabled_in_prs) {
2026 /* Enable RoCE search */
2027 ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2028 p_hwfn->b_rdma_enabled_in_prs = true;
2033 ecore_ptt_release(p_hwfn, p_ptt);
2035 OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2040 /* This function is very RoCE oriented, if another protocol in the future
2041 * will want this feature we'll need to modify the function to be more generic
2043 static enum _ecore_status_t
2044 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2045 enum ecore_cxt_elem_type elem_type,
2046 u32 start_iid, u32 count)
2048 u32 start_line, end_line, shadow_start_line, shadow_end_line;
2049 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2050 struct ecore_ilt_client_cfg *p_cli;
2051 struct ecore_ilt_cli_blk *p_blk;
2052 u32 end_iid = start_iid + count;
2053 struct ecore_ptt *p_ptt;
2054 u64 ilt_hw_entry = 0;
2057 switch (elem_type) {
2058 case ECORE_ELEM_CXT:
2059 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2060 elem_size = CONN_CXT_SIZE(p_hwfn);
2061 p_blk = &p_cli->pf_blks[CDUC_BLK];
2063 case ECORE_ELEM_SRQ:
2064 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2065 elem_size = SRQ_CXT_SIZE;
2066 p_blk = &p_cli->pf_blks[SRQ_BLK];
2068 case ECORE_ELEM_TASK:
2069 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2070 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2071 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2074 DP_NOTICE(p_hwfn, false,
2075 "ECORE_INVALID elem type = %d", elem_type);
2079 /* Calculate line in ilt */
2080 hw_p_size = p_cli->p_size.val;
2081 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2082 start_line = p_blk->start_line + (start_iid / elems_per_p);
2083 end_line = p_blk->start_line + (end_iid / elems_per_p);
2084 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2087 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2088 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2090 p_ptt = ecore_ptt_acquire(p_hwfn);
2092 DP_NOTICE(p_hwfn, false,
2093 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2094 return ECORE_TIMEOUT;
2097 for (i = shadow_start_line; i < shadow_end_line; i++) {
2098 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2101 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2102 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2103 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2104 p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2106 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2107 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2108 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2110 /* compute absolute offset */
2111 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2112 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2115 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2118 ecore_dmae_host2grc(p_hwfn, p_ptt,
2119 (u64)(osal_uintptr_t)&ilt_hw_entry,
2121 sizeof(ilt_hw_entry) / sizeof(u32),
2125 ecore_ptt_release(p_hwfn, p_ptt);
2127 return ECORE_SUCCESS;
2130 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2131 enum protocol_type proto)
2133 enum _ecore_status_t rc;
2136 /* Free Connection CXT */
2137 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2138 ecore_cxt_get_proto_cid_start(p_hwfn,
2140 ecore_cxt_get_proto_cid_count(p_hwfn,
2148 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2149 ecore_cxt_get_proto_tid_count(p_hwfn,
2155 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2156 ecore_cxt_get_srq_count(p_hwfn));
2161 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
2163 u8 ctx_type, void **pp_task_ctx)
2165 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2166 struct ecore_ilt_client_cfg *p_cli;
2167 struct ecore_ilt_cli_blk *p_seg;
2168 struct ecore_tid_seg *p_seg_info;
2171 u32 tid_size, ilt_idx;
2172 u32 num_tids_per_block;
2174 /* Verify the personality */
2175 switch (p_hwfn->hw_info.personality) {
2180 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2184 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2186 if (ctx_type == ECORE_CTX_WORKING_MEM) {
2187 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2188 } else if (ctx_type == ECORE_CTX_FL_MEM) {
2189 if (!p_seg_info->has_fl_mem)
2191 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2195 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2196 tid_size = p_mngr->task_type_size[p_seg_info->type];
2197 num_tids_per_block = p_seg->real_size_in_page / tid_size;
2199 if (total_lines < tid / num_tids_per_block)
2202 ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2203 p_mngr->pf_start_line;
2204 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2205 (tid % num_tids_per_block) * tid_size;
2207 return ECORE_SUCCESS;