2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "common_hsi.h"
12 #include "ecore_hsi_common.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_status.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_init_fw_funcs.h"
19 #include "ecore_cxt.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
23 #include "ecore_mcp.h"
25 /* Max number of connection types in HW (DQ/CDU etc.) */
26 #define MAX_CONN_TYPES PROTOCOLID_COMMON
27 #define NUM_TASK_TYPES 2
28 #define NUM_TASK_PF_SEGMENTS 4
29 #define NUM_TASK_VF_SEGMENTS 1
31 /* Doorbell-Queue constants */
32 #define DQ_RANGE_SHIFT 4
33 #define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT)
35 /* Searcher constants */
36 #define SRC_MIN_NUM_ELEMS 256
38 /* Timers constants */
40 #define TM_ALIGN (1 << TM_SHIFT)
41 #define TM_ELEM_SIZE 4
44 #define ILT_DEFAULT_HW_P_SIZE 4
46 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
47 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
49 /* ILT entry structure */
50 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
51 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
52 #define ILT_ENTRY_VALID_MASK 0x1ULL
53 #define ILT_ENTRY_VALID_SHIFT 52
54 #define ILT_ENTRY_IN_REGS 2
55 #define ILT_REG_SIZE_IN_BYTES 4
57 /* connection context union */
59 struct e4_core_conn_context core_ctx;
60 struct e4_eth_conn_context eth_ctx;
63 /* TYPE-0 task context - iSCSI, FCOE */
64 union type0_task_context {
67 /* TYPE-1 task context - ROCE */
68 union type1_task_context {
69 struct regpair reserved; /* @DPDK */
77 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
78 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
80 #define CONN_CXT_SIZE(p_hwfn) \
81 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
83 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
85 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
86 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
88 /* Alignment is inherent to the type1_task_context structure */
89 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
91 /* PF per protocl configuration object */
92 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
93 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
95 struct ecore_tid_seg {
101 struct ecore_conn_type_cfg {
104 struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
107 /* ILT Client configuration,
108 * Per connection type (protocol) resources (cids, tis, vf cids etc.)
109 * 1 - for connection context (CDUC) and for each task context we need two
110 * values, for regular task context and for force load memory
112 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
113 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
116 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
117 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS)
129 struct ilt_cfg_pair {
134 struct ecore_ilt_cli_blk {
135 u32 total_size; /* 0 means not active */
136 u32 real_size_in_page;
138 u32 dynamic_line_cnt;
141 struct ecore_ilt_client_cfg {
145 struct ilt_cfg_pair first;
146 struct ilt_cfg_pair last;
147 struct ilt_cfg_pair p_size;
149 /* ILT client blocks for PF */
150 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
153 /* ILT client blocks for VFs */
154 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
160 * Protocol acquired CID lists
161 * PF start line in ILT
163 struct ecore_dma_mem {
169 #define MAP_WORD_SIZE sizeof(unsigned long)
170 #define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8)
172 struct ecore_cid_acquired_map {
175 unsigned long *cid_map;
178 struct ecore_cxt_mngr {
179 /* Per protocl configuration */
180 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
182 /* computed ILT structure */
183 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
185 /* Task type sizes */
186 u32 task_type_size[NUM_TASK_TYPES];
188 /* total number of VFs for this hwfn -
189 * ALL VFs are symmetric in terms of HW resources
194 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
195 /* TBD - do we want this allocated to reserve space? */
196 struct ecore_cid_acquired_map
197 acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS];
199 /* ILT shadow table */
200 struct ecore_dma_mem *ilt_shadow;
203 /* Mutex for a dynamic ILT allocation */
207 struct ecore_dma_mem *t2;
212 /* The infrastructure originally was very generic and context/task
213 * oriented - per connection-type we would set how many of those
214 * are needed, and later when determining how much memory we're
215 * needing for a given block we'd iterate over all the relevant
217 * But since then we've had some additional resources, some of which
218 * require memory which is indepent of the general context/task
219 * scheme. We add those here explicitly per-feature.
222 /* total number of SRQ's for this hwfn */
225 /* Maximal number of L2 steering filters */
228 /* TODO - VF arfs filters ? */
231 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
233 return type == PROTOCOLID_TOE;
236 static bool tm_tid_proto(enum protocol_type type)
238 return type == PROTOCOLID_FCOE;
241 /* counts the iids for the CDU/CDUC ILT client configuration */
242 struct ecore_cdu_iids {
247 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
248 struct ecore_cdu_iids *iids)
252 for (type = 0; type < MAX_CONN_TYPES; type++) {
253 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
254 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
258 /* counts the iids for the Searcher block configuration */
259 struct ecore_src_iids {
264 static void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
265 struct ecore_src_iids *iids)
269 for (i = 0; i < MAX_CONN_TYPES; i++) {
270 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
271 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
274 /* Add L2 filtering filters in addition */
275 iids->pf_cids += p_mngr->arfs_count;
278 /* counts the iids for the Timers block configuration */
279 struct ecore_tm_iids {
281 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
287 static void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
288 struct ecore_tm_iids *iids)
290 bool tm_vf_required = false;
291 bool tm_required = false;
294 for (i = 0; i < MAX_CONN_TYPES; i++) {
295 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
297 if (tm_cid_proto(i) || tm_required) {
298 if (p_cfg->cid_count)
301 iids->pf_cids += p_cfg->cid_count;
304 if (tm_cid_proto(i) || tm_vf_required) {
305 if (p_cfg->cids_per_vf)
306 tm_vf_required = true;
310 if (tm_tid_proto(i)) {
311 struct ecore_tid_seg *segs = p_cfg->tid_seg;
313 /* for each segment there is at most one
314 * protocol for which count is not 0.
316 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
317 iids->pf_tids[j] += segs[j].count;
319 /* The last array elelment is for the VFs. As for PF
320 * segments there can be only one protocol for
321 * which this value is not 0.
323 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
327 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
328 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
329 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
331 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
332 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
333 iids->pf_tids_total += iids->pf_tids[j];
337 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
338 struct ecore_qm_iids *iids)
340 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
341 struct ecore_tid_seg *segs;
342 u32 vf_cids = 0, type, j;
345 for (type = 0; type < MAX_CONN_TYPES; type++) {
346 iids->cids += p_mngr->conn_cfg[type].cid_count;
347 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
349 segs = p_mngr->conn_cfg[type].tid_seg;
350 /* for each segment there is at most one
351 * protocol for which count is not 0.
353 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
354 iids->tids += segs[j].count;
356 /* The last array elelment is for the VFs. As for PF
357 * segments there can be only one protocol for
358 * which this value is not 0.
360 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
363 iids->vf_cids += vf_cids * p_mngr->vf_count;
364 iids->tids += vf_tids * p_mngr->vf_count;
366 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
367 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
368 iids->cids, iids->vf_cids, iids->tids, vf_tids);
371 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
374 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
377 /* Find the protocol with tid count > 0 for this segment.
378 * Note: there can only be one and this is already validated.
380 for (i = 0; i < MAX_CONN_TYPES; i++) {
381 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
382 return &p_cfg->conn_cfg[i].tid_seg[seg];
387 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
389 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
391 p_mgr->srq_count = num_srqs;
394 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
396 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
398 return p_mgr->srq_count;
401 /* set the iids (cid/tid) count per protocol */
402 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
403 enum protocol_type type,
404 u32 cid_count, u32 vf_cid_cnt)
406 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
407 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
409 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
410 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
413 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
414 enum protocol_type type, u32 *vf_cid)
417 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
419 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
422 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
423 enum protocol_type type)
425 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
428 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
429 enum protocol_type type)
434 for (i = 0; i < TASK_SEGMENTS; i++)
435 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
440 static OSAL_INLINE void
441 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
442 enum protocol_type proto,
443 u8 seg, u8 seg_type, u32 count, bool has_fl)
445 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
446 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
448 p_seg->count = count;
449 p_seg->has_fl_mem = has_fl;
450 p_seg->type = seg_type;
453 /* the *p_line parameter must be either 0 for the first invocation or the
454 * value returned in the previous invocation.
456 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
457 struct ecore_ilt_cli_blk *p_blk,
459 u32 total_size, u32 elem_size)
461 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
463 /* verify that it's called once for each block */
464 if (p_blk->total_size)
467 p_blk->total_size = total_size;
468 p_blk->real_size_in_page = 0;
470 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
471 p_blk->start_line = start_line;
474 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
475 struct ecore_ilt_client_cfg *p_cli,
476 struct ecore_ilt_cli_blk *p_blk,
477 u32 *p_line, enum ilt_clients client_id)
479 if (!p_blk->total_size)
483 p_cli->first.val = *p_line;
485 p_cli->active = true;
486 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
487 p_cli->last.val = *p_line - 1;
489 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
490 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
491 " [Real %08x] Start line %d\n",
492 client_id, p_cli->first.val, p_cli->last.val,
493 p_blk->total_size, p_blk->real_size_in_page,
497 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
498 enum ilt_clients ilt_client)
500 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
501 struct ecore_ilt_client_cfg *p_cli;
502 u32 lines_to_skip = 0;
505 /* TBD MK: ILT code should be simplified once PROTO enum is changed */
507 if (ilt_client == ILT_CLI_CDUC) {
508 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
510 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
511 (u32)CONN_CXT_SIZE(p_hwfn);
513 lines_to_skip = cid_count / cxts_per_p;
516 return lines_to_skip;
519 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
521 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
522 u32 curr_line, total, i, task_size, line;
523 struct ecore_ilt_client_cfg *p_cli;
524 struct ecore_ilt_cli_blk *p_blk;
525 struct ecore_cdu_iids cdu_iids;
526 struct ecore_src_iids src_iids;
527 struct ecore_qm_iids qm_iids;
528 struct ecore_tm_iids tm_iids;
529 struct ecore_tid_seg *p_seg;
531 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
532 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
533 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
534 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
536 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
538 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
539 "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
540 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
543 p_cli = &p_mngr->clients[ILT_CLI_CDUC];
545 curr_line = p_mngr->pf_start_line;
548 p_cli->pf_total_lines = 0;
550 /* get the counters for the CDUC,CDUC and QM clients */
551 ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
553 p_blk = &p_cli->pf_blks[CDUC_BLK];
555 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
557 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
558 total, CONN_CXT_SIZE(p_hwfn));
560 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
561 p_cli->pf_total_lines = curr_line - p_blk->start_line;
563 p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
567 p_blk = &p_cli->vf_blks[CDUC_BLK];
568 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
570 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
571 total, CONN_CXT_SIZE(p_hwfn));
573 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
574 p_cli->vf_total_lines = curr_line - p_blk->start_line;
576 for (i = 1; i < p_mngr->vf_count; i++)
577 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
581 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
582 p_cli->first.val = curr_line;
584 /* first the 'working' task memory */
585 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
586 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
587 if (!p_seg || p_seg->count == 0)
590 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
591 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
592 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
593 p_mngr->task_type_size[p_seg->type]);
595 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
599 /* next the 'init' task memory (forced load memory) */
600 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
601 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
602 if (!p_seg || p_seg->count == 0)
605 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
607 if (!p_seg->has_fl_mem) {
608 /* The segment is active (total size pf 'working'
609 * memory is > 0) but has no FL (forced-load, Init)
612 * 1. The total-size in the corrsponding FL block of
613 * the ILT client is set to 0 - No ILT line are
614 * provisioned and no ILT memory allocated.
616 * 2. The start-line of said block is set to the
617 * start line of the matching working memory
618 * block in the ILT client. This is later used to
619 * configure the CDU segment offset registers and
620 * results in an FL command for TIDs of this
621 * segment behaves as regular load commands
622 * (loading TIDs from the working memory).
624 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
626 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
629 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
631 ecore_ilt_cli_blk_fill(p_cli, p_blk,
633 p_mngr->task_type_size[p_seg->type]);
635 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
638 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
641 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
642 if (p_seg && p_seg->count) {
643 /* Stricly speaking we need to iterate over all VF
644 * task segment types, but a VF has only 1 segment
647 /* 'working' memory */
648 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
650 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
651 ecore_ilt_cli_blk_fill(p_cli, p_blk,
653 p_mngr->task_type_size[p_seg->type]);
655 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
659 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
660 if (!p_seg->has_fl_mem) {
661 /* see comment above */
662 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
663 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
665 task_size = p_mngr->task_type_size[p_seg->type];
666 ecore_ilt_cli_blk_fill(p_cli, p_blk,
667 curr_line, total, task_size);
668 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
671 p_cli->vf_total_lines = curr_line -
672 p_cli->vf_blks[0].start_line;
674 /* Now for the rest of the VFs */
675 for (i = 1; i < p_mngr->vf_count; i++) {
676 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
677 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
680 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
681 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
687 p_cli = &p_mngr->clients[ILT_CLI_QM];
688 p_blk = &p_cli->pf_blks[0];
690 ecore_cxt_qm_iids(p_hwfn, &qm_iids);
691 total = ecore_qm_pf_mem_size(qm_iids.cids,
692 qm_iids.vf_cids, qm_iids.tids,
693 p_hwfn->qm_info.num_pqs,
694 p_hwfn->qm_info.num_vf_pqs);
696 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
697 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
698 " num_vf_pqs=%d, memory_size=%d)\n",
699 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
700 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
702 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
705 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
706 p_cli->pf_total_lines = curr_line - p_blk->start_line;
709 p_cli = &p_mngr->clients[ILT_CLI_SRC];
710 ecore_cxt_src_iids(p_mngr, &src_iids);
712 /* Both the PF and VFs searcher connections are stored in the per PF
713 * database. Thus sum the PF searcher cids and all the VFs searcher
716 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
718 u32 local_max = OSAL_MAX_T(u32, total,
721 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
723 p_blk = &p_cli->pf_blks[0];
724 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
725 total * sizeof(struct src_ent),
726 sizeof(struct src_ent));
728 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
730 p_cli->pf_total_lines = curr_line - p_blk->start_line;
734 p_cli = &p_mngr->clients[ILT_CLI_TM];
735 ecore_cxt_tm_iids(p_mngr, &tm_iids);
736 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
738 p_blk = &p_cli->pf_blks[0];
739 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
740 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
742 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
744 p_cli->pf_total_lines = curr_line - p_blk->start_line;
748 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
750 p_blk = &p_cli->vf_blks[0];
751 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
752 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
754 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
757 p_cli->vf_total_lines = curr_line - p_blk->start_line;
758 for (i = 1; i < p_mngr->vf_count; i++) {
759 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
764 /* TSDM (SRQ CONTEXT) */
765 total = ecore_cxt_get_srq_count(p_hwfn);
768 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
769 p_blk = &p_cli->pf_blks[SRQ_BLK];
770 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
771 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
773 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
775 p_cli->pf_total_lines = curr_line - p_blk->start_line;
778 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
779 RESC_NUM(p_hwfn, ECORE_ILT)) {
780 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
781 curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
785 return ECORE_SUCCESS;
788 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
790 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
796 for (i = 0; i < p_mngr->t2_num_pages; i++)
797 if (p_mngr->t2[i].p_virt)
798 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
799 p_mngr->t2[i].p_virt,
800 p_mngr->t2[i].p_phys,
803 OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
806 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
808 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
809 u32 conn_num, total_size, ent_per_page, psz, i;
810 struct ecore_ilt_client_cfg *p_src;
811 struct ecore_src_iids src_iids;
812 struct ecore_dma_mem *p_t2;
813 enum _ecore_status_t rc;
815 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
817 /* if the SRC ILT client is inactive - there are no connection
818 * requiring the searcer, leave.
820 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
822 return ECORE_SUCCESS;
824 ecore_cxt_src_iids(p_mngr, &src_iids);
825 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
826 total_size = conn_num * sizeof(struct src_ent);
828 /* use the same page size as the SRC ILT client */
829 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
830 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
833 p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
834 p_mngr->t2_num_pages *
835 sizeof(struct ecore_dma_mem));
837 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
842 /* allocate t2 pages */
843 for (i = 0; i < p_mngr->t2_num_pages; i++) {
844 u32 size = OSAL_MIN_T(u32, total_size, psz);
845 void **p_virt = &p_mngr->t2[i].p_virt;
847 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
848 &p_mngr->t2[i].p_phys, size);
849 if (!p_mngr->t2[i].p_virt) {
853 OSAL_MEM_ZERO(*p_virt, size);
854 p_mngr->t2[i].size = size;
858 /* Set the t2 pointers */
860 /* entries per page - must be a power of two */
861 ent_per_page = psz / sizeof(struct src_ent);
863 p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
865 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
866 p_mngr->last_free = (u64)p_t2->p_phys +
867 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
869 for (i = 0; i < p_mngr->t2_num_pages; i++) {
870 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
871 struct src_ent *entries = p_mngr->t2[i].p_virt;
872 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
875 for (j = 0; j < ent_num - 1; j++) {
876 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
877 entries[j].next = OSAL_CPU_TO_BE64(val);
880 if (i < p_mngr->t2_num_pages - 1)
881 val = (u64)p_mngr->t2[i + 1].p_phys;
884 entries[j].next = OSAL_CPU_TO_BE64(val);
889 return ECORE_SUCCESS;
892 ecore_cxt_src_t2_free(p_hwfn);
896 #define for_each_ilt_valid_client(pos, clients) \
897 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
898 if (!clients[pos].active) { \
903 /* Total number of ILT lines used by this PF */
904 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
909 for_each_ilt_valid_client(i, ilt_clients)
910 size += (ilt_clients[i].last.val -
911 ilt_clients[i].first.val + 1);
916 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
918 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
919 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
922 ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
924 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
925 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
928 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
930 p_dma->p_phys, p_dma->size);
931 p_dma->p_virt = OSAL_NULL;
933 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
936 static enum _ecore_status_t
937 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
938 struct ecore_ilt_cli_blk *p_blk,
939 enum ilt_clients ilt_client, u32 start_line_offset)
941 struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
942 u32 lines, line, sz_left, lines_to_skip = 0;
944 /* Special handling for RoCE that supports dynamic allocation */
945 if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
946 return ECORE_SUCCESS;
948 lines_to_skip = p_blk->dynamic_line_cnt;
950 if (!p_blk->total_size)
951 return ECORE_SUCCESS;
953 sz_left = p_blk->total_size;
954 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
955 line = p_blk->start_line + start_line_offset -
956 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
958 for (; lines; lines--) {
963 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
966 #define ILT_BLOCK_ALIGN_SIZE 0x1000
967 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
969 ILT_BLOCK_ALIGN_SIZE);
972 OSAL_MEM_ZERO(p_virt, size);
974 ilt_shadow[line].p_phys = p_phys;
975 ilt_shadow[line].p_virt = p_virt;
976 ilt_shadow[line].size = size;
978 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
979 "ILT shadow: Line [%d] Physical 0x%lx"
980 " Virtual %p Size %d\n",
981 line, (unsigned long)p_phys, p_virt, size);
987 return ECORE_SUCCESS;
990 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
992 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
993 struct ecore_ilt_client_cfg *clients = p_mngr->clients;
994 struct ecore_ilt_cli_blk *p_blk;
996 enum _ecore_status_t rc;
998 size = ecore_cxt_ilt_shadow_size(clients);
999 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1000 size * sizeof(struct ecore_dma_mem));
1002 if (!p_mngr->ilt_shadow) {
1003 DP_NOTICE(p_hwfn, true,
1004 "Failed to allocate ilt shadow table\n");
1006 goto ilt_shadow_fail;
1009 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1010 "Allocated 0x%x bytes for ilt shadow\n",
1011 (u32)(size * sizeof(struct ecore_dma_mem)));
1013 for_each_ilt_valid_client(i, clients) {
1014 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1015 p_blk = &clients[i].pf_blks[j];
1016 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1017 if (rc != ECORE_SUCCESS)
1018 goto ilt_shadow_fail;
1020 for (k = 0; k < p_mngr->vf_count; k++) {
1021 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1022 u32 lines = clients[i].vf_total_lines * k;
1024 p_blk = &clients[i].vf_blks[j];
1025 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1027 if (rc != ECORE_SUCCESS)
1028 goto ilt_shadow_fail;
1033 return ECORE_SUCCESS;
1036 ecore_ilt_shadow_free(p_hwfn);
1040 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1042 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1045 for (type = 0; type < MAX_CONN_TYPES; type++) {
1046 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1047 p_mngr->acquired[type].max_count = 0;
1048 p_mngr->acquired[type].start_cid = 0;
1050 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1051 OSAL_FREE(p_hwfn->p_dev,
1052 p_mngr->acquired_vf[type][vf].cid_map);
1053 p_mngr->acquired_vf[type][vf].max_count = 0;
1054 p_mngr->acquired_vf[type][vf].start_cid = 0;
1059 static enum _ecore_status_t
1060 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1061 u32 cid_start, u32 cid_count,
1062 struct ecore_cid_acquired_map *p_map)
1067 return ECORE_SUCCESS;
1069 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1070 p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1071 if (p_map->cid_map == OSAL_NULL)
1074 p_map->max_count = cid_count;
1075 p_map->start_cid = cid_start;
1077 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1078 "Type %08x start: %08x count %08x\n",
1079 type, p_map->start_cid, p_map->max_count);
1081 return ECORE_SUCCESS;
1084 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1086 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1087 u32 start_cid = 0, vf_start_cid = 0;
1090 for (type = 0; type < MAX_CONN_TYPES; type++) {
1091 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1092 struct ecore_cid_acquired_map *p_map;
1094 /* Handle PF maps */
1095 p_map = &p_mngr->acquired[type];
1096 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1097 p_cfg->cid_count, p_map))
1100 /* Handle VF maps */
1101 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1102 p_map = &p_mngr->acquired_vf[type][vf];
1103 if (ecore_cid_map_alloc_single(p_hwfn, type,
1110 start_cid += p_cfg->cid_count;
1111 vf_start_cid += p_cfg->cids_per_vf;
1114 return ECORE_SUCCESS;
1117 ecore_cid_map_free(p_hwfn);
1121 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1123 struct ecore_ilt_client_cfg *clients;
1124 struct ecore_cxt_mngr *p_mngr;
1127 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1129 DP_NOTICE(p_hwfn, true,
1130 "Failed to allocate `struct ecore_cxt_mngr'\n");
1134 /* Initialize ILT client registers */
1135 clients = p_mngr->clients;
1136 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1137 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1138 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1140 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1141 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1142 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1144 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1145 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1146 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1148 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1149 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1150 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1152 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1153 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1154 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1156 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1157 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1158 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1160 /* default ILT page size for all clients is 64K */
1161 for (i = 0; i < ILT_CLI_MAX; i++)
1162 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1164 /* due to removal of ISCSI/FCoE files union type0_task_context
1165 * task_type_size will be 0. So hardcoded for now.
1167 p_mngr->task_type_size[0] = 512; /* @DPDK */
1168 p_mngr->task_type_size[1] = 128; /* @DPDK */
1170 if (p_hwfn->p_dev->p_iov_info)
1171 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1173 /* Initialize the dynamic ILT allocation mutex */
1174 #ifdef CONFIG_ECORE_LOCK_ALLOC
1175 OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1177 OSAL_MUTEX_INIT(&p_mngr->mutex);
1179 /* Set the cxt mangr pointer priori to further allocations */
1180 p_hwfn->p_cxt_mngr = p_mngr;
1182 return ECORE_SUCCESS;
1185 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1187 enum _ecore_status_t rc;
1189 /* Allocate the ILT shadow table */
1190 rc = ecore_ilt_shadow_alloc(p_hwfn);
1192 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1193 goto tables_alloc_fail;
1196 /* Allocate the T2 table */
1197 rc = ecore_cxt_src_t2_alloc(p_hwfn);
1199 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1200 goto tables_alloc_fail;
1203 /* Allocate and initialize the acquired cids bitmaps */
1204 rc = ecore_cid_map_alloc(p_hwfn);
1206 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1207 goto tables_alloc_fail;
1210 return ECORE_SUCCESS;
1213 ecore_cxt_mngr_free(p_hwfn);
1217 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1219 if (!p_hwfn->p_cxt_mngr)
1222 ecore_cid_map_free(p_hwfn);
1223 ecore_cxt_src_t2_free(p_hwfn);
1224 ecore_ilt_shadow_free(p_hwfn);
1225 #ifdef CONFIG_ECORE_LOCK_ALLOC
1226 OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1228 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1231 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1233 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1234 struct ecore_cid_acquired_map *p_map;
1235 struct ecore_conn_type_cfg *p_cfg;
1239 /* Reset acquired cids */
1240 for (type = 0; type < MAX_CONN_TYPES; type++) {
1243 p_cfg = &p_mngr->conn_cfg[type];
1244 if (p_cfg->cid_count) {
1245 p_map = &p_mngr->acquired[type];
1246 len = DIV_ROUND_UP(p_map->max_count,
1247 BITS_PER_MAP_WORD) *
1249 OSAL_MEM_ZERO(p_map->cid_map, len);
1252 if (!p_cfg->cids_per_vf)
1255 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1256 p_map = &p_mngr->acquired_vf[type][vf];
1257 len = DIV_ROUND_UP(p_map->max_count,
1258 BITS_PER_MAP_WORD) *
1260 OSAL_MEM_ZERO(p_map->cid_map, len);
1265 /* HW initialization helper (per Block, per phase) */
1268 #define CDUC_CXT_SIZE_SHIFT \
1269 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1271 #define CDUC_CXT_SIZE_MASK \
1272 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1274 #define CDUC_BLOCK_WASTE_SHIFT \
1275 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1277 #define CDUC_BLOCK_WASTE_MASK \
1278 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1280 #define CDUC_NCIB_SHIFT \
1281 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1283 #define CDUC_NCIB_MASK \
1284 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1286 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1287 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1289 #define CDUT_TYPE0_CXT_SIZE_MASK \
1290 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1291 CDUT_TYPE0_CXT_SIZE_SHIFT)
1293 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1294 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1296 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1297 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1298 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1300 #define CDUT_TYPE0_NCIB_SHIFT \
1301 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1303 #define CDUT_TYPE0_NCIB_MASK \
1304 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1305 CDUT_TYPE0_NCIB_SHIFT)
1307 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1308 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1310 #define CDUT_TYPE1_CXT_SIZE_MASK \
1311 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1312 CDUT_TYPE1_CXT_SIZE_SHIFT)
1314 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1315 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1317 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1318 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1319 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1321 #define CDUT_TYPE1_NCIB_SHIFT \
1322 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1324 #define CDUT_TYPE1_NCIB_MASK \
1325 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1326 CDUT_TYPE1_NCIB_SHIFT)
1328 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1330 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1332 /* CDUC - connection configuration */
1333 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1334 cxt_size = CONN_CXT_SIZE(p_hwfn);
1335 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1336 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1338 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1339 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1340 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1341 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1343 /* CDUT - type-0 tasks configuration */
1344 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1345 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1346 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1347 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1349 /* cxt size and block-waste are multipes of 8 */
1351 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1352 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1353 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1354 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1356 /* CDUT - type-1 tasks configuration */
1357 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1358 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1359 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1361 /* cxt size and block-waste are multipes of 8 */
1363 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1364 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1365 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1366 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1370 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1371 #define CDU_SEG_REG_TYPE_MASK 0x1
1372 #define CDU_SEG_REG_OFFSET_SHIFT 0
1373 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1375 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1377 struct ecore_ilt_client_cfg *p_cli;
1378 struct ecore_tid_seg *p_seg;
1379 u32 cdu_seg_params, offset;
1382 static const u32 rt_type_offset_arr[] = {
1383 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1384 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1385 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1386 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1389 static const u32 rt_type_offset_fl_arr[] = {
1390 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1391 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1392 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1393 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1396 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1398 /* There are initializations only for CDUT during pf Phase */
1399 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1401 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1405 /* Note: start_line is already adjusted for the CDU
1406 * segment register granularity, so we just need to
1407 * divide. Adjustment is implicit as we assume ILT
1408 * Page size is larger than 32K!
1410 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1411 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1412 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1415 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1416 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1417 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1419 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1420 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1421 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1424 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1425 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1426 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1430 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1432 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1433 struct ecore_mcp_link_state *p_link;
1434 struct ecore_qm_iids iids;
1436 OSAL_MEM_ZERO(&iids, sizeof(iids));
1437 ecore_cxt_qm_iids(p_hwfn, &iids);
1439 p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output;
1441 ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->port_id,
1442 p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1443 iids.cids, iids.vf_cids, iids.tids,
1445 qm_info->num_pqs - qm_info->num_vf_pqs,
1446 qm_info->num_vf_pqs,
1447 qm_info->start_vport,
1448 qm_info->num_vports, qm_info->pf_wfq,
1449 qm_info->pf_rl, p_link->speed,
1450 p_hwfn->qm_info.qm_pq_params,
1451 p_hwfn->qm_info.qm_vport_params);
1455 static void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1457 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1458 ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1462 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1464 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1465 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1467 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1468 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1470 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1471 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1473 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1474 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1476 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1477 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1479 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1480 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1482 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1483 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1485 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1486 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1488 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1489 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1491 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1492 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1494 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1495 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1497 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1498 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1500 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1501 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1503 /* Connection types 6 & 7 are not in use, yet they must be configured
1504 * as the highest possible connection. Not configuring them means the
1505 * defaults will be used, and with a large number of cids a bug may
1506 * occur, if the defaults will be smaller than dq_pf_max_cid /
1509 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1510 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1512 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1513 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1516 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1518 struct ecore_ilt_client_cfg *ilt_clients;
1521 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1522 for_each_ilt_valid_client(i, ilt_clients) {
1523 STORE_RT_REG(p_hwfn,
1524 ilt_clients[i].first.reg,
1525 ilt_clients[i].first.val);
1526 STORE_RT_REG(p_hwfn,
1527 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1528 STORE_RT_REG(p_hwfn,
1529 ilt_clients[i].p_size.reg,
1530 ilt_clients[i].p_size.val);
1534 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1536 struct ecore_ilt_client_cfg *p_cli;
1539 /* For simplicty we set the 'block' to be an ILT page */
1540 if (p_hwfn->p_dev->p_iov_info) {
1541 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1543 STORE_RT_REG(p_hwfn,
1544 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1545 p_iov->first_vf_in_pf);
1546 STORE_RT_REG(p_hwfn,
1547 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1548 p_iov->first_vf_in_pf + p_iov->total_vfs);
1551 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1552 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1553 if (p_cli->active) {
1554 STORE_RT_REG(p_hwfn,
1555 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1557 STORE_RT_REG(p_hwfn,
1558 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1559 p_cli->pf_total_lines);
1560 STORE_RT_REG(p_hwfn,
1561 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1562 p_cli->vf_total_lines);
1565 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1566 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1567 if (p_cli->active) {
1568 STORE_RT_REG(p_hwfn,
1569 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1571 STORE_RT_REG(p_hwfn,
1572 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1573 p_cli->pf_total_lines);
1574 STORE_RT_REG(p_hwfn,
1575 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1576 p_cli->vf_total_lines);
1579 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1580 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1581 if (p_cli->active) {
1582 STORE_RT_REG(p_hwfn,
1583 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1584 STORE_RT_REG(p_hwfn,
1585 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1586 p_cli->pf_total_lines);
1587 STORE_RT_REG(p_hwfn,
1588 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1589 p_cli->vf_total_lines);
1593 /* ILT (PSWRQ2) PF */
1594 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1596 struct ecore_ilt_client_cfg *clients;
1597 struct ecore_cxt_mngr *p_mngr;
1598 struct ecore_dma_mem *p_shdw;
1599 u32 line, rt_offst, i;
1601 ecore_ilt_bounds_init(p_hwfn);
1602 ecore_ilt_vf_bounds_init(p_hwfn);
1604 p_mngr = p_hwfn->p_cxt_mngr;
1605 p_shdw = p_mngr->ilt_shadow;
1606 clients = p_hwfn->p_cxt_mngr->clients;
1608 for_each_ilt_valid_client(i, clients) {
1609 /* Client's 1st val and RT array are absolute, ILT shadows'
1610 * lines are relative.
1612 line = clients[i].first.val - p_mngr->pf_start_line;
1613 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1614 clients[i].first.val * ILT_ENTRY_IN_REGS;
1616 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1617 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1618 u64 ilt_hw_entry = 0;
1620 /** p_virt could be OSAL_NULL incase of dynamic
1623 if (p_shdw[line].p_virt != OSAL_NULL) {
1624 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1625 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1626 (p_shdw[line].p_phys >> 12));
1628 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1629 "Setting RT[0x%08x] from"
1630 " ILT[0x%08x] [Client is %d] to"
1631 " Physical addr: 0x%lx\n",
1633 (unsigned long)(p_shdw[line].
1637 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1642 /* SRC (Searcher) PF */
1643 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1645 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1646 u32 rounded_conn_num, conn_num, conn_max;
1647 struct ecore_src_iids src_iids;
1649 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1650 ecore_cxt_src_iids(p_mngr, &src_iids);
1651 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1655 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1656 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1658 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1659 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1660 OSAL_LOG2(rounded_conn_num));
1662 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1663 p_hwfn->p_cxt_mngr->first_free);
1664 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1665 p_hwfn->p_cxt_mngr->last_free);
1666 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1667 "Configured SEARCHER for 0x%08x connections\n",
1672 #define TM_CFG_NUM_IDS_SHIFT 0
1673 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1674 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1675 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1676 #define TM_CFG_PARENT_PF_SHIFT 25
1677 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1679 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1680 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1682 #define TM_CFG_TID_OFFSET_SHIFT 30
1683 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1684 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1685 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1687 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1689 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1690 u32 active_seg_mask = 0, tm_offset, rt_reg;
1691 struct ecore_tm_iids tm_iids;
1695 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1696 ecore_cxt_tm_iids(p_mngr, &tm_iids);
1698 /* @@@TBD No pre-scan for now */
1700 /* Note: We assume consecutive VFs for a PF */
1701 for (i = 0; i < p_mngr->vf_count; i++) {
1703 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1704 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1705 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1706 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1708 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1709 (sizeof(cfg_word) / sizeof(u32)) *
1710 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1711 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1715 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1716 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1717 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1718 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1720 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1721 (sizeof(cfg_word) / sizeof(u32)) *
1722 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1723 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1726 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1727 tm_iids.pf_cids ? 0x1 : 0x0);
1729 /* @@@TBD how to enable the scan for the VFs */
1731 tm_offset = tm_iids.per_vf_cids;
1733 /* Note: We assume consecutive VFs for a PF */
1734 for (i = 0; i < p_mngr->vf_count; i++) {
1736 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1737 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1738 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1739 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1740 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1742 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1743 (sizeof(cfg_word) / sizeof(u32)) *
1744 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1746 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1749 tm_offset = tm_iids.pf_cids;
1750 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1752 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1753 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1754 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1755 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1756 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1758 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1759 (sizeof(cfg_word) / sizeof(u32)) *
1760 (NUM_OF_VFS(p_hwfn->p_dev) +
1761 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1763 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1764 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1766 tm_offset += tm_iids.pf_tids[i];
1769 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1771 /* @@@TBD how to enable the scan for the VFs */
1774 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1776 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1777 struct ecore_conn_type_cfg *p_fcoe;
1778 struct ecore_tid_seg *p_tid;
1780 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1782 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1783 if (!p_fcoe->cid_count)
1786 p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1787 STORE_RT_REG_AGG(p_hwfn,
1788 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1792 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1794 /* CDU configuration */
1795 ecore_cdu_init_common(p_hwfn);
1798 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1800 ecore_qm_init_pf(p_hwfn, p_ptt);
1801 ecore_cm_init_pf(p_hwfn);
1802 ecore_dq_init_pf(p_hwfn);
1803 ecore_cdu_init_pf(p_hwfn);
1804 ecore_ilt_init_pf(p_hwfn);
1805 ecore_src_init_pf(p_hwfn);
1806 ecore_tm_init_pf(p_hwfn);
1807 ecore_prs_init_pf(p_hwfn);
1810 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1811 enum protocol_type type,
1812 u32 *p_cid, u8 vfid)
1814 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1815 struct ecore_cid_acquired_map *p_map;
1818 if (type >= MAX_CONN_TYPES) {
1819 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1823 if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) {
1824 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1828 /* Determine the right map to take this CID from */
1829 if (vfid == ECORE_CXT_PF_CID)
1830 p_map = &p_mngr->acquired[type];
1832 p_map = &p_mngr->acquired_vf[type][vfid];
1834 if (p_map->cid_map == OSAL_NULL) {
1835 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1839 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1842 if (rel_cid >= p_map->max_count) {
1843 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1845 return ECORE_NORESOURCES;
1848 OSAL_SET_BIT(rel_cid, p_map->cid_map);
1850 *p_cid = rel_cid + p_map->start_cid;
1852 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1853 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1854 *p_cid, rel_cid, vfid, type);
1856 return ECORE_SUCCESS;
1859 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1860 enum protocol_type type,
1863 return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
1866 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1868 enum protocol_type *p_type,
1869 struct ecore_cid_acquired_map **pp_map)
1871 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1874 /* Iterate over protocols and find matching cid range */
1875 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1876 if (vfid == ECORE_CXT_PF_CID)
1877 *pp_map = &p_mngr->acquired[*p_type];
1879 *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1881 if (!((*pp_map)->cid_map))
1883 if (cid >= (*pp_map)->start_cid &&
1884 cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
1888 if (*p_type == MAX_CONN_TYPES) {
1889 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
1893 rel_cid = cid - (*pp_map)->start_cid;
1894 if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
1895 DP_NOTICE(p_hwfn, true,
1896 "CID %d [vifd %02x] not acquired", cid, vfid);
1902 *p_type = MAX_CONN_TYPES;
1903 *pp_map = OSAL_NULL;
1907 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
1909 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1910 enum protocol_type type;
1914 if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) {
1915 DP_NOTICE(p_hwfn, true,
1916 "Trying to return incorrect CID belonging to VF %02x\n",
1921 /* Test acquired and find matching per-protocol map */
1922 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
1928 rel_cid = cid - p_map->start_cid;
1929 OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
1931 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1932 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
1933 cid, rel_cid, vfid, type);
1936 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1938 _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
1941 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1942 struct ecore_cxt_info *p_info)
1944 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1945 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1946 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1947 enum protocol_type type;
1950 /* Test acquired and find matching per-protocol map */
1951 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
1958 /* set the protocl type */
1959 p_info->type = type;
1961 /* compute context virtual pointer */
1962 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1964 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1965 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1966 line = p_info->iid / cxts_per_p;
1968 /* Make sure context is allocated (dynamic allocation) */
1969 if (!p_mngr->ilt_shadow[line].p_virt)
1972 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1973 p_info->iid % cxts_per_p * conn_cxt_size;
1975 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1976 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1977 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1979 return ECORE_SUCCESS;
1982 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1984 /* Set the number of required CORE connections */
1985 u32 core_cids = 1; /* SPQ */
1987 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1989 switch (p_hwfn->hw_info.personality) {
1994 struct ecore_eth_pf_params *p_params =
1995 &p_hwfn->pf_params.eth_pf_params;
1997 if (!p_params->num_vf_cons)
1998 p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT;
1999 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2001 p_params->num_vf_cons);
2003 count = p_params->num_arfs_filters;
2005 if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS,
2006 &p_hwfn->p_dev->mf_bits))
2007 p_hwfn->p_cxt_mngr->arfs_count = count;
2015 return ECORE_SUCCESS;
2018 /* This function is very RoCE oriented, if another protocol in the future
2019 * will want this feature we'll need to modify the function to be more generic
2021 enum _ecore_status_t
2022 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2023 enum ecore_cxt_elem_type elem_type,
2026 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2027 struct ecore_ilt_client_cfg *p_cli;
2028 struct ecore_ilt_cli_blk *p_blk;
2029 struct ecore_ptt *p_ptt;
2033 enum _ecore_status_t rc = ECORE_SUCCESS;
2035 switch (elem_type) {
2036 case ECORE_ELEM_CXT:
2037 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2038 elem_size = CONN_CXT_SIZE(p_hwfn);
2039 p_blk = &p_cli->pf_blks[CDUC_BLK];
2041 case ECORE_ELEM_SRQ:
2042 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2043 elem_size = SRQ_CXT_SIZE;
2044 p_blk = &p_cli->pf_blks[SRQ_BLK];
2046 case ECORE_ELEM_TASK:
2047 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2048 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2049 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2052 DP_NOTICE(p_hwfn, false,
2053 "ECORE_INVALID elem type = %d", elem_type);
2057 /* Calculate line in ilt */
2058 hw_p_size = p_cli->p_size.val;
2059 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2060 line = p_blk->start_line + (iid / elems_per_p);
2061 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2063 /* If line is already allocated, do nothing, otherwise allocate it and
2064 * write it to the PSWRQ2 registers.
2065 * This section can be run in parallel from different contexts and thus
2066 * a mutex protection is needed.
2069 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2071 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2074 p_ptt = ecore_ptt_acquire(p_hwfn);
2076 DP_NOTICE(p_hwfn, false,
2077 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2082 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2084 p_blk->real_size_in_page);
2089 OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2091 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2092 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2093 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2094 p_blk->real_size_in_page;
2096 /* compute absolute offset */
2097 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2098 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2101 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2102 SET_FIELD(ilt_hw_entry,
2104 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2106 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2108 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2109 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2112 if (elem_type == ECORE_ELEM_CXT) {
2113 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2116 /* Update the relevant register in the parser */
2117 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2118 last_cid_allocated - 1);
2120 if (!p_hwfn->b_rdma_enabled_in_prs) {
2121 /* Enable RoCE search */
2122 ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2123 p_hwfn->b_rdma_enabled_in_prs = true;
2128 ecore_ptt_release(p_hwfn, p_ptt);
2130 OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2135 /* This function is very RoCE oriented, if another protocol in the future
2136 * will want this feature we'll need to modify the function to be more generic
2138 static enum _ecore_status_t
2139 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2140 enum ecore_cxt_elem_type elem_type,
2141 u32 start_iid, u32 count)
2143 u32 start_line, end_line, shadow_start_line, shadow_end_line;
2144 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2145 struct ecore_ilt_client_cfg *p_cli;
2146 struct ecore_ilt_cli_blk *p_blk;
2147 u32 end_iid = start_iid + count;
2148 struct ecore_ptt *p_ptt;
2149 u64 ilt_hw_entry = 0;
2152 switch (elem_type) {
2153 case ECORE_ELEM_CXT:
2154 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2155 elem_size = CONN_CXT_SIZE(p_hwfn);
2156 p_blk = &p_cli->pf_blks[CDUC_BLK];
2158 case ECORE_ELEM_SRQ:
2159 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2160 elem_size = SRQ_CXT_SIZE;
2161 p_blk = &p_cli->pf_blks[SRQ_BLK];
2163 case ECORE_ELEM_TASK:
2164 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2165 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2166 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2169 DP_NOTICE(p_hwfn, false,
2170 "ECORE_INVALID elem type = %d", elem_type);
2174 /* Calculate line in ilt */
2175 hw_p_size = p_cli->p_size.val;
2176 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2177 start_line = p_blk->start_line + (start_iid / elems_per_p);
2178 end_line = p_blk->start_line + (end_iid / elems_per_p);
2179 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2182 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2183 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2185 p_ptt = ecore_ptt_acquire(p_hwfn);
2187 DP_NOTICE(p_hwfn, false,
2188 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2189 return ECORE_TIMEOUT;
2192 for (i = shadow_start_line; i < shadow_end_line; i++) {
2193 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2196 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2197 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2198 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2199 p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2201 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2202 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2203 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2205 /* compute absolute offset */
2206 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2207 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2210 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2213 ecore_dmae_host2grc(p_hwfn, p_ptt,
2214 (u64)(osal_uintptr_t)&ilt_hw_entry,
2216 sizeof(ilt_hw_entry) / sizeof(u32),
2220 ecore_ptt_release(p_hwfn, p_ptt);
2222 return ECORE_SUCCESS;