2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "common_hsi.h"
12 #include "ecore_hsi_common.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_status.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_init_fw_funcs.h"
19 #include "ecore_cxt.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
23 #include "ecore_mcp.h"
25 /* Max number of connection types in HW (DQ/CDU etc.) */
26 #define MAX_CONN_TYPES PROTOCOLID_COMMON
27 #define NUM_TASK_TYPES 2
28 #define NUM_TASK_PF_SEGMENTS 4
29 #define NUM_TASK_VF_SEGMENTS 1
31 /* Doorbell-Queue constants */
32 #define DQ_RANGE_SHIFT 4
33 #define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT)
35 /* Searcher constants */
36 #define SRC_MIN_NUM_ELEMS 256
38 /* Timers constants */
40 #define TM_ALIGN (1 << TM_SHIFT)
41 #define TM_ELEM_SIZE 4
44 /* If for some reason, HW P size is modified to be less than 32K,
45 * special handling needs to be made for CDU initialization
47 #define ILT_DEFAULT_HW_P_SIZE 3
49 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
50 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
52 /* ILT entry structure */
53 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
54 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
55 #define ILT_ENTRY_VALID_MASK 0x1ULL
56 #define ILT_ENTRY_VALID_SHIFT 52
57 #define ILT_ENTRY_IN_REGS 2
58 #define ILT_REG_SIZE_IN_BYTES 4
60 /* connection context union */
62 struct core_conn_context core_ctx;
63 struct eth_conn_context eth_ctx;
66 /* TYPE-0 task context - iSCSI, FCOE */
67 union type0_task_context {
70 /* TYPE-1 task context - ROCE */
71 union type1_task_context {
79 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
80 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
82 #define CONN_CXT_SIZE(p_hwfn) \
83 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
85 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
87 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
88 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
90 /* Alignment is inherent to the type1_task_context structure */
91 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
93 /* PF per protocl configuration object */
94 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
95 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
97 struct ecore_tid_seg {
103 struct ecore_conn_type_cfg {
106 struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
109 /* ILT Client configuration,
110 * Per connection type (protocol) resources (cids, tis, vf cids etc.)
111 * 1 - for connection context (CDUC) and for each task context we need two
112 * values, for regular task context and for force load memory
114 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
115 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
118 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
119 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS)
131 struct ilt_cfg_pair {
136 struct ecore_ilt_cli_blk {
137 u32 total_size; /* 0 means not active */
138 u32 real_size_in_page;
140 u32 dynamic_line_cnt;
143 struct ecore_ilt_client_cfg {
147 struct ilt_cfg_pair first;
148 struct ilt_cfg_pair last;
149 struct ilt_cfg_pair p_size;
151 /* ILT client blocks for PF */
152 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
155 /* ILT client blocks for VFs */
156 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
162 * Protocol acquired CID lists
163 * PF start line in ILT
165 struct ecore_dma_mem {
171 #define MAP_WORD_SIZE sizeof(unsigned long)
172 #define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8)
174 struct ecore_cid_acquired_map {
177 unsigned long *cid_map;
180 struct ecore_cxt_mngr {
181 /* Per protocl configuration */
182 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
184 /* computed ILT structure */
185 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
187 /* Task type sizes */
188 u32 task_type_size[NUM_TASK_TYPES];
190 /* total number of VFs for this hwfn -
191 * ALL VFs are symmetric in terms of HW resources
196 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
197 /* TBD - do we want this allocated to reserve space? */
198 struct ecore_cid_acquired_map
199 acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS];
201 /* ILT shadow table */
202 struct ecore_dma_mem *ilt_shadow;
205 /* Mutex for a dynamic ILT allocation */
209 struct ecore_dma_mem *t2;
214 /* The infrastructure originally was very generic and context/task
215 * oriented - per connection-type we would set how many of those
216 * are needed, and later when determining how much memory we're
217 * needing for a given block we'd iterate over all the relevant
219 * But since then we've had some additional resources, some of which
220 * require memory which is indepent of the general context/task
221 * scheme. We add those here explicitly per-feature.
224 /* total number of SRQ's for this hwfn */
227 /* Maximal number of L2 steering filters */
230 /* TODO - VF arfs filters ? */
233 /* check if resources/configuration is required according to protocol type */
234 static OSAL_INLINE bool src_proto(struct ecore_hwfn *p_hwfn,
235 enum protocol_type type)
237 return type == PROTOCOLID_TOE;
240 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
242 return type == PROTOCOLID_TOE;
245 static bool tm_tid_proto(enum protocol_type type)
247 return type == PROTOCOLID_FCOE;
250 /* counts the iids for the CDU/CDUC ILT client configuration */
251 struct ecore_cdu_iids {
256 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
257 struct ecore_cdu_iids *iids)
261 for (type = 0; type < MAX_CONN_TYPES; type++) {
262 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
263 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
267 /* counts the iids for the Searcher block configuration */
268 struct ecore_src_iids {
273 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_hwfn *p_hwfn,
274 struct ecore_cxt_mngr *p_mngr,
275 struct ecore_src_iids *iids)
279 for (i = 0; i < MAX_CONN_TYPES; i++) {
280 if (!src_proto(p_hwfn, i))
283 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
284 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
287 /* Add L2 filtering filters in addition */
288 iids->pf_cids += p_mngr->arfs_count;
291 /* counts the iids for the Timers block configuration */
292 struct ecore_tm_iids {
294 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
300 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
301 struct ecore_tm_iids *iids)
303 bool tm_vf_required = false;
304 bool tm_required = false;
307 for (i = 0; i < MAX_CONN_TYPES; i++) {
308 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
310 if (tm_cid_proto(i) || tm_required) {
311 if (p_cfg->cid_count)
314 iids->pf_cids += p_cfg->cid_count;
317 if (tm_cid_proto(i) || tm_vf_required) {
318 if (p_cfg->cids_per_vf)
319 tm_vf_required = true;
323 if (tm_tid_proto(i)) {
324 struct ecore_tid_seg *segs = p_cfg->tid_seg;
326 /* for each segment there is at most one
327 * protocol for which count is not 0.
329 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
330 iids->pf_tids[j] += segs[j].count;
332 /* The last array elelment is for the VFs. As for PF
333 * segments there can be only one protocol for
334 * which this value is not 0.
336 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
340 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
341 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
342 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
344 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
345 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
346 iids->pf_tids_total += iids->pf_tids[j];
350 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
351 struct ecore_qm_iids *iids)
353 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
354 struct ecore_tid_seg *segs;
355 u32 vf_cids = 0, type, j;
358 for (type = 0; type < MAX_CONN_TYPES; type++) {
359 iids->cids += p_mngr->conn_cfg[type].cid_count;
360 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
362 segs = p_mngr->conn_cfg[type].tid_seg;
363 /* for each segment there is at most one
364 * protocol for which count is not 0.
366 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
367 iids->tids += segs[j].count;
369 /* The last array elelment is for the VFs. As for PF
370 * segments there can be only one protocol for
371 * which this value is not 0.
373 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
376 iids->vf_cids += vf_cids * p_mngr->vf_count;
377 iids->tids += vf_tids * p_mngr->vf_count;
379 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
380 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
381 iids->cids, iids->vf_cids, iids->tids, vf_tids);
384 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
387 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
390 /* Find the protocol with tid count > 0 for this segment.
391 * Note: there can only be one and this is already validated.
393 for (i = 0; i < MAX_CONN_TYPES; i++) {
394 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
395 return &p_cfg->conn_cfg[i].tid_seg[seg];
400 /* set the iids (cid/tid) count per protocol */
401 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
402 enum protocol_type type,
403 u32 cid_count, u32 vf_cid_cnt)
405 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
406 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
408 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
409 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
412 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
413 enum protocol_type type, u32 *vf_cid)
416 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
418 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
421 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
422 enum protocol_type type)
424 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
427 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
428 enum protocol_type type)
433 for (i = 0; i < TASK_SEGMENTS; i++)
434 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
439 static OSAL_INLINE void
440 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
441 enum protocol_type proto,
442 u8 seg, u8 seg_type, u32 count, bool has_fl)
444 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
445 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
447 p_seg->count = count;
448 p_seg->has_fl_mem = has_fl;
449 p_seg->type = seg_type;
452 /* the *p_line parameter must be either 0 for the first invocation or the
453 * value returned in the previous invocation.
455 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
456 struct ecore_ilt_cli_blk *p_blk,
458 u32 total_size, u32 elem_size)
460 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
462 /* verify that it's called once for each block */
463 if (p_blk->total_size)
466 p_blk->total_size = total_size;
467 p_blk->real_size_in_page = 0;
469 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
470 p_blk->start_line = start_line;
473 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
474 struct ecore_ilt_client_cfg *p_cli,
475 struct ecore_ilt_cli_blk *p_blk,
476 u32 *p_line, enum ilt_clients client_id)
478 if (!p_blk->total_size)
482 p_cli->first.val = *p_line;
484 p_cli->active = true;
485 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
486 p_cli->last.val = *p_line - 1;
488 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
489 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
490 " [Real %08x] Start line %d\n",
491 client_id, p_cli->first.val, p_cli->last.val,
492 p_blk->total_size, p_blk->real_size_in_page,
496 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
497 enum ilt_clients ilt_client)
499 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
500 struct ecore_ilt_client_cfg *p_cli;
501 u32 lines_to_skip = 0;
504 /* TBD MK: ILT code should be simplified once PROTO enum is changed */
506 if (ilt_client == ILT_CLI_CDUC) {
507 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
509 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
510 (u32)CONN_CXT_SIZE(p_hwfn);
512 lines_to_skip = cid_count / cxts_per_p;
515 return lines_to_skip;
518 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
520 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
521 u32 curr_line, total, i, task_size, line;
522 struct ecore_ilt_client_cfg *p_cli;
523 struct ecore_ilt_cli_blk *p_blk;
524 struct ecore_cdu_iids cdu_iids;
525 struct ecore_src_iids src_iids;
526 struct ecore_qm_iids qm_iids;
527 struct ecore_tm_iids tm_iids;
528 struct ecore_tid_seg *p_seg;
530 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
531 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
532 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
533 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
535 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
537 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
538 "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
539 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
542 p_cli = &p_mngr->clients[ILT_CLI_CDUC];
544 curr_line = p_mngr->pf_start_line;
547 p_cli->pf_total_lines = 0;
549 /* get the counters for the CDUC,CDUC and QM clients */
550 ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
552 p_blk = &p_cli->pf_blks[CDUC_BLK];
554 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
556 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
557 total, CONN_CXT_SIZE(p_hwfn));
559 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
560 p_cli->pf_total_lines = curr_line - p_blk->start_line;
562 p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
566 p_blk = &p_cli->vf_blks[CDUC_BLK];
567 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
569 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
570 total, CONN_CXT_SIZE(p_hwfn));
572 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
573 p_cli->vf_total_lines = curr_line - p_blk->start_line;
575 for (i = 1; i < p_mngr->vf_count; i++)
576 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
580 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
581 p_cli->first.val = curr_line;
583 /* first the 'working' task memory */
584 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
585 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
586 if (!p_seg || p_seg->count == 0)
589 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
590 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
591 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
592 p_mngr->task_type_size[p_seg->type]);
594 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
598 /* next the 'init' task memory (forced load memory) */
599 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
600 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
601 if (!p_seg || p_seg->count == 0)
604 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
606 if (!p_seg->has_fl_mem) {
607 /* The segment is active (total size pf 'working'
608 * memory is > 0) but has no FL (forced-load, Init)
611 * 1. The total-size in the corrsponding FL block of
612 * the ILT client is set to 0 - No ILT line are
613 * provisioned and no ILT memory allocated.
615 * 2. The start-line of said block is set to the
616 * start line of the matching working memory
617 * block in the ILT client. This is later used to
618 * configure the CDU segment offset registers and
619 * results in an FL command for TIDs of this
620 * segment behaves as regular load commands
621 * (loading TIDs from the working memory).
623 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
625 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
628 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
630 ecore_ilt_cli_blk_fill(p_cli, p_blk,
632 p_mngr->task_type_size[p_seg->type]);
634 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
637 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
640 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
641 if (p_seg && p_seg->count) {
642 /* Stricly speaking we need to iterate over all VF
643 * task segment types, but a VF has only 1 segment
646 /* 'working' memory */
647 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
649 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
650 ecore_ilt_cli_blk_fill(p_cli, p_blk,
652 p_mngr->task_type_size[p_seg->type]);
654 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
658 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
659 if (!p_seg->has_fl_mem) {
660 /* see comment above */
661 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
662 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
664 task_size = p_mngr->task_type_size[p_seg->type];
665 ecore_ilt_cli_blk_fill(p_cli, p_blk,
666 curr_line, total, task_size);
667 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
670 p_cli->vf_total_lines = curr_line -
671 p_cli->vf_blks[0].start_line;
673 /* Now for the rest of the VFs */
674 for (i = 1; i < p_mngr->vf_count; i++) {
675 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
676 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
679 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
680 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
686 p_cli = &p_mngr->clients[ILT_CLI_QM];
687 p_blk = &p_cli->pf_blks[0];
689 ecore_cxt_qm_iids(p_hwfn, &qm_iids);
690 total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
691 qm_iids.vf_cids, qm_iids.tids,
692 p_hwfn->qm_info.num_pqs,
693 p_hwfn->qm_info.num_vf_pqs);
695 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
696 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
697 " num_vf_pqs=%d, memory_size=%d)\n",
698 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
699 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
701 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
704 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
705 p_cli->pf_total_lines = curr_line - p_blk->start_line;
708 p_cli = &p_mngr->clients[ILT_CLI_SRC];
709 ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids);
711 /* Both the PF and VFs searcher connections are stored in the per PF
712 * database. Thus sum the PF searcher cids and all the VFs searcher
715 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
717 u32 local_max = OSAL_MAX_T(u32, total,
720 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
722 p_blk = &p_cli->pf_blks[0];
723 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
724 total * sizeof(struct src_ent),
725 sizeof(struct src_ent));
727 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
729 p_cli->pf_total_lines = curr_line - p_blk->start_line;
733 p_cli = &p_mngr->clients[ILT_CLI_TM];
734 ecore_cxt_tm_iids(p_mngr, &tm_iids);
735 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
737 p_blk = &p_cli->pf_blks[0];
738 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
739 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
741 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
743 p_cli->pf_total_lines = curr_line - p_blk->start_line;
747 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
749 p_blk = &p_cli->vf_blks[0];
750 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
751 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
753 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
756 p_cli->vf_total_lines = curr_line - p_blk->start_line;
757 for (i = 1; i < p_mngr->vf_count; i++) {
758 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
763 /* TSDM (SRQ CONTEXT) */
764 total = ecore_cxt_get_srq_count(p_hwfn);
767 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
768 p_blk = &p_cli->pf_blks[SRQ_BLK];
769 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
770 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
772 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
774 p_cli->pf_total_lines = curr_line - p_blk->start_line;
777 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
778 RESC_NUM(p_hwfn, ECORE_ILT)) {
779 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
780 curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
784 return ECORE_SUCCESS;
787 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
789 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
795 for (i = 0; i < p_mngr->t2_num_pages; i++)
796 if (p_mngr->t2[i].p_virt)
797 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
798 p_mngr->t2[i].p_virt,
799 p_mngr->t2[i].p_phys,
802 OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
805 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
807 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
808 u32 conn_num, total_size, ent_per_page, psz, i;
809 struct ecore_ilt_client_cfg *p_src;
810 struct ecore_src_iids src_iids;
811 struct ecore_dma_mem *p_t2;
812 enum _ecore_status_t rc;
814 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
816 /* if the SRC ILT client is inactive - there are no connection
817 * requiring the searcer, leave.
819 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
821 return ECORE_SUCCESS;
823 ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids);
824 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
825 total_size = conn_num * sizeof(struct src_ent);
827 /* use the same page size as the SRC ILT client */
828 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
829 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
832 p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
833 p_mngr->t2_num_pages *
834 sizeof(struct ecore_dma_mem));
836 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
841 /* allocate t2 pages */
842 for (i = 0; i < p_mngr->t2_num_pages; i++) {
843 u32 size = OSAL_MIN_T(u32, total_size, psz);
844 void **p_virt = &p_mngr->t2[i].p_virt;
846 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
847 &p_mngr->t2[i].p_phys, size);
848 if (!p_mngr->t2[i].p_virt) {
852 OSAL_MEM_ZERO(*p_virt, size);
853 p_mngr->t2[i].size = size;
857 /* Set the t2 pointers */
859 /* entries per page - must be a power of two */
860 ent_per_page = psz / sizeof(struct src_ent);
862 p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
864 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
865 p_mngr->last_free = (u64)p_t2->p_phys +
866 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
868 for (i = 0; i < p_mngr->t2_num_pages; i++) {
869 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
870 struct src_ent *entries = p_mngr->t2[i].p_virt;
871 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
874 for (j = 0; j < ent_num - 1; j++) {
875 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
876 entries[j].next = OSAL_CPU_TO_BE64(val);
879 if (i < p_mngr->t2_num_pages - 1)
880 val = (u64)p_mngr->t2[i + 1].p_phys;
883 entries[j].next = OSAL_CPU_TO_BE64(val);
888 return ECORE_SUCCESS;
891 ecore_cxt_src_t2_free(p_hwfn);
895 #define for_each_ilt_valid_client(pos, clients) \
896 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
897 if (!clients[pos].active) { \
902 /* Total number of ILT lines used by this PF */
903 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
908 for_each_ilt_valid_client(i, ilt_clients)
909 size += (ilt_clients[i].last.val -
910 ilt_clients[i].first.val + 1);
915 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
917 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
918 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
921 ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
923 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
924 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
927 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
929 p_dma->p_phys, p_dma->size);
930 p_dma->p_virt = OSAL_NULL;
932 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
935 static enum _ecore_status_t
936 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
937 struct ecore_ilt_cli_blk *p_blk,
938 enum ilt_clients ilt_client, u32 start_line_offset)
940 struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
941 u32 lines, line, sz_left, lines_to_skip = 0;
943 /* Special handling for RoCE that supports dynamic allocation */
944 if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
945 return ECORE_SUCCESS;
947 lines_to_skip = p_blk->dynamic_line_cnt;
949 if (!p_blk->total_size)
950 return ECORE_SUCCESS;
952 sz_left = p_blk->total_size;
953 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
954 line = p_blk->start_line + start_line_offset -
955 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
957 for (; lines; lines--) {
962 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
965 #define ILT_BLOCK_ALIGN_SIZE 0x1000
966 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
968 ILT_BLOCK_ALIGN_SIZE);
971 OSAL_MEM_ZERO(p_virt, size);
973 ilt_shadow[line].p_phys = p_phys;
974 ilt_shadow[line].p_virt = p_virt;
975 ilt_shadow[line].size = size;
977 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
978 "ILT shadow: Line [%d] Physical 0x%lx"
979 " Virtual %p Size %d\n",
980 line, (unsigned long)p_phys, p_virt, size);
986 return ECORE_SUCCESS;
989 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
991 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
992 struct ecore_ilt_client_cfg *clients = p_mngr->clients;
993 struct ecore_ilt_cli_blk *p_blk;
995 enum _ecore_status_t rc;
997 size = ecore_cxt_ilt_shadow_size(clients);
998 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
999 size * sizeof(struct ecore_dma_mem));
1001 if (!p_mngr->ilt_shadow) {
1002 DP_NOTICE(p_hwfn, true,
1003 "Failed to allocate ilt shadow table\n");
1005 goto ilt_shadow_fail;
1008 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1009 "Allocated 0x%x bytes for ilt shadow\n",
1010 (u32)(size * sizeof(struct ecore_dma_mem)));
1012 for_each_ilt_valid_client(i, clients) {
1013 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1014 p_blk = &clients[i].pf_blks[j];
1015 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1016 if (rc != ECORE_SUCCESS)
1017 goto ilt_shadow_fail;
1019 for (k = 0; k < p_mngr->vf_count; k++) {
1020 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1021 u32 lines = clients[i].vf_total_lines * k;
1023 p_blk = &clients[i].vf_blks[j];
1024 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1026 if (rc != ECORE_SUCCESS)
1027 goto ilt_shadow_fail;
1032 return ECORE_SUCCESS;
1035 ecore_ilt_shadow_free(p_hwfn);
1039 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1041 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1044 for (type = 0; type < MAX_CONN_TYPES; type++) {
1045 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1046 p_mngr->acquired[type].max_count = 0;
1047 p_mngr->acquired[type].start_cid = 0;
1049 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1050 OSAL_FREE(p_hwfn->p_dev,
1051 p_mngr->acquired_vf[type][vf].cid_map);
1052 p_mngr->acquired_vf[type][vf].max_count = 0;
1053 p_mngr->acquired_vf[type][vf].start_cid = 0;
1058 static enum _ecore_status_t
1059 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1060 u32 cid_start, u32 cid_count,
1061 struct ecore_cid_acquired_map *p_map)
1066 return ECORE_SUCCESS;
1068 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1069 p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1070 if (p_map->cid_map == OSAL_NULL)
1073 p_map->max_count = cid_count;
1074 p_map->start_cid = cid_start;
1076 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1077 "Type %08x start: %08x count %08x\n",
1078 type, p_map->start_cid, p_map->max_count);
1080 return ECORE_SUCCESS;
1083 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1085 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1086 u32 start_cid = 0, vf_start_cid = 0;
1089 for (type = 0; type < MAX_CONN_TYPES; type++) {
1090 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1091 struct ecore_cid_acquired_map *p_map;
1093 /* Handle PF maps */
1094 p_map = &p_mngr->acquired[type];
1095 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1096 p_cfg->cid_count, p_map))
1099 /* Handle VF maps */
1100 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1101 p_map = &p_mngr->acquired_vf[type][vf];
1102 if (ecore_cid_map_alloc_single(p_hwfn, type,
1109 start_cid += p_cfg->cid_count;
1110 vf_start_cid += p_cfg->cids_per_vf;
1113 return ECORE_SUCCESS;
1116 ecore_cid_map_free(p_hwfn);
1120 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1122 struct ecore_ilt_client_cfg *clients;
1123 struct ecore_cxt_mngr *p_mngr;
1126 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1128 DP_NOTICE(p_hwfn, true,
1129 "Failed to allocate `struct ecore_cxt_mngr'\n");
1133 /* Initialize ILT client registers */
1134 clients = p_mngr->clients;
1135 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1136 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1137 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1139 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1140 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1141 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1143 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1144 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1145 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1147 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1148 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1149 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1151 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1152 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1153 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1155 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1156 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1157 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1159 /* default ILT page size for all clients is 32K */
1160 for (i = 0; i < ILT_CLI_MAX; i++)
1161 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1163 /* due to removal of ISCSI/FCoE files union type0_task_context
1164 * task_type_size will be 0. So hardcoded for now.
1166 p_mngr->task_type_size[0] = 512; /* @DPDK */
1167 p_mngr->task_type_size[1] = 128; /* @DPDK */
1169 if (p_hwfn->p_dev->p_iov_info)
1170 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1172 /* Initialize the dynamic ILT allocation mutex */
1173 OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1174 OSAL_MUTEX_INIT(&p_mngr->mutex);
1176 /* Set the cxt mangr pointer priori to further allocations */
1177 p_hwfn->p_cxt_mngr = p_mngr;
1179 return ECORE_SUCCESS;
1182 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1184 enum _ecore_status_t rc;
1186 /* Allocate the ILT shadow table */
1187 rc = ecore_ilt_shadow_alloc(p_hwfn);
1189 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1190 goto tables_alloc_fail;
1193 /* Allocate the T2 table */
1194 rc = ecore_cxt_src_t2_alloc(p_hwfn);
1196 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1197 goto tables_alloc_fail;
1200 /* Allocate and initialize the acquired cids bitmaps */
1201 rc = ecore_cid_map_alloc(p_hwfn);
1203 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1204 goto tables_alloc_fail;
1207 return ECORE_SUCCESS;
1210 ecore_cxt_mngr_free(p_hwfn);
1214 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1216 if (!p_hwfn->p_cxt_mngr)
1219 ecore_cid_map_free(p_hwfn);
1220 ecore_cxt_src_t2_free(p_hwfn);
1221 ecore_ilt_shadow_free(p_hwfn);
1222 OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1223 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1226 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1228 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1229 struct ecore_cid_acquired_map *p_map;
1230 struct ecore_conn_type_cfg *p_cfg;
1234 /* Reset acquired cids */
1235 for (type = 0; type < MAX_CONN_TYPES; type++) {
1238 p_cfg = &p_mngr->conn_cfg[type];
1239 if (p_cfg->cid_count) {
1240 p_map = &p_mngr->acquired[type];
1241 len = DIV_ROUND_UP(p_map->max_count,
1242 BITS_PER_MAP_WORD) *
1244 OSAL_MEM_ZERO(p_map->cid_map, len);
1247 if (!p_cfg->cids_per_vf)
1250 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1251 p_map = &p_mngr->acquired_vf[type][vf];
1252 len = DIV_ROUND_UP(p_map->max_count,
1253 BITS_PER_MAP_WORD) *
1255 OSAL_MEM_ZERO(p_map->cid_map, len);
1260 /* HW initialization helper (per Block, per phase) */
1263 #define CDUC_CXT_SIZE_SHIFT \
1264 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1266 #define CDUC_CXT_SIZE_MASK \
1267 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1269 #define CDUC_BLOCK_WASTE_SHIFT \
1270 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1272 #define CDUC_BLOCK_WASTE_MASK \
1273 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1275 #define CDUC_NCIB_SHIFT \
1276 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1278 #define CDUC_NCIB_MASK \
1279 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1281 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1282 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1284 #define CDUT_TYPE0_CXT_SIZE_MASK \
1285 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1286 CDUT_TYPE0_CXT_SIZE_SHIFT)
1288 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1289 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1291 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1292 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1293 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1295 #define CDUT_TYPE0_NCIB_SHIFT \
1296 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1298 #define CDUT_TYPE0_NCIB_MASK \
1299 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1300 CDUT_TYPE0_NCIB_SHIFT)
1302 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1303 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1305 #define CDUT_TYPE1_CXT_SIZE_MASK \
1306 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1307 CDUT_TYPE1_CXT_SIZE_SHIFT)
1309 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1310 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1312 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1313 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1314 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1316 #define CDUT_TYPE1_NCIB_SHIFT \
1317 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1319 #define CDUT_TYPE1_NCIB_MASK \
1320 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1321 CDUT_TYPE1_NCIB_SHIFT)
1323 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1325 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1327 /* CDUC - connection configuration */
1328 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1329 cxt_size = CONN_CXT_SIZE(p_hwfn);
1330 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1331 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1333 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1334 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1335 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1336 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1338 /* CDUT - type-0 tasks configuration */
1339 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1340 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1341 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1342 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1344 /* cxt size and block-waste are multipes of 8 */
1346 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1347 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1348 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1349 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1351 /* CDUT - type-1 tasks configuration */
1352 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1353 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1354 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1356 /* cxt size and block-waste are multipes of 8 */
1358 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1359 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1360 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1361 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1365 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1366 #define CDU_SEG_REG_TYPE_MASK 0x1
1367 #define CDU_SEG_REG_OFFSET_SHIFT 0
1368 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1370 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1372 struct ecore_ilt_client_cfg *p_cli;
1373 struct ecore_tid_seg *p_seg;
1374 u32 cdu_seg_params, offset;
1377 static const u32 rt_type_offset_arr[] = {
1378 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1379 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1380 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1381 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1384 static const u32 rt_type_offset_fl_arr[] = {
1385 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1386 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1387 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1388 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1391 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1393 /* There are initializations only for CDUT during pf Phase */
1394 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1396 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1400 /* Note: start_line is already adjusted for the CDU
1401 * segment register granularity, so we just need to
1402 * divide. Adjustment is implicit as we assume ILT
1403 * Page size is larger than 32K!
1405 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1406 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1407 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1410 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1411 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1412 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1414 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1415 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1416 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1419 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1420 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1421 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1425 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1427 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1428 struct ecore_qm_iids iids;
1430 OSAL_MEM_ZERO(&iids, sizeof(iids));
1431 ecore_cxt_qm_iids(p_hwfn, &iids);
1433 ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1434 p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1435 p_hwfn->first_on_engine,
1436 iids.cids, iids.vf_cids, iids.tids,
1438 qm_info->num_pqs - qm_info->num_vf_pqs,
1439 qm_info->num_vf_pqs,
1440 qm_info->start_vport,
1441 qm_info->num_vports, qm_info->pf_wfq,
1442 qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1443 p_hwfn->qm_info.qm_vport_params);
1447 void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1449 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1450 ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1454 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1456 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1457 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1459 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1460 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1462 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1463 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1465 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1466 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1468 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1469 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1471 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1472 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1474 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1475 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1477 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1478 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1480 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1481 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1483 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1484 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1486 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1487 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1489 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1490 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1492 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1493 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1495 /* Connection types 6 & 7 are not in use, yet they must be configured
1496 * as the highest possible connection. Not configuring them means the
1497 * defaults will be used, and with a large number of cids a bug may
1498 * occur, if the defaults will be smaller than dq_pf_max_cid /
1501 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1502 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1504 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1505 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1508 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1510 struct ecore_ilt_client_cfg *ilt_clients;
1513 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1514 for_each_ilt_valid_client(i, ilt_clients) {
1515 STORE_RT_REG(p_hwfn,
1516 ilt_clients[i].first.reg,
1517 ilt_clients[i].first.val);
1518 STORE_RT_REG(p_hwfn,
1519 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1520 STORE_RT_REG(p_hwfn,
1521 ilt_clients[i].p_size.reg,
1522 ilt_clients[i].p_size.val);
1526 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1528 struct ecore_ilt_client_cfg *p_cli;
1531 /* For simplicty we set the 'block' to be an ILT page */
1532 if (p_hwfn->p_dev->p_iov_info) {
1533 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1535 STORE_RT_REG(p_hwfn,
1536 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1537 p_iov->first_vf_in_pf);
1538 STORE_RT_REG(p_hwfn,
1539 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1540 p_iov->first_vf_in_pf + p_iov->total_vfs);
1543 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1544 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1545 if (p_cli->active) {
1546 STORE_RT_REG(p_hwfn,
1547 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1549 STORE_RT_REG(p_hwfn,
1550 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1551 p_cli->pf_total_lines);
1552 STORE_RT_REG(p_hwfn,
1553 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1554 p_cli->vf_total_lines);
1557 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1558 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1559 if (p_cli->active) {
1560 STORE_RT_REG(p_hwfn,
1561 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1563 STORE_RT_REG(p_hwfn,
1564 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1565 p_cli->pf_total_lines);
1566 STORE_RT_REG(p_hwfn,
1567 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1568 p_cli->vf_total_lines);
1571 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1572 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1573 if (p_cli->active) {
1574 STORE_RT_REG(p_hwfn,
1575 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1576 STORE_RT_REG(p_hwfn,
1577 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1578 p_cli->pf_total_lines);
1579 STORE_RT_REG(p_hwfn,
1580 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1581 p_cli->vf_total_lines);
1585 /* ILT (PSWRQ2) PF */
1586 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1588 struct ecore_ilt_client_cfg *clients;
1589 struct ecore_cxt_mngr *p_mngr;
1590 struct ecore_dma_mem *p_shdw;
1591 u32 line, rt_offst, i;
1593 ecore_ilt_bounds_init(p_hwfn);
1594 ecore_ilt_vf_bounds_init(p_hwfn);
1596 p_mngr = p_hwfn->p_cxt_mngr;
1597 p_shdw = p_mngr->ilt_shadow;
1598 clients = p_hwfn->p_cxt_mngr->clients;
1600 for_each_ilt_valid_client(i, clients) {
1601 /* Client's 1st val and RT array are absolute, ILT shadows'
1602 * lines are relative.
1604 line = clients[i].first.val - p_mngr->pf_start_line;
1605 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1606 clients[i].first.val * ILT_ENTRY_IN_REGS;
1608 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1609 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1610 u64 ilt_hw_entry = 0;
1612 /** p_virt could be OSAL_NULL incase of dynamic
1615 if (p_shdw[line].p_virt != OSAL_NULL) {
1616 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1617 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1618 (p_shdw[line].p_phys >> 12));
1620 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1621 "Setting RT[0x%08x] from"
1622 " ILT[0x%08x] [Client is %d] to"
1623 " Physical addr: 0x%lx\n",
1625 (unsigned long)(p_shdw[line].
1629 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1634 /* SRC (Searcher) PF */
1635 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1637 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1638 u32 rounded_conn_num, conn_num, conn_max;
1639 struct ecore_src_iids src_iids;
1641 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1642 ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids);
1643 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1647 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1648 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1650 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1651 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1652 OSAL_LOG2(rounded_conn_num));
1654 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1655 p_hwfn->p_cxt_mngr->first_free);
1656 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1657 p_hwfn->p_cxt_mngr->last_free);
1658 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1659 "Configured SEARCHER for 0x%08x connections\n",
1664 #define TM_CFG_NUM_IDS_SHIFT 0
1665 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1666 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1667 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1668 #define TM_CFG_PARENT_PF_SHIFT 25
1669 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1671 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1672 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1674 #define TM_CFG_TID_OFFSET_SHIFT 30
1675 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1676 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1677 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1679 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1681 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1682 u32 active_seg_mask = 0, tm_offset, rt_reg;
1683 struct ecore_tm_iids tm_iids;
1687 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1688 ecore_cxt_tm_iids(p_mngr, &tm_iids);
1690 /* @@@TBD No pre-scan for now */
1692 /* Note: We assume consecutive VFs for a PF */
1693 for (i = 0; i < p_mngr->vf_count; i++) {
1695 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1696 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1697 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1698 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1700 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1701 (sizeof(cfg_word) / sizeof(u32)) *
1702 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1703 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1707 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1708 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1709 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1710 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1712 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1713 (sizeof(cfg_word) / sizeof(u32)) *
1714 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1715 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1718 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1719 tm_iids.pf_cids ? 0x1 : 0x0);
1721 /* @@@TBD how to enable the scan for the VFs */
1723 tm_offset = tm_iids.per_vf_cids;
1725 /* Note: We assume consecutive VFs for a PF */
1726 for (i = 0; i < p_mngr->vf_count; i++) {
1728 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1729 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1730 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1731 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1732 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1734 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1735 (sizeof(cfg_word) / sizeof(u32)) *
1736 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1738 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1741 tm_offset = tm_iids.pf_cids;
1742 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1744 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1745 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1746 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1747 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1748 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1750 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1751 (sizeof(cfg_word) / sizeof(u32)) *
1752 (NUM_OF_VFS(p_hwfn->p_dev) +
1753 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1755 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1756 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1758 tm_offset += tm_iids.pf_tids[i];
1761 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1763 /* @@@TBD how to enable the scan for the VFs */
1766 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1768 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1769 struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1770 struct ecore_tid_seg *p_tid;
1772 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1773 if (!p_fcoe->cid_count)
1776 p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1777 STORE_RT_REG_AGG(p_hwfn,
1778 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1782 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1784 /* CDU configuration */
1785 ecore_cdu_init_common(p_hwfn);
1788 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1790 ecore_qm_init_pf(p_hwfn);
1791 ecore_cm_init_pf(p_hwfn);
1792 ecore_dq_init_pf(p_hwfn);
1793 ecore_cdu_init_pf(p_hwfn);
1794 ecore_ilt_init_pf(p_hwfn);
1795 ecore_src_init_pf(p_hwfn);
1796 ecore_tm_init_pf(p_hwfn);
1797 ecore_prs_init_pf(p_hwfn);
1800 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1801 enum protocol_type type,
1802 u32 *p_cid, u8 vfid)
1804 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1805 struct ecore_cid_acquired_map *p_map;
1808 if (type >= MAX_CONN_TYPES) {
1809 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1813 if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) {
1814 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1818 /* Determine the right map to take this CID from */
1819 if (vfid == ECORE_CXT_PF_CID)
1820 p_map = &p_mngr->acquired[type];
1822 p_map = &p_mngr->acquired_vf[type][vfid];
1824 if (p_map->cid_map == OSAL_NULL) {
1825 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1829 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1832 if (rel_cid >= p_map->max_count) {
1833 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1835 return ECORE_NORESOURCES;
1838 OSAL_SET_BIT(rel_cid, p_map->cid_map);
1840 *p_cid = rel_cid + p_map->start_cid;
1842 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1843 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1844 *p_cid, rel_cid, vfid, type);
1846 return ECORE_SUCCESS;
1849 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1850 enum protocol_type type,
1853 return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
1856 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1858 enum protocol_type *p_type,
1859 struct ecore_cid_acquired_map **pp_map)
1861 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1864 /* Iterate over protocols and find matching cid range */
1865 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1866 if (vfid == ECORE_CXT_PF_CID)
1867 *pp_map = &p_mngr->acquired[*p_type];
1869 *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1871 if (!((*pp_map)->cid_map))
1873 if (cid >= (*pp_map)->start_cid &&
1874 cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
1878 if (*p_type == MAX_CONN_TYPES) {
1879 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
1883 rel_cid = cid - (*pp_map)->start_cid;
1884 if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
1885 DP_NOTICE(p_hwfn, true,
1886 "CID %d [vifd %02x] not acquired", cid, vfid);
1892 *p_type = MAX_CONN_TYPES;
1893 *pp_map = OSAL_NULL;
1897 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
1899 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1900 enum protocol_type type;
1904 if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) {
1905 DP_NOTICE(p_hwfn, true,
1906 "Trying to return incorrect CID belonging to VF %02x\n",
1911 /* Test acquired and find matching per-protocol map */
1912 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
1918 rel_cid = cid - p_map->start_cid;
1919 OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
1921 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1922 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
1923 cid, rel_cid, vfid, type);
1926 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1928 _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
1931 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1932 struct ecore_cxt_info *p_info)
1934 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1935 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1936 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1937 enum protocol_type type;
1940 /* Test acquired and find matching per-protocol map */
1941 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
1948 /* set the protocl type */
1949 p_info->type = type;
1951 /* compute context virtual pointer */
1952 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1954 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1955 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1956 line = p_info->iid / cxts_per_p;
1958 /* Make sure context is allocated (dynamic allocation) */
1959 if (!p_mngr->ilt_shadow[line].p_virt)
1962 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1963 p_info->iid % cxts_per_p * conn_cxt_size;
1965 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1966 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1967 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1969 return ECORE_SUCCESS;
1972 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
1974 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1976 p_mgr->srq_count = num_srqs;
1979 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
1981 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1983 return p_mgr->srq_count;
1986 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1988 /* Set the number of required CORE connections */
1989 u32 core_cids = 1; /* SPQ */
1991 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1993 switch (p_hwfn->hw_info.personality) {
1996 struct ecore_eth_pf_params *p_params =
1997 &p_hwfn->pf_params.eth_pf_params;
1999 /* TODO - we probably want to add VF number to the PF
2001 * As of now, allocates 16 * 2 per-VF [to retain regular
2004 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2005 p_params->num_cons, 32);
2006 p_hwfn->p_cxt_mngr->arfs_count =
2007 p_params->num_arfs_filters;
2014 return ECORE_SUCCESS;
2017 /* This function is very RoCE oriented, if another protocol in the future
2018 * will want this feature we'll need to modify the function to be more generic
2020 enum _ecore_status_t
2021 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2022 enum ecore_cxt_elem_type elem_type,
2025 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2026 struct ecore_ilt_client_cfg *p_cli;
2027 struct ecore_ilt_cli_blk *p_blk;
2028 struct ecore_ptt *p_ptt;
2032 enum _ecore_status_t rc = ECORE_SUCCESS;
2034 switch (elem_type) {
2035 case ECORE_ELEM_CXT:
2036 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2037 elem_size = CONN_CXT_SIZE(p_hwfn);
2038 p_blk = &p_cli->pf_blks[CDUC_BLK];
2040 case ECORE_ELEM_SRQ:
2041 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2042 elem_size = SRQ_CXT_SIZE;
2043 p_blk = &p_cli->pf_blks[SRQ_BLK];
2045 case ECORE_ELEM_TASK:
2046 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2047 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2048 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2051 DP_NOTICE(p_hwfn, false,
2052 "ECORE_INVALID elem type = %d", elem_type);
2056 /* Calculate line in ilt */
2057 hw_p_size = p_cli->p_size.val;
2058 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2059 line = p_blk->start_line + (iid / elems_per_p);
2060 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2062 /* If line is already allocated, do nothing, otherwise allocate it and
2063 * write it to the PSWRQ2 registers.
2064 * This section can be run in parallel from different contexts and thus
2065 * a mutex protection is needed.
2068 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2070 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2073 p_ptt = ecore_ptt_acquire(p_hwfn);
2075 DP_NOTICE(p_hwfn, false,
2076 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2081 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2083 p_blk->real_size_in_page);
2088 OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2090 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2091 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2092 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2093 p_blk->real_size_in_page;
2095 /* compute absolute offset */
2096 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2097 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2100 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2101 SET_FIELD(ilt_hw_entry,
2103 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2105 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2107 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2108 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2111 if (elem_type == ECORE_ELEM_CXT) {
2112 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2115 /* Update the relevant register in the parser */
2116 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2117 last_cid_allocated - 1);
2119 if (!p_hwfn->b_rdma_enabled_in_prs) {
2120 /* Enable RoCE search */
2121 ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2122 p_hwfn->b_rdma_enabled_in_prs = true;
2127 ecore_ptt_release(p_hwfn, p_ptt);
2129 OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2134 /* This function is very RoCE oriented, if another protocol in the future
2135 * will want this feature we'll need to modify the function to be more generic
2137 static enum _ecore_status_t
2138 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2139 enum ecore_cxt_elem_type elem_type,
2140 u32 start_iid, u32 count)
2142 u32 start_line, end_line, shadow_start_line, shadow_end_line;
2143 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2144 struct ecore_ilt_client_cfg *p_cli;
2145 struct ecore_ilt_cli_blk *p_blk;
2146 u32 end_iid = start_iid + count;
2147 struct ecore_ptt *p_ptt;
2148 u64 ilt_hw_entry = 0;
2151 switch (elem_type) {
2152 case ECORE_ELEM_CXT:
2153 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2154 elem_size = CONN_CXT_SIZE(p_hwfn);
2155 p_blk = &p_cli->pf_blks[CDUC_BLK];
2157 case ECORE_ELEM_SRQ:
2158 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2159 elem_size = SRQ_CXT_SIZE;
2160 p_blk = &p_cli->pf_blks[SRQ_BLK];
2162 case ECORE_ELEM_TASK:
2163 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2164 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2165 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2168 DP_NOTICE(p_hwfn, false,
2169 "ECORE_INVALID elem type = %d", elem_type);
2173 /* Calculate line in ilt */
2174 hw_p_size = p_cli->p_size.val;
2175 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2176 start_line = p_blk->start_line + (start_iid / elems_per_p);
2177 end_line = p_blk->start_line + (end_iid / elems_per_p);
2178 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2181 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2182 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2184 p_ptt = ecore_ptt_acquire(p_hwfn);
2186 DP_NOTICE(p_hwfn, false,
2187 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2188 return ECORE_TIMEOUT;
2191 for (i = shadow_start_line; i < shadow_end_line; i++) {
2192 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2195 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2196 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2197 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2198 p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2200 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2201 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2202 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2204 /* compute absolute offset */
2205 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2206 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2209 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2212 ecore_dmae_host2grc(p_hwfn, p_ptt,
2213 (u64)(osal_uintptr_t)&ilt_hw_entry,
2215 sizeof(ilt_hw_entry) / sizeof(u32),
2219 ecore_ptt_release(p_hwfn, p_ptt);
2221 return ECORE_SUCCESS;
2224 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2225 enum protocol_type proto)
2227 enum _ecore_status_t rc;
2230 /* Free Connection CXT */
2231 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2232 ecore_cxt_get_proto_cid_start(p_hwfn,
2234 ecore_cxt_get_proto_cid_count(p_hwfn,
2242 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2243 ecore_cxt_get_proto_tid_count(p_hwfn,
2249 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2250 ecore_cxt_get_srq_count(p_hwfn));