drivers/net/qede/base/ecore_cxt.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_hsi_common.h"
  12 #include "ecore_hsi_eth.h"
  13 #include "ecore_rt_defs.h"
  14 #include "ecore_status.h"
  15 #include "ecore.h"
  16 #include "ecore_init_ops.h"
  17 #include "ecore_init_fw_funcs.h"
  18 #include "ecore_cxt.h"
  19 #include "ecore_hw.h"
  20 #include "ecore_dev_api.h"
  21 #include "ecore_sriov.h"
  22 #include "ecore_mcp.h"
  23
  24 /* Max number of connection types in HW (DQ/CDU etc.) */
  25 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  26 #define NUM_TASK_TYPES          2
  27 #define NUM_TASK_PF_SEGMENTS    4
  28 #define NUM_TASK_VF_SEGMENTS    1
  29
  30 /* Doorbell-Queue constants */
  31 #define DQ_RANGE_SHIFT  4
  32 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  33
  34 /* Searcher constants */
  35 #define SRC_MIN_NUM_ELEMS 256
  36
  37 /* Timers constants */
  38 #define TM_SHIFT        7
  39 #define TM_ALIGN        (1 << TM_SHIFT)
  40 #define TM_ELEM_SIZE    4
  41
  42 /* ILT constants */
  43 /* If for some reason, HW P size is modified to be less than 32K,
  44  * special handling needs to be made for CDU initialization
  45  */
  46 #define ILT_DEFAULT_HW_P_SIZE   3
  47
  48 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  49 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  50
  51 /* ILT entry structure */
  52 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  53 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  54 #define ILT_ENTRY_VALID_MASK            0x1ULL
  55 #define ILT_ENTRY_VALID_SHIFT           52
  56 #define ILT_ENTRY_IN_REGS               2
  57 #define ILT_REG_SIZE_IN_BYTES           4
  58
  59 /* connection context union */
  60 union conn_context {
  61         struct core_conn_context core_ctx;
  62         struct eth_conn_context eth_ctx;
  63 };
  64
  65 /* TYPE-0 task context - iSCSI, FCOE */
  66 union type0_task_context {
  67 };
  68
  69 /* TYPE-1 task context - ROCE */
  70 union type1_task_context {
  71 };
  72
  73 struct src_ent {
  74         u8 opaque[56];
  75         u64 next;
  76 };
  77
  78 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  79 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  80
  81 #define CONN_CXT_SIZE(p_hwfn) \
  82         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  83
  84 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
  85
  86 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
  87         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
  88
  89 /* Alignment is inherent to the type1_task_context structure */
  90 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
  91
  92 /* PF per protocl configuration object */
  93 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
  94 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
  95
  96 struct ecore_tid_seg {
  97         u32 count;
  98         u8 type;
  99         bool has_fl_mem;
 100 };
 101
 102 struct ecore_conn_type_cfg {
 103         u32 cid_count;
 104         u32 cid_start;
 105         u32 cids_per_vf;
 106         struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
 107 };
 108
 109 /* ILT Client configuration,
 110  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
 111  * 1 - for connection context (CDUC) and for each task context we need two
 112  * values, for regular task context and for force load memory
 113  */
 114 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 115 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 116 #define CDUC_BLK                (0)
 117 #define SRQ_BLK                 (0)
 118 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 119 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 120
 121 enum ilt_clients {
 122         ILT_CLI_CDUC,
 123         ILT_CLI_CDUT,
 124         ILT_CLI_QM,
 125         ILT_CLI_TM,
 126         ILT_CLI_SRC,
 127         ILT_CLI_TSDM,
 128         ILT_CLI_MAX
 129 };
 130
 131 struct ilt_cfg_pair {
 132         u32 reg;
 133         u32 val;
 134 };
 135
 136 struct ecore_ilt_cli_blk {
 137         u32 total_size;         /* 0 means not active */
 138         u32 real_size_in_page;
 139         u32 start_line;
 140         u32 dynamic_line_cnt;
 141 };
 142
 143 struct ecore_ilt_client_cfg {
 144         bool active;
 145
 146         /* ILT boundaries */
 147         struct ilt_cfg_pair first;
 148         struct ilt_cfg_pair last;
 149         struct ilt_cfg_pair p_size;
 150
 151         /* ILT client blocks for PF */
 152         struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 153         u32 pf_total_lines;
 154
 155         /* ILT client blocks for VFs */
 156         struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 157         u32 vf_total_lines;
 158 };
 159
 160 /* Per Path -
 161  *      ILT shadow table
 162  *      Protocol acquired CID lists
 163  *      PF start line in ILT
 164  */
 165 struct ecore_dma_mem {
 166         dma_addr_t p_phys;
 167         void *p_virt;
 168         osal_size_t size;
 169 };
 170
 171 #define MAP_WORD_SIZE           sizeof(unsigned long)
 172 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 173
 174 struct ecore_cid_acquired_map {
 175         u32 start_cid;
 176         u32 max_count;
 177         unsigned long *cid_map;
 178 };
 179
 180 struct ecore_cxt_mngr {
 181         /* Per protocl configuration */
 182         struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
 183
 184         /* computed ILT structure */
 185         struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
 186
 187         /* Task type sizes */
 188         u32 task_type_size[NUM_TASK_TYPES];
 189
 190         /* total number of VFs for this hwfn -
 191          * ALL VFs are symmetric in terms of HW resources
 192          */
 193         u32 vf_count;
 194
 195         /* total number of SRQ's for this hwfn */
 196         u32                             srq_count;
 197
 198         /* Acquired CIDs */
 199         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 200
 201         /* ILT  shadow table */
 202         struct ecore_dma_mem *ilt_shadow;
 203         u32 pf_start_line;
 204
 205         /* Mutex for a dynamic ILT allocation */
 206         osal_mutex_t mutex;
 207
 208         /* SRC T2 */
 209         struct ecore_dma_mem *t2;
 210         u32 t2_num_pages;
 211         u64 first_free;
 212         u64 last_free;
 213 };
 214
 215 /* check if resources/configuration is required according to protocol type */
 216 static OSAL_INLINE bool src_proto(enum protocol_type type)
 217 {
 218         return type == PROTOCOLID_TOE;
 219 }
 220
 221 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
 222 {
 223         return type == PROTOCOLID_TOE;
 224 }
 225
 226 static bool tm_tid_proto(enum protocol_type type)
 227 {
 228         return type == PROTOCOLID_FCOE;
 229 }
 230
 231 /* counts the iids for the CDU/CDUC ILT client configuration */
 232 struct ecore_cdu_iids {
 233         u32 pf_cids;
 234         u32 per_vf_cids;
 235 };
 236
 237 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
 238                                struct ecore_cdu_iids *iids)
 239 {
 240         u32 type;
 241
 242         for (type = 0; type < MAX_CONN_TYPES; type++) {
 243                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 244                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 245         }
 246 }
 247
 248 /* counts the iids for the Searcher block configuration */
 249 struct ecore_src_iids {
 250         u32 pf_cids;
 251         u32 per_vf_cids;
 252 };
 253
 254 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
 255                                            struct ecore_src_iids *iids)
 256 {
 257         u32 i;
 258
 259         for (i = 0; i < MAX_CONN_TYPES; i++) {
 260                 if (!src_proto(i))
 261                         continue;
 262
 263                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 264                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 265         }
 266 }
 267
 268 /* counts the iids for the Timers block configuration */
 269 struct ecore_tm_iids {
 270         u32 pf_cids;
 271         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 272         u32 pf_tids_total;
 273         u32 per_vf_cids;
 274         u32 per_vf_tids;
 275 };
 276
 277 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
 278                                           struct ecore_tm_iids *iids)
 279 {
 280         bool tm_vf_required = false;
 281         bool tm_required = false;
 282         u32 i, j;
 283
 284         for (i = 0; i < MAX_CONN_TYPES; i++) {
 285                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 286
 287                 if (tm_cid_proto(i) || tm_required) {
 288                         if (p_cfg->cid_count)
 289                                 tm_required = true;
 290
 291                         iids->pf_cids += p_cfg->cid_count;
 292                 }
 293
 294                 if (tm_cid_proto(i) || tm_vf_required) {
 295                         if (p_cfg->cids_per_vf)
 296                                 tm_vf_required = true;
 297
 298                 }
 299
 300                 if (tm_tid_proto(i)) {
 301                         struct ecore_tid_seg *segs = p_cfg->tid_seg;
 302
 303                         /* for each segment there is at most one
 304                          * protocol for which count is not 0.
 305                          */
 306                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 307                                 iids->pf_tids[j] += segs[j].count;
 308
 309                         /* The last array elelment is for the VFs. As for PF
 310                          * segments there can be only one protocol for
 311                          * which this value is not 0.
 312                          */
 313                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 314                 }
 315         }
 316
 317         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 318         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 319         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 320
 321         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 322                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 323                 iids->pf_tids_total += iids->pf_tids[j];
 324         }
 325 }
 326
 327 void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids)
 328 {
 329         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 330         struct ecore_tid_seg *segs;
 331         u32 vf_cids = 0, type, j;
 332         u32 vf_tids = 0;
 333
 334         for (type = 0; type < MAX_CONN_TYPES; type++) {
 335                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 336                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 337
 338                 segs = p_mngr->conn_cfg[type].tid_seg;
 339                 /* for each segment there is at most one
 340                  * protocol for which count is not 0.
 341                  */
 342                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 343                         iids->tids += segs[j].count;
 344
 345                 /* The last array elelment is for the VFs. As for PF
 346                  * segments there can be only one protocol for
 347                  * which this value is not 0.
 348                  */
 349                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 350         }
 351
 352         iids->vf_cids += vf_cids * p_mngr->vf_count;
 353         iids->tids += vf_tids * p_mngr->vf_count;
 354
 355         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 356                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 357                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 358 }
 359
 360 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
 361                                                     u32 seg)
 362 {
 363         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 364         u32 i;
 365
 366         /* Find the protocol with tid count > 0 for this segment.
 367          * Note: there can only be one and this is already validated.
 368          */
 369         for (i = 0; i < MAX_CONN_TYPES; i++) {
 370                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 371                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 372         }
 373         return OSAL_NULL;
 374 }
 375
 376 /* set the iids (cid/tid) count per protocol */
 377 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 378                                    enum protocol_type type,
 379                                    u32 cid_count, u32 vf_cid_cnt)
 380 {
 381         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 382         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 383
 384         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 385         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 386 }
 387
 388 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
 389                                   enum protocol_type type, u32 *vf_cid)
 390 {
 391         if (vf_cid)
 392                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 393
 394         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 395 }
 396
 397 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
 398                                   enum protocol_type type)
 399 {
 400         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 401 }
 402
 403 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 404                                          enum protocol_type type)
 405 {
 406         u32 cnt = 0;
 407         int i;
 408
 409         for (i = 0; i < TASK_SEGMENTS; i++)
 410                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 411
 412         return cnt;
 413 }
 414
 415 static OSAL_INLINE void
 416 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 417                               enum protocol_type proto,
 418                               u8 seg, u8 seg_type, u32 count, bool has_fl)
 419 {
 420         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 421         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 422
 423         p_seg->count = count;
 424         p_seg->has_fl_mem = has_fl;
 425         p_seg->type = seg_type;
 426 }
 427
 428 /* the *p_line parameter must be either 0 for the first invocation or the
 429  * value returned in the previous invocation.
 430  */
 431 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
 432                                    struct ecore_ilt_cli_blk *p_blk,
 433                                    u32 start_line,
 434                                    u32 total_size, u32 elem_size)
 435 {
 436         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 437
 438         /* verify that it's called once for each block */
 439         if (p_blk->total_size)
 440                 return;
 441
 442         p_blk->total_size = total_size;
 443         p_blk->real_size_in_page = 0;
 444         if (elem_size)
 445                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 446         p_blk->start_line = start_line;
 447 }
 448
 449 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
 450                                    struct ecore_ilt_client_cfg *p_cli,
 451                                    struct ecore_ilt_cli_blk *p_blk,
 452                                    u32 *p_line, enum ilt_clients client_id)
 453 {
 454         if (!p_blk->total_size)
 455                 return;
 456
 457         if (!p_cli->active)
 458                 p_cli->first.val = *p_line;
 459
 460         p_cli->active = true;
 461         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 462         p_cli->last.val = *p_line - 1;
 463
 464         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 465                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
 466                    " [Real %08x] Start line %d\n",
 467                    client_id, p_cli->first.val, p_cli->last.val,
 468                    p_blk->total_size, p_blk->real_size_in_page,
 469                    p_blk->start_line);
 470 }
 471
 472 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 473                                           enum ilt_clients ilt_client)
 474 {
 475         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 476         struct ecore_ilt_client_cfg *p_cli;
 477         u32 lines_to_skip = 0;
 478         u32 cxts_per_p;
 479
 480         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 481
 482         if (ilt_client == ILT_CLI_CDUC) {
 483                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 484
 485                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 486                     (u32)CONN_CXT_SIZE(p_hwfn);
 487
 488                 lines_to_skip = cid_count / cxts_per_p;
 489         }
 490
 491         return lines_to_skip;
 492 }
 493
 494 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
 495 {
 496         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 497         u32 curr_line, total, i, task_size, line;
 498         struct ecore_ilt_client_cfg *p_cli;
 499         struct ecore_ilt_cli_blk *p_blk;
 500         struct ecore_cdu_iids cdu_iids;
 501         struct ecore_src_iids src_iids;
 502         struct ecore_qm_iids qm_iids;
 503         struct ecore_tm_iids tm_iids;
 504         struct ecore_tid_seg *p_seg;
 505
 506         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 507         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 508         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 509         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 510
 511         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 512
 513         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 514                    "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
 515                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 516
 517         /* CDUC */
 518         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 519
 520         curr_line = p_mngr->pf_start_line;
 521
 522         /* CDUC PF */
 523         p_cli->pf_total_lines = 0;
 524
 525         /* get the counters for the CDUC,CDUC and QM clients  */
 526         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 527
 528         p_blk = &p_cli->pf_blks[CDUC_BLK];
 529
 530         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 531
 532         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 533                                total, CONN_CXT_SIZE(p_hwfn));
 534
 535         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 536         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 537
 538         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 539                                                                  ILT_CLI_CDUC);
 540
 541         /* CDUC VF */
 542         p_blk = &p_cli->vf_blks[CDUC_BLK];
 543         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 544
 545         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 546                                total, CONN_CXT_SIZE(p_hwfn));
 547
 548         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 549         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 550
 551         for (i = 1; i < p_mngr->vf_count; i++)
 552                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 553                                        ILT_CLI_CDUC);
 554
 555         /* CDUT PF */
 556         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 557         p_cli->first.val = curr_line;
 558
 559         /* first the 'working' task memory */
 560         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 561                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 562                 if (!p_seg || p_seg->count == 0)
 563                         continue;
 564
 565                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 566                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 567                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 568                                        p_mngr->task_type_size[p_seg->type]);
 569
 570                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 571                                        ILT_CLI_CDUT);
 572         }
 573
 574         /* next the 'init' task memory (forced load memory) */
 575         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 576                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 577                 if (!p_seg || p_seg->count == 0)
 578                         continue;
 579
 580                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 581
 582                 if (!p_seg->has_fl_mem) {
 583                         /* The segment is active (total size pf 'working'
 584                          * memory is > 0) but has no FL (forced-load, Init)
 585                          * memory. Thus:
 586                          *
 587                          * 1.   The total-size in the corrsponding FL block of
 588                          *      the ILT client is set to 0 - No ILT line are
 589                          *      provisioned and no ILT memory allocated.
 590                          *
 591                          * 2.   The start-line of said block is set to the
 592                          *      start line of the matching working memory
 593                          *      block in the ILT client. This is later used to
 594                          *      configure the CDU segment offset registers and
 595                          *      results in an FL command for TIDs of this
 596                          *      segment behaves as regular load commands
 597                          *      (loading TIDs from the working memory).
 598                          */
 599                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 600
 601                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 602                         continue;
 603                 }
 604                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 605
 606                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 607                                        curr_line, total,
 608                                        p_mngr->task_type_size[p_seg->type]);
 609
 610                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 611                                        ILT_CLI_CDUT);
 612         }
 613         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 614
 615         /* CDUT VF */
 616         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 617         if (p_seg && p_seg->count) {
 618                 /* Stricly speaking we need to iterate over all VF
 619                  * task segment types, but a VF has only 1 segment
 620                  */
 621
 622                 /* 'working' memory */
 623                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 624
 625                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 626                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 627                                        curr_line, total,
 628                                        p_mngr->task_type_size[p_seg->type]);
 629
 630                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 631                                        ILT_CLI_CDUT);
 632
 633                 /* 'init' memory */
 634                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 635                 if (!p_seg->has_fl_mem) {
 636                         /* see comment above */
 637                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 638                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 639                 } else {
 640                         task_size = p_mngr->task_type_size[p_seg->type];
 641                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 642                                                curr_line, total, task_size);
 643                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 644                                                ILT_CLI_CDUT);
 645                 }
 646                 p_cli->vf_total_lines = curr_line -
 647                     p_cli->vf_blks[0].start_line;
 648
 649                 /* Now for the rest of the VFs */
 650                 for (i = 1; i < p_mngr->vf_count; i++) {
 651                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 652                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 653                                                ILT_CLI_CDUT);
 654
 655                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 656                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 657                                                ILT_CLI_CDUT);
 658                 }
 659         }
 660
 661         /* QM */
 662         p_cli = &p_mngr->clients[ILT_CLI_QM];
 663         p_blk = &p_cli->pf_blks[0];
 664
 665         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 666         total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 667                                      qm_iids.vf_cids, qm_iids.tids,
 668                                      p_hwfn->qm_info.num_pqs,
 669                                      p_hwfn->qm_info.num_vf_pqs);
 670
 671         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 672                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
 673                    " num_vf_pqs=%d, memory_size=%d)\n",
 674                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 675                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 676
 677         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 678                                QM_PQ_ELEMENT_SIZE);
 679
 680         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 681         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 682
 683         /* SRC */
 684         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 685         ecore_cxt_src_iids(p_mngr, &src_iids);
 686
 687         /* Both the PF and VFs searcher connections are stored in the per PF
 688          * database. Thus sum the PF searcher cids and all the VFs searcher
 689          * cids.
 690          */
 691         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 692         if (total) {
 693                 u32 local_max = OSAL_MAX_T(u32, total,
 694                                            SRC_MIN_NUM_ELEMS);
 695
 696                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 697
 698                 p_blk = &p_cli->pf_blks[0];
 699                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 700                                        total * sizeof(struct src_ent),
 701                                        sizeof(struct src_ent));
 702
 703                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 704                                        ILT_CLI_SRC);
 705                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 706         }
 707
 708         /* TM PF */
 709         p_cli = &p_mngr->clients[ILT_CLI_TM];
 710         ecore_cxt_tm_iids(p_mngr, &tm_iids);
 711         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 712         if (total) {
 713                 p_blk = &p_cli->pf_blks[0];
 714                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 715                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 716
 717                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 718                                        ILT_CLI_TM);
 719                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 720         }
 721
 722         /* TM VF */
 723         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 724         if (total) {
 725                 p_blk = &p_cli->vf_blks[0];
 726                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 727                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 728
 729                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 730                                        ILT_CLI_TM);
 731
 732                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 733                 for (i = 1; i < p_mngr->vf_count; i++) {
 734                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 735                                                ILT_CLI_TM);
 736                 }
 737         }
 738
 739         /* TSDM (SRQ CONTEXT) */
 740         total = ecore_cxt_get_srq_count(p_hwfn);
 741
 742         if (total) {
 743                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 744                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 745                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 746                                        total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 747
 748                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 749                                        ILT_CLI_TSDM);
 750                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 751         }
 752
 753         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 754             RESC_NUM(p_hwfn, ECORE_ILT)) {
 755                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 756                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 757                 return ECORE_INVAL;
 758         }
 759
 760         return ECORE_SUCCESS;
 761 }
 762
 763 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 764 {
 765         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 766         u32 i;
 767
 768         if (!p_mngr->t2)
 769                 return;
 770
 771         for (i = 0; i < p_mngr->t2_num_pages; i++)
 772                 if (p_mngr->t2[i].p_virt)
 773                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 774                                                p_mngr->t2[i].p_virt,
 775                                                p_mngr->t2[i].p_phys,
 776                                                p_mngr->t2[i].size);
 777
 778         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 779 }
 780
 781 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 782 {
 783         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 784         u32 conn_num, total_size, ent_per_page, psz, i;
 785         struct ecore_ilt_client_cfg *p_src;
 786         struct ecore_src_iids src_iids;
 787         struct ecore_dma_mem *p_t2;
 788         enum _ecore_status_t rc;
 789
 790         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 791
 792         /* if the SRC ILT client is inactive - there are no connection
 793          * requiring the searcer, leave.
 794          */
 795         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 796         if (!p_src->active)
 797                 return ECORE_SUCCESS;
 798
 799         ecore_cxt_src_iids(p_mngr, &src_iids);
 800         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 801         total_size = conn_num * sizeof(struct src_ent);
 802
 803         /* use the same page size as the SRC ILT client */
 804         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 805         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 806
 807         /* allocate t2 */
 808         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 809                                  p_mngr->t2_num_pages *
 810                                  sizeof(struct ecore_dma_mem));
 811         if (!p_mngr->t2) {
 812                 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
 813                 rc = ECORE_NOMEM;
 814                 goto t2_fail;
 815         }
 816
 817         /* allocate t2 pages */
 818         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 819                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 820                 void **p_virt = &p_mngr->t2[i].p_virt;
 821
 822                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 823                                                   &p_mngr->t2[i].p_phys, size);
 824                 if (!p_mngr->t2[i].p_virt) {
 825                         rc = ECORE_NOMEM;
 826                         goto t2_fail;
 827                 }
 828                 OSAL_MEM_ZERO(*p_virt, size);
 829                 p_mngr->t2[i].size = size;
 830                 total_size -= size;
 831         }
 832
 833         /* Set the t2 pointers */
 834
 835         /* entries per page - must be a power of two */
 836         ent_per_page = psz / sizeof(struct src_ent);
 837
 838         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 839
 840         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 841         p_mngr->last_free = (u64)p_t2->p_phys +
 842             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 843
 844         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 845                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
 846                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 847                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
 848                 u32 j;
 849
 850                 for (j = 0; j < ent_num - 1; j++) {
 851                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 852                         entries[j].next = OSAL_CPU_TO_BE64(val);
 853                 }
 854
 855                 if (i < p_mngr->t2_num_pages - 1)
 856                         val = (u64)p_mngr->t2[i + 1].p_phys;
 857                 else
 858                         val = 0;
 859                 entries[j].next = OSAL_CPU_TO_BE64(val);
 860
 861                 conn_num -= ent_num;
 862         }
 863
 864         return ECORE_SUCCESS;
 865
 866 t2_fail:
 867         ecore_cxt_src_t2_free(p_hwfn);
 868         return rc;
 869 }
 870
 871 #define for_each_ilt_valid_client(pos, clients)         \
 872         for (pos = 0; pos < ILT_CLI_MAX; pos++)         \
 873                 if (!clients[pos].active) {             \
 874                         continue;                       \
 875                 } else                                  \
 876
 877
 878 /* Total number of ILT lines used by this PF */
 879 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
 880 {
 881         u32 size = 0;
 882         u32 i;
 883
 884         for_each_ilt_valid_client(i, ilt_clients)
 885                 size += (ilt_clients[i].last.val -
 886                          ilt_clients[i].first.val + 1);
 887
 888         return size;
 889 }
 890
 891 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
 892 {
 893         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 894         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 895         u32 ilt_size, i;
 896
 897         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
 898
 899         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 900                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 901
 902                 if (p_dma->p_virt)
 903                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 904                                                p_dma->p_virt,
 905                                                p_dma->p_phys, p_dma->size);
 906                 p_dma->p_virt = OSAL_NULL;
 907         }
 908         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
 909 }
 910
 911 static enum _ecore_status_t
 912 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
 913                     struct ecore_ilt_cli_blk *p_blk,
 914                     enum ilt_clients ilt_client, u32 start_line_offset)
 915 {
 916         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 917         u32 lines, line, sz_left, lines_to_skip = 0;
 918
 919         /* Special handling for RoCE that supports dynamic allocation */
 920         if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
 921                 return ECORE_SUCCESS;
 922
 923         lines_to_skip = p_blk->dynamic_line_cnt;
 924
 925         if (!p_blk->total_size)
 926                 return ECORE_SUCCESS;
 927
 928         sz_left = p_blk->total_size;
 929         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 930         line = p_blk->start_line + start_line_offset -
 931             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 932
 933         for (; lines; lines--) {
 934                 dma_addr_t p_phys;
 935                 void *p_virt;
 936                 u32 size;
 937
 938                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
 939
 940 /* @DPDK */
 941 #define ILT_BLOCK_ALIGN_SIZE 0x1000
 942                 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
 943                                                          &p_phys, size,
 944                                                          ILT_BLOCK_ALIGN_SIZE);
 945                 if (!p_virt)
 946                         return ECORE_NOMEM;
 947                 OSAL_MEM_ZERO(p_virt, size);
 948
 949                 ilt_shadow[line].p_phys = p_phys;
 950                 ilt_shadow[line].p_virt = p_virt;
 951                 ilt_shadow[line].size = size;
 952
 953                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 954                            "ILT shadow: Line [%d] Physical 0x%lx"
 955                            " Virtual %p Size %d\n",
 956                            line, (unsigned long)p_phys, p_virt, size);
 957
 958                 sz_left -= size;
 959                 line++;
 960         }
 961
 962         return ECORE_SUCCESS;
 963 }
 964
 965 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
 966 {
 967         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 968         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
 969         struct ecore_ilt_cli_blk *p_blk;
 970         u32 size, i, j, k;
 971         enum _ecore_status_t rc;
 972
 973         size = ecore_cxt_ilt_shadow_size(clients);
 974         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 975                                          size * sizeof(struct ecore_dma_mem));
 976
 977         if (!p_mngr->ilt_shadow) {
 978                 DP_NOTICE(p_hwfn, true,
 979                           "Failed to allocate ilt shadow table\n");
 980                 rc = ECORE_NOMEM;
 981                 goto ilt_shadow_fail;
 982         }
 983
 984         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 985                    "Allocated 0x%x bytes for ilt shadow\n",
 986                    (u32)(size * sizeof(struct ecore_dma_mem)));
 987
 988         for_each_ilt_valid_client(i, clients) {
 989                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
 990                         p_blk = &clients[i].pf_blks[j];
 991                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
 992                         if (rc != ECORE_SUCCESS)
 993                                 goto ilt_shadow_fail;
 994                 }
 995                 for (k = 0; k < p_mngr->vf_count; k++) {
 996                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
 997                                 u32 lines = clients[i].vf_total_lines * k;
 998
 999                                 p_blk = &clients[i].vf_blks[j];
1000                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1001                                                          i, lines);
1002                                 if (rc != ECORE_SUCCESS)
1003                                         goto ilt_shadow_fail;
1004                         }
1005                 }
1006         }
1007
1008         return ECORE_SUCCESS;
1009
1010 ilt_shadow_fail:
1011         ecore_ilt_shadow_free(p_hwfn);
1012         return rc;
1013 }
1014
1015 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1016 {
1017         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1018         u32 type;
1019
1020         for (type = 0; type < MAX_CONN_TYPES; type++) {
1021                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1022                 p_mngr->acquired[type].max_count = 0;
1023                 p_mngr->acquired[type].start_cid = 0;
1024         }
1025 }
1026
1027 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1028 {
1029         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1030         u32 start_cid = 0;
1031         u32 type;
1032
1033         for (type = 0; type < MAX_CONN_TYPES; type++) {
1034                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1035                 u32 size;
1036
1037                 if (cid_cnt == 0)
1038                         continue;
1039
1040                 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD);
1041                 p_mngr->acquired[type].cid_map = OSAL_ZALLOC(p_hwfn->p_dev,
1042                                                              GFP_KERNEL, size);
1043                 if (!p_mngr->acquired[type].cid_map)
1044                         goto cid_map_fail;
1045
1046                 p_mngr->acquired[type].max_count = cid_cnt;
1047                 p_mngr->acquired[type].start_cid = start_cid;
1048
1049                 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1050
1051                 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1052                            "Type %08x start: %08x count %08x\n",
1053                            type, p_mngr->acquired[type].start_cid,
1054                            p_mngr->acquired[type].max_count);
1055                 start_cid += cid_cnt;
1056         }
1057
1058         return ECORE_SUCCESS;
1059
1060 cid_map_fail:
1061         ecore_cid_map_free(p_hwfn);
1062         return ECORE_NOMEM;
1063 }
1064
1065 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1066 {
1067         struct ecore_ilt_client_cfg *clients;
1068         struct ecore_cxt_mngr *p_mngr;
1069         u32 i;
1070
1071         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1072         if (!p_mngr) {
1073                 DP_NOTICE(p_hwfn, true,
1074                           "Failed to allocate `struct ecore_cxt_mngr'\n");
1075                 return ECORE_NOMEM;
1076         }
1077
1078         /* Initialize ILT client registers */
1079         clients = p_mngr->clients;
1080         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1081         clients[ILT_CLI_CDUC].last.reg  = ILT_CFG_REG(CDUC, LAST_ILT);
1082         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1083
1084         clients[ILT_CLI_QM].first.reg   = ILT_CFG_REG(QM, FIRST_ILT);
1085         clients[ILT_CLI_QM].last.reg    = ILT_CFG_REG(QM, LAST_ILT);
1086         clients[ILT_CLI_QM].p_size.reg  = ILT_CFG_REG(QM, P_SIZE);
1087
1088         clients[ILT_CLI_TM].first.reg   = ILT_CFG_REG(TM, FIRST_ILT);
1089         clients[ILT_CLI_TM].last.reg    = ILT_CFG_REG(TM, LAST_ILT);
1090         clients[ILT_CLI_TM].p_size.reg  = ILT_CFG_REG(TM, P_SIZE);
1091
1092         clients[ILT_CLI_SRC].first.reg  = ILT_CFG_REG(SRC, FIRST_ILT);
1093         clients[ILT_CLI_SRC].last.reg   = ILT_CFG_REG(SRC, LAST_ILT);
1094         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1095
1096         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1097         clients[ILT_CLI_CDUT].last.reg  = ILT_CFG_REG(CDUT, LAST_ILT);
1098         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1099
1100         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1101         clients[ILT_CLI_TSDM].last.reg  = ILT_CFG_REG(TSDM, LAST_ILT);
1102         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1103
1104         /* default ILT page size for all clients is 32K */
1105         for (i = 0; i < ILT_CLI_MAX; i++)
1106                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1107
1108         /* due to removal of ISCSI/FCoE files union type0_task_context
1109          * task_type_size will be 0. So hardcoded for now.
1110          */
1111         p_mngr->task_type_size[0] = 512; /* @DPDK */
1112         p_mngr->task_type_size[1] = 128; /* @DPDK */
1113
1114         if (p_hwfn->p_dev->p_iov_info)
1115                 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1116
1117         /* Initialize the dynamic ILT allocation mutex */
1118         OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1119         OSAL_MUTEX_INIT(&p_mngr->mutex);
1120
1121         /* Set the cxt mangr pointer priori to further allocations */
1122         p_hwfn->p_cxt_mngr = p_mngr;
1123
1124         return ECORE_SUCCESS;
1125 }
1126
1127 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1128 {
1129         enum _ecore_status_t rc;
1130
1131         /* Allocate the ILT shadow table */
1132         rc = ecore_ilt_shadow_alloc(p_hwfn);
1133         if (rc) {
1134                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1135                 goto tables_alloc_fail;
1136         }
1137
1138         /* Allocate the T2  table */
1139         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1140         if (rc) {
1141                 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1142                 goto tables_alloc_fail;
1143         }
1144
1145         /* Allocate and initialize the acquired cids bitmaps */
1146         rc = ecore_cid_map_alloc(p_hwfn);
1147         if (rc) {
1148                 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1149                 goto tables_alloc_fail;
1150         }
1151
1152         return ECORE_SUCCESS;
1153
1154 tables_alloc_fail:
1155         ecore_cxt_mngr_free(p_hwfn);
1156         return rc;
1157 }
1158
1159 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1160 {
1161         if (!p_hwfn->p_cxt_mngr)
1162                 return;
1163
1164         ecore_cid_map_free(p_hwfn);
1165         ecore_cxt_src_t2_free(p_hwfn);
1166         ecore_ilt_shadow_free(p_hwfn);
1167         OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1168         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1169 }
1170
1171 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1172 {
1173         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1174         int type;
1175
1176         /* Reset acquired cids */
1177         for (type = 0; type < MAX_CONN_TYPES; type++) {
1178                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1179                 u32 i;
1180
1181                 if (cid_cnt == 0)
1182                         continue;
1183
1184                 for (i = 0; i < DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD); i++)
1185                         p_mngr->acquired[type].cid_map[i] = 0;
1186         }
1187 }
1188
1189 /* HW initialization helper (per Block, per phase) */
1190
1191 /* CDU Common */
1192 #define CDUC_CXT_SIZE_SHIFT                                             \
1193         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1194
1195 #define CDUC_CXT_SIZE_MASK                                              \
1196         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1197
1198 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1199         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1200
1201 #define CDUC_BLOCK_WASTE_MASK                                           \
1202         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1203
1204 #define CDUC_NCIB_SHIFT                                                 \
1205         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1206
1207 #define CDUC_NCIB_MASK                                                  \
1208         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1209
1210 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1211         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1212
1213 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1214         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1215         CDUT_TYPE0_CXT_SIZE_SHIFT)
1216
1217 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1218         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1219
1220 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1221         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1222         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1223
1224 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1225         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1226
1227 #define CDUT_TYPE0_NCIB_MASK                                            \
1228         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1229         CDUT_TYPE0_NCIB_SHIFT)
1230
1231 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1232         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1233
1234 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1235         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1236         CDUT_TYPE1_CXT_SIZE_SHIFT)
1237
1238 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1239         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1240
1241 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1242         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1243         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1244
1245 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1246         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1247
1248 #define CDUT_TYPE1_NCIB_MASK                                            \
1249         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1250         CDUT_TYPE1_NCIB_SHIFT)
1251
1252 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1253 {
1254         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1255
1256         /* CDUC - connection configuration */
1257         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1258         cxt_size = CONN_CXT_SIZE(p_hwfn);
1259         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1260         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1261
1262         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1263         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1264         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1265         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1266
1267         /* CDUT - type-0 tasks configuration */
1268         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1269         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1270         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1271         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1272
1273         /* cxt size and block-waste are multipes of 8 */
1274         cdu_params = 0;
1275         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1276         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1277         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1278         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1279
1280         /* CDUT - type-1 tasks configuration */
1281         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1282         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1283         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1284
1285         /* cxt size and block-waste are multipes of 8 */
1286         cdu_params = 0;
1287         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1288         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1289         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1290         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1291 }
1292
1293 /* CDU PF */
1294 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1295 #define CDU_SEG_REG_TYPE_MASK           0x1
1296 #define CDU_SEG_REG_OFFSET_SHIFT        0
1297 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1298
1299 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1300 {
1301         struct ecore_ilt_client_cfg *p_cli;
1302         struct ecore_tid_seg *p_seg;
1303         u32 cdu_seg_params, offset;
1304         int i;
1305
1306         static const u32 rt_type_offset_arr[] = {
1307                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1308                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1309                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1310                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1311         };
1312
1313         static const u32 rt_type_offset_fl_arr[] = {
1314                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1315                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1316                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1317                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1318         };
1319
1320         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1321
1322         /* There are initializations only for CDUT during pf Phase */
1323         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1324                 /* Segment 0 */
1325                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1326                 if (!p_seg)
1327                         continue;
1328
1329                 /* Note: start_line is already adjusted for the CDU
1330                  * segment register granularity, so we just need to
1331                  * divide. Adjustment is implicit as we assume ILT
1332                  * Page size is larger than 32K!
1333                  */
1334                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1335                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1336                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1337
1338                 cdu_seg_params = 0;
1339                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1340                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1341                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1342
1343                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1344                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1345                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1346
1347                 cdu_seg_params = 0;
1348                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1349                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1350                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1351         }
1352 }
1353
1354 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1355 {
1356         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1357         struct ecore_qm_iids iids;
1358
1359         OSAL_MEM_ZERO(&iids, sizeof(iids));
1360         ecore_cxt_qm_iids(p_hwfn, &iids);
1361
1362         ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1363                             p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1364                             p_hwfn->first_on_engine,
1365                             iids.cids, iids.vf_cids, iids.tids,
1366                             qm_info->start_pq,
1367                             qm_info->num_pqs - qm_info->num_vf_pqs,
1368                             qm_info->num_vf_pqs,
1369                             qm_info->start_vport,
1370                             qm_info->num_vports, qm_info->pf_wfq,
1371                             qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1372                             p_hwfn->qm_info.qm_vport_params);
1373 }
1374
1375 /* CM PF */
1376 void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1377 {
1378         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1379                      ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1380 }
1381
1382 /* DQ PF */
1383 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1384 {
1385         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1386         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1387
1388         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1389         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1390
1391         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1392         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1393
1394         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1395         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1396
1397         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1398         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1399
1400         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1401         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1402
1403         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1404         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1405
1406         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1407         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1408
1409         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1410         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1411
1412         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1413         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1414
1415         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1416         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1417
1418         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1419         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1420
1421         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1422         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1423
1424         /* Connection types 6 & 7 are not in use, yet they must be configured
1425          * as the highest possible connection. Not configuring them means the
1426          * defaults will be  used, and with a large number of cids a bug may
1427          * occur, if the defaults will be smaller than dq_pf_max_cid /
1428          * dq_vf_max_cid.
1429          */
1430         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1431         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1432
1433         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1434         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1435 }
1436
1437 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1438 {
1439         struct ecore_ilt_client_cfg *ilt_clients;
1440         int i;
1441
1442         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1443         for_each_ilt_valid_client(i, ilt_clients) {
1444                 STORE_RT_REG(p_hwfn,
1445                              ilt_clients[i].first.reg,
1446                              ilt_clients[i].first.val);
1447                 STORE_RT_REG(p_hwfn,
1448                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1449                 STORE_RT_REG(p_hwfn,
1450                              ilt_clients[i].p_size.reg,
1451                              ilt_clients[i].p_size.val);
1452         }
1453 }
1454
1455 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1456 {
1457         struct ecore_ilt_client_cfg *p_cli;
1458         u32 blk_factor;
1459
1460         /* For simplicty  we set the 'block' to be an ILT page */
1461         if (p_hwfn->p_dev->p_iov_info) {
1462                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1463
1464                 STORE_RT_REG(p_hwfn,
1465                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1466                              p_iov->first_vf_in_pf);
1467                 STORE_RT_REG(p_hwfn,
1468                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1469                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1470         }
1471
1472         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1473         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1474         if (p_cli->active) {
1475                 STORE_RT_REG(p_hwfn,
1476                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1477                              blk_factor);
1478                 STORE_RT_REG(p_hwfn,
1479                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1480                              p_cli->pf_total_lines);
1481                 STORE_RT_REG(p_hwfn,
1482                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1483                              p_cli->vf_total_lines);
1484         }
1485
1486         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1487         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1488         if (p_cli->active) {
1489                 STORE_RT_REG(p_hwfn,
1490                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1491                              blk_factor);
1492                 STORE_RT_REG(p_hwfn,
1493                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1494                              p_cli->pf_total_lines);
1495                 STORE_RT_REG(p_hwfn,
1496                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1497                              p_cli->vf_total_lines);
1498         }
1499
1500         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1501         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1502         if (p_cli->active) {
1503                 STORE_RT_REG(p_hwfn,
1504                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1505                 STORE_RT_REG(p_hwfn,
1506                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1507                              p_cli->pf_total_lines);
1508                 STORE_RT_REG(p_hwfn,
1509                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1510                              p_cli->vf_total_lines);
1511         }
1512 }
1513
1514 /* ILT (PSWRQ2) PF */
1515 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1516 {
1517         struct ecore_ilt_client_cfg *clients;
1518         struct ecore_cxt_mngr *p_mngr;
1519         struct ecore_dma_mem *p_shdw;
1520         u32 line, rt_offst, i;
1521
1522         ecore_ilt_bounds_init(p_hwfn);
1523         ecore_ilt_vf_bounds_init(p_hwfn);
1524
1525         p_mngr = p_hwfn->p_cxt_mngr;
1526         p_shdw = p_mngr->ilt_shadow;
1527         clients = p_hwfn->p_cxt_mngr->clients;
1528
1529         for_each_ilt_valid_client(i, clients) {
1530                 /* Client's 1st val and RT array are absolute, ILT shadows'
1531                  * lines are relative.
1532                  */
1533                 line = clients[i].first.val - p_mngr->pf_start_line;
1534                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1535                     clients[i].first.val * ILT_ENTRY_IN_REGS;
1536
1537                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1538                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1539                         u64 ilt_hw_entry = 0;
1540
1541                         /** p_virt could be OSAL_NULL incase of dynamic
1542                          *  allocation
1543                          */
1544                         if (p_shdw[line].p_virt != OSAL_NULL) {
1545                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1546                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1547                                           (p_shdw[line].p_phys >> 12));
1548
1549                                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1550                                         "Setting RT[0x%08x] from"
1551                                         " ILT[0x%08x] [Client is %d] to"
1552                                         " Physical addr: 0x%lx\n",
1553                                         rt_offst, line, i,
1554                                         (unsigned long)(p_shdw[line].
1555                                                         p_phys >> 12));
1556                         }
1557
1558                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1559                 }
1560         }
1561 }
1562
1563 /* SRC (Searcher) PF */
1564 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1565 {
1566         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1567         u32 rounded_conn_num, conn_num, conn_max;
1568         struct ecore_src_iids src_iids;
1569
1570         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1571         ecore_cxt_src_iids(p_mngr, &src_iids);
1572         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1573         if (!conn_num)
1574                 return;
1575
1576         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1577         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1578
1579         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1580         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1581                      OSAL_LOG2(rounded_conn_num));
1582
1583         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1584                          p_hwfn->p_cxt_mngr->first_free);
1585         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1586                          p_hwfn->p_cxt_mngr->last_free);
1587 }
1588
1589 /* Timers PF */
1590 #define TM_CFG_NUM_IDS_SHIFT            0
1591 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1592 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1593 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1594 #define TM_CFG_PARENT_PF_SHIFT          25
1595 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1596
1597 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1598 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1599
1600 #define TM_CFG_TID_OFFSET_SHIFT         30
1601 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1602 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1603 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1604
1605 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1606 {
1607         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1608         u32 active_seg_mask = 0, tm_offset, rt_reg;
1609         struct ecore_tm_iids tm_iids;
1610         u64 cfg_word;
1611         u8 i;
1612
1613         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1614         ecore_cxt_tm_iids(p_mngr, &tm_iids);
1615
1616         /* @@@TBD No pre-scan for now */
1617
1618         /* Note: We assume consecutive VFs for a PF */
1619         for (i = 0; i < p_mngr->vf_count; i++) {
1620                 cfg_word = 0;
1621                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1622                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1623                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1624                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1625
1626                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1627                     (sizeof(cfg_word) / sizeof(u32)) *
1628                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1629                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1630         }
1631
1632         cfg_word = 0;
1633         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1634         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1635         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1636         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all   */
1637
1638         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1639             (sizeof(cfg_word) / sizeof(u32)) *
1640             (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1641         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1642
1643         /* enale scan */
1644         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1645                      tm_iids.pf_cids ? 0x1 : 0x0);
1646
1647         /* @@@TBD how to enable the scan for the VFs */
1648
1649         tm_offset = tm_iids.per_vf_cids;
1650
1651         /* Note: We assume consecutive VFs for a PF */
1652         for (i = 0; i < p_mngr->vf_count; i++) {
1653                 cfg_word = 0;
1654                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1655                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1656                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1657                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1658                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1659
1660                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1661                     (sizeof(cfg_word) / sizeof(u32)) *
1662                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1663
1664                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1665         }
1666
1667         tm_offset = tm_iids.pf_cids;
1668         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1669                 cfg_word = 0;
1670                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1671                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1672                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1673                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1674                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1675
1676                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1677                     (sizeof(cfg_word) / sizeof(u32)) *
1678                     (NUM_OF_VFS(p_hwfn->p_dev) +
1679                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1680
1681                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1682                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1683
1684                 tm_offset += tm_iids.pf_tids[i];
1685         }
1686
1687         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1688
1689         /* @@@TBD how to enable the scan for the VFs */
1690 }
1691
1692 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1693 {
1694         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1695         struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1696         struct ecore_tid_seg *p_tid;
1697
1698         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1699         if (!p_fcoe->cid_count)
1700                 return;
1701
1702         p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1703         STORE_RT_REG_AGG(p_hwfn,
1704                         PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1705                         p_tid->count);
1706 }
1707
1708 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1709 {
1710         /* CDU configuration */
1711         ecore_cdu_init_common(p_hwfn);
1712 }
1713
1714 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1715 {
1716         ecore_qm_init_pf(p_hwfn);
1717         ecore_cm_init_pf(p_hwfn);
1718         ecore_dq_init_pf(p_hwfn);
1719         ecore_cdu_init_pf(p_hwfn);
1720         ecore_ilt_init_pf(p_hwfn);
1721         ecore_src_init_pf(p_hwfn);
1722         ecore_tm_init_pf(p_hwfn);
1723         ecore_prs_init_pf(p_hwfn);
1724 }
1725
1726 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1727                                            enum protocol_type type, u32 *p_cid)
1728 {
1729         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1730         u32 rel_cid;
1731
1732         if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1733                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1734                 return ECORE_INVAL;
1735         }
1736
1737         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_mngr->acquired[type].cid_map,
1738                                            p_mngr->acquired[type].max_count);
1739
1740         if (rel_cid >= p_mngr->acquired[type].max_count) {
1741                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1742                           type);
1743                 return ECORE_NORESOURCES;
1744         }
1745
1746         OSAL_SET_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1747
1748         *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1749
1750         return ECORE_SUCCESS;
1751 }
1752
1753 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1754                                         u32 cid, enum protocol_type *p_type)
1755 {
1756         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1757         struct ecore_cid_acquired_map *p_map;
1758         enum protocol_type p;
1759         u32 rel_cid;
1760
1761         /* Iterate over protocols and find matching cid range */
1762         for (p = 0; p < MAX_CONN_TYPES; p++) {
1763                 p_map = &p_mngr->acquired[p];
1764
1765                 if (!p_map->cid_map)
1766                         continue;
1767                 if (cid >= p_map->start_cid &&
1768                     cid < p_map->start_cid + p_map->max_count) {
1769                         break;
1770                 }
1771         }
1772         *p_type = p;
1773
1774         if (p == MAX_CONN_TYPES) {
1775                 DP_NOTICE(p_hwfn, true, "Invalid CID %d", cid);
1776                 return false;
1777         }
1778         rel_cid = cid - p_map->start_cid;
1779         if (!OSAL_TEST_BIT(rel_cid, p_map->cid_map)) {
1780                 DP_NOTICE(p_hwfn, true, "CID %d not acquired", cid);
1781                 return false;
1782         }
1783         return true;
1784 }
1785
1786 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1787 {
1788         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1789         enum protocol_type type;
1790         bool b_acquired;
1791         u32 rel_cid;
1792
1793         /* Test acquired and find matching per-protocol map */
1794         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, &type);
1795
1796         if (!b_acquired)
1797                 return;
1798
1799         rel_cid = cid - p_mngr->acquired[type].start_cid;
1800         OSAL_CLEAR_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1801 }
1802
1803 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1804                                             struct ecore_cxt_info *p_info)
1805 {
1806         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1807         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1808         enum protocol_type type;
1809         bool b_acquired;
1810
1811         /* Test acquired and find matching per-protocol map */
1812         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1813
1814         if (!b_acquired)
1815                 return ECORE_INVAL;
1816
1817         /* set the protocl type */
1818         p_info->type = type;
1819
1820         /* compute context virtual pointer */
1821         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1822
1823         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1824         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1825         line = p_info->iid / cxts_per_p;
1826
1827         /* Make sure context is allocated (dynamic allocation) */
1828         if (!p_mngr->ilt_shadow[line].p_virt)
1829                 return ECORE_INVAL;
1830
1831         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1832             p_info->iid % cxts_per_p * conn_cxt_size;
1833
1834         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1835                 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1836                 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1837
1838         return ECORE_SUCCESS;
1839 }
1840
1841 void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
1842 {
1843         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1844
1845         p_mgr->srq_count = num_srqs;
1846 }
1847
1848 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
1849 {
1850         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1851
1852         return p_mgr->srq_count;
1853 }
1854
1855 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1856 {
1857         /* Set the number of required CORE connections */
1858         u32 core_cids = 1;      /* SPQ */
1859
1860         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1861
1862         switch (p_hwfn->hw_info.personality) {
1863         case ECORE_PCI_ETH:
1864                 {
1865                         struct ecore_eth_pf_params *p_params =
1866                             &p_hwfn->pf_params.eth_pf_params;
1867
1868                         ecore_cxt_set_proto_cid_count(p_hwfn,
1869                                 PROTOCOLID_ETH,
1870                                 p_params->num_cons, 1); /* FIXME VF count... */
1871
1872                         break;
1873                 }
1874         default:
1875                 return ECORE_INVAL;
1876         }
1877
1878         return ECORE_SUCCESS;
1879 }
1880
1881 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
1882                                                 struct ecore_tid_mem *p_info)
1883 {
1884         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1885         u32 proto, seg, total_lines, i, shadow_line;
1886         struct ecore_ilt_client_cfg *p_cli;
1887         struct ecore_ilt_cli_blk *p_fl_seg;
1888         struct ecore_tid_seg *p_seg_info;
1889
1890         /* Verify the personality */
1891         switch (p_hwfn->hw_info.personality) {
1892         default:
1893                 return ECORE_INVAL;
1894         }
1895
1896         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1897         if (!p_cli->active)
1898                 return ECORE_INVAL;
1899
1900         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1901         if (!p_seg_info->has_fl_mem)
1902                 return ECORE_INVAL;
1903
1904         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1905         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1906                                    p_fl_seg->real_size_in_page);
1907
1908         for (i = 0; i < total_lines; i++) {
1909                 shadow_line = i + p_fl_seg->start_line -
1910                     p_hwfn->p_cxt_mngr->pf_start_line;
1911                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1912         }
1913         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1914             p_fl_seg->real_size_in_page;
1915         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1916         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1917             p_info->tid_size;
1918
1919         return ECORE_SUCCESS;
1920 }
1921
1922 /* This function is very RoCE oriented, if another protocol in the future
1923  * will want this feature we'll need to modify the function to be more generic
1924  */
1925 enum _ecore_status_t
1926 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
1927                             enum ecore_cxt_elem_type elem_type,
1928                             u32 iid)
1929 {
1930         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
1931         struct ecore_ilt_client_cfg *p_cli;
1932         struct ecore_ilt_cli_blk *p_blk;
1933         struct ecore_ptt *p_ptt;
1934         dma_addr_t p_phys;
1935         u64 ilt_hw_entry;
1936         void *p_virt;
1937         enum _ecore_status_t rc = ECORE_SUCCESS;
1938
1939         switch (elem_type) {
1940         case ECORE_ELEM_CXT:
1941                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1942                 elem_size = CONN_CXT_SIZE(p_hwfn);
1943                 p_blk = &p_cli->pf_blks[CDUC_BLK];
1944                 break;
1945         case ECORE_ELEM_SRQ:
1946                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
1947                 elem_size = SRQ_CXT_SIZE;
1948                 p_blk = &p_cli->pf_blks[SRQ_BLK];
1949                 break;
1950         case ECORE_ELEM_TASK:
1951                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1952                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
1953                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
1954                 break;
1955         default:
1956                 DP_NOTICE(p_hwfn, false,
1957                           "ECORE_INVALID elem type = %d", elem_type);
1958                 return ECORE_INVAL;
1959         }
1960
1961         /* Calculate line in ilt */
1962         hw_p_size = p_cli->p_size.val;
1963         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1964         line = p_blk->start_line + (iid / elems_per_p);
1965         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
1966
1967         /* If line is already allocated, do nothing, otherwise allocate it and
1968          * write it to the PSWRQ2 registers.
1969          * This section can be run in parallel from different contexts and thus
1970          * a mutex protection is needed.
1971          */
1972
1973         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
1974
1975         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
1976                 goto out0;
1977
1978         p_ptt = ecore_ptt_acquire(p_hwfn);
1979         if (!p_ptt) {
1980                 DP_NOTICE(p_hwfn, false,
1981                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
1982                 rc = ECORE_TIMEOUT;
1983                 goto out0;
1984         }
1985
1986         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1987                                          &p_phys,
1988                                          p_blk->real_size_in_page);
1989         if (!p_virt) {
1990                 rc = ECORE_NOMEM;
1991                 goto out1;
1992         }
1993         OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
1994
1995         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
1996         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
1997         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
1998                 p_blk->real_size_in_page;
1999
2000         /* compute absolute offset */
2001         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2002                      (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2003
2004         ilt_hw_entry = 0;
2005         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2006         SET_FIELD(ilt_hw_entry,
2007                   ILT_ENTRY_PHY_ADDR,
2008                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2009
2010 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2011
2012         ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2013                             reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2014                             0 /* no flags */);
2015
2016         if (elem_type == ECORE_ELEM_CXT) {
2017                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2018                                          elems_per_p;
2019
2020                 /* Update the relevant register in the parser */
2021                 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2022                          last_cid_allocated - 1);
2023
2024                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2025                         /* Enable RoCE search */
2026                         ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2027                         p_hwfn->b_rdma_enabled_in_prs = true;
2028                 }
2029         }
2030
2031 out1:
2032         ecore_ptt_release(p_hwfn, p_ptt);
2033 out0:
2034         OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2035
2036         return rc;
2037 }
2038
2039 /* This function is very RoCE oriented, if another protocol in the future
2040  * will want this feature we'll need to modify the function to be more generic
2041  */
2042 static enum _ecore_status_t
2043 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2044                          enum ecore_cxt_elem_type elem_type,
2045                          u32 start_iid, u32 count)
2046 {
2047         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2048         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2049         struct ecore_ilt_client_cfg *p_cli;
2050         struct ecore_ilt_cli_blk *p_blk;
2051         u32 end_iid = start_iid + count;
2052         struct ecore_ptt *p_ptt;
2053         u64 ilt_hw_entry = 0;
2054         u32 i;
2055
2056         switch (elem_type) {
2057         case ECORE_ELEM_CXT:
2058                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2059                 elem_size = CONN_CXT_SIZE(p_hwfn);
2060                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2061                 break;
2062         case ECORE_ELEM_SRQ:
2063                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2064                 elem_size = SRQ_CXT_SIZE;
2065                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2066                 break;
2067         case ECORE_ELEM_TASK:
2068                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2069                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2070                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2071                 break;
2072         default:
2073                 DP_NOTICE(p_hwfn, false,
2074                           "ECORE_INVALID elem type = %d", elem_type);
2075                 return ECORE_INVAL;
2076         }
2077
2078         /* Calculate line in ilt */
2079         hw_p_size = p_cli->p_size.val;
2080         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2081         start_line = p_blk->start_line + (start_iid / elems_per_p);
2082         end_line = p_blk->start_line + (end_iid / elems_per_p);
2083         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2084                 end_line--;
2085
2086         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2087         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2088
2089         p_ptt = ecore_ptt_acquire(p_hwfn);
2090         if (!p_ptt) {
2091                 DP_NOTICE(p_hwfn, false,
2092                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2093                 return ECORE_TIMEOUT;
2094         }
2095
2096         for (i = shadow_start_line; i < shadow_end_line; i++) {
2097                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2098                         continue;
2099
2100                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2101                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2102                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2103                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2104
2105                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2106                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2107                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2108
2109                 /* compute absolute offset */
2110                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2111                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2112                      ILT_ENTRY_IN_REGS);
2113
2114                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2115                  * wide-bus.
2116                  */
2117                 ecore_dmae_host2grc(p_hwfn, p_ptt,
2118                                     (u64)(osal_uintptr_t)&ilt_hw_entry,
2119                                     reg_offset,
2120                                     sizeof(ilt_hw_entry) / sizeof(u32),
2121                                     0 /* no flags */);
2122         }
2123
2124         ecore_ptt_release(p_hwfn, p_ptt);
2125
2126         return ECORE_SUCCESS;
2127 }
2128
2129 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2130                                               enum protocol_type proto)
2131 {
2132         enum _ecore_status_t rc;
2133         u32 cid;
2134
2135         /* Free Connection CXT */
2136         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2137                                       ecore_cxt_get_proto_cid_start(p_hwfn,
2138                                                                     proto),
2139                                       ecore_cxt_get_proto_cid_count(p_hwfn,
2140                                                                     proto,
2141                                                                     &cid));
2142
2143         if (rc)
2144                 return rc;
2145
2146         /* Free Task CXT */
2147         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2148                                       ecore_cxt_get_proto_tid_count(p_hwfn,
2149                                                                     proto));
2150         if (rc)
2151                 return rc;
2152
2153         /* Free TSDM CXT */
2154         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2155                                       ecore_cxt_get_srq_count(p_hwfn));
2156
2157         return rc;
2158 }
2159
2160 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
2161                                             u32 tid,
2162                                             u8 ctx_type, void **pp_task_ctx)
2163 {
2164         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2165         struct ecore_ilt_client_cfg *p_cli;
2166         struct ecore_ilt_cli_blk *p_seg;
2167         struct ecore_tid_seg *p_seg_info;
2168         u32 proto, seg;
2169         u32 total_lines;
2170         u32 tid_size, ilt_idx;
2171         u32 num_tids_per_block;
2172
2173         /* Verify the personality */
2174         switch (p_hwfn->hw_info.personality) {
2175         default:
2176                 return ECORE_INVAL;
2177         }
2178
2179         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2180         if (!p_cli->active)
2181                 return ECORE_INVAL;
2182
2183         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2184
2185         if (ctx_type == ECORE_CTX_WORKING_MEM) {
2186                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2187         } else if (ctx_type == ECORE_CTX_FL_MEM) {
2188                 if (!p_seg_info->has_fl_mem)
2189                         return ECORE_INVAL;
2190                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2191         } else {
2192                 return ECORE_INVAL;
2193         }
2194         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2195         tid_size = p_mngr->task_type_size[p_seg_info->type];
2196         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2197
2198         if (total_lines < tid / num_tids_per_block)
2199                 return ECORE_INVAL;
2200
2201         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2202             p_mngr->pf_start_line;
2203         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2204             (tid % num_tids_per_block) * tid_size;
2205
2206         return ECORE_SUCCESS;
2207 }