drivers/net/qede/base/ecore_cxt.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_hsi_common.h"
  12 #include "ecore_hsi_eth.h"
  13 #include "ecore_rt_defs.h"
  14 #include "ecore_status.h"
  15 #include "ecore.h"
  16 #include "ecore_init_ops.h"
  17 #include "ecore_init_fw_funcs.h"
  18 #include "ecore_cxt.h"
  19 #include "ecore_hw.h"
  20 #include "ecore_dev_api.h"
  21 #include "ecore_sriov.h"
  22
  23 /* Max number of connection types in HW (DQ/CDU etc.) */
  24 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  25 #define NUM_TASK_TYPES          2
  26 #define NUM_TASK_PF_SEGMENTS    4
  27 #define NUM_TASK_VF_SEGMENTS    1
  28
  29 /* Doorbell-Queue constants */
  30 #define DQ_RANGE_SHIFT  4
  31 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  32
  33 /* Searcher constants */
  34 #define SRC_MIN_NUM_ELEMS 256
  35
  36 /* Timers constants */
  37 #define TM_SHIFT        7
  38 #define TM_ALIGN        (1 << TM_SHIFT)
  39 #define TM_ELEM_SIZE    4
  40
  41 /* ILT constants */
  42 /* If for some reason, HW P size is modified to be less than 32K,
  43  * special handling needs to be made for CDU initialization
  44  */
  45 #define ILT_DEFAULT_HW_P_SIZE   3
  46
  47 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  48 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  49
  50 /* ILT entry structure */
  51 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  52 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  53 #define ILT_ENTRY_VALID_MASK            0x1ULL
  54 #define ILT_ENTRY_VALID_SHIFT           52
  55 #define ILT_ENTRY_IN_REGS               2
  56 #define ILT_REG_SIZE_IN_BYTES           4
  57
  58 /* connection context union */
  59 union conn_context {
  60         struct core_conn_context core_ctx;
  61         struct eth_conn_context eth_ctx;
  62 };
  63
  64 /* TYPE-0 task context - iSCSI, FCOE */
  65 union type0_task_context {
  66 };
  67
  68 /* TYPE-1 task context - ROCE */
  69 union type1_task_context {
  70 };
  71
  72 struct src_ent {
  73         u8 opaque[56];
  74         u64 next;
  75 };
  76
  77 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  78 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  79
  80 #define CONN_CXT_SIZE(p_hwfn) \
  81         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  82
  83 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
  84
  85 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
  86         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
  87
  88 /* Alignment is inherent to the type1_task_context structure */
  89 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
  90
  91 /* PF per protocl configuration object */
  92 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
  93 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
  94
  95 struct ecore_tid_seg {
  96         u32 count;
  97         u8 type;
  98         bool has_fl_mem;
  99 };
 100
 101 struct ecore_conn_type_cfg {
 102         u32 cid_count;
 103         u32 cid_start;
 104         u32 cids_per_vf;
 105         struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
 106 };
 107
 108 /* ILT Client configuration,
 109  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
 110  * 1 - for connection context (CDUC) and for each task context we need two
 111  * values, for regular task context and for force load memory
 112  */
 113 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 114 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 115 #define CDUC_BLK                (0)
 116 #define SRQ_BLK                 (0)
 117 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 118 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 119
 120 enum ilt_clients {
 121         ILT_CLI_CDUC,
 122         ILT_CLI_CDUT,
 123         ILT_CLI_QM,
 124         ILT_CLI_TM,
 125         ILT_CLI_SRC,
 126         ILT_CLI_TSDM,
 127         ILT_CLI_MAX
 128 };
 129
 130 struct ilt_cfg_pair {
 131         u32 reg;
 132         u32 val;
 133 };
 134
 135 struct ecore_ilt_cli_blk {
 136         u32 total_size;         /* 0 means not active */
 137         u32 real_size_in_page;
 138         u32 start_line;
 139         u32 dynamic_line_cnt;
 140 };
 141
 142 struct ecore_ilt_client_cfg {
 143         bool active;
 144
 145         /* ILT boundaries */
 146         struct ilt_cfg_pair first;
 147         struct ilt_cfg_pair last;
 148         struct ilt_cfg_pair p_size;
 149
 150         /* ILT client blocks for PF */
 151         struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 152         u32 pf_total_lines;
 153
 154         /* ILT client blocks for VFs */
 155         struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 156         u32 vf_total_lines;
 157 };
 158
 159 /* Per Path -
 160  *      ILT shadow table
 161  *      Protocol acquired CID lists
 162  *      PF start line in ILT
 163  */
 164 struct ecore_dma_mem {
 165         dma_addr_t p_phys;
 166         void *p_virt;
 167         osal_size_t size;
 168 };
 169
 170 #define MAP_WORD_SIZE           sizeof(unsigned long)
 171 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 172
 173 struct ecore_cid_acquired_map {
 174         u32 start_cid;
 175         u32 max_count;
 176         unsigned long *cid_map;
 177 };
 178
 179 struct ecore_cxt_mngr {
 180         /* Per protocl configuration */
 181         struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
 182
 183         /* computed ILT structure */
 184         struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
 185
 186         /* Task type sizes */
 187         u32 task_type_size[NUM_TASK_TYPES];
 188
 189         /* total number of VFs for this hwfn -
 190          * ALL VFs are symmetric in terms of HW resources
 191          */
 192         u32 vf_count;
 193
 194         /* total number of SRQ's for this hwfn */
 195         u32                             srq_count;
 196
 197         /* Acquired CIDs */
 198         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 199
 200         /* ILT  shadow table */
 201         struct ecore_dma_mem *ilt_shadow;
 202         u32 pf_start_line;
 203
 204         /* Mutex for a dynamic ILT allocation */
 205         osal_mutex_t mutex;
 206
 207         /* SRC T2 */
 208         struct ecore_dma_mem *t2;
 209         u32 t2_num_pages;
 210         u64 first_free;
 211         u64 last_free;
 212 };
 213
 214 /* check if resources/configuration is required according to protocol type */
 215 static OSAL_INLINE bool src_proto(enum protocol_type type)
 216 {
 217         return type == PROTOCOLID_TOE;
 218 }
 219
 220 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
 221 {
 222         return type == PROTOCOLID_TOE;
 223 }
 224
 225 static bool tm_tid_proto(enum protocol_type type)
 226 {
 227         return type == PROTOCOLID_FCOE;
 228 }
 229
 230 /* counts the iids for the CDU/CDUC ILT client configuration */
 231 struct ecore_cdu_iids {
 232         u32 pf_cids;
 233         u32 per_vf_cids;
 234 };
 235
 236 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
 237                                struct ecore_cdu_iids *iids)
 238 {
 239         u32 type;
 240
 241         for (type = 0; type < MAX_CONN_TYPES; type++) {
 242                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 243                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 244         }
 245 }
 246
 247 /* counts the iids for the Searcher block configuration */
 248 struct ecore_src_iids {
 249         u32 pf_cids;
 250         u32 per_vf_cids;
 251 };
 252
 253 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
 254                                            struct ecore_src_iids *iids)
 255 {
 256         u32 i;
 257
 258         for (i = 0; i < MAX_CONN_TYPES; i++) {
 259                 if (!src_proto(i))
 260                         continue;
 261
 262                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 263                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 264         }
 265 }
 266
 267 /* counts the iids for the Timers block configuration */
 268 struct ecore_tm_iids {
 269         u32 pf_cids;
 270         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 271         u32 pf_tids_total;
 272         u32 per_vf_cids;
 273         u32 per_vf_tids;
 274 };
 275
 276 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
 277                                           struct ecore_tm_iids *iids)
 278 {
 279         bool tm_vf_required = false;
 280         bool tm_required = false;
 281         u32 i, j;
 282
 283         for (i = 0; i < MAX_CONN_TYPES; i++) {
 284                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 285
 286                 if (tm_cid_proto(i) || tm_required) {
 287                         if (p_cfg->cid_count)
 288                                 tm_required = true;
 289
 290                         iids->pf_cids += p_cfg->cid_count;
 291                 }
 292
 293                 if (tm_cid_proto(i) || tm_vf_required) {
 294                         if (p_cfg->cids_per_vf)
 295                                 tm_vf_required = true;
 296
 297                 }
 298
 299                 if (tm_tid_proto(i)) {
 300                         struct ecore_tid_seg *segs = p_cfg->tid_seg;
 301
 302                         /* for each segment there is at most one
 303                          * protocol for which count is not 0.
 304                          */
 305                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 306                                 iids->pf_tids[j] += segs[j].count;
 307
 308                         /* The last array elelment is for the VFs. As for PF
 309                          * segments there can be only one protocol for
 310                          * which this value is not 0.
 311                          */
 312                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 313                 }
 314         }
 315
 316         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 317         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 318         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 319
 320         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 321                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 322                 iids->pf_tids_total += iids->pf_tids[j];
 323         }
 324 }
 325
 326 void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids)
 327 {
 328         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 329         struct ecore_tid_seg *segs;
 330         u32 vf_cids = 0, type, j;
 331         u32 vf_tids = 0;
 332
 333         for (type = 0; type < MAX_CONN_TYPES; type++) {
 334                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 335                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 336
 337                 segs = p_mngr->conn_cfg[type].tid_seg;
 338                 /* for each segment there is at most one
 339                  * protocol for which count is not 0.
 340                  */
 341                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 342                         iids->tids += segs[j].count;
 343
 344                 /* The last array elelment is for the VFs. As for PF
 345                  * segments there can be only one protocol for
 346                  * which this value is not 0.
 347                  */
 348                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 349         }
 350
 351         iids->vf_cids += vf_cids * p_mngr->vf_count;
 352         iids->tids += vf_tids * p_mngr->vf_count;
 353
 354         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 355                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 356                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 357 }
 358
 359 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
 360                                                     u32 seg)
 361 {
 362         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 363         u32 i;
 364
 365         /* Find the protocol with tid count > 0 for this segment.
 366          * Note: there can only be one and this is already validated.
 367          */
 368         for (i = 0; i < MAX_CONN_TYPES; i++) {
 369                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 370                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 371         }
 372         return OSAL_NULL;
 373 }
 374
 375 /* set the iids (cid/tid) count per protocol */
 376 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 377                                    enum protocol_type type,
 378                                    u32 cid_count, u32 vf_cid_cnt)
 379 {
 380         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 381         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 382
 383         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 384         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 385 }
 386
 387 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
 388                                   enum protocol_type type, u32 *vf_cid)
 389 {
 390         if (vf_cid)
 391                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 392
 393         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 394 }
 395
 396 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
 397                                   enum protocol_type type)
 398 {
 399         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 400 }
 401
 402 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 403                                          enum protocol_type type)
 404 {
 405         u32 cnt = 0;
 406         int i;
 407
 408         for (i = 0; i < TASK_SEGMENTS; i++)
 409                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 410
 411         return cnt;
 412 }
 413
 414 static OSAL_INLINE void
 415 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 416                               enum protocol_type proto,
 417                               u8 seg, u8 seg_type, u32 count, bool has_fl)
 418 {
 419         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 420         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 421
 422         p_seg->count = count;
 423         p_seg->has_fl_mem = has_fl;
 424         p_seg->type = seg_type;
 425 }
 426
 427 /* the *p_line parameter must be either 0 for the first invocation or the
 428  * value returned in the previous invocation.
 429  */
 430 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
 431                                    struct ecore_ilt_cli_blk *p_blk,
 432                                    u32 start_line,
 433                                    u32 total_size, u32 elem_size)
 434 {
 435         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 436
 437         /* verify that it's called once for each block */
 438         if (p_blk->total_size)
 439                 return;
 440
 441         p_blk->total_size = total_size;
 442         p_blk->real_size_in_page = 0;
 443         if (elem_size)
 444                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 445         p_blk->start_line = start_line;
 446 }
 447
 448 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
 449                                    struct ecore_ilt_client_cfg *p_cli,
 450                                    struct ecore_ilt_cli_blk *p_blk,
 451                                    u32 *p_line, enum ilt_clients client_id)
 452 {
 453         if (!p_blk->total_size)
 454                 return;
 455
 456         if (!p_cli->active)
 457                 p_cli->first.val = *p_line;
 458
 459         p_cli->active = true;
 460         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 461         p_cli->last.val = *p_line - 1;
 462
 463         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 464                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
 465                    " [Real %08x] Start line %d\n",
 466                    client_id, p_cli->first.val, p_cli->last.val,
 467                    p_blk->total_size, p_blk->real_size_in_page,
 468                    p_blk->start_line);
 469 }
 470
 471 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 472                                           enum ilt_clients ilt_client)
 473 {
 474         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 475         struct ecore_ilt_client_cfg *p_cli;
 476         u32 lines_to_skip = 0;
 477         u32 cxts_per_p;
 478
 479         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 480
 481         if (ilt_client == ILT_CLI_CDUC) {
 482                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 483
 484                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 485                     (u32)CONN_CXT_SIZE(p_hwfn);
 486
 487                 lines_to_skip = cid_count / cxts_per_p;
 488         }
 489
 490         return lines_to_skip;
 491 }
 492
 493 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
 494 {
 495         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 496         u32 curr_line, total, i, task_size, line;
 497         struct ecore_ilt_client_cfg *p_cli;
 498         struct ecore_ilt_cli_blk *p_blk;
 499         struct ecore_cdu_iids cdu_iids;
 500         struct ecore_src_iids src_iids;
 501         struct ecore_qm_iids qm_iids;
 502         struct ecore_tm_iids tm_iids;
 503         struct ecore_tid_seg *p_seg;
 504
 505         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 506         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 507         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 508         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 509
 510         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 511
 512         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 513                    "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
 514                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 515
 516         /* CDUC */
 517         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 518
 519         curr_line = p_mngr->pf_start_line;
 520
 521         /* CDUC PF */
 522         p_cli->pf_total_lines = 0;
 523
 524         /* get the counters for the CDUC,CDUC and QM clients  */
 525         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 526
 527         p_blk = &p_cli->pf_blks[CDUC_BLK];
 528
 529         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 530
 531         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 532                                total, CONN_CXT_SIZE(p_hwfn));
 533
 534         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 535         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 536
 537         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 538                                                                  ILT_CLI_CDUC);
 539
 540         /* CDUC VF */
 541         p_blk = &p_cli->vf_blks[CDUC_BLK];
 542         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 543
 544         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 545                                total, CONN_CXT_SIZE(p_hwfn));
 546
 547         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 548         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 549
 550         for (i = 1; i < p_mngr->vf_count; i++)
 551                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 552                                        ILT_CLI_CDUC);
 553
 554         /* CDUT PF */
 555         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 556         p_cli->first.val = curr_line;
 557
 558         /* first the 'working' task memory */
 559         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 560                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 561                 if (!p_seg || p_seg->count == 0)
 562                         continue;
 563
 564                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 565                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 566                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 567                                        p_mngr->task_type_size[p_seg->type]);
 568
 569                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 570                                        ILT_CLI_CDUT);
 571         }
 572
 573         /* next the 'init' task memory (forced load memory) */
 574         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 575                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 576                 if (!p_seg || p_seg->count == 0)
 577                         continue;
 578
 579                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 580
 581                 if (!p_seg->has_fl_mem) {
 582                         /* The segment is active (total size pf 'working'
 583                          * memory is > 0) but has no FL (forced-load, Init)
 584                          * memory. Thus:
 585                          *
 586                          * 1.   The total-size in the corrsponding FL block of
 587                          *      the ILT client is set to 0 - No ILT line are
 588                          *      provisioned and no ILT memory allocated.
 589                          *
 590                          * 2.   The start-line of said block is set to the
 591                          *      start line of the matching working memory
 592                          *      block in the ILT client. This is later used to
 593                          *      configure the CDU segment offset registers and
 594                          *      results in an FL command for TIDs of this
 595                          *      segment behaves as regular load commands
 596                          *      (loading TIDs from the working memory).
 597                          */
 598                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 599
 600                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 601                         continue;
 602                 }
 603                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 604
 605                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 606                                        curr_line, total,
 607                                        p_mngr->task_type_size[p_seg->type]);
 608
 609                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 610                                        ILT_CLI_CDUT);
 611         }
 612         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 613
 614         /* CDUT VF */
 615         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 616         if (p_seg && p_seg->count) {
 617                 /* Stricly speaking we need to iterate over all VF
 618                  * task segment types, but a VF has only 1 segment
 619                  */
 620
 621                 /* 'working' memory */
 622                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 623
 624                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 625                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 626                                        curr_line, total,
 627                                        p_mngr->task_type_size[p_seg->type]);
 628
 629                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 630                                        ILT_CLI_CDUT);
 631
 632                 /* 'init' memory */
 633                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 634                 if (!p_seg->has_fl_mem) {
 635                         /* see comment above */
 636                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 637                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 638                 } else {
 639                         task_size = p_mngr->task_type_size[p_seg->type];
 640                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 641                                                curr_line, total, task_size);
 642                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 643                                                ILT_CLI_CDUT);
 644                 }
 645                 p_cli->vf_total_lines = curr_line -
 646                     p_cli->vf_blks[0].start_line;
 647
 648                 /* Now for the rest of the VFs */
 649                 for (i = 1; i < p_mngr->vf_count; i++) {
 650                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 651                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 652                                                ILT_CLI_CDUT);
 653
 654                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 655                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 656                                                ILT_CLI_CDUT);
 657                 }
 658         }
 659
 660         /* QM */
 661         p_cli = &p_mngr->clients[ILT_CLI_QM];
 662         p_blk = &p_cli->pf_blks[0];
 663
 664         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 665         total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 666                                      qm_iids.vf_cids, qm_iids.tids,
 667                                      p_hwfn->qm_info.num_pqs,
 668                                      p_hwfn->qm_info.num_vf_pqs);
 669
 670         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 671                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
 672                    " num_vf_pqs=%d, memory_size=%d)\n",
 673                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 674                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 675
 676         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 677                                QM_PQ_ELEMENT_SIZE);
 678
 679         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 680         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 681
 682         /* SRC */
 683         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 684         ecore_cxt_src_iids(p_mngr, &src_iids);
 685
 686         /* Both the PF and VFs searcher connections are stored in the per PF
 687          * database. Thus sum the PF searcher cids and all the VFs searcher
 688          * cids.
 689          */
 690         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 691         if (total) {
 692                 u32 local_max = OSAL_MAX_T(u32, total,
 693                                            SRC_MIN_NUM_ELEMS);
 694
 695                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 696
 697                 p_blk = &p_cli->pf_blks[0];
 698                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 699                                        total * sizeof(struct src_ent),
 700                                        sizeof(struct src_ent));
 701
 702                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 703                                        ILT_CLI_SRC);
 704                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 705         }
 706
 707         /* TM PF */
 708         p_cli = &p_mngr->clients[ILT_CLI_TM];
 709         ecore_cxt_tm_iids(p_mngr, &tm_iids);
 710         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 711         if (total) {
 712                 p_blk = &p_cli->pf_blks[0];
 713                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 714                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 715
 716                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 717                                        ILT_CLI_TM);
 718                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 719         }
 720
 721         /* TM VF */
 722         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 723         if (total) {
 724                 p_blk = &p_cli->vf_blks[0];
 725                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 726                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 727
 728                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 729                                        ILT_CLI_TM);
 730
 731                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 732                 for (i = 1; i < p_mngr->vf_count; i++) {
 733                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 734                                                ILT_CLI_TM);
 735                 }
 736         }
 737
 738         /* TSDM (SRQ CONTEXT) */
 739         total = ecore_cxt_get_srq_count(p_hwfn);
 740
 741         if (total) {
 742                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 743                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 744                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 745                                        total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 746
 747                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 748                                        ILT_CLI_TSDM);
 749                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 750         }
 751
 752         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 753             RESC_NUM(p_hwfn, ECORE_ILT)) {
 754                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 755                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 756                 return ECORE_INVAL;
 757         }
 758
 759         return ECORE_SUCCESS;
 760 }
 761
 762 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 763 {
 764         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 765         u32 i;
 766
 767         if (!p_mngr->t2)
 768                 return;
 769
 770         for (i = 0; i < p_mngr->t2_num_pages; i++)
 771                 if (p_mngr->t2[i].p_virt)
 772                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 773                                                p_mngr->t2[i].p_virt,
 774                                                p_mngr->t2[i].p_phys,
 775                                                p_mngr->t2[i].size);
 776
 777         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 778 }
 779
 780 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 781 {
 782         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 783         u32 conn_num, total_size, ent_per_page, psz, i;
 784         struct ecore_ilt_client_cfg *p_src;
 785         struct ecore_src_iids src_iids;
 786         struct ecore_dma_mem *p_t2;
 787         enum _ecore_status_t rc;
 788
 789         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 790
 791         /* if the SRC ILT client is inactive - there are no connection
 792          * requiring the searcer, leave.
 793          */
 794         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 795         if (!p_src->active)
 796                 return ECORE_SUCCESS;
 797
 798         ecore_cxt_src_iids(p_mngr, &src_iids);
 799         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 800         total_size = conn_num * sizeof(struct src_ent);
 801
 802         /* use the same page size as the SRC ILT client */
 803         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 804         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 805
 806         /* allocate t2 */
 807         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 808                                  p_mngr->t2_num_pages *
 809                                  sizeof(struct ecore_dma_mem));
 810         if (!p_mngr->t2) {
 811                 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
 812                 rc = ECORE_NOMEM;
 813                 goto t2_fail;
 814         }
 815
 816         /* allocate t2 pages */
 817         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 818                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 819                 void **p_virt = &p_mngr->t2[i].p_virt;
 820
 821                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 822                                                   &p_mngr->t2[i].p_phys, size);
 823                 if (!p_mngr->t2[i].p_virt) {
 824                         rc = ECORE_NOMEM;
 825                         goto t2_fail;
 826                 }
 827                 OSAL_MEM_ZERO(*p_virt, size);
 828                 p_mngr->t2[i].size = size;
 829                 total_size -= size;
 830         }
 831
 832         /* Set the t2 pointers */
 833
 834         /* entries per page - must be a power of two */
 835         ent_per_page = psz / sizeof(struct src_ent);
 836
 837         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 838
 839         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 840         p_mngr->last_free = (u64)p_t2->p_phys +
 841             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 842
 843         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 844                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
 845                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 846                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
 847                 u32 j;
 848
 849                 for (j = 0; j < ent_num - 1; j++) {
 850                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 851                         entries[j].next = OSAL_CPU_TO_BE64(val);
 852                 }
 853
 854                 if (i < p_mngr->t2_num_pages - 1)
 855                         val = (u64)p_mngr->t2[i + 1].p_phys;
 856                 else
 857                         val = 0;
 858                 entries[j].next = OSAL_CPU_TO_BE64(val);
 859
 860                 conn_num -= ent_num;
 861         }
 862
 863         return ECORE_SUCCESS;
 864
 865 t2_fail:
 866         ecore_cxt_src_t2_free(p_hwfn);
 867         return rc;
 868 }
 869
 870 #define for_each_ilt_valid_client(pos, clients)         \
 871         for (pos = 0; pos < ILT_CLI_MAX; pos++)         \
 872                 if (!clients[pos].active) {             \
 873                         continue;                       \
 874                 } else                                  \
 875
 876
 877 /* Total number of ILT lines used by this PF */
 878 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
 879 {
 880         u32 size = 0;
 881         u32 i;
 882
 883         for_each_ilt_valid_client(i, ilt_clients)
 884                 size += (ilt_clients[i].last.val -
 885                          ilt_clients[i].first.val + 1);
 886
 887         return size;
 888 }
 889
 890 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
 891 {
 892         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 893         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 894         u32 ilt_size, i;
 895
 896         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
 897
 898         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 899                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 900
 901                 if (p_dma->p_virt)
 902                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 903                                                p_dma->p_virt,
 904                                                p_dma->p_phys, p_dma->size);
 905                 p_dma->p_virt = OSAL_NULL;
 906         }
 907         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
 908 }
 909
 910 static enum _ecore_status_t
 911 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
 912                     struct ecore_ilt_cli_blk *p_blk,
 913                     enum ilt_clients ilt_client, u32 start_line_offset)
 914 {
 915         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 916         u32 lines, line, sz_left, lines_to_skip = 0;
 917
 918         /* Special handling for RoCE that supports dynamic allocation */
 919         if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
 920                 return ECORE_SUCCESS;
 921
 922         lines_to_skip = p_blk->dynamic_line_cnt;
 923
 924         if (!p_blk->total_size)
 925                 return ECORE_SUCCESS;
 926
 927         sz_left = p_blk->total_size;
 928         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 929         line = p_blk->start_line + start_line_offset -
 930             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 931
 932         for (; lines; lines--) {
 933                 dma_addr_t p_phys;
 934                 void *p_virt;
 935                 u32 size;
 936
 937                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
 938
 939 /* @DPDK */
 940 #define ILT_BLOCK_ALIGN_SIZE 0x1000
 941                 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
 942                                                          &p_phys, size,
 943                                                          ILT_BLOCK_ALIGN_SIZE);
 944                 if (!p_virt)
 945                         return ECORE_NOMEM;
 946                 OSAL_MEM_ZERO(p_virt, size);
 947
 948                 ilt_shadow[line].p_phys = p_phys;
 949                 ilt_shadow[line].p_virt = p_virt;
 950                 ilt_shadow[line].size = size;
 951
 952                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 953                            "ILT shadow: Line [%d] Physical 0x%lx"
 954                            " Virtual %p Size %d\n",
 955                            line, (unsigned long)p_phys, p_virt, size);
 956
 957                 sz_left -= size;
 958                 line++;
 959         }
 960
 961         return ECORE_SUCCESS;
 962 }
 963
 964 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
 965 {
 966         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 967         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
 968         struct ecore_ilt_cli_blk *p_blk;
 969         u32 size, i, j, k;
 970         enum _ecore_status_t rc;
 971
 972         size = ecore_cxt_ilt_shadow_size(clients);
 973         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 974                                          size * sizeof(struct ecore_dma_mem));
 975
 976         if (!p_mngr->ilt_shadow) {
 977                 DP_NOTICE(p_hwfn, true,
 978                           "Failed to allocate ilt shadow table\n");
 979                 rc = ECORE_NOMEM;
 980                 goto ilt_shadow_fail;
 981         }
 982
 983         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 984                    "Allocated 0x%x bytes for ilt shadow\n",
 985                    (u32)(size * sizeof(struct ecore_dma_mem)));
 986
 987         for_each_ilt_valid_client(i, clients) {
 988                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
 989                         p_blk = &clients[i].pf_blks[j];
 990                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
 991                         if (rc != ECORE_SUCCESS)
 992                                 goto ilt_shadow_fail;
 993                 }
 994                 for (k = 0; k < p_mngr->vf_count; k++) {
 995                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
 996                                 u32 lines = clients[i].vf_total_lines * k;
 997
 998                                 p_blk = &clients[i].vf_blks[j];
 999                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1000                                                          i, lines);
1001                                 if (rc != ECORE_SUCCESS)
1002                                         goto ilt_shadow_fail;
1003                         }
1004                 }
1005         }
1006
1007         return ECORE_SUCCESS;
1008
1009 ilt_shadow_fail:
1010         ecore_ilt_shadow_free(p_hwfn);
1011         return rc;
1012 }
1013
1014 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1015 {
1016         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1017         u32 type;
1018
1019         for (type = 0; type < MAX_CONN_TYPES; type++) {
1020                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1021                 p_mngr->acquired[type].max_count = 0;
1022                 p_mngr->acquired[type].start_cid = 0;
1023         }
1024 }
1025
1026 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1027 {
1028         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1029         u32 start_cid = 0;
1030         u32 type;
1031
1032         for (type = 0; type < MAX_CONN_TYPES; type++) {
1033                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1034                 u32 size;
1035
1036                 if (cid_cnt == 0)
1037                         continue;
1038
1039                 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD);
1040                 p_mngr->acquired[type].cid_map = OSAL_ZALLOC(p_hwfn->p_dev,
1041                                                              GFP_KERNEL, size);
1042                 if (!p_mngr->acquired[type].cid_map)
1043                         goto cid_map_fail;
1044
1045                 p_mngr->acquired[type].max_count = cid_cnt;
1046                 p_mngr->acquired[type].start_cid = start_cid;
1047
1048                 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1049
1050                 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1051                            "Type %08x start: %08x count %08x\n",
1052                            type, p_mngr->acquired[type].start_cid,
1053                            p_mngr->acquired[type].max_count);
1054                 start_cid += cid_cnt;
1055         }
1056
1057         return ECORE_SUCCESS;
1058
1059 cid_map_fail:
1060         ecore_cid_map_free(p_hwfn);
1061         return ECORE_NOMEM;
1062 }
1063
1064 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1065 {
1066         struct ecore_ilt_client_cfg *clients;
1067         struct ecore_cxt_mngr *p_mngr;
1068         u32 i;
1069
1070         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1071         if (!p_mngr) {
1072                 DP_NOTICE(p_hwfn, true,
1073                           "Failed to allocate `struct ecore_cxt_mngr'\n");
1074                 return ECORE_NOMEM;
1075         }
1076
1077         /* Initialize ILT client registers */
1078         clients = p_mngr->clients;
1079         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1080         clients[ILT_CLI_CDUC].last.reg  = ILT_CFG_REG(CDUC, LAST_ILT);
1081         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1082
1083         clients[ILT_CLI_QM].first.reg   = ILT_CFG_REG(QM, FIRST_ILT);
1084         clients[ILT_CLI_QM].last.reg    = ILT_CFG_REG(QM, LAST_ILT);
1085         clients[ILT_CLI_QM].p_size.reg  = ILT_CFG_REG(QM, P_SIZE);
1086
1087         clients[ILT_CLI_TM].first.reg   = ILT_CFG_REG(TM, FIRST_ILT);
1088         clients[ILT_CLI_TM].last.reg    = ILT_CFG_REG(TM, LAST_ILT);
1089         clients[ILT_CLI_TM].p_size.reg  = ILT_CFG_REG(TM, P_SIZE);
1090
1091         clients[ILT_CLI_SRC].first.reg  = ILT_CFG_REG(SRC, FIRST_ILT);
1092         clients[ILT_CLI_SRC].last.reg   = ILT_CFG_REG(SRC, LAST_ILT);
1093         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1094
1095         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1096         clients[ILT_CLI_CDUT].last.reg  = ILT_CFG_REG(CDUT, LAST_ILT);
1097         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1098
1099         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1100         clients[ILT_CLI_TSDM].last.reg  = ILT_CFG_REG(TSDM, LAST_ILT);
1101         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1102
1103         /* default ILT page size for all clients is 32K */
1104         for (i = 0; i < ILT_CLI_MAX; i++)
1105                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1106
1107         /* due to removal of ISCSI/FCoE files union type0_task_context
1108          * task_type_size will be 0. So hardcoded for now.
1109          */
1110         p_mngr->task_type_size[0] = 512; /* @DPDK */
1111         p_mngr->task_type_size[1] = 128; /* @DPDK */
1112
1113         if (p_hwfn->p_dev->p_iov_info)
1114                 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1115
1116         /* Initialize the dynamic ILT allocation mutex */
1117         OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1118         OSAL_MUTEX_INIT(&p_mngr->mutex);
1119
1120         /* Set the cxt mangr pointer priori to further allocations */
1121         p_hwfn->p_cxt_mngr = p_mngr;
1122
1123         return ECORE_SUCCESS;
1124 }
1125
1126 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1127 {
1128         enum _ecore_status_t rc;
1129
1130         /* Allocate the ILT shadow table */
1131         rc = ecore_ilt_shadow_alloc(p_hwfn);
1132         if (rc) {
1133                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1134                 goto tables_alloc_fail;
1135         }
1136
1137         /* Allocate the T2  table */
1138         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1139         if (rc) {
1140                 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1141                 goto tables_alloc_fail;
1142         }
1143
1144         /* Allocate and initialize the acquired cids bitmaps */
1145         rc = ecore_cid_map_alloc(p_hwfn);
1146         if (rc) {
1147                 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1148                 goto tables_alloc_fail;
1149         }
1150
1151         return ECORE_SUCCESS;
1152
1153 tables_alloc_fail:
1154         ecore_cxt_mngr_free(p_hwfn);
1155         return rc;
1156 }
1157
1158 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1159 {
1160         if (!p_hwfn->p_cxt_mngr)
1161                 return;
1162
1163         ecore_cid_map_free(p_hwfn);
1164         ecore_cxt_src_t2_free(p_hwfn);
1165         ecore_ilt_shadow_free(p_hwfn);
1166         OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1167         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1168 }
1169
1170 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1171 {
1172         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1173         int type;
1174
1175         /* Reset acquired cids */
1176         for (type = 0; type < MAX_CONN_TYPES; type++) {
1177                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1178                 u32 i;
1179
1180                 if (cid_cnt == 0)
1181                         continue;
1182
1183                 for (i = 0; i < DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD); i++)
1184                         p_mngr->acquired[type].cid_map[i] = 0;
1185         }
1186 }
1187
1188 /* HW initialization helper (per Block, per phase) */
1189
1190 /* CDU Common */
1191 #define CDUC_CXT_SIZE_SHIFT                                             \
1192         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1193
1194 #define CDUC_CXT_SIZE_MASK                                              \
1195         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1196
1197 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1198         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1199
1200 #define CDUC_BLOCK_WASTE_MASK                                           \
1201         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1202
1203 #define CDUC_NCIB_SHIFT                                                 \
1204         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1205
1206 #define CDUC_NCIB_MASK                                                  \
1207         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1208
1209 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1210         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1211
1212 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1213         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1214         CDUT_TYPE0_CXT_SIZE_SHIFT)
1215
1216 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1217         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1218
1219 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1220         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1221         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1222
1223 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1224         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1225
1226 #define CDUT_TYPE0_NCIB_MASK                                            \
1227         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1228         CDUT_TYPE0_NCIB_SHIFT)
1229
1230 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1231         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1232
1233 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1234         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1235         CDUT_TYPE1_CXT_SIZE_SHIFT)
1236
1237 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1238         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1239
1240 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1241         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1242         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1243
1244 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1245         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1246
1247 #define CDUT_TYPE1_NCIB_MASK                                            \
1248         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1249         CDUT_TYPE1_NCIB_SHIFT)
1250
1251 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1252 {
1253         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1254
1255         /* CDUC - connection configuration */
1256         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1257         cxt_size = CONN_CXT_SIZE(p_hwfn);
1258         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1259         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1260
1261         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1262         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1263         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1264         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1265
1266         /* CDUT - type-0 tasks configuration */
1267         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1268         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1269         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1270         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1271
1272         /* cxt size and block-waste are multipes of 8 */
1273         cdu_params = 0;
1274         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1275         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1276         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1277         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1278
1279         /* CDUT - type-1 tasks configuration */
1280         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1281         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1282         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1283
1284         /* cxt size and block-waste are multipes of 8 */
1285         cdu_params = 0;
1286         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1287         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1288         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1289         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1290 }
1291
1292 /* CDU PF */
1293 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1294 #define CDU_SEG_REG_TYPE_MASK           0x1
1295 #define CDU_SEG_REG_OFFSET_SHIFT        0
1296 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1297
1298 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1299 {
1300         struct ecore_ilt_client_cfg *p_cli;
1301         struct ecore_tid_seg *p_seg;
1302         u32 cdu_seg_params, offset;
1303         int i;
1304
1305         static const u32 rt_type_offset_arr[] = {
1306                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1307                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1308                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1309                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1310         };
1311
1312         static const u32 rt_type_offset_fl_arr[] = {
1313                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1314                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1315                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1316                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1317         };
1318
1319         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1320
1321         /* There are initializations only for CDUT during pf Phase */
1322         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1323                 /* Segment 0 */
1324                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1325                 if (!p_seg)
1326                         continue;
1327
1328                 /* Note: start_line is already adjusted for the CDU
1329                  * segment register granularity, so we just need to
1330                  * divide. Adjustment is implicit as we assume ILT
1331                  * Page size is larger than 32K!
1332                  */
1333                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1334                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1335                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1336
1337                 cdu_seg_params = 0;
1338                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1339                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1340                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1341
1342                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1343                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1344                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1345
1346                 cdu_seg_params = 0;
1347                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1348                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1349                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1350         }
1351 }
1352
1353 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1354 {
1355         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1356         struct ecore_qm_iids iids;
1357
1358         OSAL_MEM_ZERO(&iids, sizeof(iids));
1359         ecore_cxt_qm_iids(p_hwfn, &iids);
1360
1361         ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1362                             p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1363                             p_hwfn->first_on_engine,
1364                             iids.cids, iids.vf_cids, iids.tids,
1365                             qm_info->start_pq,
1366                             qm_info->num_pqs - qm_info->num_vf_pqs,
1367                             qm_info->num_vf_pqs,
1368                             qm_info->start_vport,
1369                             qm_info->num_vports, qm_info->pf_wfq,
1370                             qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1371                             p_hwfn->qm_info.qm_vport_params);
1372 }
1373
1374 /* CM PF */
1375 void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1376 {
1377         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1378                      ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1379 }
1380
1381 /* DQ PF */
1382 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1383 {
1384         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1385         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1386
1387         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1388         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1389
1390         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1391         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1392
1393         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1394         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1395
1396         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1397         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1398
1399         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1400         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1401
1402         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1403         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1404
1405         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1406         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1407
1408         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1409         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1410
1411         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1412         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1413
1414         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1415         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1416
1417         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1418         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1419
1420         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1421         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1422
1423         /* Connection types 6 & 7 are not in use, yet they must be configured
1424          * as the highest possible connection. Not configuring them means the
1425          * defaults will be  used, and with a large number of cids a bug may
1426          * occur, if the defaults will be smaller than dq_pf_max_cid /
1427          * dq_vf_max_cid.
1428          */
1429         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1430         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1431
1432         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1433         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1434 }
1435
1436 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1437 {
1438         struct ecore_ilt_client_cfg *ilt_clients;
1439         int i;
1440
1441         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1442         for_each_ilt_valid_client(i, ilt_clients) {
1443                 STORE_RT_REG(p_hwfn,
1444                              ilt_clients[i].first.reg,
1445                              ilt_clients[i].first.val);
1446                 STORE_RT_REG(p_hwfn,
1447                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1448                 STORE_RT_REG(p_hwfn,
1449                              ilt_clients[i].p_size.reg,
1450                              ilt_clients[i].p_size.val);
1451         }
1452 }
1453
1454 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1455 {
1456         struct ecore_ilt_client_cfg *p_cli;
1457         u32 blk_factor;
1458
1459         /* For simplicty  we set the 'block' to be an ILT page */
1460         if (p_hwfn->p_dev->p_iov_info) {
1461                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1462
1463                 STORE_RT_REG(p_hwfn,
1464                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1465                              p_iov->first_vf_in_pf);
1466                 STORE_RT_REG(p_hwfn,
1467                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1468                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1469         }
1470
1471         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1472         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1473         if (p_cli->active) {
1474                 STORE_RT_REG(p_hwfn,
1475                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1476                              blk_factor);
1477                 STORE_RT_REG(p_hwfn,
1478                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1479                              p_cli->pf_total_lines);
1480                 STORE_RT_REG(p_hwfn,
1481                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1482                              p_cli->vf_total_lines);
1483         }
1484
1485         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1486         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1487         if (p_cli->active) {
1488                 STORE_RT_REG(p_hwfn,
1489                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1490                              blk_factor);
1491                 STORE_RT_REG(p_hwfn,
1492                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1493                              p_cli->pf_total_lines);
1494                 STORE_RT_REG(p_hwfn,
1495                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1496                              p_cli->vf_total_lines);
1497         }
1498
1499         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1500         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1501         if (p_cli->active) {
1502                 STORE_RT_REG(p_hwfn,
1503                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1504                 STORE_RT_REG(p_hwfn,
1505                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1506                              p_cli->pf_total_lines);
1507                 STORE_RT_REG(p_hwfn,
1508                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1509                              p_cli->vf_total_lines);
1510         }
1511 }
1512
1513 /* ILT (PSWRQ2) PF */
1514 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1515 {
1516         struct ecore_ilt_client_cfg *clients;
1517         struct ecore_cxt_mngr *p_mngr;
1518         struct ecore_dma_mem *p_shdw;
1519         u32 line, rt_offst, i;
1520
1521         ecore_ilt_bounds_init(p_hwfn);
1522         ecore_ilt_vf_bounds_init(p_hwfn);
1523
1524         p_mngr = p_hwfn->p_cxt_mngr;
1525         p_shdw = p_mngr->ilt_shadow;
1526         clients = p_hwfn->p_cxt_mngr->clients;
1527
1528         for_each_ilt_valid_client(i, clients) {
1529                 /* Client's 1st val and RT array are absolute, ILT shadows'
1530                  * lines are relative.
1531                  */
1532                 line = clients[i].first.val - p_mngr->pf_start_line;
1533                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1534                     clients[i].first.val * ILT_ENTRY_IN_REGS;
1535
1536                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1537                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1538                         u64 ilt_hw_entry = 0;
1539
1540                         /** p_virt could be OSAL_NULL incase of dynamic
1541                          *  allocation
1542                          */
1543                         if (p_shdw[line].p_virt != OSAL_NULL) {
1544                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1545                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1546                                           (p_shdw[line].p_phys >> 12));
1547
1548                                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1549                                         "Setting RT[0x%08x] from"
1550                                         " ILT[0x%08x] [Client is %d] to"
1551                                         " Physical addr: 0x%lx\n",
1552                                         rt_offst, line, i,
1553                                         (unsigned long)(p_shdw[line].
1554                                                         p_phys >> 12));
1555                         }
1556
1557                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1558                 }
1559         }
1560 }
1561
1562 /* SRC (Searcher) PF */
1563 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1564 {
1565         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1566         u32 rounded_conn_num, conn_num, conn_max;
1567         struct ecore_src_iids src_iids;
1568
1569         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1570         ecore_cxt_src_iids(p_mngr, &src_iids);
1571         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1572         if (!conn_num)
1573                 return;
1574
1575         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1576         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1577
1578         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1579         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1580                      OSAL_LOG2(rounded_conn_num));
1581
1582         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1583                          p_hwfn->p_cxt_mngr->first_free);
1584         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1585                          p_hwfn->p_cxt_mngr->last_free);
1586 }
1587
1588 /* Timers PF */
1589 #define TM_CFG_NUM_IDS_SHIFT            0
1590 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1591 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1592 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1593 #define TM_CFG_PARENT_PF_SHIFT          25
1594 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1595
1596 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1597 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1598
1599 #define TM_CFG_TID_OFFSET_SHIFT         30
1600 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1601 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1602 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1603
1604 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1605 {
1606         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1607         u32 active_seg_mask = 0, tm_offset, rt_reg;
1608         struct ecore_tm_iids tm_iids;
1609         u64 cfg_word;
1610         u8 i;
1611
1612         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1613         ecore_cxt_tm_iids(p_mngr, &tm_iids);
1614
1615         /* @@@TBD No pre-scan for now */
1616
1617         /* Note: We assume consecutive VFs for a PF */
1618         for (i = 0; i < p_mngr->vf_count; i++) {
1619                 cfg_word = 0;
1620                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1621                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1622                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1623                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1624
1625                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1626                     (sizeof(cfg_word) / sizeof(u32)) *
1627                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1628                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1629         }
1630
1631         cfg_word = 0;
1632         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1633         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1634         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1635         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all   */
1636
1637         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1638             (sizeof(cfg_word) / sizeof(u32)) *
1639             (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1640         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1641
1642         /* enale scan */
1643         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1644                      tm_iids.pf_cids ? 0x1 : 0x0);
1645
1646         /* @@@TBD how to enable the scan for the VFs */
1647
1648         tm_offset = tm_iids.per_vf_cids;
1649
1650         /* Note: We assume consecutive VFs for a PF */
1651         for (i = 0; i < p_mngr->vf_count; i++) {
1652                 cfg_word = 0;
1653                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1654                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1655                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1656                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1657                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1658
1659                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1660                     (sizeof(cfg_word) / sizeof(u32)) *
1661                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1662
1663                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1664         }
1665
1666         tm_offset = tm_iids.pf_cids;
1667         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1668                 cfg_word = 0;
1669                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1670                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1671                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1672                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1673                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1674
1675                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1676                     (sizeof(cfg_word) / sizeof(u32)) *
1677                     (NUM_OF_VFS(p_hwfn->p_dev) +
1678                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1679
1680                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1681                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1682
1683                 tm_offset += tm_iids.pf_tids[i];
1684         }
1685
1686         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1687
1688         /* @@@TBD how to enable the scan for the VFs */
1689 }
1690
1691 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1692 {
1693         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1694         struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1695         struct ecore_tid_seg *p_tid;
1696
1697         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1698         if (!p_fcoe->cid_count)
1699                 return;
1700
1701         p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1702         STORE_RT_REG_AGG(p_hwfn,
1703                         PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1704                         p_tid->count);
1705 }
1706
1707 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1708 {
1709         /* CDU configuration */
1710         ecore_cdu_init_common(p_hwfn);
1711 }
1712
1713 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1714 {
1715         ecore_qm_init_pf(p_hwfn);
1716         ecore_cm_init_pf(p_hwfn);
1717         ecore_dq_init_pf(p_hwfn);
1718         ecore_cdu_init_pf(p_hwfn);
1719         ecore_ilt_init_pf(p_hwfn);
1720         ecore_src_init_pf(p_hwfn);
1721         ecore_tm_init_pf(p_hwfn);
1722         ecore_prs_init_pf(p_hwfn);
1723 }
1724
1725 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1726                                            enum protocol_type type, u32 *p_cid)
1727 {
1728         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1729         u32 rel_cid;
1730
1731         if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1732                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1733                 return ECORE_INVAL;
1734         }
1735
1736         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_mngr->acquired[type].cid_map,
1737                                            p_mngr->acquired[type].max_count);
1738
1739         if (rel_cid >= p_mngr->acquired[type].max_count) {
1740                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1741                           type);
1742                 return ECORE_NORESOURCES;
1743         }
1744
1745         OSAL_SET_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1746
1747         *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1748
1749         return ECORE_SUCCESS;
1750 }
1751
1752 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1753                                         u32 cid, enum protocol_type *p_type)
1754 {
1755         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1756         struct ecore_cid_acquired_map *p_map;
1757         enum protocol_type p;
1758         u32 rel_cid;
1759
1760         /* Iterate over protocols and find matching cid range */
1761         for (p = 0; p < MAX_CONN_TYPES; p++) {
1762                 p_map = &p_mngr->acquired[p];
1763
1764                 if (!p_map->cid_map)
1765                         continue;
1766                 if (cid >= p_map->start_cid &&
1767                     cid < p_map->start_cid + p_map->max_count) {
1768                         break;
1769                 }
1770         }
1771         *p_type = p;
1772
1773         if (p == MAX_CONN_TYPES) {
1774                 DP_NOTICE(p_hwfn, true, "Invalid CID %d", cid);
1775                 return false;
1776         }
1777         rel_cid = cid - p_map->start_cid;
1778         if (!OSAL_TEST_BIT(rel_cid, p_map->cid_map)) {
1779                 DP_NOTICE(p_hwfn, true, "CID %d not acquired", cid);
1780                 return false;
1781         }
1782         return true;
1783 }
1784
1785 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1786 {
1787         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1788         enum protocol_type type;
1789         bool b_acquired;
1790         u32 rel_cid;
1791
1792         /* Test acquired and find matching per-protocol map */
1793         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, &type);
1794
1795         if (!b_acquired)
1796                 return;
1797
1798         rel_cid = cid - p_mngr->acquired[type].start_cid;
1799         OSAL_CLEAR_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1800 }
1801
1802 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1803                                             struct ecore_cxt_info *p_info)
1804 {
1805         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1806         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1807         enum protocol_type type;
1808         bool b_acquired;
1809
1810         /* Test acquired and find matching per-protocol map */
1811         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1812
1813         if (!b_acquired)
1814                 return ECORE_INVAL;
1815
1816         /* set the protocl type */
1817         p_info->type = type;
1818
1819         /* compute context virtual pointer */
1820         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1821
1822         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1823         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1824         line = p_info->iid / cxts_per_p;
1825
1826         /* Make sure context is allocated (dynamic allocation) */
1827         if (!p_mngr->ilt_shadow[line].p_virt)
1828                 return ECORE_INVAL;
1829
1830         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1831             p_info->iid % cxts_per_p * conn_cxt_size;
1832
1833         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1834                 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1835                 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1836
1837         return ECORE_SUCCESS;
1838 }
1839
1840 void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
1841 {
1842         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1843
1844         p_mgr->srq_count = num_srqs;
1845 }
1846
1847 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
1848 {
1849         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1850
1851         return p_mgr->srq_count;
1852 }
1853
1854 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1855 {
1856         /* Set the number of required CORE connections */
1857         u32 core_cids = 1;      /* SPQ */
1858
1859         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1860
1861         switch (p_hwfn->hw_info.personality) {
1862         case ECORE_PCI_ETH:
1863                 {
1864                         struct ecore_eth_pf_params *p_params =
1865                             &p_hwfn->pf_params.eth_pf_params;
1866
1867                         ecore_cxt_set_proto_cid_count(p_hwfn,
1868                                 PROTOCOLID_ETH,
1869                                 p_params->num_cons, 1); /* FIXME VF count... */
1870
1871                         break;
1872                 }
1873         default:
1874                 return ECORE_INVAL;
1875         }
1876
1877         return ECORE_SUCCESS;
1878 }
1879
1880 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
1881                                                 struct ecore_tid_mem *p_info)
1882 {
1883         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1884         u32 proto, seg, total_lines, i, shadow_line;
1885         struct ecore_ilt_client_cfg *p_cli;
1886         struct ecore_ilt_cli_blk *p_fl_seg;
1887         struct ecore_tid_seg *p_seg_info;
1888
1889         /* Verify the personality */
1890         switch (p_hwfn->hw_info.personality) {
1891         default:
1892                 return ECORE_INVAL;
1893         }
1894
1895         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1896         if (!p_cli->active)
1897                 return ECORE_INVAL;
1898
1899         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1900         if (!p_seg_info->has_fl_mem)
1901                 return ECORE_INVAL;
1902
1903         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1904         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1905                                    p_fl_seg->real_size_in_page);
1906
1907         for (i = 0; i < total_lines; i++) {
1908                 shadow_line = i + p_fl_seg->start_line -
1909                     p_hwfn->p_cxt_mngr->pf_start_line;
1910                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1911         }
1912         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1913             p_fl_seg->real_size_in_page;
1914         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1915         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1916             p_info->tid_size;
1917
1918         return ECORE_SUCCESS;
1919 }
1920
1921 /* This function is very RoCE oriented, if another protocol in the future
1922  * will want this feature we'll need to modify the function to be more generic
1923  */
1924 enum _ecore_status_t
1925 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
1926                             enum ecore_cxt_elem_type elem_type,
1927                             u32 iid)
1928 {
1929         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
1930         struct ecore_ilt_client_cfg *p_cli;
1931         struct ecore_ilt_cli_blk *p_blk;
1932         struct ecore_ptt *p_ptt;
1933         dma_addr_t p_phys;
1934         u64 ilt_hw_entry;
1935         void *p_virt;
1936         enum _ecore_status_t rc = ECORE_SUCCESS;
1937
1938         switch (elem_type) {
1939         case ECORE_ELEM_CXT:
1940                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1941                 elem_size = CONN_CXT_SIZE(p_hwfn);
1942                 p_blk = &p_cli->pf_blks[CDUC_BLK];
1943                 break;
1944         case ECORE_ELEM_SRQ:
1945                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
1946                 elem_size = SRQ_CXT_SIZE;
1947                 p_blk = &p_cli->pf_blks[SRQ_BLK];
1948                 break;
1949         case ECORE_ELEM_TASK:
1950                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1951                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
1952                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
1953                 break;
1954         default:
1955                 DP_NOTICE(p_hwfn, false,
1956                           "ECORE_INVALID elem type = %d", elem_type);
1957                 return ECORE_INVAL;
1958         }
1959
1960         /* Calculate line in ilt */
1961         hw_p_size = p_cli->p_size.val;
1962         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1963         line = p_blk->start_line + (iid / elems_per_p);
1964         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
1965
1966         /* If line is already allocated, do nothing, otherwise allocate it and
1967          * write it to the PSWRQ2 registers.
1968          * This section can be run in parallel from different contexts and thus
1969          * a mutex protection is needed.
1970          */
1971
1972         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
1973
1974         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
1975                 goto out0;
1976
1977         p_ptt = ecore_ptt_acquire(p_hwfn);
1978         if (!p_ptt) {
1979                 DP_NOTICE(p_hwfn, false,
1980                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
1981                 rc = ECORE_TIMEOUT;
1982                 goto out0;
1983         }
1984
1985         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1986                                          &p_phys,
1987                                          p_blk->real_size_in_page);
1988         if (!p_virt) {
1989                 rc = ECORE_NOMEM;
1990                 goto out1;
1991         }
1992         OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
1993
1994         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
1995         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
1996         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
1997                 p_blk->real_size_in_page;
1998
1999         /* compute absolute offset */
2000         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2001                      (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2002
2003         ilt_hw_entry = 0;
2004         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2005         SET_FIELD(ilt_hw_entry,
2006                   ILT_ENTRY_PHY_ADDR,
2007                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2008
2009 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2010
2011         ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2012                             reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2013                             0 /* no flags */);
2014
2015         if (elem_type == ECORE_ELEM_CXT) {
2016                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2017                                          elems_per_p;
2018
2019                 /* Update the relevant register in the parser */
2020                 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2021                          last_cid_allocated - 1);
2022
2023                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2024                         /* Enable RoCE search */
2025                         ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2026                         p_hwfn->b_rdma_enabled_in_prs = true;
2027                 }
2028         }
2029
2030 out1:
2031         ecore_ptt_release(p_hwfn, p_ptt);
2032 out0:
2033         OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2034
2035         return rc;
2036 }
2037
2038 /* This function is very RoCE oriented, if another protocol in the future
2039  * will want this feature we'll need to modify the function to be more generic
2040  */
2041 static enum _ecore_status_t
2042 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2043                          enum ecore_cxt_elem_type elem_type,
2044                          u32 start_iid, u32 count)
2045 {
2046         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2047         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2048         struct ecore_ilt_client_cfg *p_cli;
2049         struct ecore_ilt_cli_blk *p_blk;
2050         u32 end_iid = start_iid + count;
2051         struct ecore_ptt *p_ptt;
2052         u64 ilt_hw_entry = 0;
2053         u32 i;
2054
2055         switch (elem_type) {
2056         case ECORE_ELEM_CXT:
2057                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2058                 elem_size = CONN_CXT_SIZE(p_hwfn);
2059                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2060                 break;
2061         case ECORE_ELEM_SRQ:
2062                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2063                 elem_size = SRQ_CXT_SIZE;
2064                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2065                 break;
2066         case ECORE_ELEM_TASK:
2067                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2068                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2069                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2070                 break;
2071         default:
2072                 DP_NOTICE(p_hwfn, false,
2073                           "ECORE_INVALID elem type = %d", elem_type);
2074                 return ECORE_INVAL;
2075         }
2076
2077         /* Calculate line in ilt */
2078         hw_p_size = p_cli->p_size.val;
2079         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2080         start_line = p_blk->start_line + (start_iid / elems_per_p);
2081         end_line = p_blk->start_line + (end_iid / elems_per_p);
2082         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2083                 end_line--;
2084
2085         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2086         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2087
2088         p_ptt = ecore_ptt_acquire(p_hwfn);
2089         if (!p_ptt) {
2090                 DP_NOTICE(p_hwfn, false,
2091                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2092                 return ECORE_TIMEOUT;
2093         }
2094
2095         for (i = shadow_start_line; i < shadow_end_line; i++) {
2096                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2097                         continue;
2098
2099                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2100                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2101                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2102                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2103
2104                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2105                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2106                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2107
2108                 /* compute absolute offset */
2109                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2110                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2111                      ILT_ENTRY_IN_REGS);
2112
2113                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2114                  * wide-bus.
2115                  */
2116                 ecore_dmae_host2grc(p_hwfn, p_ptt,
2117                                     (u64)(osal_uintptr_t)&ilt_hw_entry,
2118                                     reg_offset,
2119                                     sizeof(ilt_hw_entry) / sizeof(u32),
2120                                     0 /* no flags */);
2121         }
2122
2123         ecore_ptt_release(p_hwfn, p_ptt);
2124
2125         return ECORE_SUCCESS;
2126 }
2127
2128 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2129                                               enum protocol_type proto)
2130 {
2131         enum _ecore_status_t rc;
2132         u32 cid;
2133
2134         /* Free Connection CXT */
2135         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2136                                       ecore_cxt_get_proto_cid_start(p_hwfn,
2137                                                                     proto),
2138                                       ecore_cxt_get_proto_cid_count(p_hwfn,
2139                                                                     proto,
2140                                                                     &cid));
2141
2142         if (rc)
2143                 return rc;
2144
2145         /* Free Task CXT */
2146         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2147                                       ecore_cxt_get_proto_tid_count(p_hwfn,
2148                                                                     proto));
2149         if (rc)
2150                 return rc;
2151
2152         /* Free TSDM CXT */
2153         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2154                                       ecore_cxt_get_srq_count(p_hwfn));
2155
2156         return rc;
2157 }
2158
2159 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
2160                                             u32 tid,
2161                                             u8 ctx_type, void **pp_task_ctx)
2162 {
2163         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2164         struct ecore_ilt_client_cfg *p_cli;
2165         struct ecore_ilt_cli_blk *p_seg;
2166         struct ecore_tid_seg *p_seg_info;
2167         u32 proto, seg;
2168         u32 total_lines;
2169         u32 tid_size, ilt_idx;
2170         u32 num_tids_per_block;
2171
2172         /* Verify the personality */
2173         switch (p_hwfn->hw_info.personality) {
2174         default:
2175                 return ECORE_INVAL;
2176         }
2177
2178         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2179         if (!p_cli->active)
2180                 return ECORE_INVAL;
2181
2182         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2183
2184         if (ctx_type == ECORE_CTX_WORKING_MEM) {
2185                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2186         } else if (ctx_type == ECORE_CTX_FL_MEM) {
2187                 if (!p_seg_info->has_fl_mem)
2188                         return ECORE_INVAL;
2189                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2190         } else {
2191                 return ECORE_INVAL;
2192         }
2193         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2194         tid_size = p_mngr->task_type_size[p_seg_info->type];
2195         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2196
2197         if (total_lines < tid / num_tids_per_block)
2198                 return ECORE_INVAL;
2199
2200         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2201             p_mngr->pf_start_line;
2202         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2203             (tid % num_tids_per_block) * tid_size;
2204
2205         return ECORE_SUCCESS;
2206 }