drivers/net/qede/base/ecore_cxt.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "common_hsi.h"
  12 #include "ecore_hsi_common.h"
  13 #include "ecore_hsi_eth.h"
  14 #include "ecore_rt_defs.h"
  15 #include "ecore_status.h"
  16 #include "ecore.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_init_fw_funcs.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_hw.h"
  21 #include "ecore_dev_api.h"
  22 #include "ecore_sriov.h"
  23 #include "ecore_mcp.h"
  24
  25 /* Max number of connection types in HW (DQ/CDU etc.) */
  26 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  27 #define NUM_TASK_TYPES          2
  28 #define NUM_TASK_PF_SEGMENTS    4
  29 #define NUM_TASK_VF_SEGMENTS    1
  30
  31 /* Doorbell-Queue constants */
  32 #define DQ_RANGE_SHIFT  4
  33 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  34
  35 /* Searcher constants */
  36 #define SRC_MIN_NUM_ELEMS 256
  37
  38 /* Timers constants */
  39 #define TM_SHIFT        7
  40 #define TM_ALIGN        (1 << TM_SHIFT)
  41 #define TM_ELEM_SIZE    4
  42
  43 /* ILT constants */
  44 /* If for some reason, HW P size is modified to be less than 32K,
  45  * special handling needs to be made for CDU initialization
  46  */
  47 #define ILT_DEFAULT_HW_P_SIZE   3
  48
  49 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  50 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  51
  52 /* ILT entry structure */
  53 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  54 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  55 #define ILT_ENTRY_VALID_MASK            0x1ULL
  56 #define ILT_ENTRY_VALID_SHIFT           52
  57 #define ILT_ENTRY_IN_REGS               2
  58 #define ILT_REG_SIZE_IN_BYTES           4
  59
  60 /* connection context union */
  61 union conn_context {
  62         struct core_conn_context core_ctx;
  63         struct eth_conn_context eth_ctx;
  64 };
  65
  66 /* TYPE-0 task context - iSCSI, FCOE */
  67 union type0_task_context {
  68 };
  69
  70 /* TYPE-1 task context - ROCE */
  71 union type1_task_context {
  72 };
  73
  74 struct src_ent {
  75         u8 opaque[56];
  76         u64 next;
  77 };
  78
  79 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  80 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  81
  82 #define CONN_CXT_SIZE(p_hwfn) \
  83         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  84
  85 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
  86
  87 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
  88         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
  89
  90 /* Alignment is inherent to the type1_task_context structure */
  91 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
  92
  93 /* PF per protocl configuration object */
  94 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
  95 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
  96
  97 struct ecore_tid_seg {
  98         u32 count;
  99         u8 type;
 100         bool has_fl_mem;
 101 };
 102
 103 struct ecore_conn_type_cfg {
 104         u32 cid_count;
 105         u32 cids_per_vf;
 106         struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
 107 };
 108
 109 /* ILT Client configuration,
 110  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
 111  * 1 - for connection context (CDUC) and for each task context we need two
 112  * values, for regular task context and for force load memory
 113  */
 114 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 115 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 116 #define CDUC_BLK                (0)
 117 #define SRQ_BLK                 (0)
 118 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 119 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 120
 121 enum ilt_clients {
 122         ILT_CLI_CDUC,
 123         ILT_CLI_CDUT,
 124         ILT_CLI_QM,
 125         ILT_CLI_TM,
 126         ILT_CLI_SRC,
 127         ILT_CLI_TSDM,
 128         ILT_CLI_MAX
 129 };
 130
 131 struct ilt_cfg_pair {
 132         u32 reg;
 133         u32 val;
 134 };
 135
 136 struct ecore_ilt_cli_blk {
 137         u32 total_size;         /* 0 means not active */
 138         u32 real_size_in_page;
 139         u32 start_line;
 140         u32 dynamic_line_cnt;
 141 };
 142
 143 struct ecore_ilt_client_cfg {
 144         bool active;
 145
 146         /* ILT boundaries */
 147         struct ilt_cfg_pair first;
 148         struct ilt_cfg_pair last;
 149         struct ilt_cfg_pair p_size;
 150
 151         /* ILT client blocks for PF */
 152         struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 153         u32 pf_total_lines;
 154
 155         /* ILT client blocks for VFs */
 156         struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 157         u32 vf_total_lines;
 158 };
 159
 160 /* Per Path -
 161  *      ILT shadow table
 162  *      Protocol acquired CID lists
 163  *      PF start line in ILT
 164  */
 165 struct ecore_dma_mem {
 166         dma_addr_t p_phys;
 167         void *p_virt;
 168         osal_size_t size;
 169 };
 170
 171 #define MAP_WORD_SIZE           sizeof(unsigned long)
 172 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 173
 174 struct ecore_cid_acquired_map {
 175         u32 start_cid;
 176         u32 max_count;
 177         unsigned long *cid_map;
 178 };
 179
 180 struct ecore_cxt_mngr {
 181         /* Per protocl configuration */
 182         struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
 183
 184         /* computed ILT structure */
 185         struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
 186
 187         /* Task type sizes */
 188         u32 task_type_size[NUM_TASK_TYPES];
 189
 190         /* total number of VFs for this hwfn -
 191          * ALL VFs are symmetric in terms of HW resources
 192          */
 193         u32 vf_count;
 194
 195         /* total number of SRQ's for this hwfn */
 196         u32                             srq_count;
 197
 198         /* Acquired CIDs */
 199         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 200         /* TBD - do we want this allocated to reserve space? */
 201         struct ecore_cid_acquired_map
 202                 acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS];
 203
 204         /* ILT  shadow table */
 205         struct ecore_dma_mem *ilt_shadow;
 206         u32 pf_start_line;
 207
 208         /* Mutex for a dynamic ILT allocation */
 209         osal_mutex_t mutex;
 210
 211         /* SRC T2 */
 212         struct ecore_dma_mem *t2;
 213         u32 t2_num_pages;
 214         u64 first_free;
 215         u64 last_free;
 216 };
 217
 218 /* check if resources/configuration is required according to protocol type */
 219 static OSAL_INLINE bool src_proto(enum protocol_type type)
 220 {
 221         return type == PROTOCOLID_TOE;
 222 }
 223
 224 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
 225 {
 226         return type == PROTOCOLID_TOE;
 227 }
 228
 229 static bool tm_tid_proto(enum protocol_type type)
 230 {
 231         return type == PROTOCOLID_FCOE;
 232 }
 233
 234 /* counts the iids for the CDU/CDUC ILT client configuration */
 235 struct ecore_cdu_iids {
 236         u32 pf_cids;
 237         u32 per_vf_cids;
 238 };
 239
 240 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
 241                                struct ecore_cdu_iids *iids)
 242 {
 243         u32 type;
 244
 245         for (type = 0; type < MAX_CONN_TYPES; type++) {
 246                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 247                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 248         }
 249 }
 250
 251 /* counts the iids for the Searcher block configuration */
 252 struct ecore_src_iids {
 253         u32 pf_cids;
 254         u32 per_vf_cids;
 255 };
 256
 257 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
 258                                            struct ecore_src_iids *iids)
 259 {
 260         u32 i;
 261
 262         for (i = 0; i < MAX_CONN_TYPES; i++) {
 263                 if (!src_proto(i))
 264                         continue;
 265
 266                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 267                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 268         }
 269 }
 270
 271 /* counts the iids for the Timers block configuration */
 272 struct ecore_tm_iids {
 273         u32 pf_cids;
 274         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 275         u32 pf_tids_total;
 276         u32 per_vf_cids;
 277         u32 per_vf_tids;
 278 };
 279
 280 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
 281                                           struct ecore_tm_iids *iids)
 282 {
 283         bool tm_vf_required = false;
 284         bool tm_required = false;
 285         u32 i, j;
 286
 287         for (i = 0; i < MAX_CONN_TYPES; i++) {
 288                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 289
 290                 if (tm_cid_proto(i) || tm_required) {
 291                         if (p_cfg->cid_count)
 292                                 tm_required = true;
 293
 294                         iids->pf_cids += p_cfg->cid_count;
 295                 }
 296
 297                 if (tm_cid_proto(i) || tm_vf_required) {
 298                         if (p_cfg->cids_per_vf)
 299                                 tm_vf_required = true;
 300
 301                 }
 302
 303                 if (tm_tid_proto(i)) {
 304                         struct ecore_tid_seg *segs = p_cfg->tid_seg;
 305
 306                         /* for each segment there is at most one
 307                          * protocol for which count is not 0.
 308                          */
 309                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 310                                 iids->pf_tids[j] += segs[j].count;
 311
 312                         /* The last array elelment is for the VFs. As for PF
 313                          * segments there can be only one protocol for
 314                          * which this value is not 0.
 315                          */
 316                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 317                 }
 318         }
 319
 320         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 321         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 322         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 323
 324         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 325                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 326                 iids->pf_tids_total += iids->pf_tids[j];
 327         }
 328 }
 329
 330 void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids)
 331 {
 332         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 333         struct ecore_tid_seg *segs;
 334         u32 vf_cids = 0, type, j;
 335         u32 vf_tids = 0;
 336
 337         for (type = 0; type < MAX_CONN_TYPES; type++) {
 338                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 339                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 340
 341                 segs = p_mngr->conn_cfg[type].tid_seg;
 342                 /* for each segment there is at most one
 343                  * protocol for which count is not 0.
 344                  */
 345                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 346                         iids->tids += segs[j].count;
 347
 348                 /* The last array elelment is for the VFs. As for PF
 349                  * segments there can be only one protocol for
 350                  * which this value is not 0.
 351                  */
 352                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 353         }
 354
 355         iids->vf_cids += vf_cids * p_mngr->vf_count;
 356         iids->tids += vf_tids * p_mngr->vf_count;
 357
 358         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 359                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 360                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 361 }
 362
 363 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
 364                                                     u32 seg)
 365 {
 366         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 367         u32 i;
 368
 369         /* Find the protocol with tid count > 0 for this segment.
 370          * Note: there can only be one and this is already validated.
 371          */
 372         for (i = 0; i < MAX_CONN_TYPES; i++) {
 373                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 374                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 375         }
 376         return OSAL_NULL;
 377 }
 378
 379 /* set the iids (cid/tid) count per protocol */
 380 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 381                                    enum protocol_type type,
 382                                    u32 cid_count, u32 vf_cid_cnt)
 383 {
 384         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 385         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 386
 387         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 388         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 389 }
 390
 391 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
 392                                   enum protocol_type type, u32 *vf_cid)
 393 {
 394         if (vf_cid)
 395                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 396
 397         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 398 }
 399
 400 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
 401                                   enum protocol_type type)
 402 {
 403         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 404 }
 405
 406 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 407                                          enum protocol_type type)
 408 {
 409         u32 cnt = 0;
 410         int i;
 411
 412         for (i = 0; i < TASK_SEGMENTS; i++)
 413                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 414
 415         return cnt;
 416 }
 417
 418 static OSAL_INLINE void
 419 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 420                               enum protocol_type proto,
 421                               u8 seg, u8 seg_type, u32 count, bool has_fl)
 422 {
 423         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 424         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 425
 426         p_seg->count = count;
 427         p_seg->has_fl_mem = has_fl;
 428         p_seg->type = seg_type;
 429 }
 430
 431 /* the *p_line parameter must be either 0 for the first invocation or the
 432  * value returned in the previous invocation.
 433  */
 434 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
 435                                    struct ecore_ilt_cli_blk *p_blk,
 436                                    u32 start_line,
 437                                    u32 total_size, u32 elem_size)
 438 {
 439         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 440
 441         /* verify that it's called once for each block */
 442         if (p_blk->total_size)
 443                 return;
 444
 445         p_blk->total_size = total_size;
 446         p_blk->real_size_in_page = 0;
 447         if (elem_size)
 448                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 449         p_blk->start_line = start_line;
 450 }
 451
 452 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
 453                                    struct ecore_ilt_client_cfg *p_cli,
 454                                    struct ecore_ilt_cli_blk *p_blk,
 455                                    u32 *p_line, enum ilt_clients client_id)
 456 {
 457         if (!p_blk->total_size)
 458                 return;
 459
 460         if (!p_cli->active)
 461                 p_cli->first.val = *p_line;
 462
 463         p_cli->active = true;
 464         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 465         p_cli->last.val = *p_line - 1;
 466
 467         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 468                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
 469                    " [Real %08x] Start line %d\n",
 470                    client_id, p_cli->first.val, p_cli->last.val,
 471                    p_blk->total_size, p_blk->real_size_in_page,
 472                    p_blk->start_line);
 473 }
 474
 475 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 476                                           enum ilt_clients ilt_client)
 477 {
 478         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 479         struct ecore_ilt_client_cfg *p_cli;
 480         u32 lines_to_skip = 0;
 481         u32 cxts_per_p;
 482
 483         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 484
 485         if (ilt_client == ILT_CLI_CDUC) {
 486                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 487
 488                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 489                     (u32)CONN_CXT_SIZE(p_hwfn);
 490
 491                 lines_to_skip = cid_count / cxts_per_p;
 492         }
 493
 494         return lines_to_skip;
 495 }
 496
 497 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
 498 {
 499         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 500         u32 curr_line, total, i, task_size, line;
 501         struct ecore_ilt_client_cfg *p_cli;
 502         struct ecore_ilt_cli_blk *p_blk;
 503         struct ecore_cdu_iids cdu_iids;
 504         struct ecore_src_iids src_iids;
 505         struct ecore_qm_iids qm_iids;
 506         struct ecore_tm_iids tm_iids;
 507         struct ecore_tid_seg *p_seg;
 508
 509         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 510         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 511         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 512         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 513
 514         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 515
 516         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 517                    "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
 518                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 519
 520         /* CDUC */
 521         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 522
 523         curr_line = p_mngr->pf_start_line;
 524
 525         /* CDUC PF */
 526         p_cli->pf_total_lines = 0;
 527
 528         /* get the counters for the CDUC,CDUC and QM clients  */
 529         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 530
 531         p_blk = &p_cli->pf_blks[CDUC_BLK];
 532
 533         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 534
 535         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 536                                total, CONN_CXT_SIZE(p_hwfn));
 537
 538         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 539         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 540
 541         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 542                                                                  ILT_CLI_CDUC);
 543
 544         /* CDUC VF */
 545         p_blk = &p_cli->vf_blks[CDUC_BLK];
 546         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 547
 548         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 549                                total, CONN_CXT_SIZE(p_hwfn));
 550
 551         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 552         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 553
 554         for (i = 1; i < p_mngr->vf_count; i++)
 555                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 556                                        ILT_CLI_CDUC);
 557
 558         /* CDUT PF */
 559         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 560         p_cli->first.val = curr_line;
 561
 562         /* first the 'working' task memory */
 563         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 564                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 565                 if (!p_seg || p_seg->count == 0)
 566                         continue;
 567
 568                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 569                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 570                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 571                                        p_mngr->task_type_size[p_seg->type]);
 572
 573                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 574                                        ILT_CLI_CDUT);
 575         }
 576
 577         /* next the 'init' task memory (forced load memory) */
 578         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 579                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 580                 if (!p_seg || p_seg->count == 0)
 581                         continue;
 582
 583                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 584
 585                 if (!p_seg->has_fl_mem) {
 586                         /* The segment is active (total size pf 'working'
 587                          * memory is > 0) but has no FL (forced-load, Init)
 588                          * memory. Thus:
 589                          *
 590                          * 1.   The total-size in the corrsponding FL block of
 591                          *      the ILT client is set to 0 - No ILT line are
 592                          *      provisioned and no ILT memory allocated.
 593                          *
 594                          * 2.   The start-line of said block is set to the
 595                          *      start line of the matching working memory
 596                          *      block in the ILT client. This is later used to
 597                          *      configure the CDU segment offset registers and
 598                          *      results in an FL command for TIDs of this
 599                          *      segment behaves as regular load commands
 600                          *      (loading TIDs from the working memory).
 601                          */
 602                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 603
 604                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 605                         continue;
 606                 }
 607                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 608
 609                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 610                                        curr_line, total,
 611                                        p_mngr->task_type_size[p_seg->type]);
 612
 613                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 614                                        ILT_CLI_CDUT);
 615         }
 616         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 617
 618         /* CDUT VF */
 619         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 620         if (p_seg && p_seg->count) {
 621                 /* Stricly speaking we need to iterate over all VF
 622                  * task segment types, but a VF has only 1 segment
 623                  */
 624
 625                 /* 'working' memory */
 626                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 627
 628                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 629                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 630                                        curr_line, total,
 631                                        p_mngr->task_type_size[p_seg->type]);
 632
 633                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 634                                        ILT_CLI_CDUT);
 635
 636                 /* 'init' memory */
 637                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 638                 if (!p_seg->has_fl_mem) {
 639                         /* see comment above */
 640                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 641                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 642                 } else {
 643                         task_size = p_mngr->task_type_size[p_seg->type];
 644                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 645                                                curr_line, total, task_size);
 646                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 647                                                ILT_CLI_CDUT);
 648                 }
 649                 p_cli->vf_total_lines = curr_line -
 650                     p_cli->vf_blks[0].start_line;
 651
 652                 /* Now for the rest of the VFs */
 653                 for (i = 1; i < p_mngr->vf_count; i++) {
 654                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 655                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 656                                                ILT_CLI_CDUT);
 657
 658                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 659                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 660                                                ILT_CLI_CDUT);
 661                 }
 662         }
 663
 664         /* QM */
 665         p_cli = &p_mngr->clients[ILT_CLI_QM];
 666         p_blk = &p_cli->pf_blks[0];
 667
 668         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 669         total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 670                                      qm_iids.vf_cids, qm_iids.tids,
 671                                      p_hwfn->qm_info.num_pqs,
 672                                      p_hwfn->qm_info.num_vf_pqs);
 673
 674         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 675                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
 676                    " num_vf_pqs=%d, memory_size=%d)\n",
 677                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 678                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 679
 680         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 681                                QM_PQ_ELEMENT_SIZE);
 682
 683         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 684         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 685
 686         /* SRC */
 687         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 688         ecore_cxt_src_iids(p_mngr, &src_iids);
 689
 690         /* Both the PF and VFs searcher connections are stored in the per PF
 691          * database. Thus sum the PF searcher cids and all the VFs searcher
 692          * cids.
 693          */
 694         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 695         if (total) {
 696                 u32 local_max = OSAL_MAX_T(u32, total,
 697                                            SRC_MIN_NUM_ELEMS);
 698
 699                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 700
 701                 p_blk = &p_cli->pf_blks[0];
 702                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 703                                        total * sizeof(struct src_ent),
 704                                        sizeof(struct src_ent));
 705
 706                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 707                                        ILT_CLI_SRC);
 708                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 709         }
 710
 711         /* TM PF */
 712         p_cli = &p_mngr->clients[ILT_CLI_TM];
 713         ecore_cxt_tm_iids(p_mngr, &tm_iids);
 714         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 715         if (total) {
 716                 p_blk = &p_cli->pf_blks[0];
 717                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 718                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 719
 720                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 721                                        ILT_CLI_TM);
 722                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 723         }
 724
 725         /* TM VF */
 726         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 727         if (total) {
 728                 p_blk = &p_cli->vf_blks[0];
 729                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 730                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 731
 732                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 733                                        ILT_CLI_TM);
 734
 735                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 736                 for (i = 1; i < p_mngr->vf_count; i++) {
 737                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 738                                                ILT_CLI_TM);
 739                 }
 740         }
 741
 742         /* TSDM (SRQ CONTEXT) */
 743         total = ecore_cxt_get_srq_count(p_hwfn);
 744
 745         if (total) {
 746                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 747                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 748                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 749                                        total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 750
 751                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 752                                        ILT_CLI_TSDM);
 753                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 754         }
 755
 756         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 757             RESC_NUM(p_hwfn, ECORE_ILT)) {
 758                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 759                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 760                 return ECORE_INVAL;
 761         }
 762
 763         return ECORE_SUCCESS;
 764 }
 765
 766 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 767 {
 768         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 769         u32 i;
 770
 771         if (!p_mngr->t2)
 772                 return;
 773
 774         for (i = 0; i < p_mngr->t2_num_pages; i++)
 775                 if (p_mngr->t2[i].p_virt)
 776                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 777                                                p_mngr->t2[i].p_virt,
 778                                                p_mngr->t2[i].p_phys,
 779                                                p_mngr->t2[i].size);
 780
 781         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 782 }
 783
 784 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 785 {
 786         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 787         u32 conn_num, total_size, ent_per_page, psz, i;
 788         struct ecore_ilt_client_cfg *p_src;
 789         struct ecore_src_iids src_iids;
 790         struct ecore_dma_mem *p_t2;
 791         enum _ecore_status_t rc;
 792
 793         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 794
 795         /* if the SRC ILT client is inactive - there are no connection
 796          * requiring the searcer, leave.
 797          */
 798         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 799         if (!p_src->active)
 800                 return ECORE_SUCCESS;
 801
 802         ecore_cxt_src_iids(p_mngr, &src_iids);
 803         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 804         total_size = conn_num * sizeof(struct src_ent);
 805
 806         /* use the same page size as the SRC ILT client */
 807         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 808         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 809
 810         /* allocate t2 */
 811         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 812                                  p_mngr->t2_num_pages *
 813                                  sizeof(struct ecore_dma_mem));
 814         if (!p_mngr->t2) {
 815                 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
 816                 rc = ECORE_NOMEM;
 817                 goto t2_fail;
 818         }
 819
 820         /* allocate t2 pages */
 821         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 822                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 823                 void **p_virt = &p_mngr->t2[i].p_virt;
 824
 825                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 826                                                   &p_mngr->t2[i].p_phys, size);
 827                 if (!p_mngr->t2[i].p_virt) {
 828                         rc = ECORE_NOMEM;
 829                         goto t2_fail;
 830                 }
 831                 OSAL_MEM_ZERO(*p_virt, size);
 832                 p_mngr->t2[i].size = size;
 833                 total_size -= size;
 834         }
 835
 836         /* Set the t2 pointers */
 837
 838         /* entries per page - must be a power of two */
 839         ent_per_page = psz / sizeof(struct src_ent);
 840
 841         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 842
 843         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 844         p_mngr->last_free = (u64)p_t2->p_phys +
 845             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 846
 847         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 848                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
 849                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 850                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
 851                 u32 j;
 852
 853                 for (j = 0; j < ent_num - 1; j++) {
 854                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 855                         entries[j].next = OSAL_CPU_TO_BE64(val);
 856                 }
 857
 858                 if (i < p_mngr->t2_num_pages - 1)
 859                         val = (u64)p_mngr->t2[i + 1].p_phys;
 860                 else
 861                         val = 0;
 862                 entries[j].next = OSAL_CPU_TO_BE64(val);
 863
 864                 conn_num -= ent_num;
 865         }
 866
 867         return ECORE_SUCCESS;
 868
 869 t2_fail:
 870         ecore_cxt_src_t2_free(p_hwfn);
 871         return rc;
 872 }
 873
 874 #define for_each_ilt_valid_client(pos, clients)         \
 875         for (pos = 0; pos < ILT_CLI_MAX; pos++)         \
 876                 if (!clients[pos].active) {             \
 877                         continue;                       \
 878                 } else                                  \
 879
 880
 881 /* Total number of ILT lines used by this PF */
 882 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
 883 {
 884         u32 size = 0;
 885         u32 i;
 886
 887         for_each_ilt_valid_client(i, ilt_clients)
 888                 size += (ilt_clients[i].last.val -
 889                          ilt_clients[i].first.val + 1);
 890
 891         return size;
 892 }
 893
 894 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
 895 {
 896         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 897         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 898         u32 ilt_size, i;
 899
 900         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
 901
 902         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 903                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 904
 905                 if (p_dma->p_virt)
 906                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 907                                                p_dma->p_virt,
 908                                                p_dma->p_phys, p_dma->size);
 909                 p_dma->p_virt = OSAL_NULL;
 910         }
 911         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
 912 }
 913
 914 static enum _ecore_status_t
 915 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
 916                     struct ecore_ilt_cli_blk *p_blk,
 917                     enum ilt_clients ilt_client, u32 start_line_offset)
 918 {
 919         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 920         u32 lines, line, sz_left, lines_to_skip = 0;
 921
 922         /* Special handling for RoCE that supports dynamic allocation */
 923         if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
 924                 return ECORE_SUCCESS;
 925
 926         lines_to_skip = p_blk->dynamic_line_cnt;
 927
 928         if (!p_blk->total_size)
 929                 return ECORE_SUCCESS;
 930
 931         sz_left = p_blk->total_size;
 932         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 933         line = p_blk->start_line + start_line_offset -
 934             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 935
 936         for (; lines; lines--) {
 937                 dma_addr_t p_phys;
 938                 void *p_virt;
 939                 u32 size;
 940
 941                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
 942
 943 /* @DPDK */
 944 #define ILT_BLOCK_ALIGN_SIZE 0x1000
 945                 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
 946                                                          &p_phys, size,
 947                                                          ILT_BLOCK_ALIGN_SIZE);
 948                 if (!p_virt)
 949                         return ECORE_NOMEM;
 950                 OSAL_MEM_ZERO(p_virt, size);
 951
 952                 ilt_shadow[line].p_phys = p_phys;
 953                 ilt_shadow[line].p_virt = p_virt;
 954                 ilt_shadow[line].size = size;
 955
 956                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 957                            "ILT shadow: Line [%d] Physical 0x%lx"
 958                            " Virtual %p Size %d\n",
 959                            line, (unsigned long)p_phys, p_virt, size);
 960
 961                 sz_left -= size;
 962                 line++;
 963         }
 964
 965         return ECORE_SUCCESS;
 966 }
 967
 968 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
 969 {
 970         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 971         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
 972         struct ecore_ilt_cli_blk *p_blk;
 973         u32 size, i, j, k;
 974         enum _ecore_status_t rc;
 975
 976         size = ecore_cxt_ilt_shadow_size(clients);
 977         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 978                                          size * sizeof(struct ecore_dma_mem));
 979
 980         if (!p_mngr->ilt_shadow) {
 981                 DP_NOTICE(p_hwfn, true,
 982                           "Failed to allocate ilt shadow table\n");
 983                 rc = ECORE_NOMEM;
 984                 goto ilt_shadow_fail;
 985         }
 986
 987         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 988                    "Allocated 0x%x bytes for ilt shadow\n",
 989                    (u32)(size * sizeof(struct ecore_dma_mem)));
 990
 991         for_each_ilt_valid_client(i, clients) {
 992                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
 993                         p_blk = &clients[i].pf_blks[j];
 994                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
 995                         if (rc != ECORE_SUCCESS)
 996                                 goto ilt_shadow_fail;
 997                 }
 998                 for (k = 0; k < p_mngr->vf_count; k++) {
 999                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1000                                 u32 lines = clients[i].vf_total_lines * k;
1001
1002                                 p_blk = &clients[i].vf_blks[j];
1003                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1004                                                          i, lines);
1005                                 if (rc != ECORE_SUCCESS)
1006                                         goto ilt_shadow_fail;
1007                         }
1008                 }
1009         }
1010
1011         return ECORE_SUCCESS;
1012
1013 ilt_shadow_fail:
1014         ecore_ilt_shadow_free(p_hwfn);
1015         return rc;
1016 }
1017
1018 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1019 {
1020         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1021         u32 type, vf;
1022
1023         for (type = 0; type < MAX_CONN_TYPES; type++) {
1024                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1025                 p_mngr->acquired[type].max_count = 0;
1026                 p_mngr->acquired[type].start_cid = 0;
1027
1028                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1029                         OSAL_FREE(p_hwfn->p_dev,
1030                                   p_mngr->acquired_vf[type][vf].cid_map);
1031                         p_mngr->acquired_vf[type][vf].max_count = 0;
1032                         p_mngr->acquired_vf[type][vf].start_cid = 0;
1033                 }
1034         }
1035 }
1036
1037 static enum _ecore_status_t
1038 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1039                            u32 cid_start, u32 cid_count,
1040                            struct ecore_cid_acquired_map *p_map)
1041 {
1042         u32 size;
1043
1044         if (!cid_count)
1045                 return ECORE_SUCCESS;
1046
1047         size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1048         p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1049         if (p_map->cid_map == OSAL_NULL)
1050                 return ECORE_NOMEM;
1051
1052         p_map->max_count = cid_count;
1053         p_map->start_cid = cid_start;
1054
1055         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1056                    "Type %08x start: %08x count %08x\n",
1057                    type, p_map->start_cid, p_map->max_count);
1058
1059         return ECORE_SUCCESS;
1060 }
1061
1062 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1063 {
1064         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1065         u32 start_cid = 0, vf_start_cid = 0;
1066         u32 type, vf;
1067
1068         for (type = 0; type < MAX_CONN_TYPES; type++) {
1069                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1070                 struct ecore_cid_acquired_map *p_map;
1071
1072                 /* Handle PF maps */
1073                 p_map = &p_mngr->acquired[type];
1074                 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1075                                                p_cfg->cid_count, p_map))
1076                         goto cid_map_fail;
1077
1078                 /* Handle VF maps */
1079                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1080                         p_map = &p_mngr->acquired_vf[type][vf];
1081                         if (ecore_cid_map_alloc_single(p_hwfn, type,
1082                                                        vf_start_cid,
1083                                                        p_cfg->cids_per_vf,
1084                                                        p_map))
1085                                 goto cid_map_fail;
1086                 }
1087
1088                 start_cid += p_cfg->cid_count;
1089                 vf_start_cid += p_cfg->cids_per_vf;
1090         }
1091
1092         return ECORE_SUCCESS;
1093
1094 cid_map_fail:
1095         ecore_cid_map_free(p_hwfn);
1096         return ECORE_NOMEM;
1097 }
1098
1099 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1100 {
1101         struct ecore_ilt_client_cfg *clients;
1102         struct ecore_cxt_mngr *p_mngr;
1103         u32 i;
1104
1105         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1106         if (!p_mngr) {
1107                 DP_NOTICE(p_hwfn, true,
1108                           "Failed to allocate `struct ecore_cxt_mngr'\n");
1109                 return ECORE_NOMEM;
1110         }
1111
1112         /* Initialize ILT client registers */
1113         clients = p_mngr->clients;
1114         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1115         clients[ILT_CLI_CDUC].last.reg  = ILT_CFG_REG(CDUC, LAST_ILT);
1116         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1117
1118         clients[ILT_CLI_QM].first.reg   = ILT_CFG_REG(QM, FIRST_ILT);
1119         clients[ILT_CLI_QM].last.reg    = ILT_CFG_REG(QM, LAST_ILT);
1120         clients[ILT_CLI_QM].p_size.reg  = ILT_CFG_REG(QM, P_SIZE);
1121
1122         clients[ILT_CLI_TM].first.reg   = ILT_CFG_REG(TM, FIRST_ILT);
1123         clients[ILT_CLI_TM].last.reg    = ILT_CFG_REG(TM, LAST_ILT);
1124         clients[ILT_CLI_TM].p_size.reg  = ILT_CFG_REG(TM, P_SIZE);
1125
1126         clients[ILT_CLI_SRC].first.reg  = ILT_CFG_REG(SRC, FIRST_ILT);
1127         clients[ILT_CLI_SRC].last.reg   = ILT_CFG_REG(SRC, LAST_ILT);
1128         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1129
1130         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1131         clients[ILT_CLI_CDUT].last.reg  = ILT_CFG_REG(CDUT, LAST_ILT);
1132         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1133
1134         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1135         clients[ILT_CLI_TSDM].last.reg  = ILT_CFG_REG(TSDM, LAST_ILT);
1136         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1137
1138         /* default ILT page size for all clients is 32K */
1139         for (i = 0; i < ILT_CLI_MAX; i++)
1140                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1141
1142         /* due to removal of ISCSI/FCoE files union type0_task_context
1143          * task_type_size will be 0. So hardcoded for now.
1144          */
1145         p_mngr->task_type_size[0] = 512; /* @DPDK */
1146         p_mngr->task_type_size[1] = 128; /* @DPDK */
1147
1148         if (p_hwfn->p_dev->p_iov_info)
1149                 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1150
1151         /* Initialize the dynamic ILT allocation mutex */
1152         OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1153         OSAL_MUTEX_INIT(&p_mngr->mutex);
1154
1155         /* Set the cxt mangr pointer priori to further allocations */
1156         p_hwfn->p_cxt_mngr = p_mngr;
1157
1158         return ECORE_SUCCESS;
1159 }
1160
1161 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1162 {
1163         enum _ecore_status_t rc;
1164
1165         /* Allocate the ILT shadow table */
1166         rc = ecore_ilt_shadow_alloc(p_hwfn);
1167         if (rc) {
1168                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1169                 goto tables_alloc_fail;
1170         }
1171
1172         /* Allocate the T2  table */
1173         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1174         if (rc) {
1175                 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1176                 goto tables_alloc_fail;
1177         }
1178
1179         /* Allocate and initialize the acquired cids bitmaps */
1180         rc = ecore_cid_map_alloc(p_hwfn);
1181         if (rc) {
1182                 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1183                 goto tables_alloc_fail;
1184         }
1185
1186         return ECORE_SUCCESS;
1187
1188 tables_alloc_fail:
1189         ecore_cxt_mngr_free(p_hwfn);
1190         return rc;
1191 }
1192
1193 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1194 {
1195         if (!p_hwfn->p_cxt_mngr)
1196                 return;
1197
1198         ecore_cid_map_free(p_hwfn);
1199         ecore_cxt_src_t2_free(p_hwfn);
1200         ecore_ilt_shadow_free(p_hwfn);
1201         OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1202         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1203 }
1204
1205 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1206 {
1207         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1208         struct ecore_cid_acquired_map *p_map;
1209         struct ecore_conn_type_cfg *p_cfg;
1210         int type;
1211         u32 len;
1212
1213         /* Reset acquired cids */
1214         for (type = 0; type < MAX_CONN_TYPES; type++) {
1215                 u32 vf;
1216
1217                 p_cfg = &p_mngr->conn_cfg[type];
1218                 if (p_cfg->cid_count) {
1219                         p_map = &p_mngr->acquired[type];
1220                         len = DIV_ROUND_UP(p_map->max_count,
1221                                            BITS_PER_MAP_WORD) *
1222                               MAP_WORD_SIZE;
1223                         OSAL_MEM_ZERO(p_map->cid_map, len);
1224                 }
1225
1226                 if (!p_cfg->cids_per_vf)
1227                         continue;
1228
1229                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1230                         p_map = &p_mngr->acquired_vf[type][vf];
1231                         len = DIV_ROUND_UP(p_map->max_count,
1232                                            BITS_PER_MAP_WORD) *
1233                               MAP_WORD_SIZE;
1234                         OSAL_MEM_ZERO(p_map->cid_map, len);
1235                 }
1236         }
1237 }
1238
1239 /* HW initialization helper (per Block, per phase) */
1240
1241 /* CDU Common */
1242 #define CDUC_CXT_SIZE_SHIFT                                             \
1243         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1244
1245 #define CDUC_CXT_SIZE_MASK                                              \
1246         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1247
1248 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1249         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1250
1251 #define CDUC_BLOCK_WASTE_MASK                                           \
1252         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1253
1254 #define CDUC_NCIB_SHIFT                                                 \
1255         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1256
1257 #define CDUC_NCIB_MASK                                                  \
1258         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1259
1260 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1261         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1262
1263 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1264         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1265         CDUT_TYPE0_CXT_SIZE_SHIFT)
1266
1267 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1268         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1269
1270 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1271         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1272         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1273
1274 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1275         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1276
1277 #define CDUT_TYPE0_NCIB_MASK                                            \
1278         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1279         CDUT_TYPE0_NCIB_SHIFT)
1280
1281 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1282         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1283
1284 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1285         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1286         CDUT_TYPE1_CXT_SIZE_SHIFT)
1287
1288 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1289         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1290
1291 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1292         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1293         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1294
1295 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1296         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1297
1298 #define CDUT_TYPE1_NCIB_MASK                                            \
1299         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1300         CDUT_TYPE1_NCIB_SHIFT)
1301
1302 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1303 {
1304         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1305
1306         /* CDUC - connection configuration */
1307         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1308         cxt_size = CONN_CXT_SIZE(p_hwfn);
1309         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1310         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1311
1312         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1313         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1314         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1315         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1316
1317         /* CDUT - type-0 tasks configuration */
1318         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1319         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1320         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1321         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1322
1323         /* cxt size and block-waste are multipes of 8 */
1324         cdu_params = 0;
1325         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1326         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1327         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1328         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1329
1330         /* CDUT - type-1 tasks configuration */
1331         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1332         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1333         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1334
1335         /* cxt size and block-waste are multipes of 8 */
1336         cdu_params = 0;
1337         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1338         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1339         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1340         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1341 }
1342
1343 /* CDU PF */
1344 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1345 #define CDU_SEG_REG_TYPE_MASK           0x1
1346 #define CDU_SEG_REG_OFFSET_SHIFT        0
1347 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1348
1349 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1350 {
1351         struct ecore_ilt_client_cfg *p_cli;
1352         struct ecore_tid_seg *p_seg;
1353         u32 cdu_seg_params, offset;
1354         int i;
1355
1356         static const u32 rt_type_offset_arr[] = {
1357                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1358                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1359                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1360                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1361         };
1362
1363         static const u32 rt_type_offset_fl_arr[] = {
1364                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1365                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1366                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1367                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1368         };
1369
1370         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1371
1372         /* There are initializations only for CDUT during pf Phase */
1373         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1374                 /* Segment 0 */
1375                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1376                 if (!p_seg)
1377                         continue;
1378
1379                 /* Note: start_line is already adjusted for the CDU
1380                  * segment register granularity, so we just need to
1381                  * divide. Adjustment is implicit as we assume ILT
1382                  * Page size is larger than 32K!
1383                  */
1384                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1385                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1386                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1387
1388                 cdu_seg_params = 0;
1389                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1390                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1391                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1392
1393                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1394                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1395                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1396
1397                 cdu_seg_params = 0;
1398                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1399                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1400                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1401         }
1402 }
1403
1404 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1405 {
1406         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1407         struct ecore_qm_iids iids;
1408
1409         OSAL_MEM_ZERO(&iids, sizeof(iids));
1410         ecore_cxt_qm_iids(p_hwfn, &iids);
1411
1412         ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1413                             p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1414                             p_hwfn->first_on_engine,
1415                             iids.cids, iids.vf_cids, iids.tids,
1416                             qm_info->start_pq,
1417                             qm_info->num_pqs - qm_info->num_vf_pqs,
1418                             qm_info->num_vf_pqs,
1419                             qm_info->start_vport,
1420                             qm_info->num_vports, qm_info->pf_wfq,
1421                             qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1422                             p_hwfn->qm_info.qm_vport_params);
1423 }
1424
1425 /* CM PF */
1426 void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1427 {
1428         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1429                      ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1430 }
1431
1432 /* DQ PF */
1433 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1434 {
1435         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1436         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1437
1438         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1439         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1440
1441         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1442         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1443
1444         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1445         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1446
1447         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1448         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1449
1450         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1451         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1452
1453         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1454         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1455
1456         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1457         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1458
1459         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1460         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1461
1462         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1463         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1464
1465         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1466         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1467
1468         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1469         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1470
1471         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1472         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1473
1474         /* Connection types 6 & 7 are not in use, yet they must be configured
1475          * as the highest possible connection. Not configuring them means the
1476          * defaults will be  used, and with a large number of cids a bug may
1477          * occur, if the defaults will be smaller than dq_pf_max_cid /
1478          * dq_vf_max_cid.
1479          */
1480         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1481         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1482
1483         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1484         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1485 }
1486
1487 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1488 {
1489         struct ecore_ilt_client_cfg *ilt_clients;
1490         int i;
1491
1492         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1493         for_each_ilt_valid_client(i, ilt_clients) {
1494                 STORE_RT_REG(p_hwfn,
1495                              ilt_clients[i].first.reg,
1496                              ilt_clients[i].first.val);
1497                 STORE_RT_REG(p_hwfn,
1498                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1499                 STORE_RT_REG(p_hwfn,
1500                              ilt_clients[i].p_size.reg,
1501                              ilt_clients[i].p_size.val);
1502         }
1503 }
1504
1505 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1506 {
1507         struct ecore_ilt_client_cfg *p_cli;
1508         u32 blk_factor;
1509
1510         /* For simplicty  we set the 'block' to be an ILT page */
1511         if (p_hwfn->p_dev->p_iov_info) {
1512                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1513
1514                 STORE_RT_REG(p_hwfn,
1515                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1516                              p_iov->first_vf_in_pf);
1517                 STORE_RT_REG(p_hwfn,
1518                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1519                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1520         }
1521
1522         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1523         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1524         if (p_cli->active) {
1525                 STORE_RT_REG(p_hwfn,
1526                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1527                              blk_factor);
1528                 STORE_RT_REG(p_hwfn,
1529                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1530                              p_cli->pf_total_lines);
1531                 STORE_RT_REG(p_hwfn,
1532                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1533                              p_cli->vf_total_lines);
1534         }
1535
1536         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1537         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1538         if (p_cli->active) {
1539                 STORE_RT_REG(p_hwfn,
1540                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1541                              blk_factor);
1542                 STORE_RT_REG(p_hwfn,
1543                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1544                              p_cli->pf_total_lines);
1545                 STORE_RT_REG(p_hwfn,
1546                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1547                              p_cli->vf_total_lines);
1548         }
1549
1550         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1551         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1552         if (p_cli->active) {
1553                 STORE_RT_REG(p_hwfn,
1554                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1555                 STORE_RT_REG(p_hwfn,
1556                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1557                              p_cli->pf_total_lines);
1558                 STORE_RT_REG(p_hwfn,
1559                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1560                              p_cli->vf_total_lines);
1561         }
1562 }
1563
1564 /* ILT (PSWRQ2) PF */
1565 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1566 {
1567         struct ecore_ilt_client_cfg *clients;
1568         struct ecore_cxt_mngr *p_mngr;
1569         struct ecore_dma_mem *p_shdw;
1570         u32 line, rt_offst, i;
1571
1572         ecore_ilt_bounds_init(p_hwfn);
1573         ecore_ilt_vf_bounds_init(p_hwfn);
1574
1575         p_mngr = p_hwfn->p_cxt_mngr;
1576         p_shdw = p_mngr->ilt_shadow;
1577         clients = p_hwfn->p_cxt_mngr->clients;
1578
1579         for_each_ilt_valid_client(i, clients) {
1580                 /* Client's 1st val and RT array are absolute, ILT shadows'
1581                  * lines are relative.
1582                  */
1583                 line = clients[i].first.val - p_mngr->pf_start_line;
1584                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1585                     clients[i].first.val * ILT_ENTRY_IN_REGS;
1586
1587                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1588                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1589                         u64 ilt_hw_entry = 0;
1590
1591                         /** p_virt could be OSAL_NULL incase of dynamic
1592                          *  allocation
1593                          */
1594                         if (p_shdw[line].p_virt != OSAL_NULL) {
1595                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1596                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1597                                           (p_shdw[line].p_phys >> 12));
1598
1599                                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1600                                         "Setting RT[0x%08x] from"
1601                                         " ILT[0x%08x] [Client is %d] to"
1602                                         " Physical addr: 0x%lx\n",
1603                                         rt_offst, line, i,
1604                                         (unsigned long)(p_shdw[line].
1605                                                         p_phys >> 12));
1606                         }
1607
1608                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1609                 }
1610         }
1611 }
1612
1613 /* SRC (Searcher) PF */
1614 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1615 {
1616         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1617         u32 rounded_conn_num, conn_num, conn_max;
1618         struct ecore_src_iids src_iids;
1619
1620         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1621         ecore_cxt_src_iids(p_mngr, &src_iids);
1622         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1623         if (!conn_num)
1624                 return;
1625
1626         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1627         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1628
1629         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1630         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1631                      OSAL_LOG2(rounded_conn_num));
1632
1633         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1634                          p_hwfn->p_cxt_mngr->first_free);
1635         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1636                          p_hwfn->p_cxt_mngr->last_free);
1637 }
1638
1639 /* Timers PF */
1640 #define TM_CFG_NUM_IDS_SHIFT            0
1641 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1642 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1643 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1644 #define TM_CFG_PARENT_PF_SHIFT          25
1645 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1646
1647 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1648 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1649
1650 #define TM_CFG_TID_OFFSET_SHIFT         30
1651 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1652 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1653 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1654
1655 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1656 {
1657         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1658         u32 active_seg_mask = 0, tm_offset, rt_reg;
1659         struct ecore_tm_iids tm_iids;
1660         u64 cfg_word;
1661         u8 i;
1662
1663         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1664         ecore_cxt_tm_iids(p_mngr, &tm_iids);
1665
1666         /* @@@TBD No pre-scan for now */
1667
1668         /* Note: We assume consecutive VFs for a PF */
1669         for (i = 0; i < p_mngr->vf_count; i++) {
1670                 cfg_word = 0;
1671                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1672                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1673                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1674                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1675
1676                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1677                     (sizeof(cfg_word) / sizeof(u32)) *
1678                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1679                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1680         }
1681
1682         cfg_word = 0;
1683         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1684         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1685         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1686         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all   */
1687
1688         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1689             (sizeof(cfg_word) / sizeof(u32)) *
1690             (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1691         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1692
1693         /* enale scan */
1694         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1695                      tm_iids.pf_cids ? 0x1 : 0x0);
1696
1697         /* @@@TBD how to enable the scan for the VFs */
1698
1699         tm_offset = tm_iids.per_vf_cids;
1700
1701         /* Note: We assume consecutive VFs for a PF */
1702         for (i = 0; i < p_mngr->vf_count; i++) {
1703                 cfg_word = 0;
1704                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1705                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1706                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1707                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1708                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1709
1710                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1711                     (sizeof(cfg_word) / sizeof(u32)) *
1712                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1713
1714                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1715         }
1716
1717         tm_offset = tm_iids.pf_cids;
1718         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1719                 cfg_word = 0;
1720                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1721                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1722                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1723                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1724                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1725
1726                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1727                     (sizeof(cfg_word) / sizeof(u32)) *
1728                     (NUM_OF_VFS(p_hwfn->p_dev) +
1729                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1730
1731                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1732                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1733
1734                 tm_offset += tm_iids.pf_tids[i];
1735         }
1736
1737         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1738
1739         /* @@@TBD how to enable the scan for the VFs */
1740 }
1741
1742 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1743 {
1744         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1745         struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1746         struct ecore_tid_seg *p_tid;
1747
1748         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1749         if (!p_fcoe->cid_count)
1750                 return;
1751
1752         p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1753         STORE_RT_REG_AGG(p_hwfn,
1754                         PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1755                         p_tid->count);
1756 }
1757
1758 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1759 {
1760         /* CDU configuration */
1761         ecore_cdu_init_common(p_hwfn);
1762 }
1763
1764 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1765 {
1766         ecore_qm_init_pf(p_hwfn);
1767         ecore_cm_init_pf(p_hwfn);
1768         ecore_dq_init_pf(p_hwfn);
1769         ecore_cdu_init_pf(p_hwfn);
1770         ecore_ilt_init_pf(p_hwfn);
1771         ecore_src_init_pf(p_hwfn);
1772         ecore_tm_init_pf(p_hwfn);
1773         ecore_prs_init_pf(p_hwfn);
1774 }
1775
1776 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1777                                             enum protocol_type type,
1778                                             u32 *p_cid, u8 vfid)
1779 {
1780         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1781         struct ecore_cid_acquired_map *p_map;
1782         u32 rel_cid;
1783
1784         if (type >= MAX_CONN_TYPES) {
1785                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1786                 return ECORE_INVAL;
1787         }
1788
1789         if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) {
1790                 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1791                 return ECORE_INVAL;
1792         }
1793
1794         /* Determine the right map to take this CID from */
1795         if (vfid == ECORE_CXT_PF_CID)
1796                 p_map = &p_mngr->acquired[type];
1797         else
1798                 p_map = &p_mngr->acquired_vf[type][vfid];
1799
1800         if (p_map->cid_map == OSAL_NULL) {
1801                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1802                 return ECORE_INVAL;
1803         }
1804
1805         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1806                                            p_map->max_count);
1807
1808         if (rel_cid >= p_map->max_count) {
1809                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1810                           type);
1811                 return ECORE_NORESOURCES;
1812         }
1813
1814         OSAL_SET_BIT(rel_cid, p_map->cid_map);
1815
1816         *p_cid = rel_cid + p_map->start_cid;
1817
1818         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1819                    "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1820                    *p_cid, rel_cid, vfid, type);
1821
1822         return ECORE_SUCCESS;
1823 }
1824
1825 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1826                                            enum protocol_type type,
1827                                            u32 *p_cid)
1828 {
1829         return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
1830 }
1831
1832 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1833                                         u32 cid, u8 vfid,
1834                                         enum protocol_type *p_type,
1835                                         struct ecore_cid_acquired_map **pp_map)
1836 {
1837         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1838         u32 rel_cid;
1839
1840         /* Iterate over protocols and find matching cid range */
1841         for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1842                 if (vfid == ECORE_CXT_PF_CID)
1843                         *pp_map = &p_mngr->acquired[*p_type];
1844                 else
1845                         *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1846
1847                 if (!((*pp_map)->cid_map))
1848                         continue;
1849                 if (cid >= (*pp_map)->start_cid &&
1850                     cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
1851                         break;
1852                 }
1853         }
1854         if (*p_type == MAX_CONN_TYPES) {
1855                 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
1856                 goto fail;
1857         }
1858
1859         rel_cid = cid - (*pp_map)->start_cid;
1860         if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
1861                 DP_NOTICE(p_hwfn, true,
1862                           "CID %d [vifd %02x] not acquired", cid, vfid);
1863                 goto fail;
1864         }
1865
1866         return true;
1867 fail:
1868         *p_type = MAX_CONN_TYPES;
1869         *pp_map = OSAL_NULL;
1870         return false;
1871 }
1872
1873 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
1874 {
1875         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1876         enum protocol_type type;
1877         bool b_acquired;
1878         u32 rel_cid;
1879
1880         if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) {
1881                 DP_NOTICE(p_hwfn, true,
1882                           "Trying to return incorrect CID belonging to VF %02x\n",
1883                           vfid);
1884                 return;
1885         }
1886
1887         /* Test acquired and find matching per-protocol map */
1888         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
1889                                                  &type, &p_map);
1890
1891         if (!b_acquired)
1892                 return;
1893
1894         rel_cid = cid - p_map->start_cid;
1895         OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
1896
1897         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1898                    "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
1899                    cid, rel_cid, vfid, type);
1900 }
1901
1902 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1903 {
1904         _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
1905 }
1906
1907 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1908                                             struct ecore_cxt_info *p_info)
1909 {
1910         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1911         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1912         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1913         enum protocol_type type;
1914         bool b_acquired;
1915
1916         /* Test acquired and find matching per-protocol map */
1917         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
1918                                                  ECORE_CXT_PF_CID,
1919                                                  &type, &p_map);
1920
1921         if (!b_acquired)
1922                 return ECORE_INVAL;
1923
1924         /* set the protocl type */
1925         p_info->type = type;
1926
1927         /* compute context virtual pointer */
1928         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1929
1930         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1931         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1932         line = p_info->iid / cxts_per_p;
1933
1934         /* Make sure context is allocated (dynamic allocation) */
1935         if (!p_mngr->ilt_shadow[line].p_virt)
1936                 return ECORE_INVAL;
1937
1938         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1939             p_info->iid % cxts_per_p * conn_cxt_size;
1940
1941         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1942                 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1943                 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1944
1945         return ECORE_SUCCESS;
1946 }
1947
1948 void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
1949 {
1950         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1951
1952         p_mgr->srq_count = num_srqs;
1953 }
1954
1955 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
1956 {
1957         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1958
1959         return p_mgr->srq_count;
1960 }
1961
1962 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1963 {
1964         /* Set the number of required CORE connections */
1965         u32 core_cids = 1;      /* SPQ */
1966
1967         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1968
1969         switch (p_hwfn->hw_info.personality) {
1970         case ECORE_PCI_ETH:
1971                 {
1972                         struct ecore_eth_pf_params *p_params =
1973                             &p_hwfn->pf_params.eth_pf_params;
1974
1975                         /* TODO - we probably want to add VF number to the PF
1976                          * params;
1977                          * As of now, allocates 16 * 2 per-VF [to retain regular
1978                          * functionality].
1979                          */
1980                         ecore_cxt_set_proto_cid_count(p_hwfn,
1981                                 PROTOCOLID_ETH,
1982                                 p_params->num_cons, 32);
1983
1984                         break;
1985                 }
1986         default:
1987                 return ECORE_INVAL;
1988         }
1989
1990         return ECORE_SUCCESS;
1991 }
1992
1993 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
1994                                                 struct ecore_tid_mem *p_info)
1995 {
1996         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1997         u32 proto, seg, total_lines, i, shadow_line;
1998         struct ecore_ilt_client_cfg *p_cli;
1999         struct ecore_ilt_cli_blk *p_fl_seg;
2000         struct ecore_tid_seg *p_seg_info;
2001
2002         /* Verify the personality */
2003         switch (p_hwfn->hw_info.personality) {
2004         default:
2005                 return ECORE_INVAL;
2006         }
2007
2008         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2009         if (!p_cli->active)
2010                 return ECORE_INVAL;
2011
2012         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2013         if (!p_seg_info->has_fl_mem)
2014                 return ECORE_INVAL;
2015
2016         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2017         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
2018                                    p_fl_seg->real_size_in_page);
2019
2020         for (i = 0; i < total_lines; i++) {
2021                 shadow_line = i + p_fl_seg->start_line -
2022                     p_hwfn->p_cxt_mngr->pf_start_line;
2023                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
2024         }
2025         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
2026             p_fl_seg->real_size_in_page;
2027         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
2028         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
2029             p_info->tid_size;
2030
2031         return ECORE_SUCCESS;
2032 }
2033
2034 /* This function is very RoCE oriented, if another protocol in the future
2035  * will want this feature we'll need to modify the function to be more generic
2036  */
2037 enum _ecore_status_t
2038 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2039                             enum ecore_cxt_elem_type elem_type,
2040                             u32 iid)
2041 {
2042         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2043         struct ecore_ilt_client_cfg *p_cli;
2044         struct ecore_ilt_cli_blk *p_blk;
2045         struct ecore_ptt *p_ptt;
2046         dma_addr_t p_phys;
2047         u64 ilt_hw_entry;
2048         void *p_virt;
2049         enum _ecore_status_t rc = ECORE_SUCCESS;
2050
2051         switch (elem_type) {
2052         case ECORE_ELEM_CXT:
2053                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2054                 elem_size = CONN_CXT_SIZE(p_hwfn);
2055                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2056                 break;
2057         case ECORE_ELEM_SRQ:
2058                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2059                 elem_size = SRQ_CXT_SIZE;
2060                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2061                 break;
2062         case ECORE_ELEM_TASK:
2063                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2064                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2065                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2066                 break;
2067         default:
2068                 DP_NOTICE(p_hwfn, false,
2069                           "ECORE_INVALID elem type = %d", elem_type);
2070                 return ECORE_INVAL;
2071         }
2072
2073         /* Calculate line in ilt */
2074         hw_p_size = p_cli->p_size.val;
2075         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2076         line = p_blk->start_line + (iid / elems_per_p);
2077         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2078
2079         /* If line is already allocated, do nothing, otherwise allocate it and
2080          * write it to the PSWRQ2 registers.
2081          * This section can be run in parallel from different contexts and thus
2082          * a mutex protection is needed.
2083          */
2084
2085         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2086
2087         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2088                 goto out0;
2089
2090         p_ptt = ecore_ptt_acquire(p_hwfn);
2091         if (!p_ptt) {
2092                 DP_NOTICE(p_hwfn, false,
2093                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2094                 rc = ECORE_TIMEOUT;
2095                 goto out0;
2096         }
2097
2098         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2099                                          &p_phys,
2100                                          p_blk->real_size_in_page);
2101         if (!p_virt) {
2102                 rc = ECORE_NOMEM;
2103                 goto out1;
2104         }
2105         OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2106
2107         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2108         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2109         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2110                 p_blk->real_size_in_page;
2111
2112         /* compute absolute offset */
2113         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2114                      (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2115
2116         ilt_hw_entry = 0;
2117         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2118         SET_FIELD(ilt_hw_entry,
2119                   ILT_ENTRY_PHY_ADDR,
2120                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2121
2122 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2123
2124         ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2125                             reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2126                             0 /* no flags */);
2127
2128         if (elem_type == ECORE_ELEM_CXT) {
2129                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2130                                          elems_per_p;
2131
2132                 /* Update the relevant register in the parser */
2133                 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2134                          last_cid_allocated - 1);
2135
2136                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2137                         /* Enable RoCE search */
2138                         ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2139                         p_hwfn->b_rdma_enabled_in_prs = true;
2140                 }
2141         }
2142
2143 out1:
2144         ecore_ptt_release(p_hwfn, p_ptt);
2145 out0:
2146         OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2147
2148         return rc;
2149 }
2150
2151 /* This function is very RoCE oriented, if another protocol in the future
2152  * will want this feature we'll need to modify the function to be more generic
2153  */
2154 static enum _ecore_status_t
2155 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2156                          enum ecore_cxt_elem_type elem_type,
2157                          u32 start_iid, u32 count)
2158 {
2159         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2160         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2161         struct ecore_ilt_client_cfg *p_cli;
2162         struct ecore_ilt_cli_blk *p_blk;
2163         u32 end_iid = start_iid + count;
2164         struct ecore_ptt *p_ptt;
2165         u64 ilt_hw_entry = 0;
2166         u32 i;
2167
2168         switch (elem_type) {
2169         case ECORE_ELEM_CXT:
2170                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2171                 elem_size = CONN_CXT_SIZE(p_hwfn);
2172                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2173                 break;
2174         case ECORE_ELEM_SRQ:
2175                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2176                 elem_size = SRQ_CXT_SIZE;
2177                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2178                 break;
2179         case ECORE_ELEM_TASK:
2180                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2181                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2182                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2183                 break;
2184         default:
2185                 DP_NOTICE(p_hwfn, false,
2186                           "ECORE_INVALID elem type = %d", elem_type);
2187                 return ECORE_INVAL;
2188         }
2189
2190         /* Calculate line in ilt */
2191         hw_p_size = p_cli->p_size.val;
2192         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2193         start_line = p_blk->start_line + (start_iid / elems_per_p);
2194         end_line = p_blk->start_line + (end_iid / elems_per_p);
2195         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2196                 end_line--;
2197
2198         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2199         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2200
2201         p_ptt = ecore_ptt_acquire(p_hwfn);
2202         if (!p_ptt) {
2203                 DP_NOTICE(p_hwfn, false,
2204                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2205                 return ECORE_TIMEOUT;
2206         }
2207
2208         for (i = shadow_start_line; i < shadow_end_line; i++) {
2209                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2210                         continue;
2211
2212                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2213                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2214                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2215                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2216
2217                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2218                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2219                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2220
2221                 /* compute absolute offset */
2222                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2223                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2224                      ILT_ENTRY_IN_REGS);
2225
2226                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2227                  * wide-bus.
2228                  */
2229                 ecore_dmae_host2grc(p_hwfn, p_ptt,
2230                                     (u64)(osal_uintptr_t)&ilt_hw_entry,
2231                                     reg_offset,
2232                                     sizeof(ilt_hw_entry) / sizeof(u32),
2233                                     0 /* no flags */);
2234         }
2235
2236         ecore_ptt_release(p_hwfn, p_ptt);
2237
2238         return ECORE_SUCCESS;
2239 }
2240
2241 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2242                                               enum protocol_type proto)
2243 {
2244         enum _ecore_status_t rc;
2245         u32 cid;
2246
2247         /* Free Connection CXT */
2248         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2249                                       ecore_cxt_get_proto_cid_start(p_hwfn,
2250                                                                     proto),
2251                                       ecore_cxt_get_proto_cid_count(p_hwfn,
2252                                                                     proto,
2253                                                                     &cid));
2254
2255         if (rc)
2256                 return rc;
2257
2258         /* Free Task CXT */
2259         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2260                                       ecore_cxt_get_proto_tid_count(p_hwfn,
2261                                                                     proto));
2262         if (rc)
2263                 return rc;
2264
2265         /* Free TSDM CXT */
2266         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2267                                       ecore_cxt_get_srq_count(p_hwfn));
2268
2269         return rc;
2270 }
2271
2272 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
2273                                             u32 tid,
2274                                             u8 ctx_type, void **pp_task_ctx)
2275 {
2276         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2277         struct ecore_ilt_client_cfg *p_cli;
2278         struct ecore_ilt_cli_blk *p_seg;
2279         struct ecore_tid_seg *p_seg_info;
2280         u32 proto, seg;
2281         u32 total_lines;
2282         u32 tid_size, ilt_idx;
2283         u32 num_tids_per_block;
2284
2285         /* Verify the personality */
2286         switch (p_hwfn->hw_info.personality) {
2287         default:
2288                 return ECORE_INVAL;
2289         }
2290
2291         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2292         if (!p_cli->active)
2293                 return ECORE_INVAL;
2294
2295         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2296
2297         if (ctx_type == ECORE_CTX_WORKING_MEM) {
2298                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2299         } else if (ctx_type == ECORE_CTX_FL_MEM) {
2300                 if (!p_seg_info->has_fl_mem)
2301                         return ECORE_INVAL;
2302                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2303         } else {
2304                 return ECORE_INVAL;
2305         }
2306         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2307         tid_size = p_mngr->task_type_size[p_seg_info->type];
2308         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2309
2310         if (total_lines < tid / num_tids_per_block)
2311                 return ECORE_INVAL;
2312
2313         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2314             p_mngr->pf_start_line;
2315         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2316             (tid % num_tids_per_block) * tid_size;
2317
2318         return ECORE_SUCCESS;
2319 }