2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "common_hsi.h"
12 #include "ecore_hsi_common.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_status.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_init_fw_funcs.h"
19 #include "ecore_cxt.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
23 #include "ecore_mcp.h"
25 /* Max number of connection types in HW (DQ/CDU etc.) */
26 #define MAX_CONN_TYPES PROTOCOLID_COMMON
27 #define NUM_TASK_TYPES 2
28 #define NUM_TASK_PF_SEGMENTS 4
29 #define NUM_TASK_VF_SEGMENTS 1
31 /* Doorbell-Queue constants */
32 #define DQ_RANGE_SHIFT 4
33 #define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT)
35 /* Searcher constants */
36 #define SRC_MIN_NUM_ELEMS 256
38 /* Timers constants */
40 #define TM_ALIGN (1 << TM_SHIFT)
41 #define TM_ELEM_SIZE 4
44 /* If for some reason, HW P size is modified to be less than 32K,
45 * special handling needs to be made for CDU initialization
47 #define ILT_DEFAULT_HW_P_SIZE 3
49 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
50 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
52 /* ILT entry structure */
53 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
54 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
55 #define ILT_ENTRY_VALID_MASK 0x1ULL
56 #define ILT_ENTRY_VALID_SHIFT 52
57 #define ILT_ENTRY_IN_REGS 2
58 #define ILT_REG_SIZE_IN_BYTES 4
60 /* connection context union */
62 struct core_conn_context core_ctx;
63 struct eth_conn_context eth_ctx;
66 /* TYPE-0 task context - iSCSI, FCOE */
67 union type0_task_context {
70 /* TYPE-1 task context - ROCE */
71 union type1_task_context {
79 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
80 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
82 #define CONN_CXT_SIZE(p_hwfn) \
83 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
85 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
87 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
88 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
90 /* Alignment is inherent to the type1_task_context structure */
91 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
93 /* PF per protocl configuration object */
94 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
95 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
97 struct ecore_tid_seg {
103 struct ecore_conn_type_cfg {
106 struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
109 /* ILT Client configuration,
110 * Per connection type (protocol) resources (cids, tis, vf cids etc.)
111 * 1 - for connection context (CDUC) and for each task context we need two
112 * values, for regular task context and for force load memory
114 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
115 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
118 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
119 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS)
131 struct ilt_cfg_pair {
136 struct ecore_ilt_cli_blk {
137 u32 total_size; /* 0 means not active */
138 u32 real_size_in_page;
140 u32 dynamic_line_cnt;
143 struct ecore_ilt_client_cfg {
147 struct ilt_cfg_pair first;
148 struct ilt_cfg_pair last;
149 struct ilt_cfg_pair p_size;
151 /* ILT client blocks for PF */
152 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
155 /* ILT client blocks for VFs */
156 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
162 * Protocol acquired CID lists
163 * PF start line in ILT
165 struct ecore_dma_mem {
171 #define MAP_WORD_SIZE sizeof(unsigned long)
172 #define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8)
174 struct ecore_cid_acquired_map {
177 unsigned long *cid_map;
180 struct ecore_cxt_mngr {
181 /* Per protocl configuration */
182 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
184 /* computed ILT structure */
185 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
187 /* Task type sizes */
188 u32 task_type_size[NUM_TASK_TYPES];
190 /* total number of VFs for this hwfn -
191 * ALL VFs are symmetric in terms of HW resources
196 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
197 /* TBD - do we want this allocated to reserve space? */
198 struct ecore_cid_acquired_map
199 acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS];
201 /* ILT shadow table */
202 struct ecore_dma_mem *ilt_shadow;
205 /* Mutex for a dynamic ILT allocation */
209 struct ecore_dma_mem *t2;
214 /* The infrastructure originally was very generic and context/task
215 * oriented - per connection-type we would set how many of those
216 * are needed, and later when determining how much memory we're
217 * needing for a given block we'd iterate over all the relevant
219 * But since then we've had some additional resources, some of which
220 * require memory which is indepent of the general context/task
221 * scheme. We add those here explicitly per-feature.
224 /* total number of SRQ's for this hwfn */
227 /* Maximal number of L2 steering filters */
230 /* TODO - VF arfs filters ? */
233 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
235 return type == PROTOCOLID_TOE;
238 static bool tm_tid_proto(enum protocol_type type)
240 return type == PROTOCOLID_FCOE;
243 /* counts the iids for the CDU/CDUC ILT client configuration */
244 struct ecore_cdu_iids {
249 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
250 struct ecore_cdu_iids *iids)
254 for (type = 0; type < MAX_CONN_TYPES; type++) {
255 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
256 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
260 /* counts the iids for the Searcher block configuration */
261 struct ecore_src_iids {
266 static void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
267 struct ecore_src_iids *iids)
271 for (i = 0; i < MAX_CONN_TYPES; i++) {
272 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
273 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
276 /* Add L2 filtering filters in addition */
277 iids->pf_cids += p_mngr->arfs_count;
280 /* counts the iids for the Timers block configuration */
281 struct ecore_tm_iids {
283 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
289 static void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
290 struct ecore_tm_iids *iids)
292 bool tm_vf_required = false;
293 bool tm_required = false;
296 for (i = 0; i < MAX_CONN_TYPES; i++) {
297 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
299 if (tm_cid_proto(i) || tm_required) {
300 if (p_cfg->cid_count)
303 iids->pf_cids += p_cfg->cid_count;
306 if (tm_cid_proto(i) || tm_vf_required) {
307 if (p_cfg->cids_per_vf)
308 tm_vf_required = true;
312 if (tm_tid_proto(i)) {
313 struct ecore_tid_seg *segs = p_cfg->tid_seg;
315 /* for each segment there is at most one
316 * protocol for which count is not 0.
318 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
319 iids->pf_tids[j] += segs[j].count;
321 /* The last array elelment is for the VFs. As for PF
322 * segments there can be only one protocol for
323 * which this value is not 0.
325 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
329 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
330 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
331 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
333 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
334 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
335 iids->pf_tids_total += iids->pf_tids[j];
339 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
340 struct ecore_qm_iids *iids)
342 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
343 struct ecore_tid_seg *segs;
344 u32 vf_cids = 0, type, j;
347 for (type = 0; type < MAX_CONN_TYPES; type++) {
348 iids->cids += p_mngr->conn_cfg[type].cid_count;
349 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
351 segs = p_mngr->conn_cfg[type].tid_seg;
352 /* for each segment there is at most one
353 * protocol for which count is not 0.
355 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
356 iids->tids += segs[j].count;
358 /* The last array elelment is for the VFs. As for PF
359 * segments there can be only one protocol for
360 * which this value is not 0.
362 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
365 iids->vf_cids += vf_cids * p_mngr->vf_count;
366 iids->tids += vf_tids * p_mngr->vf_count;
368 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
369 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
370 iids->cids, iids->vf_cids, iids->tids, vf_tids);
373 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
376 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
379 /* Find the protocol with tid count > 0 for this segment.
380 * Note: there can only be one and this is already validated.
382 for (i = 0; i < MAX_CONN_TYPES; i++) {
383 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
384 return &p_cfg->conn_cfg[i].tid_seg[seg];
389 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
391 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
393 p_mgr->srq_count = num_srqs;
396 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
398 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
400 return p_mgr->srq_count;
403 /* set the iids (cid/tid) count per protocol */
404 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
405 enum protocol_type type,
406 u32 cid_count, u32 vf_cid_cnt)
408 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
409 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
411 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
412 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
415 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
416 enum protocol_type type, u32 *vf_cid)
419 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
421 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
424 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
425 enum protocol_type type)
427 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
430 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
431 enum protocol_type type)
436 for (i = 0; i < TASK_SEGMENTS; i++)
437 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
442 static OSAL_INLINE void
443 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
444 enum protocol_type proto,
445 u8 seg, u8 seg_type, u32 count, bool has_fl)
447 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
448 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
450 p_seg->count = count;
451 p_seg->has_fl_mem = has_fl;
452 p_seg->type = seg_type;
455 /* the *p_line parameter must be either 0 for the first invocation or the
456 * value returned in the previous invocation.
458 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
459 struct ecore_ilt_cli_blk *p_blk,
461 u32 total_size, u32 elem_size)
463 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
465 /* verify that it's called once for each block */
466 if (p_blk->total_size)
469 p_blk->total_size = total_size;
470 p_blk->real_size_in_page = 0;
472 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
473 p_blk->start_line = start_line;
476 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
477 struct ecore_ilt_client_cfg *p_cli,
478 struct ecore_ilt_cli_blk *p_blk,
479 u32 *p_line, enum ilt_clients client_id)
481 if (!p_blk->total_size)
485 p_cli->first.val = *p_line;
487 p_cli->active = true;
488 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
489 p_cli->last.val = *p_line - 1;
491 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
492 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
493 " [Real %08x] Start line %d\n",
494 client_id, p_cli->first.val, p_cli->last.val,
495 p_blk->total_size, p_blk->real_size_in_page,
499 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
500 enum ilt_clients ilt_client)
502 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
503 struct ecore_ilt_client_cfg *p_cli;
504 u32 lines_to_skip = 0;
507 /* TBD MK: ILT code should be simplified once PROTO enum is changed */
509 if (ilt_client == ILT_CLI_CDUC) {
510 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
512 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
513 (u32)CONN_CXT_SIZE(p_hwfn);
515 lines_to_skip = cid_count / cxts_per_p;
518 return lines_to_skip;
521 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
523 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
524 u32 curr_line, total, i, task_size, line;
525 struct ecore_ilt_client_cfg *p_cli;
526 struct ecore_ilt_cli_blk *p_blk;
527 struct ecore_cdu_iids cdu_iids;
528 struct ecore_src_iids src_iids;
529 struct ecore_qm_iids qm_iids;
530 struct ecore_tm_iids tm_iids;
531 struct ecore_tid_seg *p_seg;
533 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
534 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
535 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
536 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
538 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
540 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
541 "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
542 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
545 p_cli = &p_mngr->clients[ILT_CLI_CDUC];
547 curr_line = p_mngr->pf_start_line;
550 p_cli->pf_total_lines = 0;
552 /* get the counters for the CDUC,CDUC and QM clients */
553 ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
555 p_blk = &p_cli->pf_blks[CDUC_BLK];
557 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
559 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
560 total, CONN_CXT_SIZE(p_hwfn));
562 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
563 p_cli->pf_total_lines = curr_line - p_blk->start_line;
565 p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
569 p_blk = &p_cli->vf_blks[CDUC_BLK];
570 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
572 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
573 total, CONN_CXT_SIZE(p_hwfn));
575 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
576 p_cli->vf_total_lines = curr_line - p_blk->start_line;
578 for (i = 1; i < p_mngr->vf_count; i++)
579 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
583 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
584 p_cli->first.val = curr_line;
586 /* first the 'working' task memory */
587 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
588 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
589 if (!p_seg || p_seg->count == 0)
592 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
593 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
594 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
595 p_mngr->task_type_size[p_seg->type]);
597 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
601 /* next the 'init' task memory (forced load memory) */
602 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
603 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
604 if (!p_seg || p_seg->count == 0)
607 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
609 if (!p_seg->has_fl_mem) {
610 /* The segment is active (total size pf 'working'
611 * memory is > 0) but has no FL (forced-load, Init)
614 * 1. The total-size in the corrsponding FL block of
615 * the ILT client is set to 0 - No ILT line are
616 * provisioned and no ILT memory allocated.
618 * 2. The start-line of said block is set to the
619 * start line of the matching working memory
620 * block in the ILT client. This is later used to
621 * configure the CDU segment offset registers and
622 * results in an FL command for TIDs of this
623 * segment behaves as regular load commands
624 * (loading TIDs from the working memory).
626 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
628 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
631 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
633 ecore_ilt_cli_blk_fill(p_cli, p_blk,
635 p_mngr->task_type_size[p_seg->type]);
637 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
640 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
643 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
644 if (p_seg && p_seg->count) {
645 /* Stricly speaking we need to iterate over all VF
646 * task segment types, but a VF has only 1 segment
649 /* 'working' memory */
650 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
652 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
653 ecore_ilt_cli_blk_fill(p_cli, p_blk,
655 p_mngr->task_type_size[p_seg->type]);
657 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
661 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
662 if (!p_seg->has_fl_mem) {
663 /* see comment above */
664 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
665 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
667 task_size = p_mngr->task_type_size[p_seg->type];
668 ecore_ilt_cli_blk_fill(p_cli, p_blk,
669 curr_line, total, task_size);
670 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
673 p_cli->vf_total_lines = curr_line -
674 p_cli->vf_blks[0].start_line;
676 /* Now for the rest of the VFs */
677 for (i = 1; i < p_mngr->vf_count; i++) {
678 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
679 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
682 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
683 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
689 p_cli = &p_mngr->clients[ILT_CLI_QM];
690 p_blk = &p_cli->pf_blks[0];
692 ecore_cxt_qm_iids(p_hwfn, &qm_iids);
693 total = ecore_qm_pf_mem_size(qm_iids.cids,
694 qm_iids.vf_cids, qm_iids.tids,
695 p_hwfn->qm_info.num_pqs,
696 p_hwfn->qm_info.num_vf_pqs);
698 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
699 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
700 " num_vf_pqs=%d, memory_size=%d)\n",
701 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
702 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
704 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
707 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
708 p_cli->pf_total_lines = curr_line - p_blk->start_line;
711 p_cli = &p_mngr->clients[ILT_CLI_SRC];
712 ecore_cxt_src_iids(p_mngr, &src_iids);
714 /* Both the PF and VFs searcher connections are stored in the per PF
715 * database. Thus sum the PF searcher cids and all the VFs searcher
718 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
720 u32 local_max = OSAL_MAX_T(u32, total,
723 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
725 p_blk = &p_cli->pf_blks[0];
726 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
727 total * sizeof(struct src_ent),
728 sizeof(struct src_ent));
730 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
732 p_cli->pf_total_lines = curr_line - p_blk->start_line;
736 p_cli = &p_mngr->clients[ILT_CLI_TM];
737 ecore_cxt_tm_iids(p_mngr, &tm_iids);
738 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
740 p_blk = &p_cli->pf_blks[0];
741 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
742 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
744 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
746 p_cli->pf_total_lines = curr_line - p_blk->start_line;
750 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
752 p_blk = &p_cli->vf_blks[0];
753 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
754 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
756 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
759 p_cli->vf_total_lines = curr_line - p_blk->start_line;
760 for (i = 1; i < p_mngr->vf_count; i++) {
761 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
766 /* TSDM (SRQ CONTEXT) */
767 total = ecore_cxt_get_srq_count(p_hwfn);
770 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
771 p_blk = &p_cli->pf_blks[SRQ_BLK];
772 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
773 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
775 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
777 p_cli->pf_total_lines = curr_line - p_blk->start_line;
780 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
781 RESC_NUM(p_hwfn, ECORE_ILT)) {
782 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
783 curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
787 return ECORE_SUCCESS;
790 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
792 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
798 for (i = 0; i < p_mngr->t2_num_pages; i++)
799 if (p_mngr->t2[i].p_virt)
800 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
801 p_mngr->t2[i].p_virt,
802 p_mngr->t2[i].p_phys,
805 OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
808 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
810 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
811 u32 conn_num, total_size, ent_per_page, psz, i;
812 struct ecore_ilt_client_cfg *p_src;
813 struct ecore_src_iids src_iids;
814 struct ecore_dma_mem *p_t2;
815 enum _ecore_status_t rc;
817 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
819 /* if the SRC ILT client is inactive - there are no connection
820 * requiring the searcer, leave.
822 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
824 return ECORE_SUCCESS;
826 ecore_cxt_src_iids(p_mngr, &src_iids);
827 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
828 total_size = conn_num * sizeof(struct src_ent);
830 /* use the same page size as the SRC ILT client */
831 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
832 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
835 p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
836 p_mngr->t2_num_pages *
837 sizeof(struct ecore_dma_mem));
839 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
844 /* allocate t2 pages */
845 for (i = 0; i < p_mngr->t2_num_pages; i++) {
846 u32 size = OSAL_MIN_T(u32, total_size, psz);
847 void **p_virt = &p_mngr->t2[i].p_virt;
849 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
850 &p_mngr->t2[i].p_phys, size);
851 if (!p_mngr->t2[i].p_virt) {
855 OSAL_MEM_ZERO(*p_virt, size);
856 p_mngr->t2[i].size = size;
860 /* Set the t2 pointers */
862 /* entries per page - must be a power of two */
863 ent_per_page = psz / sizeof(struct src_ent);
865 p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
867 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
868 p_mngr->last_free = (u64)p_t2->p_phys +
869 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
871 for (i = 0; i < p_mngr->t2_num_pages; i++) {
872 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
873 struct src_ent *entries = p_mngr->t2[i].p_virt;
874 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
877 for (j = 0; j < ent_num - 1; j++) {
878 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
879 entries[j].next = OSAL_CPU_TO_BE64(val);
882 if (i < p_mngr->t2_num_pages - 1)
883 val = (u64)p_mngr->t2[i + 1].p_phys;
886 entries[j].next = OSAL_CPU_TO_BE64(val);
891 return ECORE_SUCCESS;
894 ecore_cxt_src_t2_free(p_hwfn);
898 #define for_each_ilt_valid_client(pos, clients) \
899 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
900 if (!clients[pos].active) { \
905 /* Total number of ILT lines used by this PF */
906 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
911 for_each_ilt_valid_client(i, ilt_clients)
912 size += (ilt_clients[i].last.val -
913 ilt_clients[i].first.val + 1);
918 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
920 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
921 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
924 ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
926 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
927 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
930 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
932 p_dma->p_phys, p_dma->size);
933 p_dma->p_virt = OSAL_NULL;
935 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
938 static enum _ecore_status_t
939 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
940 struct ecore_ilt_cli_blk *p_blk,
941 enum ilt_clients ilt_client, u32 start_line_offset)
943 struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
944 u32 lines, line, sz_left, lines_to_skip = 0;
946 /* Special handling for RoCE that supports dynamic allocation */
947 if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
948 return ECORE_SUCCESS;
950 lines_to_skip = p_blk->dynamic_line_cnt;
952 if (!p_blk->total_size)
953 return ECORE_SUCCESS;
955 sz_left = p_blk->total_size;
956 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
957 line = p_blk->start_line + start_line_offset -
958 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
960 for (; lines; lines--) {
965 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
968 #define ILT_BLOCK_ALIGN_SIZE 0x1000
969 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
971 ILT_BLOCK_ALIGN_SIZE);
974 OSAL_MEM_ZERO(p_virt, size);
976 ilt_shadow[line].p_phys = p_phys;
977 ilt_shadow[line].p_virt = p_virt;
978 ilt_shadow[line].size = size;
980 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
981 "ILT shadow: Line [%d] Physical 0x%lx"
982 " Virtual %p Size %d\n",
983 line, (unsigned long)p_phys, p_virt, size);
989 return ECORE_SUCCESS;
992 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
994 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
995 struct ecore_ilt_client_cfg *clients = p_mngr->clients;
996 struct ecore_ilt_cli_blk *p_blk;
998 enum _ecore_status_t rc;
1000 size = ecore_cxt_ilt_shadow_size(clients);
1001 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1002 size * sizeof(struct ecore_dma_mem));
1004 if (!p_mngr->ilt_shadow) {
1005 DP_NOTICE(p_hwfn, true,
1006 "Failed to allocate ilt shadow table\n");
1008 goto ilt_shadow_fail;
1011 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1012 "Allocated 0x%x bytes for ilt shadow\n",
1013 (u32)(size * sizeof(struct ecore_dma_mem)));
1015 for_each_ilt_valid_client(i, clients) {
1016 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1017 p_blk = &clients[i].pf_blks[j];
1018 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1019 if (rc != ECORE_SUCCESS)
1020 goto ilt_shadow_fail;
1022 for (k = 0; k < p_mngr->vf_count; k++) {
1023 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1024 u32 lines = clients[i].vf_total_lines * k;
1026 p_blk = &clients[i].vf_blks[j];
1027 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1029 if (rc != ECORE_SUCCESS)
1030 goto ilt_shadow_fail;
1035 return ECORE_SUCCESS;
1038 ecore_ilt_shadow_free(p_hwfn);
1042 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1044 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1047 for (type = 0; type < MAX_CONN_TYPES; type++) {
1048 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1049 p_mngr->acquired[type].max_count = 0;
1050 p_mngr->acquired[type].start_cid = 0;
1052 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1053 OSAL_FREE(p_hwfn->p_dev,
1054 p_mngr->acquired_vf[type][vf].cid_map);
1055 p_mngr->acquired_vf[type][vf].max_count = 0;
1056 p_mngr->acquired_vf[type][vf].start_cid = 0;
1061 static enum _ecore_status_t
1062 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1063 u32 cid_start, u32 cid_count,
1064 struct ecore_cid_acquired_map *p_map)
1069 return ECORE_SUCCESS;
1071 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1072 p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1073 if (p_map->cid_map == OSAL_NULL)
1076 p_map->max_count = cid_count;
1077 p_map->start_cid = cid_start;
1079 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1080 "Type %08x start: %08x count %08x\n",
1081 type, p_map->start_cid, p_map->max_count);
1083 return ECORE_SUCCESS;
1086 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1088 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1089 u32 start_cid = 0, vf_start_cid = 0;
1092 for (type = 0; type < MAX_CONN_TYPES; type++) {
1093 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1094 struct ecore_cid_acquired_map *p_map;
1096 /* Handle PF maps */
1097 p_map = &p_mngr->acquired[type];
1098 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1099 p_cfg->cid_count, p_map))
1102 /* Handle VF maps */
1103 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1104 p_map = &p_mngr->acquired_vf[type][vf];
1105 if (ecore_cid_map_alloc_single(p_hwfn, type,
1112 start_cid += p_cfg->cid_count;
1113 vf_start_cid += p_cfg->cids_per_vf;
1116 return ECORE_SUCCESS;
1119 ecore_cid_map_free(p_hwfn);
1123 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1125 struct ecore_ilt_client_cfg *clients;
1126 struct ecore_cxt_mngr *p_mngr;
1129 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1131 DP_NOTICE(p_hwfn, true,
1132 "Failed to allocate `struct ecore_cxt_mngr'\n");
1136 /* Initialize ILT client registers */
1137 clients = p_mngr->clients;
1138 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1139 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1140 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1142 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1143 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1144 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1146 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1147 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1148 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1150 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1151 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1152 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1154 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1155 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1156 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1158 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1159 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1160 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1162 /* default ILT page size for all clients is 32K */
1163 for (i = 0; i < ILT_CLI_MAX; i++)
1164 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1166 /* due to removal of ISCSI/FCoE files union type0_task_context
1167 * task_type_size will be 0. So hardcoded for now.
1169 p_mngr->task_type_size[0] = 512; /* @DPDK */
1170 p_mngr->task_type_size[1] = 128; /* @DPDK */
1172 if (p_hwfn->p_dev->p_iov_info)
1173 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1175 /* Initialize the dynamic ILT allocation mutex */
1176 #ifdef CONFIG_ECORE_LOCK_ALLOC
1177 OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1179 OSAL_MUTEX_INIT(&p_mngr->mutex);
1181 /* Set the cxt mangr pointer priori to further allocations */
1182 p_hwfn->p_cxt_mngr = p_mngr;
1184 return ECORE_SUCCESS;
1187 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1189 enum _ecore_status_t rc;
1191 /* Allocate the ILT shadow table */
1192 rc = ecore_ilt_shadow_alloc(p_hwfn);
1194 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1195 goto tables_alloc_fail;
1198 /* Allocate the T2 table */
1199 rc = ecore_cxt_src_t2_alloc(p_hwfn);
1201 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1202 goto tables_alloc_fail;
1205 /* Allocate and initialize the acquired cids bitmaps */
1206 rc = ecore_cid_map_alloc(p_hwfn);
1208 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1209 goto tables_alloc_fail;
1212 return ECORE_SUCCESS;
1215 ecore_cxt_mngr_free(p_hwfn);
1219 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1221 if (!p_hwfn->p_cxt_mngr)
1224 ecore_cid_map_free(p_hwfn);
1225 ecore_cxt_src_t2_free(p_hwfn);
1226 ecore_ilt_shadow_free(p_hwfn);
1227 #ifdef CONFIG_ECORE_LOCK_ALLOC
1228 OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1230 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1233 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1235 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1236 struct ecore_cid_acquired_map *p_map;
1237 struct ecore_conn_type_cfg *p_cfg;
1241 /* Reset acquired cids */
1242 for (type = 0; type < MAX_CONN_TYPES; type++) {
1245 p_cfg = &p_mngr->conn_cfg[type];
1246 if (p_cfg->cid_count) {
1247 p_map = &p_mngr->acquired[type];
1248 len = DIV_ROUND_UP(p_map->max_count,
1249 BITS_PER_MAP_WORD) *
1251 OSAL_MEM_ZERO(p_map->cid_map, len);
1254 if (!p_cfg->cids_per_vf)
1257 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1258 p_map = &p_mngr->acquired_vf[type][vf];
1259 len = DIV_ROUND_UP(p_map->max_count,
1260 BITS_PER_MAP_WORD) *
1262 OSAL_MEM_ZERO(p_map->cid_map, len);
1267 /* HW initialization helper (per Block, per phase) */
1270 #define CDUC_CXT_SIZE_SHIFT \
1271 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1273 #define CDUC_CXT_SIZE_MASK \
1274 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1276 #define CDUC_BLOCK_WASTE_SHIFT \
1277 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1279 #define CDUC_BLOCK_WASTE_MASK \
1280 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1282 #define CDUC_NCIB_SHIFT \
1283 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1285 #define CDUC_NCIB_MASK \
1286 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1288 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1289 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1291 #define CDUT_TYPE0_CXT_SIZE_MASK \
1292 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1293 CDUT_TYPE0_CXT_SIZE_SHIFT)
1295 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1296 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1298 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1299 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1300 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1302 #define CDUT_TYPE0_NCIB_SHIFT \
1303 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1305 #define CDUT_TYPE0_NCIB_MASK \
1306 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1307 CDUT_TYPE0_NCIB_SHIFT)
1309 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1310 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1312 #define CDUT_TYPE1_CXT_SIZE_MASK \
1313 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1314 CDUT_TYPE1_CXT_SIZE_SHIFT)
1316 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1317 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1319 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1320 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1321 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1323 #define CDUT_TYPE1_NCIB_SHIFT \
1324 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1326 #define CDUT_TYPE1_NCIB_MASK \
1327 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1328 CDUT_TYPE1_NCIB_SHIFT)
1330 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1332 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1334 /* CDUC - connection configuration */
1335 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1336 cxt_size = CONN_CXT_SIZE(p_hwfn);
1337 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1338 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1340 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1341 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1342 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1343 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1345 /* CDUT - type-0 tasks configuration */
1346 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1347 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1348 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1349 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1351 /* cxt size and block-waste are multipes of 8 */
1353 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1354 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1355 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1356 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1358 /* CDUT - type-1 tasks configuration */
1359 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1360 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1361 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1363 /* cxt size and block-waste are multipes of 8 */
1365 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1366 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1367 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1368 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1372 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1373 #define CDU_SEG_REG_TYPE_MASK 0x1
1374 #define CDU_SEG_REG_OFFSET_SHIFT 0
1375 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1377 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1379 struct ecore_ilt_client_cfg *p_cli;
1380 struct ecore_tid_seg *p_seg;
1381 u32 cdu_seg_params, offset;
1384 static const u32 rt_type_offset_arr[] = {
1385 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1386 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1387 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1388 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1391 static const u32 rt_type_offset_fl_arr[] = {
1392 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1393 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1394 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1395 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1398 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1400 /* There are initializations only for CDUT during pf Phase */
1401 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1403 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1407 /* Note: start_line is already adjusted for the CDU
1408 * segment register granularity, so we just need to
1409 * divide. Adjustment is implicit as we assume ILT
1410 * Page size is larger than 32K!
1412 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1413 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1414 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1417 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1418 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1419 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1421 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1422 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1423 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1426 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1427 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1428 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1432 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1434 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1435 struct ecore_qm_iids iids;
1437 OSAL_MEM_ZERO(&iids, sizeof(iids));
1438 ecore_cxt_qm_iids(p_hwfn, &iids);
1440 ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->port_id,
1441 p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1442 iids.cids, iids.vf_cids, iids.tids,
1444 qm_info->num_pqs - qm_info->num_vf_pqs,
1445 qm_info->num_vf_pqs,
1446 qm_info->start_vport,
1447 qm_info->num_vports, qm_info->pf_wfq,
1448 qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1449 p_hwfn->qm_info.qm_vport_params);
1453 static void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1455 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1456 ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1460 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1462 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1463 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1465 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1466 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1468 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1469 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1471 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1472 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1474 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1475 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1477 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1478 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1480 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1481 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1483 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1484 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1486 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1487 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1489 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1490 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1492 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1493 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1495 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1496 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1498 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1499 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1501 /* Connection types 6 & 7 are not in use, yet they must be configured
1502 * as the highest possible connection. Not configuring them means the
1503 * defaults will be used, and with a large number of cids a bug may
1504 * occur, if the defaults will be smaller than dq_pf_max_cid /
1507 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1508 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1510 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1511 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1514 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1516 struct ecore_ilt_client_cfg *ilt_clients;
1519 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1520 for_each_ilt_valid_client(i, ilt_clients) {
1521 STORE_RT_REG(p_hwfn,
1522 ilt_clients[i].first.reg,
1523 ilt_clients[i].first.val);
1524 STORE_RT_REG(p_hwfn,
1525 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1526 STORE_RT_REG(p_hwfn,
1527 ilt_clients[i].p_size.reg,
1528 ilt_clients[i].p_size.val);
1532 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1534 struct ecore_ilt_client_cfg *p_cli;
1537 /* For simplicty we set the 'block' to be an ILT page */
1538 if (p_hwfn->p_dev->p_iov_info) {
1539 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1541 STORE_RT_REG(p_hwfn,
1542 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1543 p_iov->first_vf_in_pf);
1544 STORE_RT_REG(p_hwfn,
1545 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1546 p_iov->first_vf_in_pf + p_iov->total_vfs);
1549 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1550 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1551 if (p_cli->active) {
1552 STORE_RT_REG(p_hwfn,
1553 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1555 STORE_RT_REG(p_hwfn,
1556 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1557 p_cli->pf_total_lines);
1558 STORE_RT_REG(p_hwfn,
1559 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1560 p_cli->vf_total_lines);
1563 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1564 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1565 if (p_cli->active) {
1566 STORE_RT_REG(p_hwfn,
1567 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1569 STORE_RT_REG(p_hwfn,
1570 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1571 p_cli->pf_total_lines);
1572 STORE_RT_REG(p_hwfn,
1573 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1574 p_cli->vf_total_lines);
1577 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1578 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1579 if (p_cli->active) {
1580 STORE_RT_REG(p_hwfn,
1581 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1582 STORE_RT_REG(p_hwfn,
1583 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1584 p_cli->pf_total_lines);
1585 STORE_RT_REG(p_hwfn,
1586 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1587 p_cli->vf_total_lines);
1591 /* ILT (PSWRQ2) PF */
1592 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1594 struct ecore_ilt_client_cfg *clients;
1595 struct ecore_cxt_mngr *p_mngr;
1596 struct ecore_dma_mem *p_shdw;
1597 u32 line, rt_offst, i;
1599 ecore_ilt_bounds_init(p_hwfn);
1600 ecore_ilt_vf_bounds_init(p_hwfn);
1602 p_mngr = p_hwfn->p_cxt_mngr;
1603 p_shdw = p_mngr->ilt_shadow;
1604 clients = p_hwfn->p_cxt_mngr->clients;
1606 for_each_ilt_valid_client(i, clients) {
1607 /* Client's 1st val and RT array are absolute, ILT shadows'
1608 * lines are relative.
1610 line = clients[i].first.val - p_mngr->pf_start_line;
1611 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1612 clients[i].first.val * ILT_ENTRY_IN_REGS;
1614 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1615 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1616 u64 ilt_hw_entry = 0;
1618 /** p_virt could be OSAL_NULL incase of dynamic
1621 if (p_shdw[line].p_virt != OSAL_NULL) {
1622 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1623 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1624 (p_shdw[line].p_phys >> 12));
1626 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1627 "Setting RT[0x%08x] from"
1628 " ILT[0x%08x] [Client is %d] to"
1629 " Physical addr: 0x%lx\n",
1631 (unsigned long)(p_shdw[line].
1635 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1640 /* SRC (Searcher) PF */
1641 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1643 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1644 u32 rounded_conn_num, conn_num, conn_max;
1645 struct ecore_src_iids src_iids;
1647 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1648 ecore_cxt_src_iids(p_mngr, &src_iids);
1649 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1653 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1654 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1656 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1657 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1658 OSAL_LOG2(rounded_conn_num));
1660 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1661 p_hwfn->p_cxt_mngr->first_free);
1662 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1663 p_hwfn->p_cxt_mngr->last_free);
1664 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1665 "Configured SEARCHER for 0x%08x connections\n",
1670 #define TM_CFG_NUM_IDS_SHIFT 0
1671 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1672 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1673 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1674 #define TM_CFG_PARENT_PF_SHIFT 25
1675 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1677 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1678 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1680 #define TM_CFG_TID_OFFSET_SHIFT 30
1681 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1682 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1683 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1685 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1687 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1688 u32 active_seg_mask = 0, tm_offset, rt_reg;
1689 struct ecore_tm_iids tm_iids;
1693 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1694 ecore_cxt_tm_iids(p_mngr, &tm_iids);
1696 /* @@@TBD No pre-scan for now */
1698 /* Note: We assume consecutive VFs for a PF */
1699 for (i = 0; i < p_mngr->vf_count; i++) {
1701 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1702 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1703 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1704 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1706 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1707 (sizeof(cfg_word) / sizeof(u32)) *
1708 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1709 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1713 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1714 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1715 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1716 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1718 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1719 (sizeof(cfg_word) / sizeof(u32)) *
1720 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1721 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1724 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1725 tm_iids.pf_cids ? 0x1 : 0x0);
1727 /* @@@TBD how to enable the scan for the VFs */
1729 tm_offset = tm_iids.per_vf_cids;
1731 /* Note: We assume consecutive VFs for a PF */
1732 for (i = 0; i < p_mngr->vf_count; i++) {
1734 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1735 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1736 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1737 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1738 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1740 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1741 (sizeof(cfg_word) / sizeof(u32)) *
1742 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1744 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1747 tm_offset = tm_iids.pf_cids;
1748 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1750 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1751 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1752 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1753 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1754 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1756 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1757 (sizeof(cfg_word) / sizeof(u32)) *
1758 (NUM_OF_VFS(p_hwfn->p_dev) +
1759 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1761 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1762 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1764 tm_offset += tm_iids.pf_tids[i];
1767 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1769 /* @@@TBD how to enable the scan for the VFs */
1772 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1774 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1775 struct ecore_conn_type_cfg *p_fcoe;
1776 struct ecore_tid_seg *p_tid;
1778 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1780 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1781 if (!p_fcoe->cid_count)
1784 p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1785 STORE_RT_REG_AGG(p_hwfn,
1786 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1790 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1792 /* CDU configuration */
1793 ecore_cdu_init_common(p_hwfn);
1796 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1798 ecore_qm_init_pf(p_hwfn, p_ptt);
1799 ecore_cm_init_pf(p_hwfn);
1800 ecore_dq_init_pf(p_hwfn);
1801 ecore_cdu_init_pf(p_hwfn);
1802 ecore_ilt_init_pf(p_hwfn);
1803 ecore_src_init_pf(p_hwfn);
1804 ecore_tm_init_pf(p_hwfn);
1805 ecore_prs_init_pf(p_hwfn);
1808 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1809 enum protocol_type type,
1810 u32 *p_cid, u8 vfid)
1812 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1813 struct ecore_cid_acquired_map *p_map;
1816 if (type >= MAX_CONN_TYPES) {
1817 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1821 if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) {
1822 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1826 /* Determine the right map to take this CID from */
1827 if (vfid == ECORE_CXT_PF_CID)
1828 p_map = &p_mngr->acquired[type];
1830 p_map = &p_mngr->acquired_vf[type][vfid];
1832 if (p_map->cid_map == OSAL_NULL) {
1833 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1837 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1840 if (rel_cid >= p_map->max_count) {
1841 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1843 return ECORE_NORESOURCES;
1846 OSAL_SET_BIT(rel_cid, p_map->cid_map);
1848 *p_cid = rel_cid + p_map->start_cid;
1850 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1851 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1852 *p_cid, rel_cid, vfid, type);
1854 return ECORE_SUCCESS;
1857 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1858 enum protocol_type type,
1861 return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
1864 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1866 enum protocol_type *p_type,
1867 struct ecore_cid_acquired_map **pp_map)
1869 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1872 /* Iterate over protocols and find matching cid range */
1873 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1874 if (vfid == ECORE_CXT_PF_CID)
1875 *pp_map = &p_mngr->acquired[*p_type];
1877 *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1879 if (!((*pp_map)->cid_map))
1881 if (cid >= (*pp_map)->start_cid &&
1882 cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
1886 if (*p_type == MAX_CONN_TYPES) {
1887 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
1891 rel_cid = cid - (*pp_map)->start_cid;
1892 if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
1893 DP_NOTICE(p_hwfn, true,
1894 "CID %d [vifd %02x] not acquired", cid, vfid);
1900 *p_type = MAX_CONN_TYPES;
1901 *pp_map = OSAL_NULL;
1905 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
1907 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1908 enum protocol_type type;
1912 if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) {
1913 DP_NOTICE(p_hwfn, true,
1914 "Trying to return incorrect CID belonging to VF %02x\n",
1919 /* Test acquired and find matching per-protocol map */
1920 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
1926 rel_cid = cid - p_map->start_cid;
1927 OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
1929 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1930 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
1931 cid, rel_cid, vfid, type);
1934 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1936 _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
1939 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1940 struct ecore_cxt_info *p_info)
1942 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1943 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1944 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1945 enum protocol_type type;
1948 /* Test acquired and find matching per-protocol map */
1949 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
1956 /* set the protocl type */
1957 p_info->type = type;
1959 /* compute context virtual pointer */
1960 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1962 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1963 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1964 line = p_info->iid / cxts_per_p;
1966 /* Make sure context is allocated (dynamic allocation) */
1967 if (!p_mngr->ilt_shadow[line].p_virt)
1970 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1971 p_info->iid % cxts_per_p * conn_cxt_size;
1973 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1974 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1975 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1977 return ECORE_SUCCESS;
1980 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1982 /* Set the number of required CORE connections */
1983 u32 core_cids = 1; /* SPQ */
1985 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1987 switch (p_hwfn->hw_info.personality) {
1990 struct ecore_eth_pf_params *p_params =
1991 &p_hwfn->pf_params.eth_pf_params;
1993 if (!p_params->num_vf_cons)
1994 p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT;
1995 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1997 p_params->num_vf_cons);
1998 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters;
2005 return ECORE_SUCCESS;
2008 /* This function is very RoCE oriented, if another protocol in the future
2009 * will want this feature we'll need to modify the function to be more generic
2011 enum _ecore_status_t
2012 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2013 enum ecore_cxt_elem_type elem_type,
2016 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2017 struct ecore_ilt_client_cfg *p_cli;
2018 struct ecore_ilt_cli_blk *p_blk;
2019 struct ecore_ptt *p_ptt;
2023 enum _ecore_status_t rc = ECORE_SUCCESS;
2025 switch (elem_type) {
2026 case ECORE_ELEM_CXT:
2027 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2028 elem_size = CONN_CXT_SIZE(p_hwfn);
2029 p_blk = &p_cli->pf_blks[CDUC_BLK];
2031 case ECORE_ELEM_SRQ:
2032 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2033 elem_size = SRQ_CXT_SIZE;
2034 p_blk = &p_cli->pf_blks[SRQ_BLK];
2036 case ECORE_ELEM_TASK:
2037 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2038 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2039 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2042 DP_NOTICE(p_hwfn, false,
2043 "ECORE_INVALID elem type = %d", elem_type);
2047 /* Calculate line in ilt */
2048 hw_p_size = p_cli->p_size.val;
2049 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2050 line = p_blk->start_line + (iid / elems_per_p);
2051 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2053 /* If line is already allocated, do nothing, otherwise allocate it and
2054 * write it to the PSWRQ2 registers.
2055 * This section can be run in parallel from different contexts and thus
2056 * a mutex protection is needed.
2059 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2061 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2064 p_ptt = ecore_ptt_acquire(p_hwfn);
2066 DP_NOTICE(p_hwfn, false,
2067 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2072 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2074 p_blk->real_size_in_page);
2079 OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2081 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2082 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2083 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2084 p_blk->real_size_in_page;
2086 /* compute absolute offset */
2087 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2088 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2091 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2092 SET_FIELD(ilt_hw_entry,
2094 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2096 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2098 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2099 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2102 if (elem_type == ECORE_ELEM_CXT) {
2103 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2106 /* Update the relevant register in the parser */
2107 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2108 last_cid_allocated - 1);
2110 if (!p_hwfn->b_rdma_enabled_in_prs) {
2111 /* Enable RoCE search */
2112 ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2113 p_hwfn->b_rdma_enabled_in_prs = true;
2118 ecore_ptt_release(p_hwfn, p_ptt);
2120 OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2125 /* This function is very RoCE oriented, if another protocol in the future
2126 * will want this feature we'll need to modify the function to be more generic
2128 static enum _ecore_status_t
2129 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2130 enum ecore_cxt_elem_type elem_type,
2131 u32 start_iid, u32 count)
2133 u32 start_line, end_line, shadow_start_line, shadow_end_line;
2134 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2135 struct ecore_ilt_client_cfg *p_cli;
2136 struct ecore_ilt_cli_blk *p_blk;
2137 u32 end_iid = start_iid + count;
2138 struct ecore_ptt *p_ptt;
2139 u64 ilt_hw_entry = 0;
2142 switch (elem_type) {
2143 case ECORE_ELEM_CXT:
2144 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2145 elem_size = CONN_CXT_SIZE(p_hwfn);
2146 p_blk = &p_cli->pf_blks[CDUC_BLK];
2148 case ECORE_ELEM_SRQ:
2149 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2150 elem_size = SRQ_CXT_SIZE;
2151 p_blk = &p_cli->pf_blks[SRQ_BLK];
2153 case ECORE_ELEM_TASK:
2154 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2155 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2156 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2159 DP_NOTICE(p_hwfn, false,
2160 "ECORE_INVALID elem type = %d", elem_type);
2164 /* Calculate line in ilt */
2165 hw_p_size = p_cli->p_size.val;
2166 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2167 start_line = p_blk->start_line + (start_iid / elems_per_p);
2168 end_line = p_blk->start_line + (end_iid / elems_per_p);
2169 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2172 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2173 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2175 p_ptt = ecore_ptt_acquire(p_hwfn);
2177 DP_NOTICE(p_hwfn, false,
2178 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2179 return ECORE_TIMEOUT;
2182 for (i = shadow_start_line; i < shadow_end_line; i++) {
2183 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2186 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2187 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2188 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2189 p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2191 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2192 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2193 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2195 /* compute absolute offset */
2196 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2197 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2200 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2203 ecore_dmae_host2grc(p_hwfn, p_ptt,
2204 (u64)(osal_uintptr_t)&ilt_hw_entry,
2206 sizeof(ilt_hw_entry) / sizeof(u32),
2210 ecore_ptt_release(p_hwfn, p_ptt);
2212 return ECORE_SUCCESS;
2215 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2216 enum protocol_type proto)
2218 enum _ecore_status_t rc;
2221 /* Free Connection CXT */
2222 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2223 ecore_cxt_get_proto_cid_start(p_hwfn,
2225 ecore_cxt_get_proto_cid_count(p_hwfn,
2233 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2234 ecore_cxt_get_proto_tid_count(p_hwfn,
2240 rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2241 ecore_cxt_get_srq_count(p_hwfn));