2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
35 * registers involved are not split and thus configuration is a race where
36 * some of the PFs configuration might be lost.
37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
39 * there's more than a single compiled ecore component in system].
41 static osal_spinlock_t qm_lock;
42 static bool qm_lock_init;
45 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
46 * load the driver. The number was
51 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
54 BAR_ID_0, /* used for GRC */
55 BAR_ID_1 /* Used for doorbells */
58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
60 u32 bar_reg = (bar_id == BAR_ID_0 ?
61 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
64 if (IS_VF(p_hwfn->p_dev)) {
65 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
66 * read from actual register, but we're currently not using
67 * it for actual doorbelling.
72 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
74 return 1 << (val + 15);
76 /* The above registers were updated in the past only in CMT mode. Since
77 * they were found to be useful MFW started updating them from 8.7.7.0.
78 * In older MFW versions they are set to 0 which means disabled.
80 if (p_hwfn->p_dev->num_hwfns > 1) {
81 DP_NOTICE(p_hwfn, false,
82 "BAR size not configured. Assuming BAR size of 256kB"
83 " for GRC and 512kB for DB\n");
84 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
86 DP_NOTICE(p_hwfn, false,
87 "BAR size not configured. Assuming BAR size of 512kB"
88 " for GRC and 512kB for DB\n");
95 void ecore_init_dp(struct ecore_dev *p_dev,
96 u32 dp_module, u8 dp_level, void *dp_ctx)
100 p_dev->dp_level = dp_level;
101 p_dev->dp_module = dp_module;
102 p_dev->dp_ctx = dp_ctx;
103 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
104 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
106 p_hwfn->dp_level = dp_level;
107 p_hwfn->dp_module = dp_module;
108 p_hwfn->dp_ctx = dp_ctx;
112 void ecore_init_struct(struct ecore_dev *p_dev)
116 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
117 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
119 p_hwfn->p_dev = p_dev;
121 p_hwfn->b_active = false;
123 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
124 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
127 /* hwfn 0 is always active */
128 p_dev->hwfns[0].b_active = true;
130 /* set the default cache alignment to 128 (may be overridden later) */
131 p_dev->cache_shift = 7;
134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
136 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
138 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
139 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
141 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
144 void ecore_resc_free(struct ecore_dev *p_dev)
151 OSAL_FREE(p_dev, p_dev->fw_data);
153 OSAL_FREE(p_dev, p_dev->reset_stats);
155 for_each_hwfn(p_dev, i) {
156 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
158 ecore_cxt_mngr_free(p_hwfn);
159 ecore_qm_info_free(p_hwfn);
160 ecore_spq_free(p_hwfn);
161 ecore_eq_free(p_hwfn);
162 ecore_consq_free(p_hwfn);
163 ecore_int_free(p_hwfn);
164 ecore_iov_free(p_hwfn);
165 ecore_dmae_info_free(p_hwfn);
166 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
167 /* @@@TBD Flush work-queue ? */
171 /******************** QM initialization *******************/
173 /* bitmaps for indicating active traffic classes.
174 * Special case for Arrowhead 4 port
176 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
177 #define ACTIVE_TCS_BMAP 0x9f
178 /* 0..3 actually used, OOO and high priority stuff all use 3 */
179 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
181 /* determines the physical queue flags for a given PF. */
182 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
190 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
191 flags |= PQ_FLAGS_VFS;
194 switch (p_hwfn->hw_info.personality) {
196 flags |= PQ_FLAGS_MCOS;
199 flags |= PQ_FLAGS_OFLD;
201 case ECORE_PCI_ISCSI:
202 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
204 case ECORE_PCI_ETH_ROCE:
205 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
207 case ECORE_PCI_ETH_IWARP:
208 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
212 DP_ERR(p_hwfn, "unknown personality %d\n",
213 p_hwfn->hw_info.personality);
219 /* Getters for resource amounts necessary for qm initialization */
220 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
222 return p_hwfn->hw_info.num_hw_tc;
225 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
227 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
228 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
231 #define NUM_DEFAULT_RLS 1
233 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
235 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
238 /* num RLs can't exceed resource amount of rls or vports or the
241 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
242 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
244 /* make sure after we reserve the default and VF rls we'll have
247 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
248 DP_NOTICE(p_hwfn, false,
249 "no rate limiters left for PF rate limiting"
250 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
254 /* subtract rls necessary for VFs and one default one for the PF */
255 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
260 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
262 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
264 /* all pqs share the same vport (hence the 1 below), except for vfs
267 return (!!(PQ_FLAGS_RLS & pq_flags)) *
268 ecore_init_qm_get_num_pf_rls(p_hwfn) +
269 (!!(PQ_FLAGS_VFS & pq_flags)) *
270 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
273 /* calc amount of PQs according to the requested flags */
274 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
276 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
278 return (!!(PQ_FLAGS_RLS & pq_flags)) *
279 ecore_init_qm_get_num_pf_rls(p_hwfn) +
280 (!!(PQ_FLAGS_MCOS & pq_flags)) *
281 ecore_init_qm_get_num_tcs(p_hwfn) +
282 (!!(PQ_FLAGS_LB & pq_flags)) +
283 (!!(PQ_FLAGS_OOO & pq_flags)) +
284 (!!(PQ_FLAGS_ACK & pq_flags)) +
285 (!!(PQ_FLAGS_OFLD & pq_flags)) +
286 (!!(PQ_FLAGS_VFS & pq_flags)) *
287 ecore_init_qm_get_num_vfs(p_hwfn);
290 /* initialize the top level QM params */
291 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
293 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
296 /* pq and vport bases for this PF */
297 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
298 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
300 /* rate limiting and weighted fair queueing are always enabled */
301 qm_info->vport_rl_en = 1;
302 qm_info->vport_wfq_en = 1;
304 /* TC config is different for AH 4 port */
305 four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
307 /* in AH 4 port we have fewer TCs per port */
308 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
311 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
314 if (!qm_info->ooo_tc)
315 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
319 /* initialize qm vport params */
320 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
322 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
325 /* all vports participate in weighted fair queueing */
326 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
327 qm_info->qm_vport_params[i].vport_wfq = 1;
330 /* initialize qm port params */
331 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
333 /* Initialize qm port parameters */
334 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
336 /* indicate how ooo and high pri traffic is dealt with */
337 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
338 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
340 for (i = 0; i < num_ports; i++) {
341 struct init_qm_port_params *p_qm_port =
342 &p_hwfn->qm_info.qm_port_params[i];
344 p_qm_port->active = 1;
345 p_qm_port->active_phys_tcs = active_phys_tcs;
346 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
347 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
351 /* Reset the params which must be reset for qm init. QM init may be called as
352 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
353 * params may be affected by the init but would simply recalculate to the same
354 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
355 * affected as these amounts stay the same.
357 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
359 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
361 qm_info->num_pqs = 0;
362 qm_info->num_vports = 0;
363 qm_info->num_pf_rls = 0;
364 qm_info->num_vf_pqs = 0;
365 qm_info->first_vf_pq = 0;
366 qm_info->first_mcos_pq = 0;
367 qm_info->first_rl_pq = 0;
370 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
372 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
374 qm_info->num_vports++;
376 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
378 "vport overflow! qm_info->num_vports %d,"
379 " qm_init_get_num_vports() %d\n",
381 ecore_init_qm_get_num_vports(p_hwfn));
384 /* initialize a single pq and manage qm_info resources accounting.
385 * The pq_init_flags param determines whether the PQ is rate limited
387 * and whether a new vport is allocated to the pq or not (i.e. vport will be
391 /* flags for pq init */
392 #define PQ_INIT_SHARE_VPORT (1 << 0)
393 #define PQ_INIT_PF_RL (1 << 1)
394 #define PQ_INIT_VF_RL (1 << 2)
396 /* defines for pq init */
397 #define PQ_INIT_DEFAULT_WRR_GROUP 1
398 #define PQ_INIT_DEFAULT_TC 0
399 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
401 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
402 struct ecore_qm_info *qm_info,
403 u8 tc, u32 pq_init_flags)
405 u16 pq_idx = qm_info->num_pqs, max_pq =
406 ecore_init_qm_get_num_pqs(p_hwfn);
410 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
413 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
415 qm_info->qm_pq_params[pq_idx].tc_id = tc;
416 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
417 qm_info->qm_pq_params[pq_idx].rl_valid =
418 (pq_init_flags & PQ_INIT_PF_RL ||
419 pq_init_flags & PQ_INIT_VF_RL);
421 /* qm params accounting */
423 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
424 qm_info->num_vports++;
426 if (pq_init_flags & PQ_INIT_PF_RL)
427 qm_info->num_pf_rls++;
429 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
431 "vport overflow! qm_info->num_vports %d,"
432 " qm_init_get_num_vports() %d\n",
434 ecore_init_qm_get_num_vports(p_hwfn));
436 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
437 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
438 " qm_init_get_num_pf_rls() %d\n",
440 ecore_init_qm_get_num_pf_rls(p_hwfn));
443 /* get pq index according to PQ_FLAGS */
444 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
447 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
449 /* Can't have multiple flags set here */
450 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
451 sizeof(pq_flags)) > 1)
456 return &qm_info->first_rl_pq;
458 return &qm_info->first_mcos_pq;
460 return &qm_info->pure_lb_pq;
462 return &qm_info->ooo_pq;
464 return &qm_info->pure_ack_pq;
466 return &qm_info->offload_pq;
468 return &qm_info->first_vf_pq;
474 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
478 /* save pq index in qm info */
479 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
480 u32 pq_flags, u16 pq_val)
482 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
484 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
487 /* get tx pq index, with the PQ TX base already set (ready for context init) */
488 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
490 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
492 return *base_pq_idx + CM_TX_PQ_BASE;
495 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
497 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
500 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
502 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
505 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
507 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
510 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
512 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
515 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
517 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
520 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
522 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
525 /* Functions for creating specific types of pqs */
526 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
528 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
530 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
533 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
534 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
537 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
539 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
541 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
544 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
545 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
548 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
550 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
552 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
555 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
556 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
559 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
561 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
563 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
566 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
567 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
570 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
572 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
575 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
578 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
579 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
580 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
583 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
585 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
586 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
588 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
591 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
593 qm_info->num_vf_pqs = num_vfs;
594 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
595 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
599 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
601 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
602 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
604 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
607 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
608 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
609 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
613 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
615 /* rate limited pqs, must come first (FW assumption) */
616 ecore_init_qm_rl_pqs(p_hwfn);
618 /* pqs for multi cos */
619 ecore_init_qm_mcos_pqs(p_hwfn);
621 /* pure loopback pq */
622 ecore_init_qm_lb_pq(p_hwfn);
624 /* out of order pq */
625 ecore_init_qm_ooo_pq(p_hwfn);
628 ecore_init_qm_pure_ack_pq(p_hwfn);
630 /* pq for offloaded protocol */
631 ecore_init_qm_offload_pq(p_hwfn);
633 /* done sharing vports */
634 ecore_init_qm_advance_vport(p_hwfn);
637 ecore_init_qm_vf_pqs(p_hwfn);
640 /* compare values of getters against resources amounts */
641 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
643 if (ecore_init_qm_get_num_vports(p_hwfn) >
644 RESC_NUM(p_hwfn, ECORE_VPORT)) {
645 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
649 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
650 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
654 return ECORE_SUCCESS;
658 * Function for verbose printing of the qm initialization results
660 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
662 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
663 struct init_qm_vport_params *vport;
664 struct init_qm_port_params *port;
665 struct init_qm_pq_params *pq;
668 /* top level params */
669 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
670 "qm init top level params: start_pq %d, start_vport %d,"
671 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
672 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
673 qm_info->offload_pq, qm_info->pure_ack_pq);
674 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
675 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
676 " num_vports %d, max_phys_tcs_per_port %d\n",
677 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
678 qm_info->num_vf_pqs, qm_info->num_vports,
679 qm_info->max_phys_tcs_per_port);
680 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
681 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
682 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
683 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
684 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
685 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
688 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
689 port = &qm_info->qm_port_params[i];
690 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
691 "port idx %d, active %d, active_phys_tcs %d,"
692 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
694 i, port->active, port->active_phys_tcs,
695 port->num_pbf_cmd_lines, port->num_btb_blocks,
700 for (i = 0; i < qm_info->num_vports; i++) {
701 vport = &qm_info->qm_vport_params[i];
702 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
703 "vport idx %d, vport_rl %d, wfq %d,"
704 " first_tx_pq_id [ ",
705 qm_info->start_vport + i, vport->vport_rl,
707 for (tc = 0; tc < NUM_OF_TCS; tc++)
708 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
709 vport->first_tx_pq_id[tc]);
710 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
714 for (i = 0; i < qm_info->num_pqs; i++) {
715 pq = &qm_info->qm_pq_params[i];
716 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
717 "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
719 qm_info->start_pq + i, pq->vport_id, pq->tc_id,
720 pq->wrr_group, pq->rl_valid);
724 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
726 /* reset params required for init run */
727 ecore_init_qm_reset_params(p_hwfn);
729 /* init QM top level params */
730 ecore_init_qm_params(p_hwfn);
732 /* init QM port params */
733 ecore_init_qm_port_params(p_hwfn);
735 /* init QM vport params */
736 ecore_init_qm_vport_params(p_hwfn);
738 /* init QM physical queue params */
739 ecore_init_qm_pq_params(p_hwfn);
741 /* display all that init */
742 ecore_dp_init_qm_params(p_hwfn);
745 /* This function reconfigures the QM pf on the fly.
746 * For this purpose we:
747 * 1. reconfigure the QM database
748 * 2. set new values to runtime array
749 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
750 * 4. activate init tool in QM_PF stage
751 * 5. send an sdm_qm_cmd through rbc interface to release the QM
753 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
754 struct ecore_ptt *p_ptt)
756 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
757 enum _ecore_status_t rc;
760 /* initialize ecore's qm data structure */
761 ecore_init_qm_info(p_hwfn);
763 /* stop PF's qm queues */
764 OSAL_SPIN_LOCK(&qm_lock);
765 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
766 qm_info->start_pq, qm_info->num_pqs);
767 OSAL_SPIN_UNLOCK(&qm_lock);
771 /* clear the QM_PF runtime phase leftovers from previous init */
772 ecore_init_clear_rt_data(p_hwfn);
774 /* prepare QM portion of runtime array */
775 ecore_qm_init_pf(p_hwfn);
777 /* activate init tool on runtime array */
778 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
779 p_hwfn->hw_info.hw_mode);
780 if (rc != ECORE_SUCCESS)
783 /* start PF's qm queues */
784 OSAL_SPIN_LOCK(&qm_lock);
785 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
786 qm_info->start_pq, qm_info->num_pqs);
787 OSAL_SPIN_UNLOCK(&qm_lock);
791 return ECORE_SUCCESS;
794 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
796 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
797 enum _ecore_status_t rc;
799 rc = ecore_init_qm_sanity(p_hwfn);
800 if (rc != ECORE_SUCCESS)
803 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
804 sizeof(struct init_qm_pq_params) *
805 ecore_init_qm_get_num_pqs(p_hwfn));
806 if (!qm_info->qm_pq_params)
809 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
810 sizeof(struct init_qm_vport_params) *
811 ecore_init_qm_get_num_vports(p_hwfn));
812 if (!qm_info->qm_vport_params)
815 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
816 sizeof(struct init_qm_port_params) *
817 p_hwfn->p_dev->num_ports_in_engines);
818 if (!qm_info->qm_port_params)
821 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
822 sizeof(struct ecore_wfq_data) *
823 ecore_init_qm_get_num_vports(p_hwfn));
824 if (!qm_info->wfq_data)
827 return ECORE_SUCCESS;
830 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
831 ecore_qm_info_free(p_hwfn);
834 /******************** End QM initialization ***************/
836 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
838 enum _ecore_status_t rc = ECORE_SUCCESS;
844 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
845 sizeof(*p_dev->fw_data));
849 for_each_hwfn(p_dev, i) {
850 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
851 u32 n_eqes, num_cons;
853 /* First allocate the context manager structure */
854 rc = ecore_cxt_mngr_alloc(p_hwfn);
858 /* Set the HW cid/tid numbers (in the contest manager)
859 * Must be done prior to any further computations.
861 rc = ecore_cxt_set_pf_params(p_hwfn);
865 rc = ecore_alloc_qm_data(p_hwfn);
870 ecore_init_qm_info(p_hwfn);
872 /* Compute the ILT client partition */
873 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
877 /* CID map / ILT shadow table / T2
878 * The talbes sizes are determined by the computations above
880 rc = ecore_cxt_tables_alloc(p_hwfn);
884 /* SPQ, must follow ILT because initializes SPQ context */
885 rc = ecore_spq_alloc(p_hwfn);
889 /* SP status block allocation */
890 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
893 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
897 rc = ecore_iov_alloc(p_hwfn);
902 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
903 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
904 /* Calculate the EQ size
905 * ---------------------
906 * Each ICID may generate up to one event at a time i.e.
907 * the event must be handled/cleared before a new one
908 * can be generated. We calculate the sum of events per
909 * protocol and create an EQ deep enough to handle the
911 * - Core - according to SPQ.
912 * - RoCE - per QP there are a couple of ICIDs, one
913 * responder and one requester, each can
914 * generate an EQE => n_eqes_qp = 2 * n_qp.
915 * Each CQ can generate an EQE. There are 2 CQs
916 * per QP => n_eqes_cq = 2 * n_qp.
917 * Hence the RoCE total is 4 * n_qp or
919 * - ENet - There can be up to two events per VF. One
920 * for VF-PF channel and another for VF FLR
921 * initial cleanup. The number of VFs is
922 * bounded by MAX_NUM_VFS_BB, and is much
923 * smaller than RoCE's so we avoid exact
926 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
928 ecore_cxt_get_proto_cid_count(
934 num_cons = ecore_cxt_get_proto_cid_count(
939 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
940 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
942 ecore_cxt_get_proto_cid_count(p_hwfn,
945 n_eqes += 2 * num_cons;
948 if (n_eqes > 0xFFFF) {
949 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
950 "The maximum of a u16 chain is 0x%x\n",
955 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
959 rc = ecore_consq_alloc(p_hwfn);
963 /* DMA info initialization */
964 rc = ecore_dmae_info_alloc(p_hwfn);
966 DP_NOTICE(p_hwfn, true,
967 "Failed to allocate memory for dmae_info"
972 /* DCBX initialization */
973 rc = ecore_dcbx_info_alloc(p_hwfn);
975 DP_NOTICE(p_hwfn, true,
976 "Failed to allocate memory for dcbx structure\n");
981 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
982 sizeof(*p_dev->reset_stats));
983 if (!p_dev->reset_stats) {
984 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
988 return ECORE_SUCCESS;
993 ecore_resc_free(p_dev);
997 void ecore_resc_setup(struct ecore_dev *p_dev)
1004 for_each_hwfn(p_dev, i) {
1005 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1007 ecore_cxt_mngr_setup(p_hwfn);
1008 ecore_spq_setup(p_hwfn);
1009 ecore_eq_setup(p_hwfn);
1010 ecore_consq_setup(p_hwfn);
1012 /* Read shadow of current MFW mailbox */
1013 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1014 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1015 p_hwfn->mcp_info->mfw_mb_cur,
1016 p_hwfn->mcp_info->mfw_mb_length);
1018 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1020 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1024 #define FINAL_CLEANUP_POLL_CNT (100)
1025 #define FINAL_CLEANUP_POLL_TIME (10)
1026 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1027 struct ecore_ptt *p_ptt,
1030 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1031 enum _ecore_status_t rc = ECORE_TIMEOUT;
1034 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1035 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1036 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1037 return ECORE_SUCCESS;
1041 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1042 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1047 command |= X_FINAL_CLEANUP_AGG_INT <<
1048 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1049 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1050 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1051 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1053 /* Make sure notification is not set before initiating final cleanup */
1055 if (REG_RD(p_hwfn, addr)) {
1056 DP_NOTICE(p_hwfn, false,
1057 "Unexpected; Found final cleanup notification");
1058 DP_NOTICE(p_hwfn, false,
1059 " before initiating final cleanup\n");
1060 REG_WR(p_hwfn, addr, 0);
1063 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1064 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1067 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1069 /* Poll until completion */
1070 while (!REG_RD(p_hwfn, addr) && count--)
1071 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1073 if (REG_RD(p_hwfn, addr))
1076 DP_NOTICE(p_hwfn, true,
1077 "Failed to receive FW final cleanup notification\n");
1079 /* Cleanup afterwards */
1080 REG_WR(p_hwfn, addr, 0);
1085 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1089 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1090 hw_mode |= 1 << MODE_BB;
1091 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1092 hw_mode |= 1 << MODE_K2;
1094 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1095 p_hwfn->p_dev->type);
1099 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1100 switch (p_hwfn->p_dev->num_ports_in_engines) {
1102 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1105 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1108 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1111 DP_NOTICE(p_hwfn, true,
1112 "num_ports_in_engine = %d not supported\n",
1113 p_hwfn->p_dev->num_ports_in_engines);
1117 switch (p_hwfn->p_dev->mf_mode) {
1118 case ECORE_MF_DEFAULT:
1120 hw_mode |= 1 << MODE_MF_SI;
1122 case ECORE_MF_OVLAN:
1123 hw_mode |= 1 << MODE_MF_SD;
1126 DP_NOTICE(p_hwfn, true,
1127 "Unsupported MF mode, init as DEFAULT\n");
1128 hw_mode |= 1 << MODE_MF_SI;
1132 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1133 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1134 hw_mode |= 1 << MODE_FPGA;
1136 if (p_hwfn->p_dev->b_is_emul_full)
1137 hw_mode |= 1 << MODE_EMUL_FULL;
1139 hw_mode |= 1 << MODE_EMUL_REDUCED;
1143 hw_mode |= 1 << MODE_ASIC;
1145 if (p_hwfn->p_dev->num_hwfns > 1)
1146 hw_mode |= 1 << MODE_100G;
1148 p_hwfn->hw_info.hw_mode = hw_mode;
1150 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1151 "Configuring function for hw_mode: 0x%08x\n",
1152 p_hwfn->hw_info.hw_mode);
1154 return ECORE_SUCCESS;
1158 /* MFW-replacement initializations for non-ASIC */
1159 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1160 struct ecore_ptt *p_ptt)
1162 struct ecore_dev *p_dev = p_hwfn->p_dev;
1166 if (CHIP_REV_IS_EMUL(p_dev)) {
1167 if (ECORE_IS_AH(p_dev))
1171 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1173 if (CHIP_REV_IS_EMUL(p_dev) &&
1174 (ECORE_IS_AH(p_dev)))
1175 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1178 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1179 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1180 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1181 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1183 if (CHIP_REV_IS_EMUL(p_dev)) {
1184 if (ECORE_IS_AH(p_dev)) {
1185 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1186 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1187 (p_dev->num_ports_in_engines >> 1));
1189 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1190 p_dev->num_ports_in_engines == 4 ? 0 : 3);
1195 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1196 for (i = 0; i < 100; i++) {
1198 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1202 DP_NOTICE(p_hwfn, true,
1203 "RBC done failed to complete in PSWRQ2\n");
1205 return ECORE_SUCCESS;
1209 /* Init run time data for all PFs and their VFs on an engine.
1210 * TBD - for VFs - Once we have parent PF info for each VF in
1211 * shmem available as CAU requires knowledge of parent PF for each VF.
1213 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1215 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1218 for_each_hwfn(p_dev, i) {
1219 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1220 struct ecore_igu_info *p_igu_info;
1221 struct ecore_igu_block *p_block;
1222 struct cau_sb_entry sb_entry;
1224 p_igu_info = p_hwfn->hw_info.p_igu_info;
1226 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1228 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1230 if (!p_block->is_pf)
1233 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1234 p_block->function_id, 0, 0);
1235 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1240 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1241 struct ecore_ptt *p_ptt,
1244 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1245 struct ecore_dev *p_dev = p_hwfn->p_dev;
1246 u8 vf_id, max_num_vfs;
1249 enum _ecore_status_t rc = ECORE_SUCCESS;
1251 ecore_init_cau_rt_data(p_dev);
1253 /* Program GTT windows */
1254 ecore_gtt_init(p_hwfn);
1257 if (CHIP_REV_IS_EMUL(p_dev)) {
1258 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1259 if (rc != ECORE_SUCCESS)
1264 if (p_hwfn->mcp_info) {
1265 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1266 qm_info->pf_rl_en = 1;
1267 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1268 qm_info->pf_wfq_en = 1;
1271 ecore_qm_common_rt_init(p_hwfn,
1272 p_dev->num_ports_in_engines,
1273 qm_info->max_phys_tcs_per_port,
1274 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1275 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1276 qm_info->qm_port_params);
1278 ecore_cxt_hw_init_common(p_hwfn);
1280 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1281 if (rc != ECORE_SUCCESS)
1284 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1285 * need to decide with which value, maybe runtime
1287 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1288 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1290 if (ECORE_IS_BB(p_dev)) {
1291 /* Workaround clears ROCE search for all functions to prevent
1292 * involving non initialized function in processing ROCE packet.
1294 num_pfs = NUM_OF_ENG_PFS(p_dev);
1295 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1296 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1297 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1298 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1300 /* pretend to original PF */
1301 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1304 /* Workaround for avoiding CCFC execution error when getting packets
1305 * with CRC errors, and allowing instead the invoking of the FW error
1307 * This is not done inside the init tool since it currently can't
1308 * perform a pretending to VFs.
1310 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1311 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1312 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1313 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1314 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1315 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1316 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1317 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1319 /* pretend to original PF */
1320 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1326 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1327 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1329 #define PMEG_IF_BYTE_COUNT 8
1331 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1332 struct ecore_ptt *p_ptt,
1333 u32 addr, u64 data, u8 reg_type, u8 port)
1335 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1336 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1337 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1338 (8 << PMEG_IF_BYTE_COUNT),
1339 (reg_type << 25) | (addr << 8) | port,
1340 (u32)((data >> 32) & 0xffffffff),
1341 (u32)(data & 0xffffffff));
1343 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1344 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1345 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1346 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1347 (reg_type << 25) | (addr << 8) | port);
1348 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1349 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1350 (data >> 32) & 0xffffffff);
1353 #define XLPORT_MODE_REG (0x20a)
1354 #define XLPORT_MAC_CONTROL (0x210)
1355 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1356 #define XLPORT_ENABLE_REG (0x20b)
1358 #define XLMAC_CTRL (0x600)
1359 #define XLMAC_MODE (0x601)
1360 #define XLMAC_RX_MAX_SIZE (0x608)
1361 #define XLMAC_TX_CTRL (0x604)
1362 #define XLMAC_PAUSE_CTRL (0x60d)
1363 #define XLMAC_PFC_CTRL (0x60e)
1365 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1366 struct ecore_ptt *p_ptt)
1368 u8 loopback = 0, port = p_hwfn->port_id * 2;
1370 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1372 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1373 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1375 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1376 /* XLMAC: SOFT RESET */
1377 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1378 /* XLMAC: Port Speed >= 10Gbps */
1379 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1380 /* XLMAC: Max Size */
1381 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1382 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1383 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1385 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1386 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1387 0x30ffffc000ULL, 0, port);
1388 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1389 port); /* XLMAC: TX_EN, RX_EN */
1390 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1391 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1392 0x1003 | (loopback << 2), 0, port);
1393 /* Enabled Parallel PFC interface */
1394 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1396 /* XLPORT port enable */
1397 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1400 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1401 struct ecore_ptt *p_ptt)
1403 u8 port = p_hwfn->port_id;
1404 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1406 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1408 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1409 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1411 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1412 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1414 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1415 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1417 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1418 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1420 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1421 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1423 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1424 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1426 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1428 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1430 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1432 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1436 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1437 struct ecore_ptt *p_ptt)
1439 if (ECORE_IS_AH(p_hwfn->p_dev))
1440 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1442 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1445 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1446 struct ecore_ptt *p_ptt, u8 port)
1448 int port_offset = port ? 0x800 : 0;
1449 u32 xmac_rxctrl = 0;
1452 /* FIXME: move to common start */
1453 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1454 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1456 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1457 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1459 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1461 /* Set the number of ports on the Warp Core to 10G */
1462 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1464 /* Soft reset of XMAC */
1465 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1466 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1468 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1469 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1471 /* FIXME: move to common end */
1472 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1473 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1475 /* Set Max packet size: initialize XMAC block register for port 0 */
1476 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1478 /* CRC append for Tx packets: init XMAC block register for port 1 */
1479 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1481 /* Enable TX and RX: initialize XMAC block register for port 1 */
1482 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1483 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1484 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1485 XMAC_REG_RX_CTRL_BB + port_offset);
1486 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1487 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1491 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1492 struct ecore_ptt *p_ptt,
1495 enum _ecore_status_t rc = ECORE_SUCCESS;
1497 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1499 if (rc != ECORE_SUCCESS)
1502 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1503 return ECORE_SUCCESS;
1505 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1506 if (ECORE_IS_AH(p_hwfn->p_dev))
1507 return ECORE_SUCCESS;
1508 else if (ECORE_IS_BB(p_hwfn->p_dev))
1509 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1510 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1511 if (p_hwfn->p_dev->num_hwfns > 1) {
1512 /* Activate OPTE in CMT */
1515 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1517 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1518 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1519 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1520 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1521 ecore_wr(p_hwfn, p_ptt,
1522 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1523 ecore_wr(p_hwfn, p_ptt,
1524 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1525 ecore_wr(p_hwfn, p_ptt,
1526 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1530 ecore_emul_link_init(p_hwfn, p_ptt);
1532 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1539 static enum _ecore_status_t
1540 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1541 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1543 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1544 u32 dpi_bit_shift, dpi_count;
1547 /* Calculate DPI size
1548 * ------------------
1549 * The PWM region contains Doorbell Pages. The first is reserverd for
1550 * the kernel for, e.g, L2. The others are free to be used by non-
1551 * trusted applications, typically from user space. Each page, called a
1552 * doorbell page is sectioned into windows that allow doorbells to be
1553 * issued in parallel by the kernel/application. The size of such a
1554 * window (a.k.a. WID) is 1kB.
1556 * 1kB WID x N WIDS = DPI page size
1557 * DPI page size x N DPIs = PWM region size
1559 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1560 * in order to ensure that two applications won't share the same page.
1561 * It also must contain at least one WID per CPU to allow parallelism.
1562 * It also must be a power of 2, since it is stored as a bit shift.
1564 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1565 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1566 * containing 4 WIDs.
1568 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1569 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1570 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1571 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1572 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1574 dpi_count = pwm_region_size / dpi_page_size;
1576 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1577 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1580 p_hwfn->dpi_size = dpi_page_size;
1581 p_hwfn->dpi_count = dpi_count;
1583 /* Update registers */
1584 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1586 if (dpi_count < min_dpis)
1587 return ECORE_NORESOURCES;
1589 return ECORE_SUCCESS;
1592 enum ECORE_ROCE_EDPM_MODE {
1593 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1594 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1595 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1598 static enum _ecore_status_t
1599 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1600 struct ecore_ptt *p_ptt)
1602 u32 pwm_regsize, norm_regsize;
1603 u32 non_pwm_conn, min_addr_reg1;
1604 u32 db_bar_size, n_cpus;
1607 int rc = ECORE_SUCCESS;
1610 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1611 if (p_hwfn->p_dev->num_hwfns > 1)
1614 /* Calculate doorbell regions
1615 * -----------------------------------
1616 * The doorbell BAR is made of two regions. The first is called normal
1617 * region and the second is called PWM region. In the normal region
1618 * each ICID has its own set of addresses so that writing to that
1619 * specific address identifies the ICID. In the Process Window Mode
1620 * region the ICID is given in the data written to the doorbell. The
1621 * above per PF register denotes the offset in the doorbell BAR in which
1622 * the PWM region begins.
1623 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1624 * non-PWM connection. The calculation below computes the total non-PWM
1625 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1626 * in units of 4,096 bytes.
1628 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1629 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1631 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1632 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1633 min_addr_reg1 = norm_regsize / 4096;
1634 pwm_regsize = db_bar_size - norm_regsize;
1636 /* Check that the normal and PWM sizes are valid */
1637 if (db_bar_size < norm_regsize) {
1638 DP_ERR(p_hwfn->p_dev,
1639 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1640 db_bar_size, norm_regsize);
1641 return ECORE_NORESOURCES;
1643 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1644 DP_ERR(p_hwfn->p_dev,
1645 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1646 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1648 return ECORE_NORESOURCES;
1651 /* Calculate number of DPIs */
1652 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1653 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1654 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1655 /* Either EDPM is mandatory, or we are attempting to allocate a
1658 n_cpus = OSAL_NUM_ACTIVE_CPU();
1659 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1662 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1663 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1664 if (cond || p_hwfn->dcbx_no_edpm) {
1665 /* Either EDPM is disabled from user configuration, or it is
1666 * disabled via DCBx, or it is not mandatory and we failed to
1667 * allocated a WID per CPU.
1670 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1672 /* If we entered this flow due to DCBX then the DPM register is
1673 * already configured.
1678 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1679 norm_regsize, pwm_regsize);
1681 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1682 p_hwfn->dpi_size, p_hwfn->dpi_count,
1683 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1684 "disabled" : "enabled");
1686 /* Check return codes from above calls */
1689 "Failed to allocate enough DPIs\n");
1690 return ECORE_NORESOURCES;
1694 p_hwfn->dpi_start_offset = norm_regsize;
1696 /* Update registers */
1697 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1698 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1699 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1700 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1702 return ECORE_SUCCESS;
1705 static enum _ecore_status_t
1706 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1707 struct ecore_ptt *p_ptt,
1708 struct ecore_tunnel_info *p_tunn,
1711 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1713 u8 rel_pf_id = p_hwfn->rel_pf_id;
1715 enum _ecore_status_t rc = ECORE_SUCCESS;
1719 if (p_hwfn->mcp_info) {
1720 struct ecore_mcp_function_info *p_info;
1722 p_info = &p_hwfn->mcp_info->func_info;
1723 if (p_info->bandwidth_min)
1724 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1726 /* Update rate limit once we'll actually have a link */
1727 p_hwfn->qm_info.pf_rl = 100000;
1729 ecore_cxt_hw_init_pf(p_hwfn);
1731 ecore_int_igu_init_rt(p_hwfn);
1733 /* Set VLAN in NIG if needed */
1734 if (hw_mode & (1 << MODE_MF_SD)) {
1735 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1736 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1737 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1738 p_hwfn->hw_info.ovlan);
1741 /* Enable classification by MAC if needed */
1742 if (hw_mode & (1 << MODE_MF_SI)) {
1743 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1744 "Configuring TAGMAC_CLS_TYPE\n");
1745 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1749 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1750 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1751 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1752 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1753 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1754 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1756 /* perform debug configuration when chip is out of reset */
1757 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1759 /* Cleanup chip from previous driver if such remains exist */
1760 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1761 if (rc != ECORE_SUCCESS) {
1762 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1766 /* PF Init sequence */
1767 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1771 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1772 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1776 /* Pure runtime initializations - directly to the HW */
1777 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1779 /* PCI relaxed ordering causes a decrease in the performance on some
1780 * systems. Till a root cause is found, disable this attribute in the
1784 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1786 * DP_NOTICE(p_hwfn, true,
1787 * "Failed to find the PCIe Cap\n");
1790 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1791 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1792 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1795 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1799 /* enable interrupts */
1800 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1801 if (rc != ECORE_SUCCESS)
1804 /* send function start command */
1805 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1806 allow_npar_tx_switch);
1808 DP_NOTICE(p_hwfn, true,
1809 "Function start ramrod failed\n");
1811 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1812 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1813 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1815 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1816 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1818 ecore_wr(p_hwfn, p_ptt,
1819 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1822 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1823 "PRS_REG_SEARCH registers after start PFn\n");
1824 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1825 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1826 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1827 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1828 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1829 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1830 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1831 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1832 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1833 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1834 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1835 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1836 prs_reg = ecore_rd(p_hwfn, p_ptt,
1837 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1838 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1839 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1841 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1842 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1843 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1849 static enum _ecore_status_t
1850 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1851 struct ecore_ptt *p_ptt, u8 enable)
1853 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1855 /* Change PF in PXP */
1856 ecore_wr(p_hwfn, p_ptt,
1857 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1859 /* wait until value is set - try for 1 second every 50us */
1860 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1861 val = ecore_rd(p_hwfn, p_ptt,
1862 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1869 if (val != set_val) {
1870 DP_NOTICE(p_hwfn, true,
1871 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1872 return ECORE_UNKNOWN_ERROR;
1875 return ECORE_SUCCESS;
1878 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1879 struct ecore_ptt *p_main_ptt)
1881 /* Read shadow of current MFW mailbox */
1882 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1883 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1884 p_hwfn->mcp_info->mfw_mb_cur,
1885 p_hwfn->mcp_info->mfw_mb_length);
1888 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1889 struct ecore_hw_init_params *p_params)
1891 if (p_params->p_tunn) {
1892 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1893 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1896 p_hwfn->b_int_enabled = 1;
1898 return ECORE_SUCCESS;
1901 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1902 struct ecore_hw_init_params *p_params)
1904 enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1905 u32 load_code, param, drv_mb_param;
1906 bool b_default_mtu = true;
1907 struct ecore_hwfn *p_hwfn;
1910 if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1911 (p_dev->num_hwfns > 1)) {
1912 DP_NOTICE(p_dev, false,
1913 "MSI mode is not supported for CMT devices\n");
1918 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1919 if (rc != ECORE_SUCCESS)
1923 for_each_hwfn(p_dev, i) {
1924 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1926 /* If management didn't provide a default, set one of our own */
1927 if (!p_hwfn->hw_info.mtu) {
1928 p_hwfn->hw_info.mtu = 1500;
1929 b_default_mtu = false;
1933 ecore_vf_start(p_hwfn, p_params);
1937 /* Enable DMAE in PXP */
1938 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1939 if (rc != ECORE_SUCCESS)
1942 rc = ecore_calc_hw_mode(p_hwfn);
1943 if (rc != ECORE_SUCCESS)
1946 /* @@@TBD need to add here:
1947 * Check for fan failure
1950 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1952 DP_NOTICE(p_hwfn, true,
1953 "Failed sending LOAD_REQ command\n");
1958 * When coming back from hiberbate state, the registers from
1959 * which shadow is read initially are not initialized. It turns
1960 * out that these registers get initialized during the call to
1961 * ecore_mcp_load_req request. So we need to reread them here
1962 * to get the proper shadow register value.
1963 * Note: This is a workaround for the missing MFW
1964 * initialization. It may be removed once the implementation
1967 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1969 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1970 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1973 /* Only relevant for recovery:
1974 * Clear the indication after the LOAD_REQ command is responded
1977 p_dev->recov_in_prog = false;
1979 p_hwfn->first_on_engine = (load_code ==
1980 FW_MSG_CODE_DRV_LOAD_ENGINE);
1982 if (!qm_lock_init) {
1983 OSAL_SPIN_LOCK_INIT(&qm_lock);
1984 qm_lock_init = true;
1987 switch (load_code) {
1988 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1989 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1990 p_hwfn->hw_info.hw_mode);
1994 case FW_MSG_CODE_DRV_LOAD_PORT:
1995 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1996 p_hwfn->hw_info.hw_mode);
2000 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2001 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2003 p_hwfn->hw_info.hw_mode,
2004 p_params->b_hw_start,
2006 p_params->allow_npar_tx_switch);
2013 if (rc != ECORE_SUCCESS)
2014 DP_NOTICE(p_hwfn, true,
2015 "init phase failed for loadcode 0x%x (rc %d)\n",
2018 /* ACK mfw regardless of success or failure of initialization */
2019 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2020 DRV_MSG_CODE_LOAD_DONE,
2021 0, &load_code, ¶m);
2022 if (rc != ECORE_SUCCESS)
2024 if (mfw_rc != ECORE_SUCCESS) {
2025 DP_NOTICE(p_hwfn, true,
2026 "Failed sending LOAD_DONE command\n");
2030 /* send DCBX attention request command */
2031 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2032 "sending phony dcbx set command to trigger DCBx attention handling\n");
2033 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2034 DRV_MSG_CODE_SET_DCBX,
2035 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2036 &load_code, ¶m);
2037 if (mfw_rc != ECORE_SUCCESS) {
2038 DP_NOTICE(p_hwfn, true,
2039 "Failed to send DCBX attention request\n");
2043 p_hwfn->hw_init_done = true;
2047 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2048 drv_mb_param = (FW_MAJOR_VERSION << 24) |
2049 (FW_MINOR_VERSION << 16) |
2050 (FW_REVISION_VERSION << 8) |
2051 (FW_ENGINEERING_VERSION);
2052 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2053 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2054 drv_mb_param, &load_code, ¶m);
2055 if (rc != ECORE_SUCCESS)
2056 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2059 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2060 p_hwfn->hw_info.mtu);
2061 if (rc != ECORE_SUCCESS)
2062 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2064 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2066 ECORE_OV_DRIVER_STATE_DISABLED);
2067 if (rc != ECORE_SUCCESS)
2068 DP_INFO(p_hwfn, "Failed to update driver state\n");
2074 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2075 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2076 struct ecore_hwfn *p_hwfn,
2077 struct ecore_ptt *p_ptt)
2082 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2083 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2084 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2086 if ((!ecore_rd(p_hwfn, p_ptt,
2087 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2088 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2091 /* Dependent on number of connection/tasks, possibly
2092 * 1ms sleep is required between polls
2097 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2100 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2101 " [Connection %02x Tasks %02x]\n",
2102 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2103 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2106 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2110 for_each_hwfn(p_dev, j) {
2111 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2112 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2114 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2118 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2120 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
2123 for_each_hwfn(p_dev, j) {
2124 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2125 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2127 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2130 ecore_vf_pf_int_cleanup(p_hwfn);
2134 /* mark the hw as uninitialized... */
2135 p_hwfn->hw_init_done = false;
2137 rc = ecore_sp_pf_stop(p_hwfn);
2139 DP_NOTICE(p_hwfn, true,
2140 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
2142 /* perform debug action after PF stop was sent */
2143 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
2145 /* close NIG to BRB gate */
2146 ecore_wr(p_hwfn, p_ptt,
2147 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2150 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2151 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2152 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2153 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2154 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2156 /* @@@TBD - clean transmission queues (5.b) */
2157 /* @@@TBD - clean BTB (5.c) */
2159 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2161 /* @@@TBD - verify DMAE requests are done (8) */
2163 /* Disable Attention Generation */
2164 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2165 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2166 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2167 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2168 /* Need to wait 1ms to guarantee SBs are cleared */
2173 /* Disable DMAE in PXP - in CMT, this should only be done for
2174 * first hw-function, and only after all transactions have
2175 * stopped for all active hw-functions.
2177 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
2178 p_dev->hwfns[0].p_main_ptt, false);
2179 if (t_rc != ECORE_SUCCESS)
2186 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2190 for_each_hwfn(p_dev, j) {
2191 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2192 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2195 ecore_vf_pf_int_cleanup(p_hwfn);
2199 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2200 "Shutting down the fastpath\n");
2202 ecore_wr(p_hwfn, p_ptt,
2203 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2205 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2206 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2207 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2208 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2209 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2211 /* @@@TBD - clean transmission queues (5.b) */
2212 /* @@@TBD - clean BTB (5.c) */
2214 /* @@@TBD - verify DMAE requests are done (8) */
2216 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2217 /* Need to wait 1ms to guarantee SBs are cleared */
2222 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2224 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2226 if (IS_VF(p_hwfn->p_dev))
2229 /* If roce info is allocated it means roce is initialized and should
2230 * be enabled in searcher.
2232 if (p_hwfn->p_rdma_info) {
2233 if (p_hwfn->b_rdma_enabled_in_prs)
2234 ecore_wr(p_hwfn, p_ptt,
2235 p_hwfn->rdma_prs_search_reg, 0x1);
2236 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2239 /* Re-open incoming traffic */
2240 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2241 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2244 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
2245 struct ecore_ptt *p_ptt, u32 reg,
2248 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
2250 if (assert_val != expected) {
2251 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
2253 return ECORE_UNKNOWN_ERROR;
2259 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
2261 enum _ecore_status_t rc = ECORE_SUCCESS;
2262 u32 unload_resp, unload_param;
2265 for_each_hwfn(p_dev, i) {
2266 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2269 rc = ecore_vf_pf_reset(p_hwfn);
2275 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
2277 /* Check for incorrect states */
2278 if (!p_dev->recov_in_prog) {
2279 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2280 QM_REG_USG_CNT_PF_TX, 0);
2281 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2282 QM_REG_USG_CNT_PF_OTHER, 0);
2283 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2286 /* Disable PF in HW blocks */
2287 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2288 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2290 if (p_dev->recov_in_prog) {
2291 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2292 "Recovery is in progress -> skip sending unload_req/done\n");
2296 /* Send unload command to MCP */
2297 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2298 DRV_MSG_CODE_UNLOAD_REQ,
2299 DRV_MB_PARAM_UNLOAD_WOL_MCP,
2300 &unload_resp, &unload_param);
2301 if (rc != ECORE_SUCCESS) {
2302 DP_NOTICE(p_hwfn, true,
2303 "ecore_hw_reset: UNLOAD_REQ failed\n");
2304 /* @@TBD - what to do? for now, assume ENG. */
2305 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2308 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2309 DRV_MSG_CODE_UNLOAD_DONE,
2310 0, &unload_resp, &unload_param);
2311 if (rc != ECORE_SUCCESS) {
2313 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2314 /* @@@TBD - Should it really ASSERT here ? */
2322 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2323 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2325 ecore_ptt_pool_free(p_hwfn);
2326 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2329 /* Setup bar access */
2330 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2332 /* clear indirect access */
2333 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2334 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2335 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2336 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2337 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2338 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2339 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2340 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2341 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2343 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2344 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2345 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2346 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2347 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2348 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2349 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2350 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2353 /* Clean Previous errors if such exist */
2354 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2355 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2357 /* enable internal target-read */
2358 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2359 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2362 static void get_function_id(struct ecore_hwfn *p_hwfn)
2365 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2366 PXP_PF_ME_OPAQUE_ADDR);
2368 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2370 /* Bits 16-19 from the ME registers are the pf_num */
2371 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2372 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2373 PXP_CONCRETE_FID_PFID);
2374 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2375 PXP_CONCRETE_FID_PORT);
2377 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2378 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2379 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2382 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2384 u32 *feat_num = p_hwfn->hw_info.feat_num;
2385 struct ecore_sb_cnt_info sb_cnt_info;
2386 int num_features = 1;
2388 /* L2 Queues require each: 1 status block. 1 L2 queue */
2389 feat_num[ECORE_PF_L2_QUE] =
2391 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2392 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2394 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2395 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2396 feat_num[ECORE_VF_L2_QUE] =
2398 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2399 FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2400 sb_cnt_info.sb_iov_cnt);
2402 feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2403 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2404 feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2405 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2407 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2408 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2409 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2410 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2411 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2412 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2413 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2414 RESC_NUM(p_hwfn, ECORE_SB));
2417 static enum resource_id_enum
2418 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2420 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2424 mfw_res_id = RESOURCE_NUM_SB_E;
2426 case ECORE_L2_QUEUE:
2427 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2430 mfw_res_id = RESOURCE_NUM_VPORT_E;
2433 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2436 mfw_res_id = RESOURCE_NUM_PQ_E;
2439 mfw_res_id = RESOURCE_NUM_RL_E;
2443 /* Each VFC resource can accommodate both a MAC and a VLAN */
2444 mfw_res_id = RESOURCE_VFC_FILTER_E;
2447 mfw_res_id = RESOURCE_ILT_E;
2449 case ECORE_LL2_QUEUE:
2450 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2452 case ECORE_RDMA_CNQ_RAM:
2453 case ECORE_CMDQS_CQS:
2454 /* CNQ/CMDQS are the same resource */
2455 mfw_res_id = RESOURCE_CQS_E;
2457 case ECORE_RDMA_STATS_QUEUE:
2458 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2467 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2468 enum ecore_resources res_id)
2470 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2471 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2472 struct ecore_sb_cnt_info sb_cnt_info;
2473 u32 dflt_resc_num = 0;
2477 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2478 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2479 dflt_resc_num = sb_cnt_info.sb_cnt;
2481 case ECORE_L2_QUEUE:
2482 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2483 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2486 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2487 MAX_NUM_VPORTS_BB) / num_funcs;
2490 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2491 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2494 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2495 MAX_QM_TX_QUEUES_BB) / num_funcs;
2498 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2502 /* Each VFC resource can accommodate both a MAC and a VLAN */
2503 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2506 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2507 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2509 case ECORE_LL2_QUEUE:
2510 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2512 case ECORE_RDMA_CNQ_RAM:
2513 case ECORE_CMDQS_CQS:
2514 /* CNQ/CMDQS are the same resource */
2516 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2518 case ECORE_RDMA_STATS_QUEUE:
2520 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2521 MAX_NUM_VPORTS_BB) / num_funcs;
2527 return dflt_resc_num;
2530 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2535 case ECORE_L2_QUEUE:
2549 case ECORE_RDMA_CNQ_RAM:
2550 return "RDMA_CNQ_RAM";
2553 case ECORE_LL2_QUEUE:
2555 case ECORE_CMDQS_CQS:
2557 case ECORE_RDMA_STATS_QUEUE:
2558 return "RDMA_STATS_QUEUE";
2560 return "UNKNOWN_RESOURCE";
2564 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2565 enum ecore_resources res_id,
2566 bool drv_resc_alloc)
2568 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2569 u32 *p_resc_num, *p_resc_start;
2570 struct resource_info resc_info;
2571 enum _ecore_status_t rc;
2573 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2574 p_resc_start = &RESC_START(p_hwfn, res_id);
2576 dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2577 if (!dflt_resc_num) {
2579 "Failed to get default amount for resource %d [%s]\n",
2580 res_id, ecore_hw_get_resc_name(res_id));
2583 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2586 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2587 *p_resc_num = dflt_resc_num;
2588 *p_resc_start = dflt_resc_start;
2593 OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2594 resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2595 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2597 "Failed to match resource %d with MFW resources\n",
2602 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2603 &mcp_resp, &mcp_param);
2604 if (rc != ECORE_SUCCESS) {
2605 DP_NOTICE(p_hwfn, true,
2606 "MFW response failure for an allocation request for"
2607 " resource %d [%s]\n",
2608 res_id, ecore_hw_get_resc_name(res_id));
2612 /* Default driver values are applied in the following cases:
2613 * - The resource allocation MB command is not supported by the MFW
2614 * - There is an internal error in the MFW while processing the request
2615 * - The resource ID is unknown to the MFW
2617 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2618 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2621 "Resource %d [%s]: No allocation info was received"
2622 " [mcp_resp 0x%x]. Applying default values"
2623 " [num %d, start %d].\n",
2624 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2625 dflt_resc_num, dflt_resc_start);
2627 *p_resc_num = dflt_resc_num;
2628 *p_resc_start = dflt_resc_start;
2632 /* TBD - remove this when revising the handling of the SB resource */
2633 if (res_id == ECORE_SB) {
2634 /* Excluding the slowpath SB */
2635 resc_info.size -= 1;
2636 resc_info.offset -= p_hwfn->enabled_func_idx;
2639 *p_resc_num = resc_info.size;
2640 *p_resc_start = resc_info.offset;
2642 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2644 "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2645 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2646 *p_resc_start, dflt_resc_num, dflt_resc_start,
2647 drv_resc_alloc ? " - Applying default values" : "");
2648 if (drv_resc_alloc) {
2649 *p_resc_num = dflt_resc_num;
2650 *p_resc_start = dflt_resc_start;
2654 return ECORE_SUCCESS;
2657 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2658 bool drv_resc_alloc)
2660 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2661 enum _ecore_status_t rc;
2664 u32 *resc_start = p_hwfn->hw_info.resc_start;
2665 u32 *resc_num = p_hwfn->hw_info.resc_num;
2666 /* For AH, an equal share of the ILT lines between the maximal number of
2667 * PFs is not enough for RoCE. This would be solved by the future
2668 * resource allocation scheme, but isn't currently present for
2669 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2670 * to work - the BB number of ILT lines divided by its max PFs number.
2672 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2675 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2676 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2677 if (rc != ECORE_SUCCESS)
2682 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2683 /* Reduced build contains less PQs */
2684 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2685 resc_num[ECORE_PQ] = 32;
2686 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2687 p_hwfn->enabled_func_idx;
2690 /* For AH emulation, since we have a possible maximal number of
2691 * 16 enabled PFs, in case there are not enough ILT lines -
2692 * allocate only first PF as RoCE and have all the other ETH
2693 * only with less ILT lines.
2695 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2696 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2697 resc_num[ECORE_ILT],
2698 roce_min_ilt_lines);
2701 /* Correct the common ILT calculation if PF0 has more */
2702 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2703 p_hwfn->p_dev->b_is_emul_full &&
2704 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2705 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2706 resc_num[ECORE_ILT];
2709 /* Sanity for ILT */
2710 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2711 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2712 DP_NOTICE(p_hwfn, true,
2713 "Can't assign ILT pages [%08x,...,%08x]\n",
2714 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2720 ecore_hw_set_feat(p_hwfn);
2722 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2723 "The numbers for each resource are:\n");
2724 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2725 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2726 ecore_hw_get_resc_name(res_id),
2727 RESC_NUM(p_hwfn, res_id),
2728 RESC_START(p_hwfn, res_id));
2730 return ECORE_SUCCESS;
2733 static enum _ecore_status_t
2734 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2735 struct ecore_ptt *p_ptt,
2736 struct ecore_hw_prepare_params *p_params)
2738 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2739 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2740 struct ecore_mcp_link_params *link;
2741 enum _ecore_status_t rc;
2743 /* Read global nvm_cfg address */
2744 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2746 /* Verify MCP has initialized it */
2747 if (!nvm_cfg_addr) {
2748 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2749 if (p_params->b_relaxed_probe)
2750 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2754 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2756 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2758 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2759 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2762 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2764 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2765 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2766 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2767 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2769 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2770 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2772 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2773 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2775 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2776 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2778 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2779 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2781 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2782 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2784 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2785 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2787 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2788 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2790 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2791 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2793 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2794 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2796 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2797 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2800 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2805 /* Read DCBX configuration */
2806 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2807 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2808 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2810 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2811 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2812 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2813 switch (dcbx_mode) {
2814 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2815 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2817 case NVM_CFG1_PORT_DCBX_MODE_CEE:
2818 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2820 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2821 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2824 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2827 /* Read default link configuration */
2828 link = &p_hwfn->mcp_info->link_input;
2829 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2830 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2831 link_temp = ecore_rd(p_hwfn, p_ptt,
2833 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2834 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2835 link->speed.advertised_speeds = link_temp;
2837 link_temp = link->speed.advertised_speeds;
2838 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2840 link_temp = ecore_rd(p_hwfn, p_ptt,
2842 OFFSETOF(struct nvm_cfg1_port, link_settings));
2843 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2844 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2845 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2846 link->speed.autoneg = true;
2848 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2849 link->speed.forced_speed = 1000;
2851 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2852 link->speed.forced_speed = 10000;
2854 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2855 link->speed.forced_speed = 25000;
2857 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2858 link->speed.forced_speed = 40000;
2860 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2861 link->speed.forced_speed = 50000;
2863 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2864 link->speed.forced_speed = 100000;
2867 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2870 p_hwfn->mcp_info->link_capabilities.default_speed =
2871 link->speed.forced_speed;
2872 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2873 link->speed.autoneg;
2875 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2876 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2877 link->pause.autoneg = !!(link_temp &
2878 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2879 link->pause.forced_rx = !!(link_temp &
2880 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2881 link->pause.forced_tx = !!(link_temp &
2882 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2883 link->loopback_mode = 0;
2885 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2886 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2887 link->speed.forced_speed, link->speed.advertised_speeds,
2888 link->speed.autoneg, link->pause.autoneg);
2890 /* Read Multi-function information from shmem */
2891 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2892 OFFSETOF(struct nvm_cfg1, glob) +
2893 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2895 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2897 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2898 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2901 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2902 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2904 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2905 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2907 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2908 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2911 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2912 p_hwfn->p_dev->mf_mode);
2914 /* Read Multi-function information from shmem */
2915 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2916 OFFSETOF(struct nvm_cfg1, glob) +
2917 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2919 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2920 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2921 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2922 &p_hwfn->hw_info.device_capabilities);
2923 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2924 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2925 &p_hwfn->hw_info.device_capabilities);
2926 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2927 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2928 &p_hwfn->hw_info.device_capabilities);
2929 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2930 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2931 &p_hwfn->hw_info.device_capabilities);
2932 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2933 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2934 &p_hwfn->hw_info.device_capabilities);
2936 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2937 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
2939 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
2945 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2946 struct ecore_ptt *p_ptt)
2948 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2949 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2950 struct ecore_dev *p_dev = p_hwfn->p_dev;
2952 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2954 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2955 * in the other bits are selected.
2956 * Bits 1-15 are for functions 1-15, respectively, and their value is
2957 * '0' only for enabled functions (function 0 always exists and
2959 * In case of CMT in BB, only the "even" functions are enabled, and thus
2960 * the number of functions for both hwfns is learnt from the same bits.
2962 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
2963 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
2964 MISCS_REG_FUNCTION_HIDE_BB_K2);
2966 reg_function_hide = 0;
2969 if (reg_function_hide & 0x1) {
2970 if (ECORE_IS_BB(p_dev)) {
2971 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2983 /* Get the number of the enabled functions on the engine */
2984 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2991 /* Get the PF index within the enabled functions */
2992 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2993 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3001 p_hwfn->num_funcs_on_engine = num_funcs;
3002 p_hwfn->enabled_func_idx = enabled_func_idx;
3005 if (CHIP_REV_IS_FPGA(p_dev)) {
3006 DP_NOTICE(p_hwfn, false,
3007 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3008 p_hwfn->num_funcs_on_engine = 4;
3012 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3013 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3014 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3015 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3018 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3019 struct ecore_ptt *p_ptt)
3024 /* Read the port mode */
3025 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3027 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3028 (p_hwfn->p_dev->num_hwfns > 1))
3029 /* In CMT on emulation, assume 1 port */
3033 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3035 if (port_mode < 3) {
3036 p_hwfn->p_dev->num_ports_in_engines = 1;
3037 } else if (port_mode <= 5) {
3038 p_hwfn->p_dev->num_ports_in_engines = 2;
3040 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3041 p_hwfn->p_dev->num_ports_in_engines);
3043 /* Default num_ports_in_engines to something */
3044 p_hwfn->p_dev->num_ports_in_engines = 1;
3048 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3049 struct ecore_ptt *p_ptt)
3054 p_hwfn->p_dev->num_ports_in_engines = 0;
3057 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3058 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3059 switch ((port & 0xf000) >> 12) {
3061 p_hwfn->p_dev->num_ports_in_engines = 1;
3064 p_hwfn->p_dev->num_ports_in_engines = 2;
3067 p_hwfn->p_dev->num_ports_in_engines = 4;
3070 DP_NOTICE(p_hwfn, false,
3071 "Unknown port mode in ECO_RESERVED %08x\n",
3076 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3077 port = ecore_rd(p_hwfn, p_ptt,
3078 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3081 p_hwfn->p_dev->num_ports_in_engines++;
3085 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3086 struct ecore_ptt *p_ptt)
3088 if (ECORE_IS_BB(p_hwfn->p_dev))
3089 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3091 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3094 static enum _ecore_status_t
3095 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3096 enum ecore_pci_personality personality,
3097 struct ecore_hw_prepare_params *p_params)
3099 bool drv_resc_alloc = p_params->drv_resc_alloc;
3100 enum _ecore_status_t rc;
3102 /* Since all information is common, only first hwfns should do this */
3103 if (IS_LEAD_HWFN(p_hwfn)) {
3104 rc = ecore_iov_hw_info(p_hwfn);
3105 if (rc != ECORE_SUCCESS) {
3106 if (p_params->b_relaxed_probe)
3107 p_params->p_relaxed_res =
3108 ECORE_HW_PREPARE_BAD_IOV;
3114 /* TODO In get_hw_info, amoungst others:
3115 * Get MCP FW revision and determine according to it the supported
3116 * featrues (e.g. DCB)
3118 * ecore_get_pcie_width_speed, WOL capability.
3119 * Number of global CQ-s (for storage
3121 ecore_hw_info_port_num(p_hwfn, p_ptt);
3124 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3126 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3127 if (rc != ECORE_SUCCESS)
3133 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3134 if (rc != ECORE_SUCCESS) {
3135 if (p_params->b_relaxed_probe)
3136 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3142 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3144 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3145 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3148 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3150 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3151 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3155 if (ecore_mcp_is_init(p_hwfn)) {
3156 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3157 p_hwfn->hw_info.ovlan =
3158 p_hwfn->mcp_info->func_info.ovlan;
3160 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3163 if (personality != ECORE_PCI_DEFAULT) {
3164 p_hwfn->hw_info.personality = personality;
3165 } else if (ecore_mcp_is_init(p_hwfn)) {
3166 enum ecore_pci_personality protocol;
3168 protocol = p_hwfn->mcp_info->func_info.protocol;
3169 p_hwfn->hw_info.personality = protocol;
3173 /* To overcome ILT lack for emulation, until at least until we'll have
3174 * a definite answer from system about it, allow only PF0 to be RoCE.
3176 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3177 if (!p_hwfn->rel_pf_id)
3178 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3180 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3184 /* although in BB some constellations may support more than 4 tcs,
3185 * that can result in performance penalty in some cases. 4
3186 * represents a good tradeoff between performance and flexibility.
3188 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3190 /* start out with a single active tc. This can be increased either
3191 * by dcbx negotiation or by upper layer driver
3193 p_hwfn->hw_info.num_active_tc = 1;
3195 ecore_get_num_funcs(p_hwfn, p_ptt);
3197 if (ecore_mcp_is_init(p_hwfn))
3198 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3200 /* In case of forcing the driver's default resource allocation, calling
3201 * ecore_hw_get_resc() should come after initializing the personality
3202 * and after getting the number of functions, since the calculation of
3203 * the resources/features depends on them.
3204 * This order is not harmful if not forcing.
3206 rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3207 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3209 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3215 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3217 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3220 /* Read Vendor Id / Device Id */
3221 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3223 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3226 /* Determine type */
3227 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
3228 p_dev->type = ECORE_DEV_TYPE_AH;
3230 p_dev->type = ECORE_DEV_TYPE_BB;
3232 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3233 MISCS_REG_CHIP_NUM);
3234 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3235 MISCS_REG_CHIP_REV);
3237 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3239 /* Learn number of HW-functions */
3240 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3241 MISCS_REG_CMT_ENABLED_FOR_PAIR);
3243 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3244 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3245 p_dev->num_hwfns = 2;
3247 p_dev->num_hwfns = 1;
3251 if (CHIP_REV_IS_EMUL(p_dev)) {
3252 /* For some reason we have problems with this register
3253 * in B0 emulation; Simply assume no CMT
3255 DP_NOTICE(p_dev->hwfns, false,
3256 "device on emul - assume no CMT\n");
3257 p_dev->num_hwfns = 1;
3261 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3262 MISCS_REG_CHIP_TEST_REG) >> 4;
3263 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3264 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3265 MISCS_REG_CHIP_METAL);
3266 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3267 DP_INFO(p_dev->hwfns,
3268 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3269 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3270 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3271 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3274 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3275 DP_NOTICE(p_dev->hwfns, false,
3276 "The chip type/rev (BB A0) is not supported!\n");
3277 return ECORE_ABORTED;
3280 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3281 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3282 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3284 if (CHIP_REV_IS_EMUL(p_dev)) {
3285 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3286 MISCS_REG_ECO_RESERVED);
3287 if (tmp & (1 << 29)) {
3288 DP_NOTICE(p_hwfn, false,
3289 "Emulation: Running on a FULL build\n");
3290 p_dev->b_is_emul_full = true;
3292 DP_NOTICE(p_hwfn, false,
3293 "Emulation: Running on a REDUCED build\n");
3298 return ECORE_SUCCESS;
3301 #ifndef LINUX_REMOVE
3302 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3309 for_each_hwfn(p_dev, j) {
3310 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3312 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3313 "Mark hw/fw uninitialized\n");
3315 p_hwfn->hw_init_done = false;
3316 p_hwfn->first_on_engine = false;
3318 ecore_ptt_invalidate(p_hwfn);
3323 static enum _ecore_status_t
3324 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3325 void OSAL_IOMEM * p_regview,
3326 void OSAL_IOMEM * p_doorbells,
3327 struct ecore_hw_prepare_params *p_params)
3329 struct ecore_dev *p_dev = p_hwfn->p_dev;
3330 struct ecore_mdump_info mdump_info;
3331 enum _ecore_status_t rc = ECORE_SUCCESS;
3333 /* Split PCI bars evenly between hwfns */
3334 p_hwfn->regview = p_regview;
3335 p_hwfn->doorbells = p_doorbells;
3338 return ecore_vf_hw_prepare(p_hwfn);
3340 /* Validate that chip access is feasible */
3341 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3343 "Reading the ME register returns all Fs; Preventing further chip access\n");
3344 if (p_params->b_relaxed_probe)
3345 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3349 get_function_id(p_hwfn);
3351 /* Allocate PTT pool */
3352 rc = ecore_ptt_pool_alloc(p_hwfn);
3354 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3355 if (p_params->b_relaxed_probe)
3356 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3360 /* Allocate the main PTT */
3361 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3363 /* First hwfn learns basic information, e.g., number of hwfns */
3364 if (!p_hwfn->my_id) {
3365 rc = ecore_get_dev_info(p_dev);
3366 if (rc != ECORE_SUCCESS) {
3367 if (p_params->b_relaxed_probe)
3368 p_params->p_relaxed_res =
3369 ECORE_HW_PREPARE_FAILED_DEV;
3374 ecore_hw_hwfn_prepare(p_hwfn);
3376 /* Initialize MCP structure */
3377 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3379 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3380 if (p_params->b_relaxed_probe)
3381 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3385 /* Read the device configuration information from the HW and SHMEM */
3386 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3387 p_params->personality, p_params);
3389 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3393 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3394 * called, since among others it sets the ports number in an engine.
3396 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3397 !p_dev->recov_in_prog) {
3398 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3399 if (rc != ECORE_SUCCESS)
3400 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3403 /* Check if mdump logs are present and update the epoch value */
3404 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3405 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3407 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3408 DP_NOTICE(p_hwfn, false,
3409 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3412 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3416 /* Allocate the init RT array and initialize the init-ops engine */
3417 rc = ecore_init_alloc(p_hwfn);
3419 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3420 if (p_params->b_relaxed_probe)
3421 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3425 if (CHIP_REV_IS_FPGA(p_dev)) {
3426 DP_NOTICE(p_hwfn, false,
3427 "FPGA: workaround; Prevent DMAE parities\n");
3428 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3431 DP_NOTICE(p_hwfn, false,
3432 "FPGA: workaround: Set VF bar0 size\n");
3433 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3434 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3440 if (IS_LEAD_HWFN(p_hwfn))
3441 ecore_iov_free_hw_info(p_dev);
3442 ecore_mcp_free(p_hwfn);
3444 ecore_hw_hwfn_free(p_hwfn);
3449 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3450 struct ecore_hw_prepare_params *p_params)
3452 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3453 enum _ecore_status_t rc;
3455 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3457 if (p_params->b_relaxed_probe)
3458 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3460 /* Store the precompiled init data ptrs */
3462 ecore_init_iro_array(p_dev);
3464 /* Initialize the first hwfn - will learn number of hwfns */
3465 rc = ecore_hw_prepare_single(p_hwfn,
3467 p_dev->doorbells, p_params);
3468 if (rc != ECORE_SUCCESS)
3471 p_params->personality = p_hwfn->hw_info.personality;
3473 /* initilalize 2nd hwfn if necessary */
3474 if (p_dev->num_hwfns > 1) {
3475 void OSAL_IOMEM *p_regview, *p_doorbell;
3476 u8 OSAL_IOMEM *addr;
3478 /* adjust bar offset for second engine */
3479 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3480 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3481 p_regview = (void OSAL_IOMEM *)addr;
3483 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3484 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3485 p_doorbell = (void OSAL_IOMEM *)addr;
3487 /* prepare second hw function */
3488 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3489 p_doorbell, p_params);
3491 /* in case of error, need to free the previously
3492 * initiliazed hwfn 0.
3494 if (rc != ECORE_SUCCESS) {
3495 if (p_params->b_relaxed_probe)
3496 p_params->p_relaxed_res =
3497 ECORE_HW_PREPARE_FAILED_ENG2;
3500 ecore_init_free(p_hwfn);
3501 ecore_mcp_free(p_hwfn);
3502 ecore_hw_hwfn_free(p_hwfn);
3504 DP_NOTICE(p_dev, true,
3505 "What do we need to free when VF hwfn1 init fails\n");
3514 void ecore_hw_remove(struct ecore_dev *p_dev)
3516 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3520 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3521 ECORE_OV_DRIVER_STATE_NOT_LOADED);
3523 for_each_hwfn(p_dev, i) {
3524 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3527 ecore_vf_pf_release(p_hwfn);
3531 ecore_init_free(p_hwfn);
3532 ecore_hw_hwfn_free(p_hwfn);
3533 ecore_mcp_free(p_hwfn);
3535 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3538 ecore_iov_free_hw_info(p_dev);
3541 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3542 struct ecore_chain *p_chain)
3544 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3545 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3546 struct ecore_chain_next *p_next;
3552 size = p_chain->elem_size * p_chain->usable_per_page;
3554 for (i = 0; i < p_chain->page_cnt; i++) {
3558 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3559 p_virt_next = p_next->next_virt;
3560 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3562 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3563 ECORE_CHAIN_PAGE_SIZE);
3565 p_virt = p_virt_next;
3566 p_phys = p_phys_next;
3570 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3571 struct ecore_chain *p_chain)
3573 if (!p_chain->p_virt_addr)
3576 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3577 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3580 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3581 struct ecore_chain *p_chain)
3583 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3584 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3585 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3587 if (!pp_virt_addr_tbl)
3593 for (i = 0; i < page_cnt; i++) {
3594 if (!pp_virt_addr_tbl[i])
3597 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3598 *(dma_addr_t *)p_pbl_virt,
3599 ECORE_CHAIN_PAGE_SIZE);
3601 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3604 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3606 if (!p_chain->b_external_pbl)
3607 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3608 p_chain->pbl_sp.p_phys_table, pbl_size);
3610 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3613 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3615 switch (p_chain->mode) {
3616 case ECORE_CHAIN_MODE_NEXT_PTR:
3617 ecore_chain_free_next_ptr(p_dev, p_chain);
3619 case ECORE_CHAIN_MODE_SINGLE:
3620 ecore_chain_free_single(p_dev, p_chain);
3622 case ECORE_CHAIN_MODE_PBL:
3623 ecore_chain_free_pbl(p_dev, p_chain);
3628 static enum _ecore_status_t
3629 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3630 enum ecore_chain_cnt_type cnt_type,
3631 osal_size_t elem_size, u32 page_cnt)
3633 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3635 /* The actual chain size can be larger than the maximal possible value
3636 * after rounding up the requested elements number to pages, and after
3637 * taking into acount the unusuable elements (next-ptr elements).
3638 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3639 * size/capacity fields are of a u32 type.
3641 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3642 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3643 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3644 chain_size > ECORE_U32_MAX)) {
3645 DP_NOTICE(p_dev, true,
3646 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3647 (unsigned long)chain_size);
3651 return ECORE_SUCCESS;
3654 static enum _ecore_status_t
3655 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3657 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3658 dma_addr_t p_phys = 0;
3661 for (i = 0; i < p_chain->page_cnt; i++) {
3662 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3663 ECORE_CHAIN_PAGE_SIZE);
3665 DP_NOTICE(p_dev, true,
3666 "Failed to allocate chain memory\n");
3671 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3672 ecore_chain_reset(p_chain);
3674 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3678 p_virt_prev = p_virt;
3680 /* Last page's next element should point to the beginning of the
3683 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3684 p_chain->p_virt_addr,
3685 p_chain->p_phys_addr);
3687 return ECORE_SUCCESS;
3690 static enum _ecore_status_t
3691 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3693 dma_addr_t p_phys = 0;
3694 void *p_virt = OSAL_NULL;
3696 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3698 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3702 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3703 ecore_chain_reset(p_chain);
3705 return ECORE_SUCCESS;
3708 static enum _ecore_status_t
3709 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3710 struct ecore_chain *p_chain,
3711 struct ecore_chain_ext_pbl *ext_pbl)
3713 void *p_virt = OSAL_NULL;
3714 u8 *p_pbl_virt = OSAL_NULL;
3715 void **pp_virt_addr_tbl = OSAL_NULL;
3716 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3717 u32 page_cnt = p_chain->page_cnt, size, i;
3719 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3720 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3721 if (!pp_virt_addr_tbl) {
3722 DP_NOTICE(p_dev, true,
3723 "Failed to allocate memory for the chain virtual addresses table\n");
3726 OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3728 /* The allocation of the PBL table is done with its full size, since it
3729 * is expected to be successive.
3730 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3731 * failure, since pp_virt_addr_tbl was previously allocated, and it
3732 * should be saved to allow its freeing during the error flow.
3734 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3736 if (ext_pbl == OSAL_NULL) {
3737 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3739 p_pbl_virt = ext_pbl->p_pbl_virt;
3740 p_pbl_phys = ext_pbl->p_pbl_phys;
3741 p_chain->b_external_pbl = true;
3744 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3747 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3751 for (i = 0; i < page_cnt; i++) {
3752 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3753 ECORE_CHAIN_PAGE_SIZE);
3755 DP_NOTICE(p_dev, true,
3756 "Failed to allocate chain memory\n");
3761 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3762 ecore_chain_reset(p_chain);
3765 /* Fill the PBL table with the physical address of the page */
3766 *(dma_addr_t *)p_pbl_virt = p_phys;
3767 /* Keep the virtual address of the page */
3768 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3770 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3773 return ECORE_SUCCESS;
3776 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3777 enum ecore_chain_use_mode intended_use,
3778 enum ecore_chain_mode mode,
3779 enum ecore_chain_cnt_type cnt_type,
3780 u32 num_elems, osal_size_t elem_size,
3781 struct ecore_chain *p_chain,
3782 struct ecore_chain_ext_pbl *ext_pbl)
3785 enum _ecore_status_t rc = ECORE_SUCCESS;
3787 if (mode == ECORE_CHAIN_MODE_SINGLE)
3790 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3792 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3795 DP_NOTICE(p_dev, true,
3796 "Cannot allocate a chain with the given arguments:\n"
3797 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3798 intended_use, mode, cnt_type, num_elems, elem_size);
3802 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3803 mode, cnt_type, p_dev->dp_ctx);
3806 case ECORE_CHAIN_MODE_NEXT_PTR:
3807 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3809 case ECORE_CHAIN_MODE_SINGLE:
3810 rc = ecore_chain_alloc_single(p_dev, p_chain);
3812 case ECORE_CHAIN_MODE_PBL:
3813 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3819 return ECORE_SUCCESS;
3822 ecore_chain_free(p_dev, p_chain);
3826 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3827 u16 src_id, u16 *dst_id)
3829 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3832 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3833 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3834 DP_NOTICE(p_hwfn, true,
3835 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3841 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3843 return ECORE_SUCCESS;
3846 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3847 u8 src_id, u8 *dst_id)
3849 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3852 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3853 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3854 DP_NOTICE(p_hwfn, true,
3855 "vport id [%d] is not valid, available indices [%d - %d]\n",
3861 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3863 return ECORE_SUCCESS;
3866 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3867 u8 src_id, u8 *dst_id)
3869 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3872 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3873 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3874 DP_NOTICE(p_hwfn, true,
3875 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3881 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3883 return ECORE_SUCCESS;
3886 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3887 struct ecore_ptt *p_ptt,
3893 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3894 return ECORE_SUCCESS;
3896 high = p_filter[1] | (p_filter[0] << 8);
3897 low = p_filter[5] | (p_filter[4] << 8) |
3898 (p_filter[3] << 16) | (p_filter[2] << 24);
3900 /* Find a free entry and utilize it */
3901 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3902 en = ecore_rd(p_hwfn, p_ptt,
3903 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3906 ecore_wr(p_hwfn, p_ptt,
3907 NIG_REG_LLH_FUNC_FILTER_VALUE +
3908 2 * i * sizeof(u32), low);
3909 ecore_wr(p_hwfn, p_ptt,
3910 NIG_REG_LLH_FUNC_FILTER_VALUE +
3911 (2 * i + 1) * sizeof(u32), high);
3912 ecore_wr(p_hwfn, p_ptt,
3913 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3914 ecore_wr(p_hwfn, p_ptt,
3915 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3916 i * sizeof(u32), 0);
3917 ecore_wr(p_hwfn, p_ptt,
3918 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3921 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3922 DP_NOTICE(p_hwfn, false,
3923 "Failed to find an empty LLH filter to utilize\n");
3927 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3928 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3929 p_filter[0], p_filter[1], p_filter[2],
3930 p_filter[3], p_filter[4], p_filter[5], i);
3932 return ECORE_SUCCESS;
3935 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3936 struct ecore_ptt *p_ptt, u8 *p_filter)
3941 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3944 high = p_filter[1] | (p_filter[0] << 8);
3945 low = p_filter[5] | (p_filter[4] << 8) |
3946 (p_filter[3] << 16) | (p_filter[2] << 24);
3948 /* Find the entry and clean it */
3949 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3950 if (ecore_rd(p_hwfn, p_ptt,
3951 NIG_REG_LLH_FUNC_FILTER_VALUE +
3952 2 * i * sizeof(u32)) != low)
3954 if (ecore_rd(p_hwfn, p_ptt,
3955 NIG_REG_LLH_FUNC_FILTER_VALUE +
3956 (2 * i + 1) * sizeof(u32)) != high)
3959 ecore_wr(p_hwfn, p_ptt,
3960 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3961 ecore_wr(p_hwfn, p_ptt,
3962 NIG_REG_LLH_FUNC_FILTER_VALUE +
3963 2 * i * sizeof(u32), 0);
3964 ecore_wr(p_hwfn, p_ptt,
3965 NIG_REG_LLH_FUNC_FILTER_VALUE +
3966 (2 * i + 1) * sizeof(u32), 0);
3969 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3970 DP_NOTICE(p_hwfn, false,
3971 "Tried to remove a non-configured filter\n");
3974 enum _ecore_status_t
3975 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3976 struct ecore_ptt *p_ptt,
3977 u16 source_port_or_eth_type,
3979 enum ecore_llh_port_filter_type_t type)
3984 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3985 return ECORE_SUCCESS;
3990 case ECORE_LLH_FILTER_ETHERTYPE:
3991 high = source_port_or_eth_type;
3993 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3994 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3995 low = source_port_or_eth_type << 16;
3997 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3998 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4001 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4002 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4003 low = (source_port_or_eth_type << 16) | dest_port;
4006 DP_NOTICE(p_hwfn, true,
4007 "Non valid LLH protocol filter type %d\n", type);
4010 /* Find a free entry and utilize it */
4011 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4012 en = ecore_rd(p_hwfn, p_ptt,
4013 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4016 ecore_wr(p_hwfn, p_ptt,
4017 NIG_REG_LLH_FUNC_FILTER_VALUE +
4018 2 * i * sizeof(u32), low);
4019 ecore_wr(p_hwfn, p_ptt,
4020 NIG_REG_LLH_FUNC_FILTER_VALUE +
4021 (2 * i + 1) * sizeof(u32), high);
4022 ecore_wr(p_hwfn, p_ptt,
4023 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4024 ecore_wr(p_hwfn, p_ptt,
4025 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4026 i * sizeof(u32), 1 << type);
4027 ecore_wr(p_hwfn, p_ptt,
4028 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4031 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4032 DP_NOTICE(p_hwfn, false,
4033 "Failed to find an empty LLH filter to utilize\n");
4034 return ECORE_NORESOURCES;
4037 case ECORE_LLH_FILTER_ETHERTYPE:
4038 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4039 "ETH type %x is added at %d\n",
4040 source_port_or_eth_type, i);
4042 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4043 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4044 "TCP src port %x is added at %d\n",
4045 source_port_or_eth_type, i);
4047 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4048 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4049 "UDP src port %x is added at %d\n",
4050 source_port_or_eth_type, i);
4052 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4053 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4054 "TCP dst port %x is added at %d\n", dest_port, i);
4056 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4057 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4058 "UDP dst port %x is added at %d\n", dest_port, i);
4060 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4061 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4062 "TCP src/dst ports %x/%x are added at %d\n",
4063 source_port_or_eth_type, dest_port, i);
4065 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4066 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4067 "UDP src/dst ports %x/%x are added at %d\n",
4068 source_port_or_eth_type, dest_port, i);
4071 return ECORE_SUCCESS;
4075 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4076 struct ecore_ptt *p_ptt,
4077 u16 source_port_or_eth_type,
4079 enum ecore_llh_port_filter_type_t type)
4084 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4090 case ECORE_LLH_FILTER_ETHERTYPE:
4091 high = source_port_or_eth_type;
4093 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4094 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4095 low = source_port_or_eth_type << 16;
4097 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4098 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4101 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4102 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4103 low = (source_port_or_eth_type << 16) | dest_port;
4106 DP_NOTICE(p_hwfn, true,
4107 "Non valid LLH protocol filter type %d\n", type);
4111 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4112 if (!ecore_rd(p_hwfn, p_ptt,
4113 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4115 if (!ecore_rd(p_hwfn, p_ptt,
4116 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4118 if (!(ecore_rd(p_hwfn, p_ptt,
4119 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4120 i * sizeof(u32)) & (1 << type)))
4122 if (ecore_rd(p_hwfn, p_ptt,
4123 NIG_REG_LLH_FUNC_FILTER_VALUE +
4124 2 * i * sizeof(u32)) != low)
4126 if (ecore_rd(p_hwfn, p_ptt,
4127 NIG_REG_LLH_FUNC_FILTER_VALUE +
4128 (2 * i + 1) * sizeof(u32)) != high)
4131 ecore_wr(p_hwfn, p_ptt,
4132 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4133 ecore_wr(p_hwfn, p_ptt,
4134 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4135 ecore_wr(p_hwfn, p_ptt,
4136 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4137 i * sizeof(u32), 0);
4138 ecore_wr(p_hwfn, p_ptt,
4139 NIG_REG_LLH_FUNC_FILTER_VALUE +
4140 2 * i * sizeof(u32), 0);
4141 ecore_wr(p_hwfn, p_ptt,
4142 NIG_REG_LLH_FUNC_FILTER_VALUE +
4143 (2 * i + 1) * sizeof(u32), 0);
4147 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4148 DP_NOTICE(p_hwfn, false,
4149 "Tried to remove a non-configured filter\n");
4152 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4153 struct ecore_ptt *p_ptt)
4157 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4160 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4161 ecore_wr(p_hwfn, p_ptt,
4162 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4163 ecore_wr(p_hwfn, p_ptt,
4164 NIG_REG_LLH_FUNC_FILTER_VALUE +
4165 2 * i * sizeof(u32), 0);
4166 ecore_wr(p_hwfn, p_ptt,
4167 NIG_REG_LLH_FUNC_FILTER_VALUE +
4168 (2 * i + 1) * sizeof(u32), 0);
4172 enum _ecore_status_t
4173 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4174 struct ecore_ptt *p_ptt)
4176 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4177 ecore_wr(p_hwfn, p_ptt,
4178 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4179 1 << p_hwfn->abs_pf_id / 2);
4180 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4181 return ECORE_SUCCESS;
4184 DP_NOTICE(p_hwfn, false,
4185 "This function can't be set as default\n");
4189 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4190 struct ecore_ptt *p_ptt,
4191 u32 hw_addr, void *p_eth_qzone,
4192 osal_size_t eth_qzone_size,
4195 struct coalescing_timeset *p_coal_timeset;
4197 if (IS_VF(p_hwfn->p_dev)) {
4198 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
4202 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4203 DP_NOTICE(p_hwfn, true,
4204 "Coalescing configuration not enabled\n");
4208 p_coal_timeset = p_eth_qzone;
4209 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4210 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4211 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4212 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4214 return ECORE_SUCCESS;
4217 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4218 struct ecore_ptt *p_ptt,
4219 u16 coalesce, u16 qid, u16 sb_id)
4221 struct ustorm_eth_queue_zone eth_qzone;
4222 u8 timeset, timer_res;
4225 enum _ecore_status_t rc;
4227 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4228 if (coalesce <= 0x7F) {
4230 } else if (coalesce <= 0xFF) {
4232 } else if (coalesce <= 0x1FF) {
4235 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4238 timeset = (u8)(coalesce >> timer_res);
4240 rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4241 if (rc != ECORE_SUCCESS)
4244 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
4245 if (rc != ECORE_SUCCESS)
4248 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4250 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4251 sizeof(struct ustorm_eth_queue_zone), timeset);
4252 if (rc != ECORE_SUCCESS)
4255 p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
4260 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4261 struct ecore_ptt *p_ptt,
4262 u16 coalesce, u16 qid, u16 sb_id)
4264 struct xstorm_eth_queue_zone eth_qzone;
4265 u8 timeset, timer_res;
4268 enum _ecore_status_t rc;
4270 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4271 if (coalesce <= 0x7F) {
4273 } else if (coalesce <= 0xFF) {
4275 } else if (coalesce <= 0x1FF) {
4278 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4282 timeset = (u8)(coalesce >> timer_res);
4284 rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4285 if (rc != ECORE_SUCCESS)
4288 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
4289 if (rc != ECORE_SUCCESS)
4292 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4294 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4295 sizeof(struct xstorm_eth_queue_zone), timeset);
4296 if (rc != ECORE_SUCCESS)
4299 p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
4304 /* Calculate final WFQ values for all vports and configure it.
4305 * After this configuration each vport must have
4306 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4308 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4309 struct ecore_ptt *p_ptt,
4312 struct init_qm_vport_params *vport_params;
4315 vport_params = p_hwfn->qm_info.qm_vport_params;
4317 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4318 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4320 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4322 ecore_init_vport_wfq(p_hwfn, p_ptt,
4323 vport_params[i].first_tx_pq_id,
4324 vport_params[i].vport_wfq);
4329 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4333 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4334 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4337 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4338 struct ecore_ptt *p_ptt,
4341 struct init_qm_vport_params *vport_params;
4344 vport_params = p_hwfn->qm_info.qm_vport_params;
4346 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4347 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4348 ecore_init_vport_wfq(p_hwfn, p_ptt,
4349 vport_params[i].first_tx_pq_id,
4350 vport_params[i].vport_wfq);
4354 /* This function performs several validations for WFQ
4355 * configuration and required min rate for a given vport
4356 * 1. req_rate must be greater than one percent of min_pf_rate.
4357 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4358 * rates to get less than one percent of min_pf_rate.
4359 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4361 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4362 u16 vport_id, u32 req_rate,
4365 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4366 int non_requested_count = 0, req_count = 0, i, num_vports;
4368 num_vports = p_hwfn->qm_info.num_vports;
4370 /* Accounting for the vports which are configured for WFQ explicitly */
4372 for (i = 0; i < num_vports; i++) {
4375 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4377 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4378 total_req_min_rate += tmp_speed;
4382 /* Include current vport data as well */
4384 total_req_min_rate += req_rate;
4385 non_requested_count = num_vports - req_count;
4387 /* validate possible error cases */
4388 if (req_rate > min_pf_rate) {
4389 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4390 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4391 vport_id, req_rate, min_pf_rate);
4395 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4396 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4397 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4398 vport_id, req_rate, min_pf_rate);
4402 /* TBD - for number of vports greater than 100 */
4403 if (num_vports > ECORE_WFQ_UNIT) {
4404 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4405 "Number of vports is greater than %d\n",
4410 if (total_req_min_rate > min_pf_rate) {
4411 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4412 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4413 total_req_min_rate, min_pf_rate);
4417 /* Data left for non requested vports */
4418 total_left_rate = min_pf_rate - total_req_min_rate;
4419 left_rate_per_vp = total_left_rate / non_requested_count;
4421 /* validate if non requested get < 1% of min bw */
4422 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4423 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4424 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4425 left_rate_per_vp, min_pf_rate);
4429 /* now req_rate for given vport passes all scenarios.
4430 * assign final wfq rates to all vports.
4432 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4433 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4435 for (i = 0; i < num_vports; i++) {
4436 if (p_hwfn->qm_info.wfq_data[i].configured)
4439 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4442 return ECORE_SUCCESS;
4445 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4446 struct ecore_ptt *p_ptt,
4447 u16 vp_id, u32 rate)
4449 struct ecore_mcp_link_state *p_link;
4450 int rc = ECORE_SUCCESS;
4452 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4454 if (!p_link->min_pf_rate) {
4455 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4456 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4460 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4462 if (rc == ECORE_SUCCESS)
4463 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4464 p_link->min_pf_rate);
4466 DP_NOTICE(p_hwfn, false,
4467 "Validation failed while configuring min rate\n");
4472 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4473 struct ecore_ptt *p_ptt,
4476 bool use_wfq = false;
4477 int rc = ECORE_SUCCESS;
4480 /* Validate all pre configured vports for wfq */
4481 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4484 if (!p_hwfn->qm_info.wfq_data[i].configured)
4487 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4490 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4491 if (rc != ECORE_SUCCESS) {
4492 DP_NOTICE(p_hwfn, false,
4493 "WFQ validation failed while configuring min rate\n");
4498 if (rc == ECORE_SUCCESS && use_wfq)
4499 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4501 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4506 /* Main API for ecore clients to configure vport min rate.
4507 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4508 * rate - Speed in Mbps needs to be assigned to a given vport.
4510 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4512 int i, rc = ECORE_INVAL;
4514 /* TBD - for multiple hardware functions - that is 100 gig */
4515 if (p_dev->num_hwfns > 1) {
4516 DP_NOTICE(p_dev, false,
4517 "WFQ configuration is not supported for this device\n");
4521 for_each_hwfn(p_dev, i) {
4522 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4523 struct ecore_ptt *p_ptt;
4525 p_ptt = ecore_ptt_acquire(p_hwfn);
4527 return ECORE_TIMEOUT;
4529 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4531 if (rc != ECORE_SUCCESS) {
4532 ecore_ptt_release(p_hwfn, p_ptt);
4536 ecore_ptt_release(p_hwfn, p_ptt);
4542 /* API to configure WFQ from mcp link change */
4543 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4548 /* TBD - for multiple hardware functions - that is 100 gig */
4549 if (p_dev->num_hwfns > 1) {
4550 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4551 "WFQ configuration is not supported for this device\n");
4555 for_each_hwfn(p_dev, i) {
4556 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4558 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4564 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4565 struct ecore_ptt *p_ptt,
4566 struct ecore_mcp_link_state *p_link,
4569 int rc = ECORE_SUCCESS;
4571 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4573 if (!p_link->line_speed && (max_bw != 100))
4576 p_link->speed = (p_link->line_speed * max_bw) / 100;
4577 p_hwfn->qm_info.pf_rl = p_link->speed;
4579 /* Since the limiter also affects Tx-switched traffic, we don't want it
4580 * to limit such traffic in case there's no actual limit.
4581 * In that case, set limit to imaginary high boundary.
4584 p_hwfn->qm_info.pf_rl = 100000;
4586 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4587 p_hwfn->qm_info.pf_rl);
4589 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4590 "Configured MAX bandwidth to be %08x Mb/sec\n",
4596 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4597 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4599 int i, rc = ECORE_INVAL;
4601 if (max_bw < 1 || max_bw > 100) {
4602 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4606 for_each_hwfn(p_dev, i) {
4607 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4608 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4609 struct ecore_mcp_link_state *p_link;
4610 struct ecore_ptt *p_ptt;
4612 p_link = &p_lead->mcp_info->link_output;
4614 p_ptt = ecore_ptt_acquire(p_hwfn);
4616 return ECORE_TIMEOUT;
4618 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4621 ecore_ptt_release(p_hwfn, p_ptt);
4623 if (rc != ECORE_SUCCESS)
4630 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4631 struct ecore_ptt *p_ptt,
4632 struct ecore_mcp_link_state *p_link,
4635 int rc = ECORE_SUCCESS;
4637 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4638 p_hwfn->qm_info.pf_wfq = min_bw;
4640 if (!p_link->line_speed)
4643 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4645 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4647 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4648 "Configured MIN bandwidth to be %d Mb/sec\n",
4649 p_link->min_pf_rate);
4654 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4655 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4657 int i, rc = ECORE_INVAL;
4659 if (min_bw < 1 || min_bw > 100) {
4660 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4664 for_each_hwfn(p_dev, i) {
4665 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4666 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4667 struct ecore_mcp_link_state *p_link;
4668 struct ecore_ptt *p_ptt;
4670 p_link = &p_lead->mcp_info->link_output;
4672 p_ptt = ecore_ptt_acquire(p_hwfn);
4674 return ECORE_TIMEOUT;
4676 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4678 if (rc != ECORE_SUCCESS) {
4679 ecore_ptt_release(p_hwfn, p_ptt);
4683 if (p_link->min_pf_rate) {
4684 u32 min_rate = p_link->min_pf_rate;
4686 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4691 ecore_ptt_release(p_hwfn, p_ptt);
4697 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4699 struct ecore_mcp_link_state *p_link;
4701 p_link = &p_hwfn->mcp_info->link_output;
4703 if (p_link->min_pf_rate)
4704 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4705 p_link->min_pf_rate);
4707 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4708 sizeof(*p_hwfn->qm_info.wfq_data) *
4709 p_hwfn->qm_info.num_vports);
4712 int ecore_device_num_engines(struct ecore_dev *p_dev)
4714 return ECORE_IS_BB(p_dev) ? 2 : 1;
4717 int ecore_device_num_ports(struct ecore_dev *p_dev)
4719 /* in CMT always only one port */
4720 if (p_dev->num_hwfns > 1)
4723 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4726 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4731 ((u8 *)fw_msb)[0] = mac[1];
4732 ((u8 *)fw_msb)[1] = mac[0];
4733 ((u8 *)fw_mid)[0] = mac[3];
4734 ((u8 *)fw_mid)[1] = mac[2];
4735 ((u8 *)fw_lsb)[0] = mac[5];
4736 ((u8 *)fw_lsb)[1] = mac[4];