drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dcbx.h"
  32 #include "ecore_l2.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /******************** Doorbell Recovery *******************/
  45 /* The doorbell recovery mechanism consists of a list of entries which represent
  46  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  47  * entity needs to register with the mechanism and provide the parameters
  48  * describing it's doorbell, including a location where last used doorbell data
  49  * can be found. The doorbell execute function will traverse the list and
  50  * doorbell all of the registered entries.
  51  */
  52 struct ecore_db_recovery_entry {
  53         osal_list_entry_t       list_entry;
  54         void OSAL_IOMEM         *db_addr;
  55         void                    *db_data;
  56         enum ecore_db_rec_width db_width;
  57         enum ecore_db_rec_space db_space;
  58         u8                      hwfn_idx;
  59 };
  60
  61 /* display a single doorbell recovery entry */
  62 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  63                                 struct ecore_db_recovery_entry *db_entry,
  64                                 const char *action)
  65 {
  66         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  67                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  68                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  69                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  70                    db_entry->hwfn_idx);
  71 }
  72
  73 /* doorbell address sanity (address within doorbell bar range) */
  74 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  75                          void *db_data)
  76 {
  77         /* make sure doorbell address  is within the doorbell bar */
  78         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  79                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  80                 OSAL_WARN(true,
  81                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  82                           db_addr, p_dev->doorbells,
  83                           (u8 *)p_dev->doorbells + p_dev->db_size);
  84                 return false;
  85         }
  86
  87         /* make sure doorbell data pointer is not null */
  88         if (!db_data) {
  89                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  90                 return false;
  91         }
  92
  93         return true;
  94 }
  95
  96 /* find hwfn according to the doorbell address */
  97 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
  98                                           void OSAL_IOMEM *db_addr)
  99 {
 100         struct ecore_hwfn *p_hwfn;
 101
 102         /* In CMT doorbell bar is split down the middle between engine 0 and
 103          * enigne 1
 104          */
 105         if (ECORE_IS_CMT(p_dev))
 106                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 107                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 108         else
 109                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 110
 111         return p_hwfn;
 112 }
 113
 114 /* add a new entry to the doorbell recovery mechanism */
 115 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 116                                            void OSAL_IOMEM *db_addr,
 117                                            void *db_data,
 118                                            enum ecore_db_rec_width db_width,
 119                                            enum ecore_db_rec_space db_space)
 120 {
 121         struct ecore_db_recovery_entry *db_entry;
 122         struct ecore_hwfn *p_hwfn;
 123
 124         /* shortcircuit VFs, for now */
 125         if (IS_VF(p_dev)) {
 126                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 127                 return ECORE_SUCCESS;
 128         }
 129
 130         /* sanitize doorbell address */
 131         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 132                 return ECORE_INVAL;
 133
 134         /* obtain hwfn from doorbell address */
 135         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 136
 137         /* create entry */
 138         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 139         if (!db_entry) {
 140                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 141                 return ECORE_NOMEM;
 142         }
 143
 144         /* populate entry */
 145         db_entry->db_addr = db_addr;
 146         db_entry->db_data = db_data;
 147         db_entry->db_width = db_width;
 148         db_entry->db_space = db_space;
 149         db_entry->hwfn_idx = p_hwfn->my_id;
 150
 151         /* display */
 152         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 153
 154         /* protect the list */
 155         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 156         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 157                             &p_hwfn->db_recovery_info.list);
 158         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 159
 160         return ECORE_SUCCESS;
 161 }
 162
 163 /* remove an entry from the doorbell recovery mechanism */
 164 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 165                                            void OSAL_IOMEM *db_addr,
 166                                            void *db_data)
 167 {
 168         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 169         enum _ecore_status_t rc = ECORE_INVAL;
 170         struct ecore_hwfn *p_hwfn;
 171
 172         /* shortcircuit VFs, for now */
 173         if (IS_VF(p_dev)) {
 174                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 175                 return ECORE_SUCCESS;
 176         }
 177
 178         /* sanitize doorbell address */
 179         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 180                 return ECORE_INVAL;
 181
 182         /* obtain hwfn from doorbell address */
 183         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 184
 185         /* protect the list */
 186         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 187         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 188                                  &p_hwfn->db_recovery_info.list,
 189                                  list_entry,
 190                                  struct ecore_db_recovery_entry) {
 191                 /* search according to db_data addr since db_addr is not unique
 192                  * (roce)
 193                  */
 194                 if (db_entry->db_data == db_data) {
 195                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 196                                                    "Deleting");
 197                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 198                                                &p_hwfn->db_recovery_info.list);
 199                         rc = ECORE_SUCCESS;
 200                         break;
 201                 }
 202         }
 203
 204         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 205
 206         if (rc == ECORE_INVAL)
 207                 /*OSAL_WARN(true,*/
 208                 DP_NOTICE(p_hwfn, false,
 209                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 210                           db_data, db_addr);
 211         else
 212                 OSAL_FREE(p_dev, db_entry);
 213
 214         return rc;
 215 }
 216
 217 /* initialize the doorbell recovery mechanism */
 218 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 219 {
 220         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 221
 222         /* make sure db_size was set in p_dev */
 223         if (!p_hwfn->p_dev->db_size) {
 224                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 225                 return ECORE_INVAL;
 226         }
 227
 228         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 229 #ifdef CONFIG_ECORE_LOCK_ALLOC
 230         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
 231 #endif
 232         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 233         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 234
 235         return ECORE_SUCCESS;
 236 }
 237
 238 /* destroy the doorbell recovery mechanism */
 239 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 240 {
 241         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 242
 243         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 244         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 245                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 246                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 247                         db_entry = OSAL_LIST_FIRST_ENTRY(
 248                                                 &p_hwfn->db_recovery_info.list,
 249                                                 struct ecore_db_recovery_entry,
 250                                                 list_entry);
 251                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 252                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 253                                                &p_hwfn->db_recovery_info.list);
 254                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 255                 }
 256         }
 257 #ifdef CONFIG_ECORE_LOCK_ALLOC
 258         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 259 #endif
 260         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 261 }
 262
 263 /* print the content of the doorbell recovery mechanism */
 264 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 265 {
 266         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 267
 268         DP_NOTICE(p_hwfn, false,
 269                   "Dispalying doorbell recovery database. Counter was %d\n",
 270                   p_hwfn->db_recovery_info.db_recovery_counter);
 271
 272         /* protect the list */
 273         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 274         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 275                                  &p_hwfn->db_recovery_info.list,
 276                                  list_entry,
 277                                  struct ecore_db_recovery_entry) {
 278                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 279         }
 280
 281         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 282 }
 283
 284 /* ring the doorbell of a single doorbell recovery entry */
 285 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 286                             struct ecore_db_recovery_entry *db_entry,
 287                             enum ecore_db_rec_exec db_exec)
 288 {
 289         /* Print according to width */
 290         if (db_entry->db_width == DB_REC_WIDTH_32B)
 291                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 292                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 293                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 294         else
 295                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 296                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 297                            db_entry->db_addr,
 298                            *(unsigned long *)(db_entry->db_data));
 299
 300         /* Sanity */
 301         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 302                                  db_entry->db_data))
 303                 return;
 304
 305         /* Flush the write combined buffer. Since there are multiple doorbelling
 306          * entities using the same address, if we don't flush, a transaction
 307          * could be lost.
 308          */
 309         OSAL_WMB(p_hwfn->p_dev);
 310
 311         /* Ring the doorbell */
 312         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 313                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 314                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 315                                       *(u32 *)(db_entry->db_data));
 316                 else
 317                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 318                                         *(u64 *)(db_entry->db_data));
 319         }
 320
 321         /* Flush the write combined buffer. Next doorbell may come from a
 322          * different entity to the same address...
 323          */
 324         OSAL_WMB(p_hwfn->p_dev);
 325 }
 326
 327 /* traverse the doorbell recovery entry list and ring all the doorbells */
 328 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 329                                enum ecore_db_rec_exec db_exec)
 330 {
 331         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 332
 333         if (db_exec != DB_REC_ONCE) {
 334                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 335                           p_hwfn->db_recovery_info.db_recovery_counter);
 336
 337                 /* track amount of times recovery was executed */
 338                 p_hwfn->db_recovery_info.db_recovery_counter++;
 339         }
 340
 341         /* protect the list */
 342         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 343         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 344                                  &p_hwfn->db_recovery_info.list,
 345                                  list_entry,
 346                                  struct ecore_db_recovery_entry) {
 347                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 348                 if (db_exec == DB_REC_ONCE)
 349                         break;
 350         }
 351
 352         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 353 }
 354 /******************** Doorbell Recovery end ****************/
 355
 356 /* Configurable */
 357 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
 358                                          * load the driver. The number was
 359                                          * arbitrarily set.
 360                                          */
 361
 362 /* Derived */
 363 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
 364
 365 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
 366                              struct ecore_ptt *p_ptt,
 367                              enum BAR_ID bar_id)
 368 {
 369         u32 bar_reg = (bar_id == BAR_ID_0 ?
 370                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 371         u32 val;
 372
 373         if (IS_VF(p_hwfn->p_dev))
 374                 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
 375
 376         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
 377         if (val)
 378                 return 1 << (val + 15);
 379
 380         /* The above registers were updated in the past only in CMT mode. Since
 381          * they were found to be useful MFW started updating them from 8.7.7.0.
 382          * In older MFW versions they are set to 0 which means disabled.
 383          */
 384         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
 385                 DP_INFO(p_hwfn,
 386                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 387                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 388         } else {
 389                 DP_INFO(p_hwfn,
 390                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 391                 val = 512 * 1024;
 392         }
 393
 394         return val;
 395 }
 396
 397 void ecore_init_dp(struct ecore_dev *p_dev,
 398                    u32 dp_module, u8 dp_level, void *dp_ctx)
 399 {
 400         u32 i;
 401
 402         p_dev->dp_level = dp_level;
 403         p_dev->dp_module = dp_module;
 404         p_dev->dp_ctx = dp_ctx;
 405         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 406                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 407
 408                 p_hwfn->dp_level = dp_level;
 409                 p_hwfn->dp_module = dp_module;
 410                 p_hwfn->dp_ctx = dp_ctx;
 411         }
 412 }
 413
 414 void ecore_init_struct(struct ecore_dev *p_dev)
 415 {
 416         u8 i;
 417
 418         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 419                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 420
 421                 p_hwfn->p_dev = p_dev;
 422                 p_hwfn->my_id = i;
 423                 p_hwfn->b_active = false;
 424
 425 #ifdef CONFIG_ECORE_LOCK_ALLOC
 426                 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock);
 427 #endif
 428                 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
 429         }
 430
 431         /* hwfn 0 is always active */
 432         p_dev->hwfns[0].b_active = true;
 433
 434         /* set the default cache alignment to 128 (may be overridden later) */
 435         p_dev->cache_shift = 7;
 436 }
 437
 438 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 439 {
 440         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 441
 442         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 443         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 444         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 445         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 446 }
 447
 448 void ecore_resc_free(struct ecore_dev *p_dev)
 449 {
 450         int i;
 451
 452         if (IS_VF(p_dev)) {
 453                 for_each_hwfn(p_dev, i)
 454                         ecore_l2_free(&p_dev->hwfns[i]);
 455                 return;
 456         }
 457
 458         OSAL_FREE(p_dev, p_dev->fw_data);
 459
 460         OSAL_FREE(p_dev, p_dev->reset_stats);
 461
 462         for_each_hwfn(p_dev, i) {
 463                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 464
 465                 ecore_cxt_mngr_free(p_hwfn);
 466                 ecore_qm_info_free(p_hwfn);
 467                 ecore_spq_free(p_hwfn);
 468                 ecore_eq_free(p_hwfn);
 469                 ecore_consq_free(p_hwfn);
 470                 ecore_int_free(p_hwfn);
 471                 ecore_iov_free(p_hwfn);
 472                 ecore_l2_free(p_hwfn);
 473                 ecore_dmae_info_free(p_hwfn);
 474                 ecore_dcbx_info_free(p_hwfn);
 475                 /* @@@TBD Flush work-queue ? */
 476
 477                 /* destroy doorbell recovery mechanism */
 478                 ecore_db_recovery_teardown(p_hwfn);
 479         }
 480 }
 481
 482 /******************** QM initialization *******************/
 483
 484 /* bitmaps for indicating active traffic classes.
 485  * Special case for Arrowhead 4 port
 486  */
 487 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 488 #define ACTIVE_TCS_BMAP 0x9f
 489 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 490 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 491
 492 /* determines the physical queue flags for a given PF. */
 493 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 494 {
 495         u32 flags;
 496
 497         /* common flags */
 498         flags = PQ_FLAGS_LB;
 499
 500         /* feature flags */
 501         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 502                 flags |= PQ_FLAGS_VFS;
 503
 504         /* protocol flags */
 505         switch (p_hwfn->hw_info.personality) {
 506         case ECORE_PCI_ETH:
 507                 flags |= PQ_FLAGS_MCOS;
 508                 break;
 509         case ECORE_PCI_FCOE:
 510                 flags |= PQ_FLAGS_OFLD;
 511                 break;
 512         case ECORE_PCI_ISCSI:
 513                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 514                 break;
 515         case ECORE_PCI_ETH_ROCE:
 516                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 517                 break;
 518         case ECORE_PCI_ETH_IWARP:
 519                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 520                          PQ_FLAGS_OFLD;
 521                 break;
 522         default:
 523                 DP_ERR(p_hwfn, "unknown personality %d\n",
 524                        p_hwfn->hw_info.personality);
 525                 return 0;
 526         }
 527         return flags;
 528 }
 529
 530 /* Getters for resource amounts necessary for qm initialization */
 531 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 532 {
 533         return p_hwfn->hw_info.num_hw_tc;
 534 }
 535
 536 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 537 {
 538         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 539                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 540 }
 541
 542 #define NUM_DEFAULT_RLS 1
 543
 544 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 545 {
 546         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 547
 548         /* @DPDK */
 549         /* num RLs can't exceed resource amount of rls or vports or the
 550          * dcqcn qps
 551          */
 552         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 553                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 554
 555         /* make sure after we reserve the default and VF rls we'll have
 556          * something left
 557          */
 558         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 559                 DP_NOTICE(p_hwfn, false,
 560                           "no rate limiters left for PF rate limiting"
 561                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 562                 return 0;
 563         }
 564
 565         /* subtract rls necessary for VFs and one default one for the PF */
 566         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 567
 568         return num_pf_rls;
 569 }
 570
 571 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 572 {
 573         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 574
 575         /* all pqs share the same vport (hence the 1 below), except for vfs
 576          * and pf_rl pqs
 577          */
 578         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 579                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 580                (!!(PQ_FLAGS_VFS & pq_flags)) *
 581                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 582 }
 583
 584 /* calc amount of PQs according to the requested flags */
 585 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 586 {
 587         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 588
 589         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 590                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 591                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 592                 ecore_init_qm_get_num_tcs(p_hwfn) +
 593                (!!(PQ_FLAGS_LB & pq_flags)) +
 594                (!!(PQ_FLAGS_OOO & pq_flags)) +
 595                (!!(PQ_FLAGS_ACK & pq_flags)) +
 596                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 597                (!!(PQ_FLAGS_VFS & pq_flags)) *
 598                 ecore_init_qm_get_num_vfs(p_hwfn);
 599 }
 600
 601 /* initialize the top level QM params */
 602 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 603 {
 604         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 605         bool four_port;
 606
 607         /* pq and vport bases for this PF */
 608         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 609         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 610
 611         /* rate limiting and weighted fair queueing are always enabled */
 612         qm_info->vport_rl_en = 1;
 613         qm_info->vport_wfq_en = 1;
 614
 615         /* TC config is different for AH 4 port */
 616         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 617
 618         /* in AH 4 port we have fewer TCs per port */
 619         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 620                                                      NUM_OF_PHYS_TCS;
 621
 622         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 623          * 4 otherwise
 624          */
 625         if (!qm_info->ooo_tc)
 626                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 627                                               DCBX_TCP_OOO_TC;
 628 }
 629
 630 /* initialize qm vport params */
 631 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 632 {
 633         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 634         u8 i;
 635
 636         /* all vports participate in weighted fair queueing */
 637         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 638                 qm_info->qm_vport_params[i].vport_wfq = 1;
 639 }
 640
 641 /* initialize qm port params */
 642 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 643 {
 644         /* Initialize qm port parameters */
 645         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
 646
 647         /* indicate how ooo and high pri traffic is dealt with */
 648         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 649                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 650
 651         for (i = 0; i < num_ports; i++) {
 652                 struct init_qm_port_params *p_qm_port =
 653                         &p_hwfn->qm_info.qm_port_params[i];
 654
 655                 p_qm_port->active = 1;
 656                 p_qm_port->active_phys_tcs = active_phys_tcs;
 657                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
 658                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 659         }
 660 }
 661
 662 /* Reset the params which must be reset for qm init. QM init may be called as
 663  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 664  * params may be affected by the init but would simply recalculate to the same
 665  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 666  * affected as these amounts stay the same.
 667  */
 668 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 669 {
 670         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 671
 672         qm_info->num_pqs = 0;
 673         qm_info->num_vports = 0;
 674         qm_info->num_pf_rls = 0;
 675         qm_info->num_vf_pqs = 0;
 676         qm_info->first_vf_pq = 0;
 677         qm_info->first_mcos_pq = 0;
 678         qm_info->first_rl_pq = 0;
 679 }
 680
 681 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 682 {
 683         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 684
 685         qm_info->num_vports++;
 686
 687         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 688                 DP_ERR(p_hwfn,
 689                        "vport overflow! qm_info->num_vports %d,"
 690                        " qm_init_get_num_vports() %d\n",
 691                        qm_info->num_vports,
 692                        ecore_init_qm_get_num_vports(p_hwfn));
 693 }
 694
 695 /* initialize a single pq and manage qm_info resources accounting.
 696  * The pq_init_flags param determines whether the PQ is rate limited
 697  * (for VF or PF)
 698  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 699  * shared)
 700  */
 701
 702 /* flags for pq init */
 703 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 704 #define PQ_INIT_PF_RL           (1 << 1)
 705 #define PQ_INIT_VF_RL           (1 << 2)
 706
 707 /* defines for pq init */
 708 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 709 #define PQ_INIT_DEFAULT_TC              0
 710 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 711
 712 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 713                              struct ecore_qm_info *qm_info,
 714                              u8 tc, u32 pq_init_flags)
 715 {
 716         u16 pq_idx = qm_info->num_pqs, max_pq =
 717                                         ecore_init_qm_get_num_pqs(p_hwfn);
 718
 719         if (pq_idx > max_pq)
 720                 DP_ERR(p_hwfn,
 721                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 722
 723         /* init pq params */
 724         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
 725         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 726                                                  qm_info->num_vports;
 727         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 728         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 729         qm_info->qm_pq_params[pq_idx].rl_valid =
 730                 (pq_init_flags & PQ_INIT_PF_RL ||
 731                  pq_init_flags & PQ_INIT_VF_RL);
 732
 733         /* qm params accounting */
 734         qm_info->num_pqs++;
 735         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 736                 qm_info->num_vports++;
 737
 738         if (pq_init_flags & PQ_INIT_PF_RL)
 739                 qm_info->num_pf_rls++;
 740
 741         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 742                 DP_ERR(p_hwfn,
 743                        "vport overflow! qm_info->num_vports %d,"
 744                        " qm_init_get_num_vports() %d\n",
 745                        qm_info->num_vports,
 746                        ecore_init_qm_get_num_vports(p_hwfn));
 747
 748         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 749                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 750                        " qm_init_get_num_pf_rls() %d\n",
 751                        qm_info->num_pf_rls,
 752                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 753 }
 754
 755 /* get pq index according to PQ_FLAGS */
 756 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 757                                              u32 pq_flags)
 758 {
 759         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 760
 761         /* Can't have multiple flags set here */
 762         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 763                                 sizeof(pq_flags)) > 1)
 764                 goto err;
 765
 766         switch (pq_flags) {
 767         case PQ_FLAGS_RLS:
 768                 return &qm_info->first_rl_pq;
 769         case PQ_FLAGS_MCOS:
 770                 return &qm_info->first_mcos_pq;
 771         case PQ_FLAGS_LB:
 772                 return &qm_info->pure_lb_pq;
 773         case PQ_FLAGS_OOO:
 774                 return &qm_info->ooo_pq;
 775         case PQ_FLAGS_ACK:
 776                 return &qm_info->pure_ack_pq;
 777         case PQ_FLAGS_OFLD:
 778                 return &qm_info->offload_pq;
 779         case PQ_FLAGS_VFS:
 780                 return &qm_info->first_vf_pq;
 781         default:
 782                 goto err;
 783         }
 784
 785 err:
 786         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 787         return OSAL_NULL;
 788 }
 789
 790 /* save pq index in qm info */
 791 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 792                                   u32 pq_flags, u16 pq_val)
 793 {
 794         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 795
 796         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 797 }
 798
 799 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 800 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 801 {
 802         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 803
 804         return *base_pq_idx + CM_TX_PQ_BASE;
 805 }
 806
 807 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 808 {
 809         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 810
 811         if (tc > max_tc)
 812                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 813
 814         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 815 }
 816
 817 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 818 {
 819         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 820
 821         if (vf > max_vf)
 822                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 823
 824         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 825 }
 826
 827 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 828 {
 829         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 830
 831         if (rl > max_rl)
 832                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 833
 834         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 835 }
 836
 837 /* Functions for creating specific types of pqs */
 838 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 839 {
 840         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 841
 842         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 843                 return;
 844
 845         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 846         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 847 }
 848
 849 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 850 {
 851         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 852
 853         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 854                 return;
 855
 856         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 857         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 858 }
 859
 860 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 861 {
 862         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 863
 864         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 865                 return;
 866
 867         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 868         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 869 }
 870
 871 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 872 {
 873         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 874
 875         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 876                 return;
 877
 878         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 879         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 880 }
 881
 882 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 883 {
 884         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 885         u8 tc_idx;
 886
 887         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 888                 return;
 889
 890         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 891         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 892                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 893 }
 894
 895 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 896 {
 897         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 898         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 899
 900         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 901                 return;
 902
 903         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 904
 905         qm_info->num_vf_pqs = num_vfs;
 906         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 907                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 908                                  PQ_INIT_VF_RL);
 909 }
 910
 911 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 912 {
 913         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 914         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 915
 916         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 917                 return;
 918
 919         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 920         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 921                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 922                                  PQ_INIT_PF_RL);
 923 }
 924
 925 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 926 {
 927         /* rate limited pqs, must come first (FW assumption) */
 928         ecore_init_qm_rl_pqs(p_hwfn);
 929
 930         /* pqs for multi cos */
 931         ecore_init_qm_mcos_pqs(p_hwfn);
 932
 933         /* pure loopback pq */
 934         ecore_init_qm_lb_pq(p_hwfn);
 935
 936         /* out of order pq */
 937         ecore_init_qm_ooo_pq(p_hwfn);
 938
 939         /* pure ack pq */
 940         ecore_init_qm_pure_ack_pq(p_hwfn);
 941
 942         /* pq for offloaded protocol */
 943         ecore_init_qm_offload_pq(p_hwfn);
 944
 945         /* done sharing vports */
 946         ecore_init_qm_advance_vport(p_hwfn);
 947
 948         /* pqs for vfs */
 949         ecore_init_qm_vf_pqs(p_hwfn);
 950 }
 951
 952 /* compare values of getters against resources amounts */
 953 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 954 {
 955         if (ecore_init_qm_get_num_vports(p_hwfn) >
 956             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 957                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 958                 return ECORE_INVAL;
 959         }
 960
 961         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 962                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 963                 return ECORE_INVAL;
 964         }
 965
 966         return ECORE_SUCCESS;
 967 }
 968
 969 /*
 970  * Function for verbose printing of the qm initialization results
 971  */
 972 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 973 {
 974         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 975         struct init_qm_vport_params *vport;
 976         struct init_qm_port_params *port;
 977         struct init_qm_pq_params *pq;
 978         int i, tc;
 979
 980         /* top level params */
 981         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 982                    "qm init top level params: start_pq %d, start_vport %d,"
 983                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 984                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 985                    qm_info->offload_pq, qm_info->pure_ack_pq);
 986         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 987                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 988                    " num_vports %d, max_phys_tcs_per_port %d\n",
 989                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 990                    qm_info->num_vf_pqs, qm_info->num_vports,
 991                    qm_info->max_phys_tcs_per_port);
 992         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 993                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 994                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 995                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 996                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 997                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 998
 999         /* port table */
1000         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1001                 port = &qm_info->qm_port_params[i];
1002                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1003                            "port idx %d, active %d, active_phys_tcs %d,"
1004                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1005                            " reserved %d\n",
1006                            i, port->active, port->active_phys_tcs,
1007                            port->num_pbf_cmd_lines, port->num_btb_blocks,
1008                            port->reserved);
1009         }
1010
1011         /* vport table */
1012         for (i = 0; i < qm_info->num_vports; i++) {
1013                 vport = &qm_info->qm_vport_params[i];
1014                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1015                            "vport idx %d, vport_rl %d, wfq %d,"
1016                            " first_tx_pq_id [ ",
1017                            qm_info->start_vport + i, vport->vport_rl,
1018                            vport->vport_wfq);
1019                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1020                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1021                                    vport->first_tx_pq_id[tc]);
1022                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1023         }
1024
1025         /* pq table */
1026         for (i = 0; i < qm_info->num_pqs; i++) {
1027                 pq = &qm_info->qm_pq_params[i];
1028                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1029                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1030                            qm_info->start_pq + i, pq->port_id, pq->vport_id,
1031                            pq->tc_id, pq->wrr_group, pq->rl_valid);
1032         }
1033 }
1034
1035 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1036 {
1037         /* reset params required for init run */
1038         ecore_init_qm_reset_params(p_hwfn);
1039
1040         /* init QM top level params */
1041         ecore_init_qm_params(p_hwfn);
1042
1043         /* init QM port params */
1044         ecore_init_qm_port_params(p_hwfn);
1045
1046         /* init QM vport params */
1047         ecore_init_qm_vport_params(p_hwfn);
1048
1049         /* init QM physical queue params */
1050         ecore_init_qm_pq_params(p_hwfn);
1051
1052         /* display all that init */
1053         ecore_dp_init_qm_params(p_hwfn);
1054 }
1055
1056 /* This function reconfigures the QM pf on the fly.
1057  * For this purpose we:
1058  * 1. reconfigure the QM database
1059  * 2. set new values to runtime array
1060  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1061  * 4. activate init tool in QM_PF stage
1062  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1063  */
1064 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1065                                      struct ecore_ptt *p_ptt)
1066 {
1067         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1068         bool b_rc;
1069         enum _ecore_status_t rc;
1070
1071         /* initialize ecore's qm data structure */
1072         ecore_init_qm_info(p_hwfn);
1073
1074         /* stop PF's qm queues */
1075         OSAL_SPIN_LOCK(&qm_lock);
1076         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1077                                       qm_info->start_pq, qm_info->num_pqs);
1078         OSAL_SPIN_UNLOCK(&qm_lock);
1079         if (!b_rc)
1080                 return ECORE_INVAL;
1081
1082         /* clear the QM_PF runtime phase leftovers from previous init */
1083         ecore_init_clear_rt_data(p_hwfn);
1084
1085         /* prepare QM portion of runtime array */
1086         ecore_qm_init_pf(p_hwfn, p_ptt, false);
1087
1088         /* activate init tool on runtime array */
1089         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1090                             p_hwfn->hw_info.hw_mode);
1091         if (rc != ECORE_SUCCESS)
1092                 return rc;
1093
1094         /* start PF's qm queues */
1095         OSAL_SPIN_LOCK(&qm_lock);
1096         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1097                                       qm_info->start_pq, qm_info->num_pqs);
1098         OSAL_SPIN_UNLOCK(&qm_lock);
1099         if (!b_rc)
1100                 return ECORE_INVAL;
1101
1102         return ECORE_SUCCESS;
1103 }
1104
1105 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1106 {
1107         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1108         enum _ecore_status_t rc;
1109
1110         rc = ecore_init_qm_sanity(p_hwfn);
1111         if (rc != ECORE_SUCCESS)
1112                 goto alloc_err;
1113
1114         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1115                                             sizeof(struct init_qm_pq_params) *
1116                                             ecore_init_qm_get_num_pqs(p_hwfn));
1117         if (!qm_info->qm_pq_params)
1118                 goto alloc_err;
1119
1120         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1121                                        sizeof(struct init_qm_vport_params) *
1122                                        ecore_init_qm_get_num_vports(p_hwfn));
1123         if (!qm_info->qm_vport_params)
1124                 goto alloc_err;
1125
1126         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1127                                       sizeof(struct init_qm_port_params) *
1128                                       p_hwfn->p_dev->num_ports_in_engine);
1129         if (!qm_info->qm_port_params)
1130                 goto alloc_err;
1131
1132         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1133                                         sizeof(struct ecore_wfq_data) *
1134                                         ecore_init_qm_get_num_vports(p_hwfn));
1135         if (!qm_info->wfq_data)
1136                 goto alloc_err;
1137
1138         return ECORE_SUCCESS;
1139
1140 alloc_err:
1141         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1142         ecore_qm_info_free(p_hwfn);
1143         return ECORE_NOMEM;
1144 }
1145 /******************** End QM initialization ***************/
1146
1147 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1148 {
1149         enum _ecore_status_t rc = ECORE_SUCCESS;
1150         int i;
1151
1152         if (IS_VF(p_dev)) {
1153                 for_each_hwfn(p_dev, i) {
1154                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1155                         if (rc != ECORE_SUCCESS)
1156                                 return rc;
1157                 }
1158                 return rc;
1159         }
1160
1161         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1162                                      sizeof(*p_dev->fw_data));
1163         if (!p_dev->fw_data)
1164                 return ECORE_NOMEM;
1165
1166         for_each_hwfn(p_dev, i) {
1167                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1168                 u32 n_eqes, num_cons;
1169
1170                 /* initialize the doorbell recovery mechanism */
1171                 rc = ecore_db_recovery_setup(p_hwfn);
1172                 if (rc)
1173                         goto alloc_err;
1174
1175                 /* First allocate the context manager structure */
1176                 rc = ecore_cxt_mngr_alloc(p_hwfn);
1177                 if (rc)
1178                         goto alloc_err;
1179
1180                 /* Set the HW cid/tid numbers (in the context manager)
1181                  * Must be done prior to any further computations.
1182                  */
1183                 rc = ecore_cxt_set_pf_params(p_hwfn);
1184                 if (rc)
1185                         goto alloc_err;
1186
1187                 rc = ecore_alloc_qm_data(p_hwfn);
1188                 if (rc)
1189                         goto alloc_err;
1190
1191                 /* init qm info */
1192                 ecore_init_qm_info(p_hwfn);
1193
1194                 /* Compute the ILT client partition */
1195                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1196                 if (rc)
1197                         goto alloc_err;
1198
1199                 /* CID map / ILT shadow table / T2
1200                  * The talbes sizes are determined by the computations above
1201                  */
1202                 rc = ecore_cxt_tables_alloc(p_hwfn);
1203                 if (rc)
1204                         goto alloc_err;
1205
1206                 /* SPQ, must follow ILT because initializes SPQ context */
1207                 rc = ecore_spq_alloc(p_hwfn);
1208                 if (rc)
1209                         goto alloc_err;
1210
1211                 /* SP status block allocation */
1212                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1213                                                            RESERVED_PTT_DPC);
1214
1215                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1216                 if (rc)
1217                         goto alloc_err;
1218
1219                 rc = ecore_iov_alloc(p_hwfn);
1220                 if (rc)
1221                         goto alloc_err;
1222
1223                 /* EQ */
1224                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1225                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1226                         /* Calculate the EQ size
1227                          * ---------------------
1228                          * Each ICID may generate up to one event at a time i.e.
1229                          * the event must be handled/cleared before a new one
1230                          * can be generated. We calculate the sum of events per
1231                          * protocol and create an EQ deep enough to handle the
1232                          * worst case:
1233                          * - Core - according to SPQ.
1234                          * - RoCE - per QP there are a couple of ICIDs, one
1235                          *        responder and one requester, each can
1236                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
1237                          *        Each CQ can generate an EQE. There are 2 CQs
1238                          *        per QP => n_eqes_cq = 2 * n_qp.
1239                          *        Hence the RoCE total is 4 * n_qp or
1240                          *        2 * num_cons.
1241                          * - ENet - There can be up to two events per VF. One
1242                          *        for VF-PF channel and another for VF FLR
1243                          *        initial cleanup. The number of VFs is
1244                          *        bounded by MAX_NUM_VFS_BB, and is much
1245                          *        smaller than RoCE's so we avoid exact
1246                          *        calculation.
1247                          */
1248                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1249                                 num_cons =
1250                                     ecore_cxt_get_proto_cid_count(
1251                                                 p_hwfn,
1252                                                 PROTOCOLID_ROCE,
1253                                                 OSAL_NULL);
1254                                 num_cons *= 2;
1255                         } else {
1256                                 num_cons = ecore_cxt_get_proto_cid_count(
1257                                                 p_hwfn,
1258                                                 PROTOCOLID_IWARP,
1259                                                 OSAL_NULL);
1260                         }
1261                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1262                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1263                         num_cons =
1264                             ecore_cxt_get_proto_cid_count(p_hwfn,
1265                                                           PROTOCOLID_ISCSI,
1266                                                           OSAL_NULL);
1267                         n_eqes += 2 * num_cons;
1268                 }
1269
1270                 if (n_eqes > 0xFFFF) {
1271                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1272                                        "The maximum of a u16 chain is 0x%x\n",
1273                                n_eqes, 0xFFFF);
1274                         goto alloc_no_mem;
1275                 }
1276
1277                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1278                 if (rc)
1279                         goto alloc_err;
1280
1281                 rc = ecore_consq_alloc(p_hwfn);
1282                 if (rc)
1283                         goto alloc_err;
1284
1285                 rc = ecore_l2_alloc(p_hwfn);
1286                 if (rc != ECORE_SUCCESS)
1287                         goto alloc_err;
1288
1289                 /* DMA info initialization */
1290                 rc = ecore_dmae_info_alloc(p_hwfn);
1291                 if (rc) {
1292                         DP_NOTICE(p_hwfn, true,
1293                                   "Failed to allocate memory for dmae_info"
1294                                   " structure\n");
1295                         goto alloc_err;
1296                 }
1297
1298                 /* DCBX initialization */
1299                 rc = ecore_dcbx_info_alloc(p_hwfn);
1300                 if (rc) {
1301                         DP_NOTICE(p_hwfn, true,
1302                                   "Failed to allocate memory for dcbx structure\n");
1303                         goto alloc_err;
1304                 }
1305         }
1306
1307         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1308                                          sizeof(*p_dev->reset_stats));
1309         if (!p_dev->reset_stats) {
1310                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1311                 goto alloc_no_mem;
1312         }
1313
1314         return ECORE_SUCCESS;
1315
1316 alloc_no_mem:
1317         rc = ECORE_NOMEM;
1318 alloc_err:
1319         ecore_resc_free(p_dev);
1320         return rc;
1321 }
1322
1323 void ecore_resc_setup(struct ecore_dev *p_dev)
1324 {
1325         int i;
1326
1327         if (IS_VF(p_dev)) {
1328                 for_each_hwfn(p_dev, i)
1329                         ecore_l2_setup(&p_dev->hwfns[i]);
1330                 return;
1331         }
1332
1333         for_each_hwfn(p_dev, i) {
1334                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1335
1336                 ecore_cxt_mngr_setup(p_hwfn);
1337                 ecore_spq_setup(p_hwfn);
1338                 ecore_eq_setup(p_hwfn);
1339                 ecore_consq_setup(p_hwfn);
1340
1341                 /* Read shadow of current MFW mailbox */
1342                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1343                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1344                             p_hwfn->mcp_info->mfw_mb_cur,
1345                             p_hwfn->mcp_info->mfw_mb_length);
1346
1347                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1348
1349                 ecore_l2_setup(p_hwfn);
1350                 ecore_iov_setup(p_hwfn);
1351         }
1352 }
1353
1354 #define FINAL_CLEANUP_POLL_CNT  (100)
1355 #define FINAL_CLEANUP_POLL_TIME (10)
1356 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1357                                          struct ecore_ptt *p_ptt,
1358                                          u16 id, bool is_vf)
1359 {
1360         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1361         enum _ecore_status_t rc = ECORE_TIMEOUT;
1362
1363 #ifndef ASIC_ONLY
1364         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1365             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1366                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1367                 return ECORE_SUCCESS;
1368         }
1369 #endif
1370
1371         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1372             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1373
1374         if (is_vf)
1375                 id += 0x10;
1376
1377         command |= X_FINAL_CLEANUP_AGG_INT <<
1378             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1379         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1380         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1381         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1382
1383 /* Make sure notification is not set before initiating final cleanup */
1384
1385         if (REG_RD(p_hwfn, addr)) {
1386                 DP_NOTICE(p_hwfn, false,
1387                           "Unexpected; Found final cleanup notification");
1388                 DP_NOTICE(p_hwfn, false,
1389                           " before initiating final cleanup\n");
1390                 REG_WR(p_hwfn, addr, 0);
1391         }
1392
1393         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1394                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1395                    id, command);
1396
1397         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1398
1399         /* Poll until completion */
1400         while (!REG_RD(p_hwfn, addr) && count--)
1401                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1402
1403         if (REG_RD(p_hwfn, addr))
1404                 rc = ECORE_SUCCESS;
1405         else
1406                 DP_NOTICE(p_hwfn, true,
1407                           "Failed to receive FW final cleanup notification\n");
1408
1409         /* Cleanup afterwards */
1410         REG_WR(p_hwfn, addr, 0);
1411
1412         return rc;
1413 }
1414
1415 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1416 {
1417         int hw_mode = 0;
1418
1419         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1420                 hw_mode |= 1 << MODE_BB;
1421         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1422                 hw_mode |= 1 << MODE_K2;
1423         } else {
1424                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1425                           p_hwfn->p_dev->type);
1426                 return ECORE_INVAL;
1427         }
1428
1429         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1430         switch (p_hwfn->p_dev->num_ports_in_engine) {
1431         case 1:
1432                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1433                 break;
1434         case 2:
1435                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1436                 break;
1437         case 4:
1438                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1439                 break;
1440         default:
1441                 DP_NOTICE(p_hwfn, true,
1442                           "num_ports_in_engine = %d not supported\n",
1443                           p_hwfn->p_dev->num_ports_in_engine);
1444                 return ECORE_INVAL;
1445         }
1446
1447         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1448                           &p_hwfn->p_dev->mf_bits))
1449                 hw_mode |= 1 << MODE_MF_SD;
1450         else
1451                 hw_mode |= 1 << MODE_MF_SI;
1452
1453 #ifndef ASIC_ONLY
1454         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1455                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1456                         hw_mode |= 1 << MODE_FPGA;
1457                 } else {
1458                         if (p_hwfn->p_dev->b_is_emul_full)
1459                                 hw_mode |= 1 << MODE_EMUL_FULL;
1460                         else
1461                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1462                 }
1463         } else
1464 #endif
1465                 hw_mode |= 1 << MODE_ASIC;
1466
1467         if (ECORE_IS_CMT(p_hwfn->p_dev))
1468                 hw_mode |= 1 << MODE_100G;
1469
1470         p_hwfn->hw_info.hw_mode = hw_mode;
1471
1472         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1473                    "Configuring function for hw_mode: 0x%08x\n",
1474                    p_hwfn->hw_info.hw_mode);
1475
1476         return ECORE_SUCCESS;
1477 }
1478
1479 #ifndef ASIC_ONLY
1480 /* MFW-replacement initializations for non-ASIC */
1481 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1482                                                struct ecore_ptt *p_ptt)
1483 {
1484         struct ecore_dev *p_dev = p_hwfn->p_dev;
1485         u32 pl_hv = 1;
1486         int i;
1487
1488         if (CHIP_REV_IS_EMUL(p_dev)) {
1489                 if (ECORE_IS_AH(p_dev))
1490                         pl_hv |= 0x600;
1491         }
1492
1493         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1494
1495         if (CHIP_REV_IS_EMUL(p_dev) &&
1496             (ECORE_IS_AH(p_dev)))
1497                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1498                          0x3ffffff);
1499
1500         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1501         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1502         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1503                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1504
1505         if (CHIP_REV_IS_EMUL(p_dev)) {
1506                 if (ECORE_IS_AH(p_dev)) {
1507                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1508                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1509                                  (p_dev->num_ports_in_engine >> 1));
1510
1511                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1512                                  p_dev->num_ports_in_engine == 4 ? 0 : 3);
1513                 }
1514         }
1515
1516         /* Poll on RBC */
1517         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1518         for (i = 0; i < 100; i++) {
1519                 OSAL_UDELAY(50);
1520                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1521                         break;
1522         }
1523         if (i == 100)
1524                 DP_NOTICE(p_hwfn, true,
1525                           "RBC done failed to complete in PSWRQ2\n");
1526
1527         return ECORE_SUCCESS;
1528 }
1529 #endif
1530
1531 /* Init run time data for all PFs and their VFs on an engine.
1532  * TBD - for VFs - Once we have parent PF info for each VF in
1533  * shmem available as CAU requires knowledge of parent PF for each VF.
1534  */
1535 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1536 {
1537         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1538         int i, igu_sb_id;
1539
1540         for_each_hwfn(p_dev, i) {
1541                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1542                 struct ecore_igu_info *p_igu_info;
1543                 struct ecore_igu_block *p_block;
1544                 struct cau_sb_entry sb_entry;
1545
1546                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1547
1548                 for (igu_sb_id = 0;
1549                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1550                      igu_sb_id++) {
1551                         p_block = &p_igu_info->entry[igu_sb_id];
1552
1553                         if (!p_block->is_pf)
1554                                 continue;
1555
1556                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1557                                                 p_block->function_id, 0, 0);
1558                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1559                                          sb_entry);
1560                 }
1561         }
1562 }
1563
1564 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1565                                        struct ecore_ptt *p_ptt)
1566 {
1567         u32 val, wr_mbs, cache_line_size;
1568
1569         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1570         switch (val) {
1571         case 0:
1572                 wr_mbs = 128;
1573                 break;
1574         case 1:
1575                 wr_mbs = 256;
1576                 break;
1577         case 2:
1578                 wr_mbs = 512;
1579                 break;
1580         default:
1581                 DP_INFO(p_hwfn,
1582                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1583                         val);
1584                 return;
1585         }
1586
1587         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1588         switch (cache_line_size) {
1589         case 32:
1590                 val = 0;
1591                 break;
1592         case 64:
1593                 val = 1;
1594                 break;
1595         case 128:
1596                 val = 2;
1597                 break;
1598         case 256:
1599                 val = 3;
1600                 break;
1601         default:
1602                 DP_INFO(p_hwfn,
1603                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1604                         cache_line_size);
1605         }
1606
1607         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1608                 DP_INFO(p_hwfn,
1609                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1610                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1611
1612         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1613         if (val > 0) {
1614                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1615                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1616         }
1617 }
1618
1619 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1620                                                  struct ecore_ptt *p_ptt,
1621                                                  int hw_mode)
1622 {
1623         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1624         struct ecore_dev *p_dev = p_hwfn->p_dev;
1625         u8 vf_id, max_num_vfs;
1626         u16 num_pfs, pf_id;
1627         u32 concrete_fid;
1628         enum _ecore_status_t rc = ECORE_SUCCESS;
1629
1630         ecore_init_cau_rt_data(p_dev);
1631
1632         /* Program GTT windows */
1633         ecore_gtt_init(p_hwfn, p_ptt);
1634
1635 #ifndef ASIC_ONLY
1636         if (CHIP_REV_IS_EMUL(p_dev)) {
1637                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1638                 if (rc != ECORE_SUCCESS)
1639                         return rc;
1640         }
1641 #endif
1642
1643         if (p_hwfn->mcp_info) {
1644                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1645                         qm_info->pf_rl_en = 1;
1646                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1647                         qm_info->pf_wfq_en = 1;
1648         }
1649
1650         ecore_qm_common_rt_init(p_hwfn,
1651                                 p_dev->num_ports_in_engine,
1652                                 qm_info->max_phys_tcs_per_port,
1653                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1654                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1655                                 qm_info->qm_port_params);
1656
1657         ecore_cxt_hw_init_common(p_hwfn);
1658
1659         ecore_init_cache_line_size(p_hwfn, p_ptt);
1660
1661         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
1662                             hw_mode);
1663         if (rc != ECORE_SUCCESS)
1664                 return rc;
1665
1666         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1667          * need to decide with which value, maybe runtime
1668          */
1669         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1670         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1671
1672         if (ECORE_IS_BB(p_dev)) {
1673                 /* Workaround clears ROCE search for all functions to prevent
1674                  * involving non initialized function in processing ROCE packet.
1675                  */
1676                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1677                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1678                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1679                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1680                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1681                 }
1682                 /* pretend to original PF */
1683                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1684         }
1685
1686         /* Workaround for avoiding CCFC execution error when getting packets
1687          * with CRC errors, and allowing instead the invoking of the FW error
1688          * handler.
1689          * This is not done inside the init tool since it currently can't
1690          * perform a pretending to VFs.
1691          */
1692         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1693         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1694                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1695                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1696                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1697                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1698                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1699                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1700         }
1701         /* pretend to original PF */
1702         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1703
1704         return rc;
1705 }
1706
1707 #ifndef ASIC_ONLY
1708 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1709 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1710
1711 #define PMEG_IF_BYTE_COUNT      8
1712
1713 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1714                              struct ecore_ptt *p_ptt,
1715                              u32 addr, u64 data, u8 reg_type, u8 port)
1716 {
1717         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1718                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1719                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1720                    (8 << PMEG_IF_BYTE_COUNT),
1721                    (reg_type << 25) | (addr << 8) | port,
1722                    (u32)((data >> 32) & 0xffffffff),
1723                    (u32)(data & 0xffffffff));
1724
1725         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1726                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1727                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1728         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1729                  (reg_type << 25) | (addr << 8) | port);
1730         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1731         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1732                  (data >> 32) & 0xffffffff);
1733 }
1734
1735 #define XLPORT_MODE_REG (0x20a)
1736 #define XLPORT_MAC_CONTROL (0x210)
1737 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1738 #define XLPORT_ENABLE_REG (0x20b)
1739
1740 #define XLMAC_CTRL (0x600)
1741 #define XLMAC_MODE (0x601)
1742 #define XLMAC_RX_MAX_SIZE (0x608)
1743 #define XLMAC_TX_CTRL (0x604)
1744 #define XLMAC_PAUSE_CTRL (0x60d)
1745 #define XLMAC_PFC_CTRL (0x60e)
1746
1747 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1748                                     struct ecore_ptt *p_ptt)
1749 {
1750         u8 loopback = 0, port = p_hwfn->port_id * 2;
1751
1752         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1753
1754         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1755         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1756                          port);
1757         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1758         /* XLMAC: SOFT RESET */
1759         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1760         /* XLMAC: Port Speed >= 10Gbps */
1761         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1762         /* XLMAC: Max Size */
1763         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1764         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1765                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1766                          0, port);
1767         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1768         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1769                          0x30ffffc000ULL, 0, port);
1770         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1771                          port); /* XLMAC: TX_EN, RX_EN */
1772         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1773         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1774                          0x1003 | (loopback << 2), 0, port);
1775         /* Enabled Parallel PFC interface */
1776         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1777
1778         /* XLPORT port enable */
1779         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1780 }
1781
1782 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1783                                        struct ecore_ptt *p_ptt)
1784 {
1785         u8 port = p_hwfn->port_id;
1786         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1787
1788         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1789
1790         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1791                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1792                  (port <<
1793                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1794                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1795
1796         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1797                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1798
1799         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1800                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1801
1802         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1803                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1804
1805         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1806                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1807
1808         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1809                  (0xA <<
1810                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1811                  (8 <<
1812                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1813
1814         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1815                  0xa853);
1816 }
1817
1818 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1819                                  struct ecore_ptt *p_ptt)
1820 {
1821         if (ECORE_IS_AH(p_hwfn->p_dev))
1822                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1823         else /* BB */
1824                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1825 }
1826
1827 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1828                                struct ecore_ptt *p_ptt,  u8 port)
1829 {
1830         int port_offset = port ? 0x800 : 0;
1831         u32 xmac_rxctrl = 0;
1832
1833         /* Reset of XMAC */
1834         /* FIXME: move to common start */
1835         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1836                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1837         OSAL_MSLEEP(1);
1838         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1839                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1840
1841         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1842
1843         /* Set the number of ports on the Warp Core to 10G */
1844         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1845
1846         /* Soft reset of XMAC */
1847         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1848                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1849         OSAL_MSLEEP(1);
1850         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1851                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1852
1853         /* FIXME: move to common end */
1854         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1855                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1856
1857         /* Set Max packet size: initialize XMAC block register for port 0 */
1858         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1859
1860         /* CRC append for Tx packets: init XMAC block register for port 1 */
1861         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1862
1863         /* Enable TX and RX: initialize XMAC block register for port 1 */
1864         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1865                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1866         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1867                                XMAC_REG_RX_CTRL_BB + port_offset);
1868         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1869         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1870 }
1871 #endif
1872
1873 static enum _ecore_status_t
1874 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1875                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1876 {
1877         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1878         u32 min_dpis;
1879         u32 n_wids;
1880
1881         /* Calculate DPI size
1882          * ------------------
1883          * The PWM region contains Doorbell Pages. The first is reserverd for
1884          * the kernel for, e.g, L2. The others are free to be used by non-
1885          * trusted applications, typically from user space. Each page, called a
1886          * doorbell page is sectioned into windows that allow doorbells to be
1887          * issued in parallel by the kernel/application. The size of such a
1888          * window (a.k.a. WID) is 1kB.
1889          * Summary:
1890          *    1kB WID x N WIDS = DPI page size
1891          *    DPI page size x N DPIs = PWM region size
1892          * Notes:
1893          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1894          * in order to ensure that two applications won't share the same page.
1895          * It also must contain at least one WID per CPU to allow parallelism.
1896          * It also must be a power of 2, since it is stored as a bit shift.
1897          *
1898          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1899          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1900          * containing 4 WIDs.
1901          */
1902         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1903         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1904         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1905                         ~(OSAL_PAGE_SIZE - 1);
1906         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1907         dpi_count = pwm_region_size / dpi_page_size;
1908
1909         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1910         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1911
1912         /* Update hwfn */
1913         p_hwfn->dpi_size = dpi_page_size;
1914         p_hwfn->dpi_count = dpi_count;
1915
1916         /* Update registers */
1917         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1918
1919         if (dpi_count < min_dpis)
1920                 return ECORE_NORESOURCES;
1921
1922         return ECORE_SUCCESS;
1923 }
1924
1925 enum ECORE_ROCE_EDPM_MODE {
1926         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1927         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1928         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1929 };
1930
1931 static enum _ecore_status_t
1932 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1933                               struct ecore_ptt *p_ptt)
1934 {
1935         u32 pwm_regsize, norm_regsize;
1936         u32 non_pwm_conn, min_addr_reg1;
1937         u32 db_bar_size, n_cpus;
1938         u32 roce_edpm_mode;
1939         u32 pf_dems_shift;
1940         enum _ecore_status_t rc = ECORE_SUCCESS;
1941         u8 cond;
1942
1943         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1944         if (ECORE_IS_CMT(p_hwfn->p_dev))
1945                 db_bar_size /= 2;
1946
1947         /* Calculate doorbell regions
1948          * -----------------------------------
1949          * The doorbell BAR is made of two regions. The first is called normal
1950          * region and the second is called PWM region. In the normal region
1951          * each ICID has its own set of addresses so that writing to that
1952          * specific address identifies the ICID. In the Process Window Mode
1953          * region the ICID is given in the data written to the doorbell. The
1954          * above per PF register denotes the offset in the doorbell BAR in which
1955          * the PWM region begins.
1956          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1957          * non-PWM connection. The calculation below computes the total non-PWM
1958          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1959          * in units of 4,096 bytes.
1960          */
1961         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1962             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1963                                           OSAL_NULL) +
1964             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1965         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
1966                                OSAL_PAGE_SIZE);
1967         min_addr_reg1 = norm_regsize / 4096;
1968         pwm_regsize = db_bar_size - norm_regsize;
1969
1970         /* Check that the normal and PWM sizes are valid */
1971         if (db_bar_size < norm_regsize) {
1972                 DP_ERR(p_hwfn->p_dev,
1973                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1974                        db_bar_size, norm_regsize);
1975                 return ECORE_NORESOURCES;
1976         }
1977         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1978                 DP_ERR(p_hwfn->p_dev,
1979                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1980                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1981                        norm_regsize);
1982                 return ECORE_NORESOURCES;
1983         }
1984
1985         /* Calculate number of DPIs */
1986         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1987         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1988             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1989                 /* Either EDPM is mandatory, or we are attempting to allocate a
1990                  * WID per CPU.
1991                  */
1992                 n_cpus = OSAL_NUM_CPUS();
1993                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1994         }
1995
1996         cond = ((rc != ECORE_SUCCESS) &&
1997                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1998                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1999         if (cond || p_hwfn->dcbx_no_edpm) {
2000                 /* Either EDPM is disabled from user configuration, or it is
2001                  * disabled via DCBx, or it is not mandatory and we failed to
2002                  * allocated a WID per CPU.
2003                  */
2004                 n_cpus = 1;
2005                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2006
2007                 /* If we entered this flow due to DCBX then the DPM register is
2008                  * already configured.
2009                  */
2010         }
2011
2012         DP_INFO(p_hwfn,
2013                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2014                 norm_regsize, pwm_regsize);
2015         DP_INFO(p_hwfn,
2016                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2017                 p_hwfn->dpi_size, p_hwfn->dpi_count,
2018                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2019                 "disabled" : "enabled");
2020
2021         /* Check return codes from above calls */
2022         if (rc != ECORE_SUCCESS) {
2023                 DP_ERR(p_hwfn,
2024                        "Failed to allocate enough DPIs\n");
2025                 return ECORE_NORESOURCES;
2026         }
2027
2028         /* Update hwfn */
2029         p_hwfn->dpi_start_offset = norm_regsize;
2030
2031         /* Update registers */
2032         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2033         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2034         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2035         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2036
2037         return ECORE_SUCCESS;
2038 }
2039
2040 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2041                                                struct ecore_ptt *p_ptt,
2042                                                int hw_mode)
2043 {
2044         u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2045         u32 val;
2046         enum _ecore_status_t rc = ECORE_SUCCESS;
2047         u8 i;
2048
2049         /* In CMT for non-RoCE packets - use connection based classification */
2050         val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2051         for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2052                 ppf_to_eng_sel[i] = val;
2053         STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2054                          ppf_to_eng_sel);
2055
2056         /* In CMT the gate should be cleared by the 2nd hwfn */
2057         if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2058                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2059
2060         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2061                             hw_mode);
2062         if (rc != ECORE_SUCCESS)
2063                 return rc;
2064
2065         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2066
2067 #ifndef ASIC_ONLY
2068         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2069                 return ECORE_SUCCESS;
2070
2071         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2072                 if (ECORE_IS_AH(p_hwfn->p_dev))
2073                         return ECORE_SUCCESS;
2074                 else if (ECORE_IS_BB(p_hwfn->p_dev))
2075                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2076         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2077                 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2078                         /* Activate OPTE in CMT */
2079                         u32 val;
2080
2081                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2082                         val |= 0x10;
2083                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2084                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2085                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2086                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2087                         ecore_wr(p_hwfn, p_ptt,
2088                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2089                         ecore_wr(p_hwfn, p_ptt,
2090                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2091                         ecore_wr(p_hwfn, p_ptt,
2092                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2093                                  0x55555555);
2094                 }
2095
2096                 ecore_emul_link_init(p_hwfn, p_ptt);
2097         } else {
2098                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2099         }
2100 #endif
2101
2102         return rc;
2103 }
2104
2105 static enum _ecore_status_t
2106 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2107                  struct ecore_ptt *p_ptt,
2108                  struct ecore_tunnel_info *p_tunn,
2109                  int hw_mode,
2110                  bool b_hw_start,
2111                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2112 {
2113         u8 rel_pf_id = p_hwfn->rel_pf_id;
2114         u32 prs_reg;
2115         enum _ecore_status_t rc = ECORE_SUCCESS;
2116         u16 ctrl;
2117         int pos;
2118
2119         if (p_hwfn->mcp_info) {
2120                 struct ecore_mcp_function_info *p_info;
2121
2122                 p_info = &p_hwfn->mcp_info->func_info;
2123                 if (p_info->bandwidth_min)
2124                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2125
2126                 /* Update rate limit once we'll actually have a link */
2127                 p_hwfn->qm_info.pf_rl = 100000;
2128         }
2129         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2130
2131         ecore_int_igu_init_rt(p_hwfn);
2132
2133         /* Set VLAN in NIG if needed */
2134         if (hw_mode & (1 << MODE_MF_SD)) {
2135                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2136                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2137                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2138                              p_hwfn->hw_info.ovlan);
2139
2140                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2141                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2142                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2143                              1);
2144         }
2145
2146         /* Enable classification by MAC if needed */
2147         if (hw_mode & (1 << MODE_MF_SI)) {
2148                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2149                            "Configuring TAGMAC_CLS_TYPE\n");
2150                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2151                              1);
2152         }
2153
2154         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
2155         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2156                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2157         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2158                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2159         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2160
2161         /* perform debug configuration when chip is out of reset */
2162         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2163
2164         /* Sanity check before the PF init sequence that uses DMAE */
2165         rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2166         if (rc)
2167                 return rc;
2168
2169         /* PF Init sequence */
2170         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2171         if (rc)
2172                 return rc;
2173
2174         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2175         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2176         if (rc)
2177                 return rc;
2178
2179         /* Pure runtime initializations - directly to the HW  */
2180         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2181
2182         /* PCI relaxed ordering causes a decrease in the performance on some
2183          * systems. Till a root cause is found, disable this attribute in the
2184          * PCI config space.
2185          */
2186         /* Not in use @DPDK
2187         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2188         * if (!pos) {
2189         *       DP_NOTICE(p_hwfn, true,
2190         *                 "Failed to find the PCIe Cap\n");
2191         *       return ECORE_IO;
2192         * }
2193         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2194         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2195         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2196         */
2197
2198         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2199         if (rc)
2200                 return rc;
2201         if (b_hw_start) {
2202                 /* enable interrupts */
2203                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2204                 if (rc != ECORE_SUCCESS)
2205                         return rc;
2206
2207                 /* send function start command */
2208                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2209                                        allow_npar_tx_switch);
2210                 if (rc) {
2211                         DP_NOTICE(p_hwfn, true,
2212                                   "Function start ramrod failed\n");
2213                 } else {
2214                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2215                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2216                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2217
2218                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2219                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2220                                          (1 << 2));
2221                                 ecore_wr(p_hwfn, p_ptt,
2222                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2223                                     0x100);
2224                         }
2225                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2226                                    "PRS_REG_SEARCH registers after start PFn\n");
2227                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2228                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2229                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2230                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2231                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2232                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2233                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2234                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2235                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2236                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2237                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2238                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2239                         prs_reg = ecore_rd(p_hwfn, p_ptt,
2240                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
2241                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2242                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2243                                    prs_reg);
2244                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2245                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2246                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2247                 }
2248         }
2249         return rc;
2250 }
2251
2252 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2253                                                   struct ecore_ptt *p_ptt,
2254                                                   bool b_enable)
2255 {
2256         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2257
2258         /* Configure the PF's internal FID_enable for master transactions */
2259         ecore_wr(p_hwfn, p_ptt,
2260                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2261
2262         /* Wait until value is set - try for 1 second every 50us */
2263         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2264                 val = ecore_rd(p_hwfn, p_ptt,
2265                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2266                 if (val == set_val)
2267                         break;
2268
2269                 OSAL_UDELAY(50);
2270         }
2271
2272         if (val != set_val) {
2273                 DP_NOTICE(p_hwfn, true,
2274                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2275                 return ECORE_UNKNOWN_ERROR;
2276         }
2277
2278         return ECORE_SUCCESS;
2279 }
2280
2281 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2282                                   struct ecore_ptt *p_main_ptt)
2283 {
2284         /* Read shadow of current MFW mailbox */
2285         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2286         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2287                     p_hwfn->mcp_info->mfw_mb_cur,
2288                     p_hwfn->mcp_info->mfw_mb_length);
2289 }
2290
2291 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2292                                    struct ecore_ptt *p_ptt)
2293 {
2294         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2295                  1 << p_hwfn->abs_pf_id);
2296 }
2297
2298 static enum _ecore_status_t
2299 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
2300                            struct ecore_load_req_params *p_load_req,
2301                            struct ecore_drv_load_params *p_drv_load)
2302 {
2303         /* Make sure that if ecore-client didn't provide inputs, all the
2304          * expected defaults are indeed zero.
2305          */
2306         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2307         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2308         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2309
2310         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2311
2312         if (p_drv_load == OSAL_NULL)
2313                 goto out;
2314
2315         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2316                                ECORE_DRV_ROLE_KDUMP :
2317                                ECORE_DRV_ROLE_OS;
2318         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2319         p_load_req->override_force_load = p_drv_load->override_force_load;
2320
2321         /* Old MFW versions don't support timeout values other than default and
2322          * none, so these values are replaced according to the fall-back action.
2323          */
2324
2325         if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
2326             p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
2327             (p_hwfn->mcp_info->capabilities &
2328              FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
2329                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2330                 goto out;
2331         }
2332
2333         switch (p_drv_load->mfw_timeout_fallback) {
2334         case ECORE_TO_FALLBACK_TO_NONE:
2335                 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
2336                 break;
2337         case ECORE_TO_FALLBACK_TO_DEFAULT:
2338                 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
2339                 break;
2340         case ECORE_TO_FALLBACK_FAIL_LOAD:
2341                 DP_NOTICE(p_hwfn, false,
2342                           "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
2343                           p_drv_load->mfw_timeout_val,
2344                           ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
2345                           ECORE_LOAD_REQ_LOCK_TO_NONE);
2346                 return ECORE_ABORTED;
2347         }
2348
2349         DP_INFO(p_hwfn,
2350                 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
2351                 p_drv_load->mfw_timeout_val,
2352                 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
2353                 "default" : "none",
2354                 p_load_req->timeout_val);
2355 out:
2356         return ECORE_SUCCESS;
2357 }
2358
2359 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2360                                     struct ecore_hw_init_params *p_params)
2361 {
2362         if (p_params->p_tunn) {
2363                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2364                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2365         }
2366
2367         p_hwfn->b_int_enabled = 1;
2368
2369         return ECORE_SUCCESS;
2370 }
2371
2372 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2373                                    struct ecore_hw_init_params *p_params)
2374 {
2375         struct ecore_load_req_params load_req_params;
2376         u32 load_code, resp, param, drv_mb_param;
2377         bool b_default_mtu = true;
2378         struct ecore_hwfn *p_hwfn;
2379         enum _ecore_status_t rc = ECORE_SUCCESS;
2380         int i;
2381
2382         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2383                 DP_NOTICE(p_dev, false,
2384                           "MSI mode is not supported for CMT devices\n");
2385                 return ECORE_INVAL;
2386         }
2387
2388         if (IS_PF(p_dev)) {
2389                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2390                 if (rc != ECORE_SUCCESS)
2391                         return rc;
2392         }
2393
2394         for_each_hwfn(p_dev, i) {
2395                 p_hwfn = &p_dev->hwfns[i];
2396
2397                 /* If management didn't provide a default, set one of our own */
2398                 if (!p_hwfn->hw_info.mtu) {
2399                         p_hwfn->hw_info.mtu = 1500;
2400                         b_default_mtu = false;
2401                 }
2402
2403                 if (IS_VF(p_dev)) {
2404                         ecore_vf_start(p_hwfn, p_params);
2405                         continue;
2406                 }
2407
2408                 rc = ecore_calc_hw_mode(p_hwfn);
2409                 if (rc != ECORE_SUCCESS)
2410                         return rc;
2411
2412                 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
2413
2414                 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
2415                                                 p_params->p_drv_load_params);
2416                 if (rc != ECORE_SUCCESS)
2417                         return rc;
2418
2419                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2420                                         &load_req_params);
2421                 if (rc != ECORE_SUCCESS) {
2422                         DP_NOTICE(p_hwfn, true,
2423                                   "Failed sending a LOAD_REQ command\n");
2424                         return rc;
2425                 }
2426
2427                 load_code = load_req_params.load_code;
2428                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2429                            "Load request was sent. Load code: 0x%x\n",
2430                            load_code);
2431
2432                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2433
2434                 /* CQ75580:
2435                  * When coming back from hiberbate state, the registers from
2436                  * which shadow is read initially are not initialized. It turns
2437                  * out that these registers get initialized during the call to
2438                  * ecore_mcp_load_req request. So we need to reread them here
2439                  * to get the proper shadow register value.
2440                  * Note: This is a workaround for the missing MFW
2441                  * initialization. It may be removed once the implementation
2442                  * is done.
2443                  */
2444                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2445
2446                 /* Only relevant for recovery:
2447                  * Clear the indication after the LOAD_REQ command is responded
2448                  * by the MFW.
2449                  */
2450                 p_dev->recov_in_prog = false;
2451
2452                 p_hwfn->first_on_engine = (load_code ==
2453                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2454
2455                 if (!qm_lock_init) {
2456                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2457                         qm_lock_init = true;
2458                 }
2459
2460                 /* Clean up chip from previous driver if such remains exist.
2461                  * This is not needed when the PF is the first one on the
2462                  * engine, since afterwards we are going to init the FW.
2463                  */
2464                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2465                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2466                                                  p_hwfn->rel_pf_id, false);
2467                         if (rc != ECORE_SUCCESS) {
2468                                 ecore_hw_err_notify(p_hwfn,
2469                                                     ECORE_HW_ERR_RAMROD_FAIL);
2470                                 goto load_err;
2471                         }
2472                 }
2473
2474                 /* Log and clean previous pglue_b errors if such exist */
2475                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2476                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2477
2478                 /* Enable the PF's internal FID_enable in the PXP */
2479                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2480                                                   true);
2481                 if (rc != ECORE_SUCCESS)
2482                         goto load_err;
2483
2484                 switch (load_code) {
2485                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2486                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2487                                                   p_hwfn->hw_info.hw_mode);
2488                         if (rc != ECORE_SUCCESS)
2489                                 break;
2490                         /* Fall into */
2491                 case FW_MSG_CODE_DRV_LOAD_PORT:
2492                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2493                                                 p_hwfn->hw_info.hw_mode);
2494                         if (rc != ECORE_SUCCESS)
2495                                 break;
2496                         /* Fall into */
2497                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2498                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2499                                               p_params->p_tunn,
2500                                               p_hwfn->hw_info.hw_mode,
2501                                               p_params->b_hw_start,
2502                                               p_params->int_mode,
2503                                               p_params->allow_npar_tx_switch);
2504                         break;
2505                 default:
2506                         DP_NOTICE(p_hwfn, false,
2507                                   "Unexpected load code [0x%08x]", load_code);
2508                         rc = ECORE_NOTIMPL;
2509                         break;
2510                 }
2511
2512                 if (rc != ECORE_SUCCESS) {
2513                         DP_NOTICE(p_hwfn, true,
2514                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2515                                   load_code, rc);
2516                         goto load_err;
2517                 }
2518
2519                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2520                 if (rc != ECORE_SUCCESS)
2521                         return rc;
2522
2523                 /* send DCBX attention request command */
2524                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2525                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2526                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2527                                    DRV_MSG_CODE_SET_DCBX,
2528                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2529                                    &param);
2530                 if (rc != ECORE_SUCCESS) {
2531                         DP_NOTICE(p_hwfn, true,
2532                                   "Failed to send DCBX attention request\n");
2533                         return rc;
2534                 }
2535
2536                 p_hwfn->hw_init_done = true;
2537         }
2538
2539         if (IS_PF(p_dev)) {
2540                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2541                 drv_mb_param = STORM_FW_VERSION;
2542                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2543                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2544                                    drv_mb_param, &resp, &param);
2545                 if (rc != ECORE_SUCCESS)
2546                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2547
2548                 if (!b_default_mtu)
2549                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2550                                                       p_hwfn->hw_info.mtu);
2551                 if (rc != ECORE_SUCCESS)
2552                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2553
2554                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2555                                                       p_hwfn->p_main_ptt,
2556                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2557                 if (rc != ECORE_SUCCESS)
2558                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2559         }
2560
2561         return rc;
2562
2563 load_err:
2564         /* The MFW load lock should be released regardless of success or failure
2565          * of initialization.
2566          * TODO: replace this with an attempt to send cancel_load.
2567          */
2568         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2569         return rc;
2570 }
2571
2572 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2573 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2574                                  struct ecore_hwfn *p_hwfn,
2575                                  struct ecore_ptt *p_ptt)
2576 {
2577         int i;
2578
2579         /* close timers */
2580         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2581         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2582         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2583                                                                         i++) {
2584                 if ((!ecore_rd(p_hwfn, p_ptt,
2585                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2586                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2587                         break;
2588
2589                 /* Dependent on number of connection/tasks, possibly
2590                  * 1ms sleep is required between polls
2591                  */
2592                 OSAL_MSLEEP(1);
2593         }
2594
2595         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2596                 return;
2597
2598         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2599                   " [Connection %02x Tasks %02x]\n",
2600                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2601                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2602 }
2603
2604 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2605 {
2606         int j;
2607
2608         for_each_hwfn(p_dev, j) {
2609                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2610                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2611
2612                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2613         }
2614 }
2615
2616 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2617                                                  struct ecore_ptt *p_ptt,
2618                                                  u32 addr, u32 expected_val)
2619 {
2620         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2621
2622         if (val != expected_val) {
2623                 DP_NOTICE(p_hwfn, true,
2624                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2625                           addr, val, expected_val);
2626                 return ECORE_UNKNOWN_ERROR;
2627         }
2628
2629         return ECORE_SUCCESS;
2630 }
2631
2632 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2633 {
2634         struct ecore_hwfn *p_hwfn;
2635         struct ecore_ptt *p_ptt;
2636         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2637         int j;
2638
2639         for_each_hwfn(p_dev, j) {
2640                 p_hwfn = &p_dev->hwfns[j];
2641                 p_ptt = p_hwfn->p_main_ptt;
2642
2643                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2644
2645                 if (IS_VF(p_dev)) {
2646                         ecore_vf_pf_int_cleanup(p_hwfn);
2647                         rc = ecore_vf_pf_reset(p_hwfn);
2648                         if (rc != ECORE_SUCCESS) {
2649                                 DP_NOTICE(p_hwfn, true,
2650                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2651                                           rc);
2652                                 rc2 = ECORE_UNKNOWN_ERROR;
2653                         }
2654                         continue;
2655                 }
2656
2657                 /* mark the hw as uninitialized... */
2658                 p_hwfn->hw_init_done = false;
2659
2660                 /* Send unload command to MCP */
2661                 if (!p_dev->recov_in_prog) {
2662                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2663                         if (rc != ECORE_SUCCESS) {
2664                                 DP_NOTICE(p_hwfn, true,
2665                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2666                                           rc);
2667                                 rc2 = ECORE_UNKNOWN_ERROR;
2668                         }
2669                 }
2670
2671                 OSAL_DPC_SYNC(p_hwfn);
2672
2673                 /* After this point no MFW attentions are expected, e.g. prevent
2674                  * race between pf stop and dcbx pf update.
2675                  */
2676
2677                 rc = ecore_sp_pf_stop(p_hwfn);
2678                 if (rc != ECORE_SUCCESS) {
2679                         DP_NOTICE(p_hwfn, true,
2680                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2681                                   rc);
2682                         rc2 = ECORE_UNKNOWN_ERROR;
2683                 }
2684
2685                 /* perform debug action after PF stop was sent */
2686                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2687
2688                 /* close NIG to BRB gate */
2689                 ecore_wr(p_hwfn, p_ptt,
2690                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2691
2692                 /* close parser */
2693                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2694                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2695                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2696                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2697                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2698
2699                 /* @@@TBD - clean transmission queues (5.b) */
2700                 /* @@@TBD - clean BTB (5.c) */
2701
2702                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2703
2704                 /* @@@TBD - verify DMAE requests are done (8) */
2705
2706                 /* Disable Attention Generation */
2707                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2708                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2709                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2710                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2711                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2712                 if (rc != ECORE_SUCCESS) {
2713                         DP_NOTICE(p_hwfn, true,
2714                                   "Failed to return IGU CAM to default\n");
2715                         rc2 = ECORE_UNKNOWN_ERROR;
2716                 }
2717
2718                 /* Need to wait 1ms to guarantee SBs are cleared */
2719                 OSAL_MSLEEP(1);
2720
2721                 if (!p_dev->recov_in_prog) {
2722                         ecore_verify_reg_val(p_hwfn, p_ptt,
2723                                              QM_REG_USG_CNT_PF_TX, 0);
2724                         ecore_verify_reg_val(p_hwfn, p_ptt,
2725                                              QM_REG_USG_CNT_PF_OTHER, 0);
2726                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2727                 }
2728
2729                 /* Disable PF in HW blocks */
2730                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2731                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2732
2733                 if (!p_dev->recov_in_prog) {
2734                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2735                         if (rc != ECORE_SUCCESS) {
2736                                 DP_NOTICE(p_hwfn, true,
2737                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2738                                           rc);
2739                                 rc2 = ECORE_UNKNOWN_ERROR;
2740                         }
2741                 }
2742         } /* hwfn loop */
2743
2744         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2745                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2746                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2747
2748                  /* Clear the PF's internal FID_enable in the PXP.
2749                   * In CMT this should only be done for first hw-function, and
2750                   * only after all transactions have stopped for all active
2751                   * hw-functions.
2752                   */
2753                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2754                                                   false);
2755                 if (rc != ECORE_SUCCESS) {
2756                         DP_NOTICE(p_hwfn, true,
2757                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2758                                   rc);
2759                         rc2 = ECORE_UNKNOWN_ERROR;
2760                 }
2761         }
2762
2763         return rc2;
2764 }
2765
2766 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2767 {
2768         int j;
2769
2770         for_each_hwfn(p_dev, j) {
2771                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2772                 struct ecore_ptt *p_ptt;
2773
2774                 if (IS_VF(p_dev)) {
2775                         ecore_vf_pf_int_cleanup(p_hwfn);
2776                         continue;
2777                 }
2778                 p_ptt = ecore_ptt_acquire(p_hwfn);
2779                 if (!p_ptt)
2780                         return ECORE_AGAIN;
2781
2782                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2783                            "Shutting down the fastpath\n");
2784
2785                 ecore_wr(p_hwfn, p_ptt,
2786                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2787
2788                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2789                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2790                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2791                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2792                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2793
2794                 /* @@@TBD - clean transmission queues (5.b) */
2795                 /* @@@TBD - clean BTB (5.c) */
2796
2797                 /* @@@TBD - verify DMAE requests are done (8) */
2798
2799                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2800                 /* Need to wait 1ms to guarantee SBs are cleared */
2801                 OSAL_MSLEEP(1);
2802                 ecore_ptt_release(p_hwfn, p_ptt);
2803         }
2804
2805         return ECORE_SUCCESS;
2806 }
2807
2808 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2809 {
2810         struct ecore_ptt *p_ptt;
2811
2812         if (IS_VF(p_hwfn->p_dev))
2813                 return ECORE_SUCCESS;
2814
2815         p_ptt = ecore_ptt_acquire(p_hwfn);
2816         if (!p_ptt)
2817                 return ECORE_AGAIN;
2818
2819         /* If roce info is allocated it means roce is initialized and should
2820          * be enabled in searcher.
2821          */
2822         if (p_hwfn->p_rdma_info) {
2823                 if (p_hwfn->b_rdma_enabled_in_prs)
2824                         ecore_wr(p_hwfn, p_ptt,
2825                                  p_hwfn->rdma_prs_search_reg, 0x1);
2826                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2827         }
2828
2829         /* Re-open incoming traffic */
2830         ecore_wr(p_hwfn, p_ptt,
2831                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2832         ecore_ptt_release(p_hwfn, p_ptt);
2833
2834         return ECORE_SUCCESS;
2835 }
2836
2837 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2838 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2839 {
2840         ecore_ptt_pool_free(p_hwfn);
2841         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2842 }
2843
2844 /* Setup bar access */
2845 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2846 {
2847         /* clear indirect access */
2848         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2849                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2850                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2851                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2852                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2853                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2854                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2855                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2856                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2857         } else {
2858                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2859                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2860                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2861                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2862                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2863                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2864                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2865                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2866         }
2867
2868         /* Clean previous pglue_b errors if such exist */
2869         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2870
2871         /* enable internal target-read */
2872         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2873                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2874 }
2875
2876 static void get_function_id(struct ecore_hwfn *p_hwfn)
2877 {
2878         /* ME Register */
2879         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2880                                                   PXP_PF_ME_OPAQUE_ADDR);
2881
2882         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2883
2884         /* Bits 16-19 from the ME registers are the pf_num */
2885         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2886         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2887                                       PXP_CONCRETE_FID_PFID);
2888         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2889                                     PXP_CONCRETE_FID_PORT);
2890
2891         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2892                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2893                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2894 }
2895
2896 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2897 {
2898         u32 *feat_num = p_hwfn->hw_info.feat_num;
2899         struct ecore_sb_cnt_info sb_cnt;
2900         u32 non_l2_sbs = 0;
2901
2902         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2903         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2904
2905         /* L2 Queues require each: 1 status block. 1 L2 queue */
2906         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2907                 /* Start by allocating VF queues, then PF's */
2908                 feat_num[ECORE_VF_L2_QUE] =
2909                         OSAL_MIN_T(u32,
2910                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2911                                    sb_cnt.iov_cnt);
2912                 feat_num[ECORE_PF_L2_QUE] =
2913                         OSAL_MIN_T(u32,
2914                                    sb_cnt.cnt - non_l2_sbs,
2915                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2916                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2917         }
2918
2919         if (ECORE_IS_FCOE_PERSONALITY(p_hwfn))
2920                 feat_num[ECORE_FCOE_CQ] =
2921                         OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2922                                                              ECORE_CMDQS_CQS));
2923
2924         if (ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
2925                 feat_num[ECORE_ISCSI_CQ] =
2926                         OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2927                                                              ECORE_CMDQS_CQS));
2928
2929         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2930                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2931                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2932                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2933                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2934                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2935                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2936                    (int)sb_cnt.cnt);
2937 }
2938
2939 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2940 {
2941         switch (res_id) {
2942         case ECORE_L2_QUEUE:
2943                 return "L2_QUEUE";
2944         case ECORE_VPORT:
2945                 return "VPORT";
2946         case ECORE_RSS_ENG:
2947                 return "RSS_ENG";
2948         case ECORE_PQ:
2949                 return "PQ";
2950         case ECORE_RL:
2951                 return "RL";
2952         case ECORE_MAC:
2953                 return "MAC";
2954         case ECORE_VLAN:
2955                 return "VLAN";
2956         case ECORE_RDMA_CNQ_RAM:
2957                 return "RDMA_CNQ_RAM";
2958         case ECORE_ILT:
2959                 return "ILT";
2960         case ECORE_LL2_QUEUE:
2961                 return "LL2_QUEUE";
2962         case ECORE_CMDQS_CQS:
2963                 return "CMDQS_CQS";
2964         case ECORE_RDMA_STATS_QUEUE:
2965                 return "RDMA_STATS_QUEUE";
2966         case ECORE_BDQ:
2967                 return "BDQ";
2968         case ECORE_SB:
2969                 return "SB";
2970         default:
2971                 return "UNKNOWN_RESOURCE";
2972         }
2973 }
2974
2975 static enum _ecore_status_t
2976 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2977                               struct ecore_ptt *p_ptt,
2978                               enum ecore_resources res_id,
2979                               u32 resc_max_val,
2980                               u32 *p_mcp_resp)
2981 {
2982         enum _ecore_status_t rc;
2983
2984         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2985                                         resc_max_val, p_mcp_resp);
2986         if (rc != ECORE_SUCCESS) {
2987                 DP_NOTICE(p_hwfn, true,
2988                           "MFW response failure for a max value setting of resource %d [%s]\n",
2989                           res_id, ecore_hw_get_resc_name(res_id));
2990                 return rc;
2991         }
2992
2993         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2994                 DP_INFO(p_hwfn,
2995                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2996                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2997
2998         return ECORE_SUCCESS;
2999 }
3000
3001 static enum _ecore_status_t
3002 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3003                             struct ecore_ptt *p_ptt)
3004 {
3005         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3006         u32 resc_max_val, mcp_resp;
3007         u8 res_id;
3008         enum _ecore_status_t rc;
3009
3010         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3011                 /* @DPDK */
3012                 switch (res_id) {
3013                 case ECORE_LL2_QUEUE:
3014                 case ECORE_RDMA_CNQ_RAM:
3015                 case ECORE_RDMA_STATS_QUEUE:
3016                 case ECORE_BDQ:
3017                         resc_max_val = 0;
3018                         break;
3019                 default:
3020                         continue;
3021                 }
3022
3023                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3024                                                    resc_max_val, &mcp_resp);
3025                 if (rc != ECORE_SUCCESS)
3026                         return rc;
3027
3028                 /* There's no point to continue to the next resource if the
3029                  * command is not supported by the MFW.
3030                  * We do continue if the command is supported but the resource
3031                  * is unknown to the MFW. Such a resource will be later
3032                  * configured with the default allocation values.
3033                  */
3034                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3035                         return ECORE_NOTIMPL;
3036         }
3037
3038         return ECORE_SUCCESS;
3039 }
3040
3041 static
3042 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3043                                             enum ecore_resources res_id,
3044                                             u32 *p_resc_num, u32 *p_resc_start)
3045 {
3046         u8 num_funcs = p_hwfn->num_funcs_on_engine;
3047         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3048
3049         switch (res_id) {
3050         case ECORE_L2_QUEUE:
3051                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3052                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
3053                 break;
3054         case ECORE_VPORT:
3055                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3056                                  MAX_NUM_VPORTS_BB) / num_funcs;
3057                 break;
3058         case ECORE_RSS_ENG:
3059                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3060                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3061                 break;
3062         case ECORE_PQ:
3063                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3064                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
3065                 break;
3066         case ECORE_RL:
3067                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3068                 break;
3069         case ECORE_MAC:
3070         case ECORE_VLAN:
3071                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3072                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3073                 break;
3074         case ECORE_ILT:
3075                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3076                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3077                 break;
3078         case ECORE_LL2_QUEUE:
3079                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3080                 break;
3081         case ECORE_RDMA_CNQ_RAM:
3082         case ECORE_CMDQS_CQS:
3083                 /* CNQ/CMDQS are the same resource */
3084                 /* @DPDK */
3085                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3086                 break;
3087         case ECORE_RDMA_STATS_QUEUE:
3088                 /* @DPDK */
3089                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3090                                  MAX_NUM_VPORTS_BB) / num_funcs;
3091                 break;
3092         case ECORE_BDQ:
3093                 /* @DPDK */
3094                 *p_resc_num = 0;
3095                 break;
3096         default:
3097                 break;
3098         }
3099
3100
3101         switch (res_id) {
3102         case ECORE_BDQ:
3103                 if (!*p_resc_num)
3104                         *p_resc_start = 0;
3105                 break;
3106         case ECORE_SB:
3107                 /* Since we want its value to reflect whether MFW supports
3108                  * the new scheme, have a default of 0.
3109                  */
3110                 *p_resc_num = 0;
3111                 break;
3112         default:
3113                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3114                 break;
3115         }
3116
3117         return ECORE_SUCCESS;
3118 }
3119
3120 static enum _ecore_status_t
3121 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3122                          bool drv_resc_alloc)
3123 {
3124         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3125         u32 mcp_resp, *p_resc_num, *p_resc_start;
3126         enum _ecore_status_t rc;
3127
3128         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3129         p_resc_start = &RESC_START(p_hwfn, res_id);
3130
3131         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3132                                     &dflt_resc_start);
3133         if (rc != ECORE_SUCCESS) {
3134                 DP_ERR(p_hwfn,
3135                        "Failed to get default amount for resource %d [%s]\n",
3136                         res_id, ecore_hw_get_resc_name(res_id));
3137                 return rc;
3138         }
3139
3140 #ifndef ASIC_ONLY
3141         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3142                 *p_resc_num = dflt_resc_num;
3143                 *p_resc_start = dflt_resc_start;
3144                 goto out;
3145         }
3146 #endif
3147
3148         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3149                                      &mcp_resp, p_resc_num, p_resc_start);
3150         if (rc != ECORE_SUCCESS) {
3151                 DP_NOTICE(p_hwfn, true,
3152                           "MFW response failure for an allocation request for"
3153                           " resource %d [%s]\n",
3154                           res_id, ecore_hw_get_resc_name(res_id));
3155                 return rc;
3156         }
3157
3158         /* Default driver values are applied in the following cases:
3159          * - The resource allocation MB command is not supported by the MFW
3160          * - There is an internal error in the MFW while processing the request
3161          * - The resource ID is unknown to the MFW
3162          */
3163         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3164                 DP_INFO(p_hwfn,
3165                         "Failed to receive allocation info for resource %d [%s]."
3166                         " mcp_resp = 0x%x. Applying default values"
3167                         " [%d,%d].\n",
3168                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3169                         dflt_resc_num, dflt_resc_start);
3170
3171                 *p_resc_num = dflt_resc_num;
3172                 *p_resc_start = dflt_resc_start;
3173                 goto out;
3174         }
3175
3176         if ((*p_resc_num != dflt_resc_num ||
3177              *p_resc_start != dflt_resc_start) &&
3178             res_id != ECORE_SB) {
3179                 DP_INFO(p_hwfn,
3180                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3181                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3182                         *p_resc_start, dflt_resc_num, dflt_resc_start,
3183                         drv_resc_alloc ? " - Applying default values" : "");
3184                 if (drv_resc_alloc) {
3185                         *p_resc_num = dflt_resc_num;
3186                         *p_resc_start = dflt_resc_start;
3187                 }
3188         }
3189 out:
3190         return ECORE_SUCCESS;
3191 }
3192
3193 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3194                                                    bool drv_resc_alloc)
3195 {
3196         enum _ecore_status_t rc;
3197         u8 res_id;
3198
3199         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3200                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3201                 if (rc != ECORE_SUCCESS)
3202                         return rc;
3203         }
3204
3205         return ECORE_SUCCESS;
3206 }
3207
3208 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3209                                               struct ecore_ptt *p_ptt,
3210                                               bool drv_resc_alloc)
3211 {
3212         struct ecore_resc_unlock_params resc_unlock_params;
3213         struct ecore_resc_lock_params resc_lock_params;
3214         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3215         u8 res_id;
3216         enum _ecore_status_t rc;
3217 #ifndef ASIC_ONLY
3218         u32 *resc_start = p_hwfn->hw_info.resc_start;
3219         u32 *resc_num = p_hwfn->hw_info.resc_num;
3220         /* For AH, an equal share of the ILT lines between the maximal number of
3221          * PFs is not enough for RoCE. This would be solved by the future
3222          * resource allocation scheme, but isn't currently present for
3223          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3224          * to work - the BB number of ILT lines divided by its max PFs number.
3225          */
3226         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3227 #endif
3228
3229         /* Setting the max values of the soft resources and the following
3230          * resources allocation queries should be atomic. Since several PFs can
3231          * run in parallel - a resource lock is needed.
3232          * If either the resource lock or resource set value commands are not
3233          * supported - skip the max values setting, release the lock if
3234          * needed, and proceed to the queries. Other failures, including a
3235          * failure to acquire the lock, will cause this function to fail.
3236          * Old drivers that don't acquire the lock can run in parallel, and
3237          * their allocation values won't be affected by the updated max values.
3238          */
3239         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3240                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
3241
3242         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3243         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3244                 return rc;
3245         } else if (rc == ECORE_NOTIMPL) {
3246                 DP_INFO(p_hwfn,
3247                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3248         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3249                 DP_NOTICE(p_hwfn, false,
3250                           "Failed to acquire the resource lock for the resource allocation commands\n");
3251                 rc = ECORE_BUSY;
3252                 goto unlock_and_exit;
3253         } else {
3254                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3255                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3256                         DP_NOTICE(p_hwfn, false,
3257                                   "Failed to set the max values of the soft resources\n");
3258                         goto unlock_and_exit;
3259                 } else if (rc == ECORE_NOTIMPL) {
3260                         DP_INFO(p_hwfn,
3261                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3262                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3263                                                    &resc_unlock_params);
3264                         if (rc != ECORE_SUCCESS)
3265                                 DP_INFO(p_hwfn,
3266                                         "Failed to release the resource lock for the resource allocation commands\n");
3267                 }
3268         }
3269
3270         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3271         if (rc != ECORE_SUCCESS)
3272                 goto unlock_and_exit;
3273
3274         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3275                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3276                                            &resc_unlock_params);
3277                 if (rc != ECORE_SUCCESS)
3278                         DP_INFO(p_hwfn,
3279                                 "Failed to release the resource lock for the resource allocation commands\n");
3280         }
3281
3282 #ifndef ASIC_ONLY
3283         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3284                 /* Reduced build contains less PQs */
3285                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3286                         resc_num[ECORE_PQ] = 32;
3287                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3288                             p_hwfn->enabled_func_idx;
3289                 }
3290
3291                 /* For AH emulation, since we have a possible maximal number of
3292                  * 16 enabled PFs, in case there are not enough ILT lines -
3293                  * allocate only first PF as RoCE and have all the other ETH
3294                  * only with less ILT lines.
3295                  */
3296                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3297                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3298                                                          resc_num[ECORE_ILT],
3299                                                          roce_min_ilt_lines);
3300         }
3301
3302         /* Correct the common ILT calculation if PF0 has more */
3303         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3304             p_hwfn->p_dev->b_is_emul_full &&
3305             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3306                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3307                     resc_num[ECORE_ILT];
3308 #endif
3309
3310         /* Sanity for ILT */
3311         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3312             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3313                 DP_NOTICE(p_hwfn, true,
3314                           "Can't assign ILT pages [%08x,...,%08x]\n",
3315                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3316                                                                   ECORE_ILT) -
3317                           1);
3318                 return ECORE_INVAL;
3319         }
3320
3321         /* This will also learn the number of SBs from MFW */
3322         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3323                 return ECORE_INVAL;
3324
3325         ecore_hw_set_feat(p_hwfn);
3326
3327         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3328                    "The numbers for each resource are:\n");
3329         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3330                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3331                            ecore_hw_get_resc_name(res_id),
3332                            RESC_NUM(p_hwfn, res_id),
3333                            RESC_START(p_hwfn, res_id));
3334
3335         return ECORE_SUCCESS;
3336
3337 unlock_and_exit:
3338         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3339                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3340                                       &resc_unlock_params);
3341         return rc;
3342 }
3343
3344 static enum _ecore_status_t
3345 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3346                       struct ecore_ptt *p_ptt,
3347                       struct ecore_hw_prepare_params *p_params)
3348 {
3349         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3350         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3351         struct ecore_mcp_link_capabilities *p_caps;
3352         struct ecore_mcp_link_params *link;
3353         enum _ecore_status_t rc;
3354
3355         /* Read global nvm_cfg address */
3356         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3357
3358         /* Verify MCP has initialized it */
3359         if (!nvm_cfg_addr) {
3360                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3361                 if (p_params->b_relaxed_probe)
3362                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3363                 return ECORE_INVAL;
3364         }
3365
3366 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3367
3368         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3369
3370         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3371                    OFFSETOF(struct nvm_cfg1, glob) +
3372                    OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3373
3374         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3375
3376         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3377                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3378         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3379                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3380                 break;
3381         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3382                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3383                 break;
3384         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3385                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3386                 break;
3387         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3388                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3389                 break;
3390         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3391                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3392                 break;
3393         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3394                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3395                 break;
3396         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3397                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3398                 break;
3399         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3400                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3401                 break;
3402         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3403                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3404                 break;
3405         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3406                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3407                 break;
3408         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3409                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3410                 break;
3411         default:
3412                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3413                           core_cfg);
3414                 break;
3415         }
3416
3417         /* Read DCBX configuration */
3418         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3419                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3420         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3421                              port_cfg_addr +
3422                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3423         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3424                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3425         switch (dcbx_mode) {
3426         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3427                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3428                 break;
3429         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3430                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3431                 break;
3432         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3433                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3434                 break;
3435         default:
3436                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3437         }
3438
3439         /* Read default link configuration */
3440         link = &p_hwfn->mcp_info->link_input;
3441         p_caps = &p_hwfn->mcp_info->link_capabilities;
3442         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3443             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3444         link_temp = ecore_rd(p_hwfn, p_ptt,
3445                              port_cfg_addr +
3446                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3447         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3448         link->speed.advertised_speeds = link_temp;
3449         p_caps->speed_capabilities = link->speed.advertised_speeds;
3450
3451         link_temp = ecore_rd(p_hwfn, p_ptt,
3452                                  port_cfg_addr +
3453                                  OFFSETOF(struct nvm_cfg1_port, link_settings));
3454         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3455                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3456         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3457                 link->speed.autoneg = true;
3458                 break;
3459         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3460                 link->speed.forced_speed = 1000;
3461                 break;
3462         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3463                 link->speed.forced_speed = 10000;
3464                 break;
3465         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3466                 link->speed.forced_speed = 25000;
3467                 break;
3468         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3469                 link->speed.forced_speed = 40000;
3470                 break;
3471         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3472                 link->speed.forced_speed = 50000;
3473                 break;
3474         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3475                 link->speed.forced_speed = 100000;
3476                 break;
3477         default:
3478                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3479         }
3480
3481         p_caps->default_speed = link->speed.forced_speed;
3482         p_caps->default_speed_autoneg = link->speed.autoneg;
3483
3484         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3485         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3486         link->pause.autoneg = !!(link_temp &
3487                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3488         link->pause.forced_rx = !!(link_temp &
3489                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3490         link->pause.forced_tx = !!(link_temp &
3491                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3492         link->loopback_mode = 0;
3493
3494         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3495                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3496                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3497                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3498                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3499                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3500                 link->eee.enable = true;
3501                 switch (link_temp) {
3502                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3503                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3504                         link->eee.enable = false;
3505                         break;
3506                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3507                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3508                         break;
3509                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3510                         p_caps->eee_lpi_timer =
3511                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3512                         break;
3513                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3514                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3515                         break;
3516                 }
3517
3518                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3519                 link->eee.tx_lpi_enable = link->eee.enable;
3520                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3521         } else {
3522                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3523         }
3524
3525         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3526                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3527                    link->speed.forced_speed, link->speed.advertised_speeds,
3528                    link->speed.autoneg, link->pause.autoneg,
3529                    p_caps->default_eee, p_caps->eee_lpi_timer);
3530
3531         /* Read Multi-function information from shmem */
3532         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3533                    OFFSETOF(struct nvm_cfg1, glob) +
3534                    OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3535
3536         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3537
3538         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3539             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3540
3541         switch (mf_mode) {
3542         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3543                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3544                 break;
3545         case NVM_CFG1_GLOB_MF_MODE_UFP:
3546                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3547                                          1 << ECORE_MF_UFP_SPECIFIC;
3548                 break;
3549
3550         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3551                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3552                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3553                                          1 << ECORE_MF_LL2_NON_UNICAST |
3554                                          1 << ECORE_MF_INTER_PF_SWITCH |
3555                                          1 << ECORE_MF_DISABLE_ARFS;
3556                 break;
3557         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3558                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3559                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3560                                          1 << ECORE_MF_LL2_NON_UNICAST;
3561                 if (ECORE_IS_BB(p_hwfn->p_dev))
3562                         p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3563                 break;
3564         }
3565         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3566                 p_hwfn->p_dev->mf_bits);
3567
3568         if (ECORE_IS_CMT(p_hwfn->p_dev))
3569                 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3570
3571         /* It's funny since we have another switch, but it's easier
3572          * to throw this away in linux this way. Long term, it might be
3573          * better to have have getters for needed ECORE_MF_* fields,
3574          * convert client code and eliminate this.
3575          */
3576         switch (mf_mode) {
3577         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3578                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3579                 break;
3580         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3581                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3582                 break;
3583         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3584                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3585                 break;
3586         case NVM_CFG1_GLOB_MF_MODE_UFP:
3587                 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3588                 break;
3589         }
3590
3591         /* Read Multi-function information from shmem */
3592         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3593                    OFFSETOF(struct nvm_cfg1, glob) +
3594                    OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3595
3596         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3597         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3598                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3599                                 &p_hwfn->hw_info.device_capabilities);
3600         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3601                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3602                                 &p_hwfn->hw_info.device_capabilities);
3603         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3604                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3605                                 &p_hwfn->hw_info.device_capabilities);
3606         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3607                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3608                                 &p_hwfn->hw_info.device_capabilities);
3609         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3610                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3611                                 &p_hwfn->hw_info.device_capabilities);
3612
3613         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3614         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3615                 rc = ECORE_SUCCESS;
3616                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3617         }
3618
3619         return rc;
3620 }
3621
3622 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3623                                 struct ecore_ptt *p_ptt)
3624 {
3625         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3626         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3627         struct ecore_dev *p_dev = p_hwfn->p_dev;
3628
3629         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3630
3631         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3632          * in the other bits are selected.
3633          * Bits 1-15 are for functions 1-15, respectively, and their value is
3634          * '0' only for enabled functions (function 0 always exists and
3635          * enabled).
3636          * In case of CMT in BB, only the "even" functions are enabled, and thus
3637          * the number of functions for both hwfns is learnt from the same bits.
3638          */
3639         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3640                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3641                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3642         } else { /* E5 */
3643                 reg_function_hide = 0;
3644         }
3645
3646         if (reg_function_hide & 0x1) {
3647                 if (ECORE_IS_BB(p_dev)) {
3648                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3649                                 num_funcs = 0;
3650                                 eng_mask = 0xaaaa;
3651                         } else {
3652                                 num_funcs = 1;
3653                                 eng_mask = 0x5554;
3654                         }
3655                 } else {
3656                         num_funcs = 1;
3657                         eng_mask = 0xfffe;
3658                 }
3659
3660                 /* Get the number of the enabled functions on the engine */
3661                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3662                 while (tmp) {
3663                         if (tmp & 0x1)
3664                                 num_funcs++;
3665                         tmp >>= 0x1;
3666                 }
3667
3668                 /* Get the PF index within the enabled functions */
3669                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3670                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3671                 while (tmp) {
3672                         if (tmp & 0x1)
3673                                 enabled_func_idx--;
3674                         tmp >>= 0x1;
3675                 }
3676         }
3677
3678         p_hwfn->num_funcs_on_engine = num_funcs;
3679         p_hwfn->enabled_func_idx = enabled_func_idx;
3680
3681 #ifndef ASIC_ONLY
3682         if (CHIP_REV_IS_FPGA(p_dev)) {
3683                 DP_NOTICE(p_hwfn, false,
3684                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3685                 p_hwfn->num_funcs_on_engine = 4;
3686         }
3687 #endif
3688
3689         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3690                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3691                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3692                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3693 }
3694
3695 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3696                                       struct ecore_ptt *p_ptt)
3697 {
3698         struct ecore_dev *p_dev = p_hwfn->p_dev;
3699         u32 port_mode;
3700
3701 #ifndef ASIC_ONLY
3702         /* Read the port mode */
3703         if (CHIP_REV_IS_FPGA(p_dev))
3704                 port_mode = 4;
3705         else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3706                 /* In CMT on emulation, assume 1 port */
3707                 port_mode = 1;
3708         else
3709 #endif
3710         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3711
3712         if (port_mode < 3) {
3713                 p_dev->num_ports_in_engine = 1;
3714         } else if (port_mode <= 5) {
3715                 p_dev->num_ports_in_engine = 2;
3716         } else {
3717                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3718                           p_dev->num_ports_in_engine);
3719
3720                 /* Default num_ports_in_engine to something */
3721                 p_dev->num_ports_in_engine = 1;
3722         }
3723 }
3724
3725 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3726                                          struct ecore_ptt *p_ptt)
3727 {
3728         struct ecore_dev *p_dev = p_hwfn->p_dev;
3729         u32 port;
3730         int i;
3731
3732         p_dev->num_ports_in_engine = 0;
3733
3734 #ifndef ASIC_ONLY
3735         if (CHIP_REV_IS_EMUL(p_dev)) {
3736                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3737                 switch ((port & 0xf000) >> 12) {
3738                 case 1:
3739                         p_dev->num_ports_in_engine = 1;
3740                         break;
3741                 case 3:
3742                         p_dev->num_ports_in_engine = 2;
3743                         break;
3744                 case 0xf:
3745                         p_dev->num_ports_in_engine = 4;
3746                         break;
3747                 default:
3748                         DP_NOTICE(p_hwfn, false,
3749                                   "Unknown port mode in ECO_RESERVED %08x\n",
3750                                   port);
3751                 }
3752         } else
3753 #endif
3754                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3755                         port = ecore_rd(p_hwfn, p_ptt,
3756                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3757                                         (i * 4));
3758                         if (port & 1)
3759                                 p_dev->num_ports_in_engine++;
3760                 }
3761
3762         if (!p_dev->num_ports_in_engine) {
3763                 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3764
3765                 /* Default num_ports_in_engine to something */
3766                 p_dev->num_ports_in_engine = 1;
3767         }
3768 }
3769
3770 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3771                                    struct ecore_ptt *p_ptt)
3772 {
3773         struct ecore_dev *p_dev = p_hwfn->p_dev;
3774
3775         /* Determine the number of ports per engine */
3776         if (ECORE_IS_BB(p_dev))
3777                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3778         else
3779                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3780
3781         /* Get the total number of ports of the device */
3782         if (ECORE_IS_CMT(p_dev)) {
3783                 /* In CMT there is always only one port */
3784                 p_dev->num_ports = 1;
3785 #ifndef ASIC_ONLY
3786         } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3787                 p_dev->num_ports = p_dev->num_ports_in_engine *
3788                                    ecore_device_num_engines(p_dev);
3789 #endif
3790         } else {
3791                 u32 addr, global_offsize, global_addr;
3792
3793                 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3794                                             PUBLIC_GLOBAL);
3795                 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3796                 global_addr = SECTION_ADDR(global_offsize, 0);
3797                 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3798                 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3799         }
3800 }
3801
3802 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3803                                    struct ecore_ptt *p_ptt)
3804 {
3805         struct ecore_mcp_link_capabilities *p_caps;
3806         u32 eee_status;
3807
3808         p_caps = &p_hwfn->mcp_info->link_capabilities;
3809         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3810                 return;
3811
3812         p_caps->eee_speed_caps = 0;
3813         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3814                               OFFSETOF(struct public_port, eee_status));
3815         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3816                         EEE_SUPPORTED_SPEED_OFFSET;
3817         if (eee_status & EEE_1G_SUPPORTED)
3818                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3819         if (eee_status & EEE_10G_ADV)
3820                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3821 }
3822
3823 static enum _ecore_status_t
3824 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3825                   enum ecore_pci_personality personality,
3826                   struct ecore_hw_prepare_params *p_params)
3827 {
3828         bool drv_resc_alloc = p_params->drv_resc_alloc;
3829         enum _ecore_status_t rc;
3830
3831         /* Since all information is common, only first hwfns should do this */
3832         if (IS_LEAD_HWFN(p_hwfn)) {
3833                 rc = ecore_iov_hw_info(p_hwfn);
3834                 if (rc != ECORE_SUCCESS) {
3835                         if (p_params->b_relaxed_probe)
3836                                 p_params->p_relaxed_res =
3837                                                 ECORE_HW_PREPARE_BAD_IOV;
3838                         else
3839                                 return rc;
3840                 }
3841         }
3842
3843         if (IS_LEAD_HWFN(p_hwfn))
3844                 ecore_hw_info_port_num(p_hwfn, p_ptt);
3845
3846         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3847
3848 #ifndef ASIC_ONLY
3849         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3850 #endif
3851         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3852         if (rc != ECORE_SUCCESS)
3853                 return rc;
3854 #ifndef ASIC_ONLY
3855         }
3856 #endif
3857
3858         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3859         if (rc != ECORE_SUCCESS) {
3860                 if (p_params->b_relaxed_probe)
3861                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3862                 else
3863                         return rc;
3864         }
3865
3866 #ifndef ASIC_ONLY
3867         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3868 #endif
3869                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3870                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3871 #ifndef ASIC_ONLY
3872         } else {
3873                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3874
3875                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3876                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3877         }
3878 #endif
3879
3880         if (ecore_mcp_is_init(p_hwfn)) {
3881                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3882                         p_hwfn->hw_info.ovlan =
3883                             p_hwfn->mcp_info->func_info.ovlan;
3884
3885                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3886
3887                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3888
3889                 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
3890         }
3891
3892         if (personality != ECORE_PCI_DEFAULT) {
3893                 p_hwfn->hw_info.personality = personality;
3894         } else if (ecore_mcp_is_init(p_hwfn)) {
3895                 enum ecore_pci_personality protocol;
3896
3897                 protocol = p_hwfn->mcp_info->func_info.protocol;
3898                 p_hwfn->hw_info.personality = protocol;
3899         }
3900
3901 #ifndef ASIC_ONLY
3902         /* To overcome ILT lack for emulation, until at least until we'll have
3903          * a definite answer from system about it, allow only PF0 to be RoCE.
3904          */
3905         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3906                 if (!p_hwfn->rel_pf_id)
3907                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3908                 else
3909                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3910         }
3911 #endif
3912
3913         /* although in BB some constellations may support more than 4 tcs,
3914          * that can result in performance penalty in some cases. 4
3915          * represents a good tradeoff between performance and flexibility.
3916          */
3917         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3918
3919         /* start out with a single active tc. This can be increased either
3920          * by dcbx negotiation or by upper layer driver
3921          */
3922         p_hwfn->hw_info.num_active_tc = 1;
3923
3924         ecore_get_num_funcs(p_hwfn, p_ptt);
3925
3926         if (ecore_mcp_is_init(p_hwfn))
3927                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3928
3929         /* In case of forcing the driver's default resource allocation, calling
3930          * ecore_hw_get_resc() should come after initializing the personality
3931          * and after getting the number of functions, since the calculation of
3932          * the resources/features depends on them.
3933          * This order is not harmful if not forcing.
3934          */
3935         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3936         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3937                 rc = ECORE_SUCCESS;
3938                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3939         }
3940
3941         return rc;
3942 }
3943
3944 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3945                                                struct ecore_ptt *p_ptt)
3946 {
3947         struct ecore_dev *p_dev = p_hwfn->p_dev;
3948         u16 device_id_mask;
3949         u32 tmp;
3950
3951         /* Read Vendor Id / Device Id */
3952         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3953                                   &p_dev->vendor_id);
3954         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3955                                   &p_dev->device_id);
3956
3957         /* Determine type */
3958         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3959         switch (device_id_mask) {
3960         case ECORE_DEV_ID_MASK_BB:
3961                 p_dev->type = ECORE_DEV_TYPE_BB;
3962                 break;
3963         case ECORE_DEV_ID_MASK_AH:
3964                 p_dev->type = ECORE_DEV_TYPE_AH;
3965                 break;
3966         default:
3967                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3968                           p_dev->device_id);
3969                 return ECORE_ABORTED;
3970         }
3971
3972         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3973         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
3974         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3975         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
3976
3977         /* Learn number of HW-functions */
3978         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3979
3980         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3981                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3982                 p_dev->num_hwfns = 2;
3983         } else {
3984                 p_dev->num_hwfns = 1;
3985         }
3986
3987 #ifndef ASIC_ONLY
3988         if (CHIP_REV_IS_EMUL(p_dev)) {
3989                 /* For some reason we have problems with this register
3990                  * in B0 emulation; Simply assume no CMT
3991                  */
3992                 DP_NOTICE(p_dev->hwfns, false,
3993                           "device on emul - assume no CMT\n");
3994                 p_dev->num_hwfns = 1;
3995         }
3996 #endif
3997
3998         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
3999         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
4000         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4001         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
4002
4003         DP_INFO(p_dev->hwfns,
4004                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
4005                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
4006                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
4007                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
4008                 p_dev->chip_metal);
4009
4010         if (ECORE_IS_BB_A0(p_dev)) {
4011                 DP_NOTICE(p_dev->hwfns, false,
4012                           "The chip type/rev (BB A0) is not supported!\n");
4013                 return ECORE_ABORTED;
4014         }
4015 #ifndef ASIC_ONLY
4016         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
4017                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
4018
4019         if (CHIP_REV_IS_EMUL(p_dev)) {
4020                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
4021                 if (tmp & (1 << 29)) {
4022                         DP_NOTICE(p_hwfn, false,
4023                                   "Emulation: Running on a FULL build\n");
4024                         p_dev->b_is_emul_full = true;
4025                 } else {
4026                         DP_NOTICE(p_hwfn, false,
4027                                   "Emulation: Running on a REDUCED build\n");
4028                 }
4029         }
4030 #endif
4031
4032         return ECORE_SUCCESS;
4033 }
4034
4035 #ifndef LINUX_REMOVE
4036 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
4037 {
4038         int j;
4039
4040         if (IS_VF(p_dev))
4041                 return;
4042
4043         for_each_hwfn(p_dev, j) {
4044                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4045
4046                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4047                            "Mark hw/fw uninitialized\n");
4048
4049                 p_hwfn->hw_init_done = false;
4050
4051                 ecore_ptt_invalidate(p_hwfn);
4052         }
4053 }
4054 #endif
4055
4056 static enum _ecore_status_t
4057 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4058                         void OSAL_IOMEM * p_regview,
4059                         void OSAL_IOMEM * p_doorbells,
4060                         struct ecore_hw_prepare_params *p_params)
4061 {
4062         struct ecore_mdump_retain_data mdump_retain;
4063         struct ecore_dev *p_dev = p_hwfn->p_dev;
4064         struct ecore_mdump_info mdump_info;
4065         enum _ecore_status_t rc = ECORE_SUCCESS;
4066
4067         /* Split PCI bars evenly between hwfns */
4068         p_hwfn->regview = p_regview;
4069         p_hwfn->doorbells = p_doorbells;
4070
4071         if (IS_VF(p_dev))
4072                 return ecore_vf_hw_prepare(p_hwfn);
4073
4074         /* Validate that chip access is feasible */
4075         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4076                 DP_ERR(p_hwfn,
4077                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4078                 if (p_params->b_relaxed_probe)
4079                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4080                 return ECORE_INVAL;
4081         }
4082
4083         get_function_id(p_hwfn);
4084
4085         /* Allocate PTT pool */
4086         rc = ecore_ptt_pool_alloc(p_hwfn);
4087         if (rc) {
4088                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
4089                 if (p_params->b_relaxed_probe)
4090                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4091                 goto err0;
4092         }
4093
4094         /* Allocate the main PTT */
4095         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4096
4097         /* First hwfn learns basic information, e.g., number of hwfns */
4098         if (!p_hwfn->my_id) {
4099                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4100                 if (rc != ECORE_SUCCESS) {
4101                         if (p_params->b_relaxed_probe)
4102                                 p_params->p_relaxed_res =
4103                                         ECORE_HW_PREPARE_FAILED_DEV;
4104                         goto err1;
4105                 }
4106         }
4107
4108         ecore_hw_hwfn_prepare(p_hwfn);
4109
4110         /* Initialize MCP structure */
4111         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4112         if (rc) {
4113                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
4114                 if (p_params->b_relaxed_probe)
4115                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4116                 goto err1;
4117         }
4118
4119         /* Read the device configuration information from the HW and SHMEM */
4120         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4121                                p_params->personality, p_params);
4122         if (rc) {
4123                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
4124                 goto err2;
4125         }
4126
4127         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4128          * called, since among others it sets the ports number in an engine.
4129          */
4130         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4131             !p_dev->recov_in_prog) {
4132                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4133                 if (rc != ECORE_SUCCESS)
4134                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4135         }
4136
4137         /* Check if mdump logs/data are present and update the epoch value */
4138         if (IS_LEAD_HWFN(p_hwfn)) {
4139 #ifndef ASIC_ONLY
4140                 if (!CHIP_REV_IS_EMUL(p_dev)) {
4141 #endif
4142                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4143                                               &mdump_info);
4144                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4145                         DP_NOTICE(p_hwfn, false,
4146                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4147
4148                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4149                                                 &mdump_retain);
4150                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4151                         DP_NOTICE(p_hwfn, false,
4152                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4153                                   mdump_retain.epoch, mdump_retain.pf,
4154                                   mdump_retain.status);
4155
4156                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4157                                            p_params->epoch);
4158 #ifndef ASIC_ONLY
4159                 }
4160 #endif
4161         }
4162
4163         /* Allocate the init RT array and initialize the init-ops engine */
4164         rc = ecore_init_alloc(p_hwfn);
4165         if (rc) {
4166                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
4167                 if (p_params->b_relaxed_probe)
4168                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4169                 goto err2;
4170         }
4171 #ifndef ASIC_ONLY
4172         if (CHIP_REV_IS_FPGA(p_dev)) {
4173                 DP_NOTICE(p_hwfn, false,
4174                           "FPGA: workaround; Prevent DMAE parities\n");
4175                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4176                          7);
4177
4178                 DP_NOTICE(p_hwfn, false,
4179                           "FPGA: workaround: Set VF bar0 size\n");
4180                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4181                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4182         }
4183 #endif
4184
4185         return rc;
4186 err2:
4187         if (IS_LEAD_HWFN(p_hwfn))
4188                 ecore_iov_free_hw_info(p_dev);
4189         ecore_mcp_free(p_hwfn);
4190 err1:
4191         ecore_hw_hwfn_free(p_hwfn);
4192 err0:
4193         return rc;
4194 }
4195
4196 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4197                                       struct ecore_hw_prepare_params *p_params)
4198 {
4199         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4200         enum _ecore_status_t rc;
4201
4202         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4203         p_dev->allow_mdump = p_params->allow_mdump;
4204
4205         if (p_params->b_relaxed_probe)
4206                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4207
4208         /* Store the precompiled init data ptrs */
4209         if (IS_PF(p_dev))
4210                 ecore_init_iro_array(p_dev);
4211
4212         /* Initialize the first hwfn - will learn number of hwfns */
4213         rc = ecore_hw_prepare_single(p_hwfn,
4214                                      p_dev->regview,
4215                                      p_dev->doorbells, p_params);
4216         if (rc != ECORE_SUCCESS)
4217                 return rc;
4218
4219         p_params->personality = p_hwfn->hw_info.personality;
4220
4221         /* initilalize 2nd hwfn if necessary */
4222         if (ECORE_IS_CMT(p_dev)) {
4223                 void OSAL_IOMEM *p_regview, *p_doorbell;
4224                 u8 OSAL_IOMEM *addr;
4225
4226                 /* adjust bar offset for second engine */
4227                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4228                                         ecore_hw_bar_size(p_hwfn,
4229                                                           p_hwfn->p_main_ptt,
4230                                                           BAR_ID_0) / 2;
4231                 p_regview = (void OSAL_IOMEM *)addr;
4232
4233                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4234                                         ecore_hw_bar_size(p_hwfn,
4235                                                           p_hwfn->p_main_ptt,
4236                                                           BAR_ID_1) / 2;
4237                 p_doorbell = (void OSAL_IOMEM *)addr;
4238
4239                 /* prepare second hw function */
4240                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4241                                              p_doorbell, p_params);
4242
4243                 /* in case of error, need to free the previously
4244                  * initiliazed hwfn 0.
4245                  */
4246                 if (rc != ECORE_SUCCESS) {
4247                         if (p_params->b_relaxed_probe)
4248                                 p_params->p_relaxed_res =
4249                                                 ECORE_HW_PREPARE_FAILED_ENG2;
4250
4251                         if (IS_PF(p_dev)) {
4252                                 ecore_init_free(p_hwfn);
4253                                 ecore_mcp_free(p_hwfn);
4254                                 ecore_hw_hwfn_free(p_hwfn);
4255                         } else {
4256                                 DP_NOTICE(p_dev, true,
4257                                           "What do we need to free when VF hwfn1 init fails\n");
4258                         }
4259                         return rc;
4260                 }
4261         }
4262
4263         return rc;
4264 }
4265
4266 void ecore_hw_remove(struct ecore_dev *p_dev)
4267 {
4268         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4269         int i;
4270
4271         if (IS_PF(p_dev))
4272                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4273                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
4274
4275         for_each_hwfn(p_dev, i) {
4276                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4277
4278                 if (IS_VF(p_dev)) {
4279                         ecore_vf_pf_release(p_hwfn);
4280                         continue;
4281                 }
4282
4283                 ecore_init_free(p_hwfn);
4284                 ecore_hw_hwfn_free(p_hwfn);
4285                 ecore_mcp_free(p_hwfn);
4286
4287 #ifdef CONFIG_ECORE_LOCK_ALLOC
4288                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
4289 #endif
4290         }
4291
4292         ecore_iov_free_hw_info(p_dev);
4293 }
4294
4295 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4296                                       struct ecore_chain *p_chain)
4297 {
4298         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4299         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4300         struct ecore_chain_next *p_next;
4301         u32 size, i;
4302
4303         if (!p_virt)
4304                 return;
4305
4306         size = p_chain->elem_size * p_chain->usable_per_page;
4307
4308         for (i = 0; i < p_chain->page_cnt; i++) {
4309                 if (!p_virt)
4310                         break;
4311
4312                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4313                 p_virt_next = p_next->next_virt;
4314                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4315
4316                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4317                                        ECORE_CHAIN_PAGE_SIZE);
4318
4319                 p_virt = p_virt_next;
4320                 p_phys = p_phys_next;
4321         }
4322 }
4323
4324 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4325                                     struct ecore_chain *p_chain)
4326 {
4327         if (!p_chain->p_virt_addr)
4328                 return;
4329
4330         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4331                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4332 }
4333
4334 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4335                                  struct ecore_chain *p_chain)
4336 {
4337         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4338         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4339         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4340
4341         if (!pp_virt_addr_tbl)
4342                 return;
4343
4344         if (!p_pbl_virt)
4345                 goto out;
4346
4347         for (i = 0; i < page_cnt; i++) {
4348                 if (!pp_virt_addr_tbl[i])
4349                         break;
4350
4351                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4352                                        *(dma_addr_t *)p_pbl_virt,
4353                                        ECORE_CHAIN_PAGE_SIZE);
4354
4355                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4356         }
4357
4358         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4359
4360         if (!p_chain->b_external_pbl)
4361                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4362                                        p_chain->pbl_sp.p_phys_table, pbl_size);
4363 out:
4364         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4365 }
4366
4367 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4368 {
4369         switch (p_chain->mode) {
4370         case ECORE_CHAIN_MODE_NEXT_PTR:
4371                 ecore_chain_free_next_ptr(p_dev, p_chain);
4372                 break;
4373         case ECORE_CHAIN_MODE_SINGLE:
4374                 ecore_chain_free_single(p_dev, p_chain);
4375                 break;
4376         case ECORE_CHAIN_MODE_PBL:
4377                 ecore_chain_free_pbl(p_dev, p_chain);
4378                 break;
4379         }
4380 }
4381
4382 static enum _ecore_status_t
4383 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4384                                enum ecore_chain_cnt_type cnt_type,
4385                                osal_size_t elem_size, u32 page_cnt)
4386 {
4387         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4388
4389         /* The actual chain size can be larger than the maximal possible value
4390          * after rounding up the requested elements number to pages, and after
4391          * taking into acount the unusuable elements (next-ptr elements).
4392          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4393          * size/capacity fields are of a u32 type.
4394          */
4395         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4396              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4397             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4398              chain_size > ECORE_U32_MAX)) {
4399                 DP_NOTICE(p_dev, true,
4400                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4401                           (unsigned long)chain_size);
4402                 return ECORE_INVAL;
4403         }
4404
4405         return ECORE_SUCCESS;
4406 }
4407
4408 static enum _ecore_status_t
4409 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4410 {
4411         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4412         dma_addr_t p_phys = 0;
4413         u32 i;
4414
4415         for (i = 0; i < p_chain->page_cnt; i++) {
4416                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4417                                                  ECORE_CHAIN_PAGE_SIZE);
4418                 if (!p_virt) {
4419                         DP_NOTICE(p_dev, true,
4420                                   "Failed to allocate chain memory\n");
4421                         return ECORE_NOMEM;
4422                 }
4423
4424                 if (i == 0) {
4425                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4426                         ecore_chain_reset(p_chain);
4427                 } else {
4428                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4429                                                        p_virt, p_phys);
4430                 }
4431
4432                 p_virt_prev = p_virt;
4433         }
4434         /* Last page's next element should point to the beginning of the
4435          * chain.
4436          */
4437         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4438                                        p_chain->p_virt_addr,
4439                                        p_chain->p_phys_addr);
4440
4441         return ECORE_SUCCESS;
4442 }
4443
4444 static enum _ecore_status_t
4445 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4446 {
4447         dma_addr_t p_phys = 0;
4448         void *p_virt = OSAL_NULL;
4449
4450         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4451         if (!p_virt) {
4452                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4453                 return ECORE_NOMEM;
4454         }
4455
4456         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4457         ecore_chain_reset(p_chain);
4458
4459         return ECORE_SUCCESS;
4460 }
4461
4462 static enum _ecore_status_t
4463 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4464                       struct ecore_chain *p_chain,
4465                       struct ecore_chain_ext_pbl *ext_pbl)
4466 {
4467         u32 page_cnt = p_chain->page_cnt, size, i;
4468         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4469         void **pp_virt_addr_tbl = OSAL_NULL;
4470         u8 *p_pbl_virt = OSAL_NULL;
4471         void *p_virt = OSAL_NULL;
4472
4473         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4474         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4475         if (!pp_virt_addr_tbl) {
4476                 DP_NOTICE(p_dev, true,
4477                           "Failed to allocate memory for the chain virtual addresses table\n");
4478                 return ECORE_NOMEM;
4479         }
4480
4481         /* The allocation of the PBL table is done with its full size, since it
4482          * is expected to be successive.
4483          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4484          * failure, since pp_virt_addr_tbl was previously allocated, and it
4485          * should be saved to allow its freeing during the error flow.
4486          */
4487         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4488
4489         if (ext_pbl == OSAL_NULL) {
4490                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4491         } else {
4492                 p_pbl_virt = ext_pbl->p_pbl_virt;
4493                 p_pbl_phys = ext_pbl->p_pbl_phys;
4494                 p_chain->b_external_pbl = true;
4495         }
4496
4497         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4498                                  pp_virt_addr_tbl);
4499         if (!p_pbl_virt) {
4500                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4501                 return ECORE_NOMEM;
4502         }
4503
4504         for (i = 0; i < page_cnt; i++) {
4505                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4506                                                  ECORE_CHAIN_PAGE_SIZE);
4507                 if (!p_virt) {
4508                         DP_NOTICE(p_dev, true,
4509                                   "Failed to allocate chain memory\n");
4510                         return ECORE_NOMEM;
4511                 }
4512
4513                 if (i == 0) {
4514                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4515                         ecore_chain_reset(p_chain);
4516                 }
4517
4518                 /* Fill the PBL table with the physical address of the page */
4519                 *(dma_addr_t *)p_pbl_virt = p_phys;
4520                 /* Keep the virtual address of the page */
4521                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4522
4523                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4524         }
4525
4526         return ECORE_SUCCESS;
4527 }
4528
4529 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4530                                        enum ecore_chain_use_mode intended_use,
4531                                        enum ecore_chain_mode mode,
4532                                        enum ecore_chain_cnt_type cnt_type,
4533                                        u32 num_elems, osal_size_t elem_size,
4534                                        struct ecore_chain *p_chain,
4535                                        struct ecore_chain_ext_pbl *ext_pbl)
4536 {
4537         u32 page_cnt;
4538         enum _ecore_status_t rc = ECORE_SUCCESS;
4539
4540         if (mode == ECORE_CHAIN_MODE_SINGLE)
4541                 page_cnt = 1;
4542         else
4543                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4544
4545         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4546                                             page_cnt);
4547         if (rc) {
4548                 DP_NOTICE(p_dev, true,
4549                           "Cannot allocate a chain with the given arguments:\n"
4550                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4551                           intended_use, mode, cnt_type, num_elems, elem_size);
4552                 return rc;
4553         }
4554
4555         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4556                                 mode, cnt_type, p_dev->dp_ctx);
4557
4558         switch (mode) {
4559         case ECORE_CHAIN_MODE_NEXT_PTR:
4560                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4561                 break;
4562         case ECORE_CHAIN_MODE_SINGLE:
4563                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4564                 break;
4565         case ECORE_CHAIN_MODE_PBL:
4566                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4567                 break;
4568         }
4569         if (rc)
4570                 goto nomem;
4571
4572         return ECORE_SUCCESS;
4573
4574 nomem:
4575         ecore_chain_free(p_dev, p_chain);
4576         return rc;
4577 }
4578
4579 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4580                                        u16 src_id, u16 *dst_id)
4581 {
4582         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4583                 u16 min, max;
4584
4585                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4586                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4587                 DP_NOTICE(p_hwfn, true,
4588                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4589                           src_id, min, max);
4590
4591                 return ECORE_INVAL;
4592         }
4593
4594         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4595
4596         return ECORE_SUCCESS;
4597 }
4598
4599 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4600                                     u8 src_id, u8 *dst_id)
4601 {
4602         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4603                 u8 min, max;
4604
4605                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4606                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4607                 DP_NOTICE(p_hwfn, true,
4608                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4609                           src_id, min, max);
4610
4611                 return ECORE_INVAL;
4612         }
4613
4614         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4615
4616         return ECORE_SUCCESS;
4617 }
4618
4619 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4620                                       u8 src_id, u8 *dst_id)
4621 {
4622         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4623                 u8 min, max;
4624
4625                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4626                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4627                 DP_NOTICE(p_hwfn, true,
4628                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4629                           src_id, min, max);
4630
4631                 return ECORE_INVAL;
4632         }
4633
4634         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4635
4636         return ECORE_SUCCESS;
4637 }
4638
4639 static enum _ecore_status_t
4640 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4641                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4642                                u32 *p_entry_num)
4643 {
4644         u32 en;
4645         int i;
4646
4647         /* Find a free entry and utilize it */
4648         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4649                 en = ecore_rd(p_hwfn, p_ptt,
4650                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4651                               i * sizeof(u32));
4652                 if (en)
4653                         continue;
4654                 ecore_wr(p_hwfn, p_ptt,
4655                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4656                          2 * i * sizeof(u32), low);
4657                 ecore_wr(p_hwfn, p_ptt,
4658                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4659                          (2 * i + 1) * sizeof(u32), high);
4660                 ecore_wr(p_hwfn, p_ptt,
4661                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4662                          i * sizeof(u32), 0);
4663                 ecore_wr(p_hwfn, p_ptt,
4664                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4665                          i * sizeof(u32), 0);
4666                 ecore_wr(p_hwfn, p_ptt,
4667                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4668                          i * sizeof(u32), 1);
4669                 break;
4670         }
4671
4672         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4673                 return ECORE_NORESOURCES;
4674
4675         *p_entry_num = i;
4676
4677         return ECORE_SUCCESS;
4678 }
4679
4680 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4681                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4682 {
4683         u32 high, low, entry_num;
4684         enum _ecore_status_t rc = ECORE_SUCCESS;
4685
4686         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4687                            &p_hwfn->p_dev->mf_bits))
4688                 return ECORE_SUCCESS;
4689
4690         high = p_filter[1] | (p_filter[0] << 8);
4691         low = p_filter[5] | (p_filter[4] << 8) |
4692               (p_filter[3] << 16) | (p_filter[2] << 24);
4693
4694         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4695                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4696                                                     &entry_num);
4697         if (rc != ECORE_SUCCESS) {
4698                 DP_NOTICE(p_hwfn, false,
4699                           "Failed to find an empty LLH filter to utilize\n");
4700                 return rc;
4701         }
4702
4703         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4704                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4705                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4706                    p_filter[4], p_filter[5], entry_num);
4707
4708         return rc;
4709 }
4710
4711 static enum _ecore_status_t
4712 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4713                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4714                                   u32 *p_entry_num)
4715 {
4716         int i;
4717
4718         /* Find the entry and clean it */
4719         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4720                 if (ecore_rd(p_hwfn, p_ptt,
4721                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4722                              2 * i * sizeof(u32)) != low)
4723                         continue;
4724                 if (ecore_rd(p_hwfn, p_ptt,
4725                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4726                              (2 * i + 1) * sizeof(u32)) != high)
4727                         continue;
4728
4729                 ecore_wr(p_hwfn, p_ptt,
4730                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4731                 ecore_wr(p_hwfn, p_ptt,
4732                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4733                          2 * i * sizeof(u32), 0);
4734                 ecore_wr(p_hwfn, p_ptt,
4735                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4736                          (2 * i + 1) * sizeof(u32), 0);
4737                 break;
4738         }
4739
4740         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4741                 return ECORE_INVAL;
4742
4743         *p_entry_num = i;
4744
4745         return ECORE_SUCCESS;
4746 }
4747
4748 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4749                              struct ecore_ptt *p_ptt, u8 *p_filter)
4750 {
4751         u32 high, low, entry_num;
4752         enum _ecore_status_t rc = ECORE_SUCCESS;
4753
4754         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4755                            &p_hwfn->p_dev->mf_bits))
4756                 return;
4757
4758         high = p_filter[1] | (p_filter[0] << 8);
4759         low = p_filter[5] | (p_filter[4] << 8) |
4760               (p_filter[3] << 16) | (p_filter[2] << 24);
4761
4762         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4763                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4764                                                        low, &entry_num);
4765         if (rc != ECORE_SUCCESS) {
4766                 DP_NOTICE(p_hwfn, false,
4767                           "Tried to remove a non-configured filter\n");
4768                 return;
4769         }
4770
4771
4772         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4773                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4774                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4775                    p_filter[4], p_filter[5], entry_num);
4776 }
4777
4778 static enum _ecore_status_t
4779 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4780                                     struct ecore_ptt *p_ptt,
4781                                     enum ecore_llh_port_filter_type_t type,
4782                                     u32 high, u32 low, u32 *p_entry_num)
4783 {
4784         u32 en;
4785         int i;
4786
4787         /* Find a free entry and utilize it */
4788         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4789                 en = ecore_rd(p_hwfn, p_ptt,
4790                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4791                               i * sizeof(u32));
4792                 if (en)
4793                         continue;
4794                 ecore_wr(p_hwfn, p_ptt,
4795                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4796                          2 * i * sizeof(u32), low);
4797                 ecore_wr(p_hwfn, p_ptt,
4798                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4799                          (2 * i + 1) * sizeof(u32), high);
4800                 ecore_wr(p_hwfn, p_ptt,
4801                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4802                          i * sizeof(u32), 1);
4803                 ecore_wr(p_hwfn, p_ptt,
4804                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4805                          i * sizeof(u32), 1 << type);
4806                 ecore_wr(p_hwfn, p_ptt,
4807                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4808                 break;
4809         }
4810
4811         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4812                 return ECORE_NORESOURCES;
4813
4814         *p_entry_num = i;
4815
4816         return ECORE_SUCCESS;
4817 }
4818
4819 enum _ecore_status_t
4820 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4821                               struct ecore_ptt *p_ptt,
4822                               u16 source_port_or_eth_type,
4823                               u16 dest_port,
4824                               enum ecore_llh_port_filter_type_t type)
4825 {
4826         u32 high, low, entry_num;
4827         enum _ecore_status_t rc = ECORE_SUCCESS;
4828
4829         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4830                            &p_hwfn->p_dev->mf_bits))
4831                 return rc;
4832
4833         high = 0;
4834         low = 0;
4835
4836         switch (type) {
4837         case ECORE_LLH_FILTER_ETHERTYPE:
4838                 high = source_port_or_eth_type;
4839                 break;
4840         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4841         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4842                 low = source_port_or_eth_type << 16;
4843                 break;
4844         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4845         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4846                 low = dest_port;
4847                 break;
4848         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4849         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4850                 low = (source_port_or_eth_type << 16) | dest_port;
4851                 break;
4852         default:
4853                 DP_NOTICE(p_hwfn, true,
4854                           "Non valid LLH protocol filter type %d\n", type);
4855                 return ECORE_INVAL;
4856         }
4857
4858         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4859                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4860                                                          high, low, &entry_num);
4861         if (rc != ECORE_SUCCESS) {
4862                 DP_NOTICE(p_hwfn, false,
4863                           "Failed to find an empty LLH filter to utilize\n");
4864                 return rc;
4865         }
4866         switch (type) {
4867         case ECORE_LLH_FILTER_ETHERTYPE:
4868                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4869                            "ETH type %x is added at %d\n",
4870                            source_port_or_eth_type, entry_num);
4871                 break;
4872         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4873                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4874                            "TCP src port %x is added at %d\n",
4875                            source_port_or_eth_type, entry_num);
4876                 break;
4877         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4878                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4879                            "UDP src port %x is added at %d\n",
4880                            source_port_or_eth_type, entry_num);
4881                 break;
4882         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4883                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4884                            "TCP dst port %x is added at %d\n", dest_port,
4885                            entry_num);
4886                 break;
4887         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4888                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4889                            "UDP dst port %x is added at %d\n", dest_port,
4890                            entry_num);
4891                 break;
4892         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4893                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4894                            "TCP src/dst ports %x/%x are added at %d\n",
4895                            source_port_or_eth_type, dest_port, entry_num);
4896                 break;
4897         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4898                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4899                            "UDP src/dst ports %x/%x are added at %d\n",
4900                            source_port_or_eth_type, dest_port, entry_num);
4901                 break;
4902         }
4903
4904         return rc;
4905 }
4906
4907 static enum _ecore_status_t
4908 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4909                                        struct ecore_ptt *p_ptt,
4910                                        enum ecore_llh_port_filter_type_t type,
4911                                        u32 high, u32 low, u32 *p_entry_num)
4912 {
4913         int i;
4914
4915         /* Find the entry and clean it */
4916         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4917                 if (!ecore_rd(p_hwfn, p_ptt,
4918                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4919                               i * sizeof(u32)))
4920                         continue;
4921                 if (!ecore_rd(p_hwfn, p_ptt,
4922                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4923                               i * sizeof(u32)))
4924                         continue;
4925                 if (!(ecore_rd(p_hwfn, p_ptt,
4926                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4927                                i * sizeof(u32)) & (1 << type)))
4928                         continue;
4929                 if (ecore_rd(p_hwfn, p_ptt,
4930                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4931                              2 * i * sizeof(u32)) != low)
4932                         continue;
4933                 if (ecore_rd(p_hwfn, p_ptt,
4934                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4935                              (2 * i + 1) * sizeof(u32)) != high)
4936                         continue;
4937
4938                 ecore_wr(p_hwfn, p_ptt,
4939                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4940                 ecore_wr(p_hwfn, p_ptt,
4941                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4942                          i * sizeof(u32), 0);
4943                 ecore_wr(p_hwfn, p_ptt,
4944                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4945                          i * sizeof(u32), 0);
4946                 ecore_wr(p_hwfn, p_ptt,
4947                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4948                          2 * i * sizeof(u32), 0);
4949                 ecore_wr(p_hwfn, p_ptt,
4950                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4951                          (2 * i + 1) * sizeof(u32), 0);
4952                 break;
4953         }
4954
4955         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4956                 return ECORE_INVAL;
4957
4958         *p_entry_num = i;
4959
4960         return ECORE_SUCCESS;
4961 }
4962
4963 void
4964 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4965                                  struct ecore_ptt *p_ptt,
4966                                  u16 source_port_or_eth_type,
4967                                  u16 dest_port,
4968                                  enum ecore_llh_port_filter_type_t type)
4969 {
4970         u32 high, low, entry_num;
4971         enum _ecore_status_t rc = ECORE_SUCCESS;
4972
4973         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4974                            &p_hwfn->p_dev->mf_bits))
4975                 return;
4976
4977         high = 0;
4978         low = 0;
4979
4980         switch (type) {
4981         case ECORE_LLH_FILTER_ETHERTYPE:
4982                 high = source_port_or_eth_type;
4983                 break;
4984         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4985         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4986                 low = source_port_or_eth_type << 16;
4987                 break;
4988         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4989         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4990                 low = dest_port;
4991                 break;
4992         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4993         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4994                 low = (source_port_or_eth_type << 16) | dest_port;
4995                 break;
4996         default:
4997                 DP_NOTICE(p_hwfn, true,
4998                           "Non valid LLH protocol filter type %d\n", type);
4999                 return;
5000         }
5001
5002         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5003                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5004                                                             high, low,
5005                                                             &entry_num);
5006         if (rc != ECORE_SUCCESS) {
5007                 DP_NOTICE(p_hwfn, false,
5008                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
5009                           type, source_port_or_eth_type, dest_port);
5010                 return;
5011         }
5012
5013         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5014                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
5015                    type, source_port_or_eth_type, dest_port, entry_num);
5016 }
5017
5018 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
5019                                               struct ecore_ptt *p_ptt)
5020 {
5021         int i;
5022
5023         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
5024                 return;
5025
5026         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5027                 ecore_wr(p_hwfn, p_ptt,
5028                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
5029                          i * sizeof(u32), 0);
5030                 ecore_wr(p_hwfn, p_ptt,
5031                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5032                          2 * i * sizeof(u32), 0);
5033                 ecore_wr(p_hwfn, p_ptt,
5034                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5035                          (2 * i + 1) * sizeof(u32), 0);
5036         }
5037 }
5038
5039 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
5040                              struct ecore_ptt *p_ptt)
5041 {
5042         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5043                            &p_hwfn->p_dev->mf_bits) &&
5044             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5045                            &p_hwfn->p_dev->mf_bits))
5046                 return;
5047
5048         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5049                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5050 }
5051
5052 enum _ecore_status_t
5053 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5054                                   struct ecore_ptt *p_ptt)
5055 {
5056         if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5057                 ecore_wr(p_hwfn, p_ptt,
5058                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5059                          1 << p_hwfn->abs_pf_id / 2);
5060                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5061                 return ECORE_SUCCESS;
5062         }
5063
5064         DP_NOTICE(p_hwfn, false,
5065                   "This function can't be set as default\n");
5066         return ECORE_INVAL;
5067 }
5068
5069 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5070                                                struct ecore_ptt *p_ptt,
5071                                                u32 hw_addr, void *p_eth_qzone,
5072                                                osal_size_t eth_qzone_size,
5073                                                u8 timeset)
5074 {
5075         struct coalescing_timeset *p_coal_timeset;
5076
5077         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5078                 DP_NOTICE(p_hwfn, true,
5079                           "Coalescing configuration not enabled\n");
5080                 return ECORE_INVAL;
5081         }
5082
5083         p_coal_timeset = p_eth_qzone;
5084         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5085         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5086         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5087         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5088
5089         return ECORE_SUCCESS;
5090 }
5091
5092 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5093                                               u16 rx_coal, u16 tx_coal,
5094                                               void *p_handle)
5095 {
5096         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5097         enum _ecore_status_t rc = ECORE_SUCCESS;
5098         struct ecore_ptt *p_ptt;
5099
5100         /* TODO - Configuring a single queue's coalescing but
5101          * claiming all queues are abiding same configuration
5102          * for PF and VF both.
5103          */
5104
5105         if (IS_VF(p_hwfn->p_dev))
5106                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5107                                                 tx_coal, p_cid);
5108
5109         p_ptt = ecore_ptt_acquire(p_hwfn);
5110         if (!p_ptt)
5111                 return ECORE_AGAIN;
5112
5113         if (rx_coal) {
5114                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5115                 if (rc)
5116                         goto out;
5117                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5118         }
5119
5120         if (tx_coal) {
5121                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5122                 if (rc)
5123                         goto out;
5124                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5125         }
5126 out:
5127         ecore_ptt_release(p_hwfn, p_ptt);
5128
5129         return rc;
5130 }
5131
5132 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5133                                             struct ecore_ptt *p_ptt,
5134                                             u16 coalesce,
5135                                             struct ecore_queue_cid *p_cid)
5136 {
5137         struct ustorm_eth_queue_zone eth_qzone;
5138         u8 timeset, timer_res;
5139         u32 address;
5140         enum _ecore_status_t rc;
5141
5142         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5143         if (coalesce <= 0x7F) {
5144                 timer_res = 0;
5145         } else if (coalesce <= 0xFF) {
5146                 timer_res = 1;
5147         } else if (coalesce <= 0x1FF) {
5148                 timer_res = 2;
5149         } else {
5150                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5151                 return ECORE_INVAL;
5152         }
5153         timeset = (u8)(coalesce >> timer_res);
5154
5155         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5156                                      p_cid->sb_igu_id, false);
5157         if (rc != ECORE_SUCCESS)
5158                 goto out;
5159
5160         address = BAR0_MAP_REG_USDM_RAM +
5161                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5162
5163         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5164                                 sizeof(struct ustorm_eth_queue_zone), timeset);
5165         if (rc != ECORE_SUCCESS)
5166                 goto out;
5167
5168 out:
5169         return rc;
5170 }
5171
5172 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5173                                             struct ecore_ptt *p_ptt,
5174                                             u16 coalesce,
5175                                             struct ecore_queue_cid *p_cid)
5176 {
5177         struct xstorm_eth_queue_zone eth_qzone;
5178         u8 timeset, timer_res;
5179         u32 address;
5180         enum _ecore_status_t rc;
5181
5182         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5183         if (coalesce <= 0x7F) {
5184                 timer_res = 0;
5185         } else if (coalesce <= 0xFF) {
5186                 timer_res = 1;
5187         } else if (coalesce <= 0x1FF) {
5188                 timer_res = 2;
5189         } else {
5190                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5191                 return ECORE_INVAL;
5192         }
5193
5194         timeset = (u8)(coalesce >> timer_res);
5195
5196         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5197                                      p_cid->sb_igu_id, true);
5198         if (rc != ECORE_SUCCESS)
5199                 goto out;
5200
5201         address = BAR0_MAP_REG_XSDM_RAM +
5202                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5203
5204         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5205                                 sizeof(struct xstorm_eth_queue_zone), timeset);
5206 out:
5207         return rc;
5208 }
5209
5210 /* Calculate final WFQ values for all vports and configure it.
5211  * After this configuration each vport must have
5212  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5213  */
5214 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5215                                                struct ecore_ptt *p_ptt,
5216                                                u32 min_pf_rate)
5217 {
5218         struct init_qm_vport_params *vport_params;
5219         int i;
5220
5221         vport_params = p_hwfn->qm_info.qm_vport_params;
5222
5223         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5224                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5225
5226                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5227                     min_pf_rate;
5228                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5229                                      vport_params[i].first_tx_pq_id,
5230                                      vport_params[i].vport_wfq);
5231         }
5232 }
5233
5234 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5235 {
5236         int i;
5237
5238         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5239                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5240 }
5241
5242 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5243                                              struct ecore_ptt *p_ptt)
5244 {
5245         struct init_qm_vport_params *vport_params;
5246         int i;
5247
5248         vport_params = p_hwfn->qm_info.qm_vport_params;
5249
5250         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5251                 ecore_init_wfq_default_param(p_hwfn);
5252                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5253                                      vport_params[i].first_tx_pq_id,
5254                                      vport_params[i].vport_wfq);
5255         }
5256 }
5257
5258 /* This function performs several validations for WFQ
5259  * configuration and required min rate for a given vport
5260  * 1. req_rate must be greater than one percent of min_pf_rate.
5261  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5262  *    rates to get less than one percent of min_pf_rate.
5263  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5264  */
5265 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5266                                                  u16 vport_id, u32 req_rate,
5267                                                  u32 min_pf_rate)
5268 {
5269         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5270         int non_requested_count = 0, req_count = 0, i, num_vports;
5271
5272         num_vports = p_hwfn->qm_info.num_vports;
5273
5274 /* Accounting for the vports which are configured for WFQ explicitly */
5275
5276         for (i = 0; i < num_vports; i++) {
5277                 u32 tmp_speed;
5278
5279                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5280                         req_count++;
5281                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5282                         total_req_min_rate += tmp_speed;
5283                 }
5284         }
5285
5286         /* Include current vport data as well */
5287         req_count++;
5288         total_req_min_rate += req_rate;
5289         non_requested_count = num_vports - req_count;
5290
5291         /* validate possible error cases */
5292         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5293                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5294                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5295                            vport_id, req_rate, min_pf_rate);
5296                 return ECORE_INVAL;
5297         }
5298
5299         /* TBD - for number of vports greater than 100 */
5300         if (num_vports > ECORE_WFQ_UNIT) {
5301                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5302                            "Number of vports is greater than %d\n",
5303                            ECORE_WFQ_UNIT);
5304                 return ECORE_INVAL;
5305         }
5306
5307         if (total_req_min_rate > min_pf_rate) {
5308                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5309                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5310                            total_req_min_rate, min_pf_rate);
5311                 return ECORE_INVAL;
5312         }
5313
5314         /* Data left for non requested vports */
5315         total_left_rate = min_pf_rate - total_req_min_rate;
5316         left_rate_per_vp = total_left_rate / non_requested_count;
5317
5318         /* validate if non requested get < 1% of min bw */
5319         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5320                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5321                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5322                            left_rate_per_vp, min_pf_rate);
5323                 return ECORE_INVAL;
5324         }
5325
5326         /* now req_rate for given vport passes all scenarios.
5327          * assign final wfq rates to all vports.
5328          */
5329         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5330         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5331
5332         for (i = 0; i < num_vports; i++) {
5333                 if (p_hwfn->qm_info.wfq_data[i].configured)
5334                         continue;
5335
5336                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5337         }
5338
5339         return ECORE_SUCCESS;
5340 }
5341
5342 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5343                                        struct ecore_ptt *p_ptt,
5344                                        u16 vp_id, u32 rate)
5345 {
5346         struct ecore_mcp_link_state *p_link;
5347         int rc = ECORE_SUCCESS;
5348
5349         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5350
5351         if (!p_link->min_pf_rate) {
5352                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5353                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5354                 return rc;
5355         }
5356
5357         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5358
5359         if (rc == ECORE_SUCCESS)
5360                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5361                                                    p_link->min_pf_rate);
5362         else
5363                 DP_NOTICE(p_hwfn, false,
5364                           "Validation failed while configuring min rate\n");
5365
5366         return rc;
5367 }
5368
5369 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5370                                                    struct ecore_ptt *p_ptt,
5371                                                    u32 min_pf_rate)
5372 {
5373         bool use_wfq = false;
5374         int rc = ECORE_SUCCESS;
5375         u16 i;
5376
5377         /* Validate all pre configured vports for wfq */
5378         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5379                 u32 rate;
5380
5381                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5382                         continue;
5383
5384                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5385                 use_wfq = true;
5386
5387                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5388                 if (rc != ECORE_SUCCESS) {
5389                         DP_NOTICE(p_hwfn, false,
5390                                   "WFQ validation failed while configuring min rate\n");
5391                         break;
5392                 }
5393         }
5394
5395         if (rc == ECORE_SUCCESS && use_wfq)
5396                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5397         else
5398                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5399
5400         return rc;
5401 }
5402
5403 /* Main API for ecore clients to configure vport min rate.
5404  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5405  * rate - Speed in Mbps needs to be assigned to a given vport.
5406  */
5407 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5408 {
5409         int i, rc = ECORE_INVAL;
5410
5411         /* TBD - for multiple hardware functions - that is 100 gig */
5412         if (ECORE_IS_CMT(p_dev)) {
5413                 DP_NOTICE(p_dev, false,
5414                           "WFQ configuration is not supported for this device\n");
5415                 return rc;
5416         }
5417
5418         for_each_hwfn(p_dev, i) {
5419                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5420                 struct ecore_ptt *p_ptt;
5421
5422                 p_ptt = ecore_ptt_acquire(p_hwfn);
5423                 if (!p_ptt)
5424                         return ECORE_TIMEOUT;
5425
5426                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5427
5428                 if (rc != ECORE_SUCCESS) {
5429                         ecore_ptt_release(p_hwfn, p_ptt);
5430                         return rc;
5431                 }
5432
5433                 ecore_ptt_release(p_hwfn, p_ptt);
5434         }
5435
5436         return rc;
5437 }
5438
5439 /* API to configure WFQ from mcp link change */
5440 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5441                                            struct ecore_ptt *p_ptt,
5442                                            u32 min_pf_rate)
5443 {
5444         int i;
5445
5446         /* TBD - for multiple hardware functions - that is 100 gig */
5447         if (ECORE_IS_CMT(p_dev)) {
5448                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5449                            "WFQ configuration is not supported for this device\n");
5450                 return;
5451         }
5452
5453         for_each_hwfn(p_dev, i) {
5454                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5455
5456                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5457                                                         min_pf_rate);
5458         }
5459 }
5460
5461 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5462                                        struct ecore_ptt *p_ptt,
5463                                        struct ecore_mcp_link_state *p_link,
5464                                        u8 max_bw)
5465 {
5466         int rc = ECORE_SUCCESS;
5467
5468         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5469
5470         if (!p_link->line_speed && (max_bw != 100))
5471                 return rc;
5472
5473         p_link->speed = (p_link->line_speed * max_bw) / 100;
5474         p_hwfn->qm_info.pf_rl = p_link->speed;
5475
5476         /* Since the limiter also affects Tx-switched traffic, we don't want it
5477          * to limit such traffic in case there's no actual limit.
5478          * In that case, set limit to imaginary high boundary.
5479          */
5480         if (max_bw == 100)
5481                 p_hwfn->qm_info.pf_rl = 100000;
5482
5483         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5484                               p_hwfn->qm_info.pf_rl);
5485
5486         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5487                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5488                    p_link->speed);
5489
5490         return rc;
5491 }
5492
5493 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5494 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5495 {
5496         int i, rc = ECORE_INVAL;
5497
5498         if (max_bw < 1 || max_bw > 100) {
5499                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5500                 return rc;
5501         }
5502
5503         for_each_hwfn(p_dev, i) {
5504                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5505                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5506                 struct ecore_mcp_link_state *p_link;
5507                 struct ecore_ptt *p_ptt;
5508
5509                 p_link = &p_lead->mcp_info->link_output;
5510
5511                 p_ptt = ecore_ptt_acquire(p_hwfn);
5512                 if (!p_ptt)
5513                         return ECORE_TIMEOUT;
5514
5515                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5516                                                         p_link, max_bw);
5517
5518                 ecore_ptt_release(p_hwfn, p_ptt);
5519
5520                 if (rc != ECORE_SUCCESS)
5521                         break;
5522         }
5523
5524         return rc;
5525 }
5526
5527 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5528                                        struct ecore_ptt *p_ptt,
5529                                        struct ecore_mcp_link_state *p_link,
5530                                        u8 min_bw)
5531 {
5532         int rc = ECORE_SUCCESS;
5533
5534         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5535         p_hwfn->qm_info.pf_wfq = min_bw;
5536
5537         if (!p_link->line_speed)
5538                 return rc;
5539
5540         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5541
5542         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5543
5544         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5545                    "Configured MIN bandwidth to be %d Mb/sec\n",
5546                    p_link->min_pf_rate);
5547
5548         return rc;
5549 }
5550
5551 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5552 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5553 {
5554         int i, rc = ECORE_INVAL;
5555
5556         if (min_bw < 1 || min_bw > 100) {
5557                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5558                 return rc;
5559         }
5560
5561         for_each_hwfn(p_dev, i) {
5562                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5563                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5564                 struct ecore_mcp_link_state *p_link;
5565                 struct ecore_ptt *p_ptt;
5566
5567                 p_link = &p_lead->mcp_info->link_output;
5568
5569                 p_ptt = ecore_ptt_acquire(p_hwfn);
5570                 if (!p_ptt)
5571                         return ECORE_TIMEOUT;
5572
5573                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5574                                                         p_link, min_bw);
5575                 if (rc != ECORE_SUCCESS) {
5576                         ecore_ptt_release(p_hwfn, p_ptt);
5577                         return rc;
5578                 }
5579
5580                 if (p_link->min_pf_rate) {
5581                         u32 min_rate = p_link->min_pf_rate;
5582
5583                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5584                                                                      p_ptt,
5585                                                                      min_rate);
5586                 }
5587
5588                 ecore_ptt_release(p_hwfn, p_ptt);
5589         }
5590
5591         return rc;
5592 }
5593
5594 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5595 {
5596         struct ecore_mcp_link_state *p_link;
5597
5598         p_link = &p_hwfn->mcp_info->link_output;
5599
5600         if (p_link->min_pf_rate)
5601                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5602
5603         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5604                     sizeof(*p_hwfn->qm_info.wfq_data) *
5605                     p_hwfn->qm_info.num_vports);
5606 }
5607
5608 int ecore_device_num_engines(struct ecore_dev *p_dev)
5609 {
5610         return ECORE_IS_BB(p_dev) ? 2 : 1;
5611 }
5612
5613 int ecore_device_num_ports(struct ecore_dev *p_dev)
5614 {
5615         return p_dev->num_ports;
5616 }
5617
5618 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5619                           __le16 *fw_mid,
5620                           __le16 *fw_lsb,
5621                           u8 *mac)
5622 {
5623         ((u8 *)fw_msb)[0] = mac[1];
5624         ((u8 *)fw_msb)[1] = mac[0];
5625         ((u8 *)fw_mid)[0] = mac[3];
5626         ((u8 *)fw_mid)[1] = mac[2];
5627         ((u8 *)fw_lsb)[0] = mac[5];
5628         ((u8 *)fw_lsb)[1] = mac[4];
5629 }