1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
9 #include "ecore_gtt_reg_addr.h"
11 #include "ecore_chain.h"
12 #include "ecore_status.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_init_ops.h"
16 #include "ecore_int.h"
17 #include "ecore_cxt.h"
18 #include "ecore_spq.h"
19 #include "ecore_init_fw_funcs.h"
20 #include "ecore_sp_commands.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
24 #include "ecore_mcp.h"
25 #include "ecore_hw_defs.h"
26 #include "mcp_public.h"
27 #include "ecore_iro.h"
29 #include "ecore_dcbx.h"
32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
33 * registers involved are not split and thus configuration is a race where
34 * some of the PFs configuration might be lost.
35 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
36 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
37 * there's more than a single compiled ecore component in system].
39 static osal_spinlock_t qm_lock;
40 static u32 qm_lock_ref_cnt;
43 static bool b_ptt_gtt_init;
46 /******************** Doorbell Recovery *******************/
47 /* The doorbell recovery mechanism consists of a list of entries which represent
48 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
49 * entity needs to register with the mechanism and provide the parameters
50 * describing it's doorbell, including a location where last used doorbell data
51 * can be found. The doorbell execute function will traverse the list and
52 * doorbell all of the registered entries.
54 struct ecore_db_recovery_entry {
55 osal_list_entry_t list_entry;
56 void OSAL_IOMEM *db_addr;
58 enum ecore_db_rec_width db_width;
59 enum ecore_db_rec_space db_space;
63 /* display a single doorbell recovery entry */
64 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
65 struct ecore_db_recovery_entry *db_entry,
68 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
69 action, db_entry, db_entry->db_addr, db_entry->db_data,
70 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
71 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
75 /* doorbell address sanity (address within doorbell bar range) */
76 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
79 /* make sure doorbell address is within the doorbell bar */
80 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
81 (u8 *)p_dev->doorbells + p_dev->db_size) {
83 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
84 db_addr, p_dev->doorbells,
85 (u8 *)p_dev->doorbells + p_dev->db_size);
89 /* make sure doorbell data pointer is not null */
91 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
98 /* find hwfn according to the doorbell address */
99 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
100 void OSAL_IOMEM *db_addr)
102 struct ecore_hwfn *p_hwfn;
104 /* In CMT doorbell bar is split down the middle between engine 0 and
107 if (ECORE_IS_CMT(p_dev))
108 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
109 &p_dev->hwfns[0] : &p_dev->hwfns[1];
111 p_hwfn = ECORE_LEADING_HWFN(p_dev);
116 /* add a new entry to the doorbell recovery mechanism */
117 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
118 void OSAL_IOMEM *db_addr,
120 enum ecore_db_rec_width db_width,
121 enum ecore_db_rec_space db_space)
123 struct ecore_db_recovery_entry *db_entry;
124 struct ecore_hwfn *p_hwfn;
126 /* shortcircuit VFs, for now */
128 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
129 return ECORE_SUCCESS;
132 /* sanitize doorbell address */
133 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
136 /* obtain hwfn from doorbell address */
137 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
140 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
142 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
147 db_entry->db_addr = db_addr;
148 db_entry->db_data = db_data;
149 db_entry->db_width = db_width;
150 db_entry->db_space = db_space;
151 db_entry->hwfn_idx = p_hwfn->my_id;
154 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
156 /* protect the list */
157 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
158 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
159 &p_hwfn->db_recovery_info.list);
160 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
162 return ECORE_SUCCESS;
165 /* remove an entry from the doorbell recovery mechanism */
166 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
167 void OSAL_IOMEM *db_addr,
170 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
171 enum _ecore_status_t rc = ECORE_INVAL;
172 struct ecore_hwfn *p_hwfn;
174 /* shortcircuit VFs, for now */
176 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
177 return ECORE_SUCCESS;
180 /* sanitize doorbell address */
181 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
184 /* obtain hwfn from doorbell address */
185 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
187 /* protect the list */
188 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
189 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
190 &p_hwfn->db_recovery_info.list,
192 struct ecore_db_recovery_entry) {
193 /* search according to db_data addr since db_addr is not unique
196 if (db_entry->db_data == db_data) {
197 ecore_db_recovery_dp_entry(p_hwfn, db_entry,
199 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
200 &p_hwfn->db_recovery_info.list);
206 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
208 if (rc == ECORE_INVAL)
210 DP_NOTICE(p_hwfn, false,
211 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
214 OSAL_FREE(p_dev, db_entry);
219 /* initialize the doorbell recovery mechanism */
220 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
222 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
224 /* make sure db_size was set in p_dev */
225 if (!p_hwfn->p_dev->db_size) {
226 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
230 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
231 #ifdef CONFIG_ECORE_LOCK_ALLOC
232 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
235 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
236 p_hwfn->db_recovery_info.db_recovery_counter = 0;
238 return ECORE_SUCCESS;
241 /* destroy the doorbell recovery mechanism */
242 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
244 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
246 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
247 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
248 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
249 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
250 db_entry = OSAL_LIST_FIRST_ENTRY(
251 &p_hwfn->db_recovery_info.list,
252 struct ecore_db_recovery_entry,
254 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
255 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
256 &p_hwfn->db_recovery_info.list);
257 OSAL_FREE(p_hwfn->p_dev, db_entry);
260 #ifdef CONFIG_ECORE_LOCK_ALLOC
261 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
263 p_hwfn->db_recovery_info.db_recovery_counter = 0;
266 /* print the content of the doorbell recovery mechanism */
267 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
269 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
271 DP_NOTICE(p_hwfn, false,
272 "Dispalying doorbell recovery database. Counter was %d\n",
273 p_hwfn->db_recovery_info.db_recovery_counter);
275 /* protect the list */
276 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
277 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
278 &p_hwfn->db_recovery_info.list,
280 struct ecore_db_recovery_entry) {
281 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
284 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
287 /* ring the doorbell of a single doorbell recovery entry */
288 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
289 struct ecore_db_recovery_entry *db_entry,
290 enum ecore_db_rec_exec db_exec)
292 /* Print according to width */
293 if (db_entry->db_width == DB_REC_WIDTH_32B)
294 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
295 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
296 db_entry->db_addr, *(u32 *)db_entry->db_data);
298 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
299 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
301 *(unsigned long *)(db_entry->db_data));
304 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
308 /* Flush the write combined buffer. Since there are multiple doorbelling
309 * entities using the same address, if we don't flush, a transaction
312 OSAL_WMB(p_hwfn->p_dev);
314 /* Ring the doorbell */
315 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
316 if (db_entry->db_width == DB_REC_WIDTH_32B)
317 DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
318 *(u32 *)(db_entry->db_data));
320 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
321 *(u64 *)(db_entry->db_data));
324 /* Flush the write combined buffer. Next doorbell may come from a
325 * different entity to the same address...
327 OSAL_WMB(p_hwfn->p_dev);
330 /* traverse the doorbell recovery entry list and ring all the doorbells */
331 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
332 enum ecore_db_rec_exec db_exec)
334 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
336 if (db_exec != DB_REC_ONCE) {
337 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
338 p_hwfn->db_recovery_info.db_recovery_counter);
340 /* track amount of times recovery was executed */
341 p_hwfn->db_recovery_info.db_recovery_counter++;
344 /* protect the list */
345 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
346 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
347 &p_hwfn->db_recovery_info.list,
349 struct ecore_db_recovery_entry) {
350 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
351 if (db_exec == DB_REC_ONCE)
355 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
357 /******************** Doorbell Recovery end ****************/
359 /********************************** NIG LLH ***********************************/
361 enum ecore_llh_filter_type {
362 ECORE_LLH_FILTER_TYPE_MAC,
363 ECORE_LLH_FILTER_TYPE_PROTOCOL,
366 struct ecore_llh_mac_filter {
370 struct ecore_llh_protocol_filter {
371 enum ecore_llh_prot_filter_type_t type;
372 u16 source_port_or_eth_type;
376 union ecore_llh_filter {
377 struct ecore_llh_mac_filter mac;
378 struct ecore_llh_protocol_filter protocol;
381 struct ecore_llh_filter_info {
384 enum ecore_llh_filter_type type;
385 union ecore_llh_filter filter;
388 struct ecore_llh_info {
389 /* Number of LLH filters banks */
392 #define MAX_NUM_PPFID 8
393 u8 ppfid_array[MAX_NUM_PPFID];
395 /* Array of filters arrays:
396 * "num_ppfid" elements of filters banks, where each is an array of
397 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
399 struct ecore_llh_filter_info **pp_filters;
402 static void ecore_llh_free(struct ecore_dev *p_dev)
404 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
407 if (p_llh_info != OSAL_NULL) {
408 if (p_llh_info->pp_filters != OSAL_NULL) {
409 for (i = 0; i < p_llh_info->num_ppfid; i++)
410 OSAL_FREE(p_dev, p_llh_info->pp_filters[i]);
413 OSAL_FREE(p_dev, p_llh_info->pp_filters);
416 OSAL_FREE(p_dev, p_llh_info);
417 p_dev->p_llh_info = OSAL_NULL;
420 static enum _ecore_status_t ecore_llh_alloc(struct ecore_dev *p_dev)
422 struct ecore_llh_info *p_llh_info;
426 p_llh_info = OSAL_ZALLOC(p_dev, GFP_KERNEL, sizeof(*p_llh_info));
429 p_dev->p_llh_info = p_llh_info;
431 for (i = 0; i < MAX_NUM_PPFID; i++) {
432 if (!(p_dev->ppfid_bitmap & (0x1 << i)))
435 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
436 DP_VERBOSE(p_dev, ECORE_MSG_SP, "ppfid_array[%d] = %hhd\n",
437 p_llh_info->num_ppfid, i);
438 p_llh_info->num_ppfid++;
441 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
442 p_llh_info->pp_filters = OSAL_ZALLOC(p_dev, GFP_KERNEL, size);
443 if (!p_llh_info->pp_filters)
446 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
447 sizeof(**p_llh_info->pp_filters);
448 for (i = 0; i < p_llh_info->num_ppfid; i++) {
449 p_llh_info->pp_filters[i] = OSAL_ZALLOC(p_dev, GFP_KERNEL,
451 if (!p_llh_info->pp_filters[i])
455 return ECORE_SUCCESS;
458 static enum _ecore_status_t ecore_llh_shadow_sanity(struct ecore_dev *p_dev,
459 u8 ppfid, u8 filter_idx,
462 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
464 if (ppfid >= p_llh_info->num_ppfid) {
465 DP_NOTICE(p_dev, false,
466 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
467 action, ppfid, p_llh_info->num_ppfid);
471 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
472 DP_NOTICE(p_dev, false,
473 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
474 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
478 return ECORE_SUCCESS;
481 #define ECORE_LLH_INVALID_FILTER_IDX 0xff
483 static enum _ecore_status_t
484 ecore_llh_shadow_search_filter(struct ecore_dev *p_dev, u8 ppfid,
485 union ecore_llh_filter *p_filter,
488 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
489 struct ecore_llh_filter_info *p_filters;
490 enum _ecore_status_t rc;
493 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "search");
494 if (rc != ECORE_SUCCESS)
497 *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
499 p_filters = p_llh_info->pp_filters[ppfid];
500 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
501 if (!OSAL_MEMCMP(p_filter, &p_filters[i].filter,
502 sizeof(*p_filter))) {
508 return ECORE_SUCCESS;
511 static enum _ecore_status_t
512 ecore_llh_shadow_get_free_idx(struct ecore_dev *p_dev, u8 ppfid,
515 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
516 struct ecore_llh_filter_info *p_filters;
517 enum _ecore_status_t rc;
520 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "get_free_idx");
521 if (rc != ECORE_SUCCESS)
524 *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
526 p_filters = p_llh_info->pp_filters[ppfid];
527 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
528 if (!p_filters[i].b_enabled) {
534 return ECORE_SUCCESS;
537 static enum _ecore_status_t
538 __ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid, u8 filter_idx,
539 enum ecore_llh_filter_type type,
540 union ecore_llh_filter *p_filter, u32 *p_ref_cnt)
542 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
543 struct ecore_llh_filter_info *p_filters;
544 enum _ecore_status_t rc;
546 rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "add");
547 if (rc != ECORE_SUCCESS)
550 p_filters = p_llh_info->pp_filters[ppfid];
551 if (!p_filters[filter_idx].ref_cnt) {
552 p_filters[filter_idx].b_enabled = true;
553 p_filters[filter_idx].type = type;
554 OSAL_MEMCPY(&p_filters[filter_idx].filter, p_filter,
555 sizeof(p_filters[filter_idx].filter));
558 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
560 return ECORE_SUCCESS;
563 static enum _ecore_status_t
564 ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid,
565 enum ecore_llh_filter_type type,
566 union ecore_llh_filter *p_filter,
567 u8 *p_filter_idx, u32 *p_ref_cnt)
569 enum _ecore_status_t rc;
571 /* Check if the same filter already exist */
572 rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
574 if (rc != ECORE_SUCCESS)
577 /* Find a new entry in case of a new filter */
578 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
579 rc = ecore_llh_shadow_get_free_idx(p_dev, ppfid, p_filter_idx);
580 if (rc != ECORE_SUCCESS)
584 /* No free entry was found */
585 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
586 DP_NOTICE(p_dev, false,
587 "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
589 return ECORE_NORESOURCES;
592 return __ecore_llh_shadow_add_filter(p_dev, ppfid, *p_filter_idx, type,
593 p_filter, p_ref_cnt);
596 static enum _ecore_status_t
597 __ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
598 u8 filter_idx, u32 *p_ref_cnt)
600 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
601 struct ecore_llh_filter_info *p_filters;
602 enum _ecore_status_t rc;
604 rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "remove");
605 if (rc != ECORE_SUCCESS)
608 p_filters = p_llh_info->pp_filters[ppfid];
609 if (!p_filters[filter_idx].ref_cnt) {
610 DP_NOTICE(p_dev, false,
611 "LLH shadow: trying to remove a filter with ref_cnt=0\n");
615 *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
616 if (!p_filters[filter_idx].ref_cnt)
617 OSAL_MEM_ZERO(&p_filters[filter_idx],
618 sizeof(p_filters[filter_idx]));
620 return ECORE_SUCCESS;
623 static enum _ecore_status_t
624 ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
625 union ecore_llh_filter *p_filter,
626 u8 *p_filter_idx, u32 *p_ref_cnt)
628 enum _ecore_status_t rc;
630 rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
632 if (rc != ECORE_SUCCESS)
635 /* No matching filter was found */
636 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
637 DP_NOTICE(p_dev, false,
638 "Failed to find a filter in the LLH shadow\n");
642 return __ecore_llh_shadow_remove_filter(p_dev, ppfid, *p_filter_idx,
646 static enum _ecore_status_t
647 ecore_llh_shadow_remove_all_filters(struct ecore_dev *p_dev, u8 ppfid)
649 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
650 struct ecore_llh_filter_info *p_filters;
651 enum _ecore_status_t rc;
653 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "remove_all");
654 if (rc != ECORE_SUCCESS)
657 p_filters = p_llh_info->pp_filters[ppfid];
658 OSAL_MEM_ZERO(p_filters,
659 NIG_REG_LLH_FUNC_FILTER_EN_SIZE * sizeof(*p_filters));
661 return ECORE_SUCCESS;
664 static enum _ecore_status_t ecore_abs_ppfid(struct ecore_dev *p_dev,
665 u8 rel_ppfid, u8 *p_abs_ppfid)
667 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
668 u8 ppfids = p_llh_info->num_ppfid - 1;
670 if (rel_ppfid >= p_llh_info->num_ppfid) {
671 DP_NOTICE(p_dev, false,
672 "rel_ppfid %d is not valid, available indices are 0..%hhd\n",
677 *p_abs_ppfid = p_llh_info->ppfid_array[rel_ppfid];
679 return ECORE_SUCCESS;
682 static enum _ecore_status_t
683 __ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
685 struct ecore_dev *p_dev = p_hwfn->p_dev;
688 enum _ecore_status_t rc;
690 rc = ecore_mcp_get_engine_config(p_hwfn, p_ptt);
691 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
692 DP_NOTICE(p_hwfn, false,
693 "Failed to get the engine affinity configuration\n");
697 /* RoCE PF is bound to a single engine */
698 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
699 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
700 rc = ecore_llh_set_roce_affinity(p_dev, eng);
701 if (rc != ECORE_SUCCESS) {
702 DP_NOTICE(p_dev, false,
703 "Failed to set the RoCE engine affinity\n");
707 DP_VERBOSE(p_dev, ECORE_MSG_SP,
708 "LLH: Set the engine affinity of RoCE packets as %d\n",
712 /* Storage PF is bound to a single engine while L2 PF uses both */
713 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
714 ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
715 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
716 else /* L2_PERSONALITY */
717 eng = ECORE_BOTH_ENG;
719 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
720 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
721 if (rc != ECORE_SUCCESS) {
722 DP_NOTICE(p_dev, false,
723 "Failed to set the engine affinity of ppfid %d\n",
729 DP_VERBOSE(p_dev, ECORE_MSG_SP,
730 "LLH: Set the engine affinity of non-RoCE packets as %d\n",
733 return ECORE_SUCCESS;
736 static enum _ecore_status_t
737 ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
738 bool avoid_eng_affin)
740 struct ecore_dev *p_dev = p_hwfn->p_dev;
741 enum _ecore_status_t rc;
743 /* Backwards compatible mode:
744 * - RoCE packets - Use engine 0.
745 * - Non-RoCE packets - Use connection based classification for L2 PFs,
746 * and engine 0 otherwise.
748 if (avoid_eng_affin) {
752 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
754 rc = ecore_llh_set_roce_affinity(p_dev, eng);
755 if (rc != ECORE_SUCCESS) {
756 DP_NOTICE(p_dev, false,
757 "Failed to set the RoCE engine affinity\n");
761 DP_VERBOSE(p_dev, ECORE_MSG_SP,
762 "LLH [backwards compatible mode]: Set the engine affinity of RoCE packets as %d\n",
766 eng = (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
767 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) ? ECORE_ENG0
769 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
770 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
771 if (rc != ECORE_SUCCESS) {
772 DP_NOTICE(p_dev, false,
773 "Failed to set the engine affinity of ppfid %d\n",
779 DP_VERBOSE(p_dev, ECORE_MSG_SP,
780 "LLH [backwards compatible mode]: Set the engine affinity of non-RoCE packets as %d\n",
783 return ECORE_SUCCESS;
786 return __ecore_llh_set_engine_affin(p_hwfn, p_ptt);
789 static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn,
790 struct ecore_ptt *p_ptt,
791 bool avoid_eng_affin)
793 struct ecore_dev *p_dev = p_hwfn->p_dev;
795 enum _ecore_status_t rc;
797 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
800 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
801 if (rc != ECORE_SUCCESS)
804 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
805 ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
808 if (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
809 !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {
810 rc = ecore_llh_add_mac_filter(p_dev, 0,
811 p_hwfn->hw_info.hw_mac_addr);
812 if (rc != ECORE_SUCCESS)
813 DP_NOTICE(p_dev, false,
814 "Failed to add an LLH filter with the primary MAC\n");
817 if (ECORE_IS_CMT(p_dev)) {
818 rc = ecore_llh_set_engine_affin(p_hwfn, p_ptt, avoid_eng_affin);
819 if (rc != ECORE_SUCCESS)
823 return ECORE_SUCCESS;
826 u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev)
828 return p_dev->p_llh_info->num_ppfid;
831 enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev)
833 return p_dev->l2_affin_hint ? ECORE_ENG1 : ECORE_ENG0;
836 /* TBD - should be removed when these definitions are available in reg_addr.h */
837 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3
838 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0
839 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3
840 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2
842 enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev,
843 u8 ppfid, enum ecore_eng eng)
845 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
846 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
847 u32 addr, val, eng_sel;
848 enum _ecore_status_t rc = ECORE_SUCCESS;
851 if (p_ptt == OSAL_NULL)
854 if (!ECORE_IS_CMT(p_dev))
857 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
858 if (rc != ECORE_SUCCESS)
872 DP_NOTICE(p_dev, false,
873 "Invalid affinity value for ppfid [%d]\n", eng);
878 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
879 val = ecore_rd(p_hwfn, p_ptt, addr);
880 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
881 ecore_wr(p_hwfn, p_ptt, addr, val);
883 /* The iWARP affinity is set as the affinity of ppfid 0 */
884 if (!ppfid && ECORE_IS_IWARP_PERSONALITY(p_hwfn))
885 p_dev->iwarp_affin = (eng == ECORE_ENG1) ? 1 : 0;
887 ecore_ptt_release(p_hwfn, p_ptt);
892 enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,
895 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
896 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
897 u32 addr, val, eng_sel;
898 enum _ecore_status_t rc = ECORE_SUCCESS;
901 if (p_ptt == OSAL_NULL)
904 if (!ECORE_IS_CMT(p_dev))
916 ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
917 0xf /* QP bit 15 */);
920 DP_NOTICE(p_dev, false,
921 "Invalid affinity value for RoCE [%d]\n", eng);
926 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
927 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
928 if (rc != ECORE_SUCCESS)
931 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
932 val = ecore_rd(p_hwfn, p_ptt, addr);
933 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
934 ecore_wr(p_hwfn, p_ptt, addr, val);
937 ecore_ptt_release(p_hwfn, p_ptt);
942 struct ecore_llh_filter_details {
950 static enum _ecore_status_t
951 ecore_llh_access_filter(struct ecore_hwfn *p_hwfn,
952 struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx,
953 struct ecore_llh_filter_details *p_details,
956 u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
957 struct dmae_params params;
958 enum _ecore_status_t rc;
961 /* The NIG/LLH registers that are accessed in this function have only 16
962 * rows which are exposed to a PF. I.e. only the 16 filters of its
964 * Accessing filters of other ppfids requires pretending to other PFs,
965 * and thus the usage of the ecore_ppfid_rd/wr() functions.
968 /* Filter enable - should be done first when removing a filter */
969 if (b_write_access && !p_details->enable) {
970 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
971 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
976 addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
977 OSAL_MEMSET(¶ms, 0, sizeof(params));
979 if (b_write_access) {
980 SET_FIELD(params.flags, DMAE_PARAMS_DST_PF_VALID, 0x1);
981 params.dst_pf_id = pfid;
982 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
983 (u64)(osal_uintptr_t)&p_details->value,
984 addr, 2 /* size_in_dwords */, ¶ms);
986 SET_FIELD(params.flags, DMAE_PARAMS_SRC_PF_VALID, 0x1);
987 SET_FIELD(params.flags, DMAE_PARAMS_COMPLETION_DST, 0x1);
988 params.src_pf_id = pfid;
989 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, addr,
990 (u64)(osal_uintptr_t)&p_details->value,
991 2 /* size_in_dwords */, ¶ms);
994 if (rc != ECORE_SUCCESS)
998 addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
1000 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, p_details->mode);
1002 p_details->mode = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1005 /* Filter protocol type */
1006 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
1008 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1009 p_details->protocol_type);
1011 p_details->protocol_type = ecore_ppfid_rd(p_hwfn, p_ptt,
1014 /* Filter header select */
1015 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
1017 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1018 p_details->hdr_sel);
1020 p_details->hdr_sel = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1023 /* Filter enable - should be done last when adding a filter */
1024 if (!b_write_access || p_details->enable) {
1025 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
1027 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1030 p_details->enable = ecore_ppfid_rd(p_hwfn, p_ptt,
1034 return ECORE_SUCCESS;
1037 static enum _ecore_status_t
1038 ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1039 u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type,
1042 struct ecore_llh_filter_details filter_details;
1044 filter_details.enable = 1;
1045 filter_details.value = ((u64)high << 32) | low;
1046 filter_details.hdr_sel =
1047 OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
1048 1 : /* inner/encapsulated header */
1049 0; /* outer/tunnel header */
1050 filter_details.protocol_type = filter_prot_type;
1051 filter_details.mode = filter_prot_type ?
1052 1 : /* protocol-based classification */
1053 0; /* MAC-address based classification */
1055 return ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1057 true /* write access */);
1060 static enum _ecore_status_t
1061 ecore_llh_remove_filter(struct ecore_hwfn *p_hwfn,
1062 struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
1064 struct ecore_llh_filter_details filter_details;
1066 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1068 return ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1070 true /* write access */);
1073 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1074 u8 mac_addr[ETH_ALEN])
1076 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1077 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1078 union ecore_llh_filter filter;
1079 u8 filter_idx, abs_ppfid;
1080 u32 high, low, ref_cnt;
1081 enum _ecore_status_t rc = ECORE_SUCCESS;
1083 if (p_ptt == OSAL_NULL)
1086 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1089 OSAL_MEM_ZERO(&filter, sizeof(filter));
1090 OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1091 rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1092 ECORE_LLH_FILTER_TYPE_MAC,
1093 &filter, &filter_idx, &ref_cnt);
1094 if (rc != ECORE_SUCCESS)
1097 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1098 if (rc != ECORE_SUCCESS)
1101 /* Configure the LLH only in case of a new the filter */
1103 high = mac_addr[1] | (mac_addr[0] << 8);
1104 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1105 (mac_addr[2] << 24);
1106 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1108 if (rc != ECORE_SUCCESS)
1112 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1113 "LLH: Added MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1114 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1115 mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1121 DP_NOTICE(p_dev, false,
1122 "LLH: Failed to add MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd\n",
1123 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1124 mac_addr[4], mac_addr[5], ppfid);
1126 ecore_ptt_release(p_hwfn, p_ptt);
1131 static enum _ecore_status_t
1132 ecore_llh_protocol_filter_stringify(struct ecore_dev *p_dev,
1133 enum ecore_llh_prot_filter_type_t type,
1134 u16 source_port_or_eth_type, u16 dest_port,
1135 char *str, osal_size_t str_len)
1138 case ECORE_LLH_FILTER_ETHERTYPE:
1139 OSAL_SNPRINTF(str, str_len, "Ethertype 0x%04x",
1140 source_port_or_eth_type);
1142 case ECORE_LLH_FILTER_TCP_SRC_PORT:
1143 OSAL_SNPRINTF(str, str_len, "TCP src port 0x%04x",
1144 source_port_or_eth_type);
1146 case ECORE_LLH_FILTER_UDP_SRC_PORT:
1147 OSAL_SNPRINTF(str, str_len, "UDP src port 0x%04x",
1148 source_port_or_eth_type);
1150 case ECORE_LLH_FILTER_TCP_DEST_PORT:
1151 OSAL_SNPRINTF(str, str_len, "TCP dst port 0x%04x", dest_port);
1153 case ECORE_LLH_FILTER_UDP_DEST_PORT:
1154 OSAL_SNPRINTF(str, str_len, "UDP dst port 0x%04x", dest_port);
1156 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1157 OSAL_SNPRINTF(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1158 source_port_or_eth_type, dest_port);
1160 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1161 OSAL_SNPRINTF(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1162 source_port_or_eth_type, dest_port);
1165 DP_NOTICE(p_dev, true,
1166 "Non valid LLH protocol filter type %d\n", type);
1170 return ECORE_SUCCESS;
1173 static enum _ecore_status_t
1174 ecore_llh_protocol_filter_to_hilo(struct ecore_dev *p_dev,
1175 enum ecore_llh_prot_filter_type_t type,
1176 u16 source_port_or_eth_type, u16 dest_port,
1177 u32 *p_high, u32 *p_low)
1183 case ECORE_LLH_FILTER_ETHERTYPE:
1184 *p_high = source_port_or_eth_type;
1186 case ECORE_LLH_FILTER_TCP_SRC_PORT:
1187 case ECORE_LLH_FILTER_UDP_SRC_PORT:
1188 *p_low = source_port_or_eth_type << 16;
1190 case ECORE_LLH_FILTER_TCP_DEST_PORT:
1191 case ECORE_LLH_FILTER_UDP_DEST_PORT:
1194 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1195 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1196 *p_low = (source_port_or_eth_type << 16) | dest_port;
1199 DP_NOTICE(p_dev, true,
1200 "Non valid LLH protocol filter type %d\n", type);
1204 return ECORE_SUCCESS;
1207 enum _ecore_status_t
1208 ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1209 enum ecore_llh_prot_filter_type_t type,
1210 u16 source_port_or_eth_type, u16 dest_port)
1212 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1213 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1214 u8 filter_idx, abs_ppfid, type_bitmap;
1216 union ecore_llh_filter filter;
1217 u32 high, low, ref_cnt;
1218 enum _ecore_status_t rc = ECORE_SUCCESS;
1220 if (p_ptt == OSAL_NULL)
1223 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1226 rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1227 source_port_or_eth_type,
1228 dest_port, str, sizeof(str));
1229 if (rc != ECORE_SUCCESS)
1232 OSAL_MEM_ZERO(&filter, sizeof(filter));
1233 filter.protocol.type = type;
1234 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1235 filter.protocol.dest_port = dest_port;
1236 rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1237 ECORE_LLH_FILTER_TYPE_PROTOCOL,
1238 &filter, &filter_idx, &ref_cnt);
1239 if (rc != ECORE_SUCCESS)
1242 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1243 if (rc != ECORE_SUCCESS)
1246 /* Configure the LLH only in case of a new the filter */
1248 rc = ecore_llh_protocol_filter_to_hilo(p_dev, type,
1249 source_port_or_eth_type,
1250 dest_port, &high, &low);
1251 if (rc != ECORE_SUCCESS)
1254 type_bitmap = 0x1 << type;
1255 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1256 type_bitmap, high, low);
1257 if (rc != ECORE_SUCCESS)
1261 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1262 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1263 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1268 DP_NOTICE(p_hwfn, false,
1269 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1272 ecore_ptt_release(p_hwfn, p_ptt);
1277 void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1278 u8 mac_addr[ETH_ALEN])
1280 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1281 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1282 union ecore_llh_filter filter;
1283 u8 filter_idx, abs_ppfid;
1284 enum _ecore_status_t rc = ECORE_SUCCESS;
1287 if (p_ptt == OSAL_NULL)
1290 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1293 OSAL_MEM_ZERO(&filter, sizeof(filter));
1294 OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1295 rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1297 if (rc != ECORE_SUCCESS)
1300 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1301 if (rc != ECORE_SUCCESS)
1304 /* Remove from the LLH in case the filter is not in use */
1306 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1308 if (rc != ECORE_SUCCESS)
1312 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1313 "LLH: Removed MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1314 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1315 mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1321 DP_NOTICE(p_dev, false,
1322 "LLH: Failed to remove MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd\n",
1323 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1324 mac_addr[4], mac_addr[5], ppfid);
1326 ecore_ptt_release(p_hwfn, p_ptt);
1329 void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1330 enum ecore_llh_prot_filter_type_t type,
1331 u16 source_port_or_eth_type,
1334 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1335 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1336 u8 filter_idx, abs_ppfid;
1338 union ecore_llh_filter filter;
1339 enum _ecore_status_t rc = ECORE_SUCCESS;
1342 if (p_ptt == OSAL_NULL)
1345 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1348 rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1349 source_port_or_eth_type,
1350 dest_port, str, sizeof(str));
1351 if (rc != ECORE_SUCCESS)
1354 OSAL_MEM_ZERO(&filter, sizeof(filter));
1355 filter.protocol.type = type;
1356 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1357 filter.protocol.dest_port = dest_port;
1358 rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1360 if (rc != ECORE_SUCCESS)
1363 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1364 if (rc != ECORE_SUCCESS)
1367 /* Remove from the LLH in case the filter is not in use */
1369 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1371 if (rc != ECORE_SUCCESS)
1375 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1376 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1377 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1382 DP_NOTICE(p_dev, false,
1383 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1386 ecore_ptt_release(p_hwfn, p_ptt);
1389 void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid)
1391 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1392 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1393 u8 filter_idx, abs_ppfid;
1394 enum _ecore_status_t rc = ECORE_SUCCESS;
1396 if (p_ptt == OSAL_NULL)
1399 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1400 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1403 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1404 if (rc != ECORE_SUCCESS)
1407 rc = ecore_llh_shadow_remove_all_filters(p_dev, ppfid);
1408 if (rc != ECORE_SUCCESS)
1411 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1413 rc = ecore_llh_remove_filter(p_hwfn, p_ptt,
1414 abs_ppfid, filter_idx);
1415 if (rc != ECORE_SUCCESS)
1419 ecore_ptt_release(p_hwfn, p_ptt);
1422 void ecore_llh_clear_all_filters(struct ecore_dev *p_dev)
1426 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1427 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1430 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)
1431 ecore_llh_clear_ppfid_filters(p_dev, ppfid);
1434 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1435 struct ecore_ptt *p_ptt, u32 addr,
1438 struct ecore_dev *p_dev = p_hwfn->p_dev;
1439 u8 ppfid, abs_ppfid;
1440 enum _ecore_status_t rc;
1442 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1443 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1444 if (rc != ECORE_SUCCESS)
1447 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, val);
1450 return ECORE_SUCCESS;
1453 enum _ecore_status_t
1454 ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid)
1456 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1457 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1458 struct ecore_llh_filter_details filter_details;
1459 u8 abs_ppfid, filter_idx;
1461 enum _ecore_status_t rc;
1466 rc = ecore_abs_ppfid(p_hwfn->p_dev, ppfid, &abs_ppfid);
1467 if (rc != ECORE_SUCCESS)
1470 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
1471 DP_NOTICE(p_hwfn, false,
1472 "[rel_pf_id %hhd, ppfid={rel %hhd, abs %hhd}, engine_sel 0x%x]\n",
1473 p_hwfn->rel_pf_id, ppfid, abs_ppfid,
1474 ecore_rd(p_hwfn, p_ptt, addr));
1476 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1478 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1479 rc = ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid,
1480 filter_idx, &filter_details,
1481 false /* read access */);
1482 if (rc != ECORE_SUCCESS)
1485 DP_NOTICE(p_hwfn, false,
1486 "filter %2hhd: enable %d, value 0x%016lx, mode %d, protocol_type 0x%x, hdr_sel 0x%x\n",
1487 filter_idx, filter_details.enable,
1488 (unsigned long)filter_details.value,
1489 filter_details.mode,
1490 filter_details.protocol_type, filter_details.hdr_sel);
1495 ecore_ptt_release(p_hwfn, p_ptt);
1500 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev)
1503 enum _ecore_status_t rc;
1505 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1506 rc = ecore_llh_dump_ppfid(p_dev, ppfid);
1507 if (rc != ECORE_SUCCESS)
1511 return ECORE_SUCCESS;
1514 /******************************* NIG LLH - End ********************************/
1517 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
1518 * load the driver. The number was
1523 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
1525 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
1526 struct ecore_ptt *p_ptt,
1529 u32 bar_reg = (bar_id == BAR_ID_0 ?
1530 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1533 if (IS_VF(p_hwfn->p_dev))
1534 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
1536 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
1538 return 1 << (val + 15);
1540 /* The above registers were updated in the past only in CMT mode. Since
1541 * they were found to be useful MFW started updating them from 8.7.7.0.
1542 * In older MFW versions they are set to 0 which means disabled.
1544 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
1546 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1547 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1550 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1557 void ecore_init_dp(struct ecore_dev *p_dev,
1558 u32 dp_module, u8 dp_level, void *dp_ctx)
1562 p_dev->dp_level = dp_level;
1563 p_dev->dp_module = dp_module;
1564 p_dev->dp_ctx = dp_ctx;
1565 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1566 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1568 p_hwfn->dp_level = dp_level;
1569 p_hwfn->dp_module = dp_module;
1570 p_hwfn->dp_ctx = dp_ctx;
1574 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
1578 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1579 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1581 p_hwfn->p_dev = p_dev;
1583 p_hwfn->b_active = false;
1585 #ifdef CONFIG_ECORE_LOCK_ALLOC
1586 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
1589 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
1592 /* hwfn 0 is always active */
1593 p_dev->hwfns[0].b_active = true;
1595 /* set the default cache alignment to 128 (may be overridden later) */
1596 p_dev->cache_shift = 7;
1597 return ECORE_SUCCESS;
1598 #ifdef CONFIG_ECORE_LOCK_ALLOC
1601 struct ecore_hwfn *p_hwfn = OSAL_NULL;
1603 p_hwfn = &p_dev->hwfns[i];
1604 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
1610 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
1612 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1614 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
1615 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
1616 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
1617 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
1620 static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)
1622 OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);
1623 p_hwfn->dbg_user_info = OSAL_NULL;
1626 void ecore_resc_free(struct ecore_dev *p_dev)
1631 for_each_hwfn(p_dev, i)
1632 ecore_l2_free(&p_dev->hwfns[i]);
1636 OSAL_FREE(p_dev, p_dev->fw_data);
1638 OSAL_FREE(p_dev, p_dev->reset_stats);
1640 ecore_llh_free(p_dev);
1642 for_each_hwfn(p_dev, i) {
1643 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1645 ecore_cxt_mngr_free(p_hwfn);
1646 ecore_qm_info_free(p_hwfn);
1647 ecore_spq_free(p_hwfn);
1648 ecore_eq_free(p_hwfn);
1649 ecore_consq_free(p_hwfn);
1650 ecore_int_free(p_hwfn);
1651 ecore_iov_free(p_hwfn);
1652 ecore_l2_free(p_hwfn);
1653 ecore_dmae_info_free(p_hwfn);
1654 ecore_dcbx_info_free(p_hwfn);
1655 ecore_dbg_user_data_free(p_hwfn);
1656 /* @@@TBD Flush work-queue ? */
1658 /* destroy doorbell recovery mechanism */
1659 ecore_db_recovery_teardown(p_hwfn);
1663 /******************** QM initialization *******************/
1665 /* bitmaps for indicating active traffic classes.
1666 * Special case for Arrowhead 4 port
1668 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
1669 #define ACTIVE_TCS_BMAP 0x9f
1670 /* 0..3 actually used, OOO and high priority stuff all use 3 */
1671 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1673 /* determines the physical queue flags for a given PF. */
1674 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
1679 flags = PQ_FLAGS_LB;
1682 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
1683 flags |= PQ_FLAGS_VFS;
1684 if (IS_ECORE_PACING(p_hwfn))
1685 flags |= PQ_FLAGS_RLS;
1687 /* protocol flags */
1688 switch (p_hwfn->hw_info.personality) {
1690 if (!IS_ECORE_PACING(p_hwfn))
1691 flags |= PQ_FLAGS_MCOS;
1693 case ECORE_PCI_FCOE:
1694 flags |= PQ_FLAGS_OFLD;
1696 case ECORE_PCI_ISCSI:
1697 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1699 case ECORE_PCI_ETH_ROCE:
1700 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1701 if (!IS_ECORE_PACING(p_hwfn))
1702 flags |= PQ_FLAGS_MCOS;
1704 case ECORE_PCI_ETH_IWARP:
1705 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1706 if (!IS_ECORE_PACING(p_hwfn))
1707 flags |= PQ_FLAGS_MCOS;
1710 DP_ERR(p_hwfn, "unknown personality %d\n",
1711 p_hwfn->hw_info.personality);
1717 /* Getters for resource amounts necessary for qm initialization */
1718 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
1720 return p_hwfn->hw_info.num_hw_tc;
1723 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
1725 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
1726 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
1729 #define NUM_DEFAULT_RLS 1
1731 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
1733 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
1735 /* num RLs can't exceed resource amount of rls or vports or the
1738 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
1739 RESC_NUM(p_hwfn, ECORE_VPORT));
1741 /* make sure after we reserve the default and VF rls we'll have
1744 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
1745 DP_NOTICE(p_hwfn, false,
1746 "no rate limiters left for PF rate limiting"
1747 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
1751 /* subtract rls necessary for VFs and one default one for the PF */
1752 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1757 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
1759 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1761 /* all pqs share the same vport (hence the 1 below), except for vfs
1764 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1765 ecore_init_qm_get_num_pf_rls(p_hwfn) +
1766 (!!(PQ_FLAGS_VFS & pq_flags)) *
1767 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
1770 /* calc amount of PQs according to the requested flags */
1771 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
1773 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1775 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1776 ecore_init_qm_get_num_pf_rls(p_hwfn) +
1777 (!!(PQ_FLAGS_MCOS & pq_flags)) *
1778 ecore_init_qm_get_num_tcs(p_hwfn) +
1779 (!!(PQ_FLAGS_LB & pq_flags)) +
1780 (!!(PQ_FLAGS_OOO & pq_flags)) +
1781 (!!(PQ_FLAGS_ACK & pq_flags)) +
1782 (!!(PQ_FLAGS_OFLD & pq_flags)) +
1783 (!!(PQ_FLAGS_VFS & pq_flags)) *
1784 ecore_init_qm_get_num_vfs(p_hwfn);
1787 /* initialize the top level QM params */
1788 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
1790 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1793 /* pq and vport bases for this PF */
1794 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
1795 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
1797 /* rate limiting and weighted fair queueing are always enabled */
1798 qm_info->vport_rl_en = 1;
1799 qm_info->vport_wfq_en = 1;
1801 /* TC config is different for AH 4 port */
1802 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1804 /* in AH 4 port we have fewer TCs per port */
1805 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1808 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
1811 if (!qm_info->ooo_tc)
1812 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1816 /* initialize qm vport params */
1817 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
1819 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1822 /* all vports participate in weighted fair queueing */
1823 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
1824 qm_info->qm_vport_params[i].wfq = 1;
1827 /* initialize qm port params */
1828 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
1830 /* Initialize qm port parameters */
1831 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
1832 struct ecore_dev *p_dev = p_hwfn->p_dev;
1834 /* indicate how ooo and high pri traffic is dealt with */
1835 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1836 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
1838 for (i = 0; i < num_ports; i++) {
1839 struct init_qm_port_params *p_qm_port =
1840 &p_hwfn->qm_info.qm_port_params[i];
1841 u16 pbf_max_cmd_lines;
1843 p_qm_port->active = 1;
1844 p_qm_port->active_phys_tcs = active_phys_tcs;
1845 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(p_dev);
1846 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
1847 p_qm_port->num_btb_blocks =
1848 NUM_OF_BTB_BLOCKS(p_dev) / num_ports;
1852 /* Reset the params which must be reset for qm init. QM init may be called as
1853 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1854 * params may be affected by the init but would simply recalculate to the same
1855 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1856 * affected as these amounts stay the same.
1858 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
1860 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1862 qm_info->num_pqs = 0;
1863 qm_info->num_vports = 0;
1864 qm_info->num_pf_rls = 0;
1865 qm_info->num_vf_pqs = 0;
1866 qm_info->first_vf_pq = 0;
1867 qm_info->first_mcos_pq = 0;
1868 qm_info->first_rl_pq = 0;
1871 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
1873 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1875 qm_info->num_vports++;
1877 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1879 "vport overflow! qm_info->num_vports %d,"
1880 " qm_init_get_num_vports() %d\n",
1881 qm_info->num_vports,
1882 ecore_init_qm_get_num_vports(p_hwfn));
1885 /* initialize a single pq and manage qm_info resources accounting.
1886 * The pq_init_flags param determines whether the PQ is rate limited
1888 * and whether a new vport is allocated to the pq or not (i.e. vport will be
1892 /* flags for pq init */
1893 #define PQ_INIT_SHARE_VPORT (1 << 0)
1894 #define PQ_INIT_PF_RL (1 << 1)
1895 #define PQ_INIT_VF_RL (1 << 2)
1897 /* defines for pq init */
1898 #define PQ_INIT_DEFAULT_WRR_GROUP 1
1899 #define PQ_INIT_DEFAULT_TC 0
1900 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
1902 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
1903 struct ecore_qm_info *qm_info,
1904 u8 tc, u32 pq_init_flags)
1906 u16 pq_idx = qm_info->num_pqs, max_pq =
1907 ecore_init_qm_get_num_pqs(p_hwfn);
1909 if (pq_idx > max_pq)
1911 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1913 /* init pq params */
1914 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1915 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1916 qm_info->num_vports;
1917 qm_info->qm_pq_params[pq_idx].tc_id = tc;
1918 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1919 qm_info->qm_pq_params[pq_idx].rl_valid =
1920 (pq_init_flags & PQ_INIT_PF_RL ||
1921 pq_init_flags & PQ_INIT_VF_RL);
1923 /* The "rl_id" is set as the "vport_id" */
1924 qm_info->qm_pq_params[pq_idx].rl_id =
1925 qm_info->qm_pq_params[pq_idx].vport_id;
1927 /* qm params accounting */
1929 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1930 qm_info->num_vports++;
1932 if (pq_init_flags & PQ_INIT_PF_RL)
1933 qm_info->num_pf_rls++;
1935 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1937 "vport overflow! qm_info->num_vports %d,"
1938 " qm_init_get_num_vports() %d\n",
1939 qm_info->num_vports,
1940 ecore_init_qm_get_num_vports(p_hwfn));
1942 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
1943 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
1944 " qm_init_get_num_pf_rls() %d\n",
1945 qm_info->num_pf_rls,
1946 ecore_init_qm_get_num_pf_rls(p_hwfn));
1949 /* get pq index according to PQ_FLAGS */
1950 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
1953 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1955 /* Can't have multiple flags set here */
1956 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
1957 sizeof(pq_flags)) > 1)
1962 return &qm_info->first_rl_pq;
1964 return &qm_info->first_mcos_pq;
1966 return &qm_info->pure_lb_pq;
1968 return &qm_info->ooo_pq;
1970 return &qm_info->pure_ack_pq;
1972 return &qm_info->offload_pq;
1974 return &qm_info->first_vf_pq;
1980 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
1984 /* save pq index in qm info */
1985 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
1986 u32 pq_flags, u16 pq_val)
1988 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1990 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
1993 /* get tx pq index, with the PQ TX base already set (ready for context init) */
1994 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
1996 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1998 return *base_pq_idx + CM_TX_PQ_BASE;
2001 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
2003 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
2006 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
2008 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
2011 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
2013 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
2016 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
2018 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
2021 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
2023 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
2025 /* for rate limiters, it is okay to use the modulo behavior - no
2028 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + (rl % max_rl);
2031 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
2033 u16 start_pq, pq, qm_pq_idx;
2035 pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
2036 start_pq = p_hwfn->qm_info.start_pq;
2037 qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;
2039 if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
2041 "qm_pq_idx %d must be smaller than %d\n",
2042 qm_pq_idx, p_hwfn->qm_info.num_pqs);
2045 return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
2048 /* Functions for creating specific types of pqs */
2049 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
2051 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2053 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
2056 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
2057 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
2060 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
2062 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2064 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
2067 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
2068 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
2071 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
2073 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2075 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
2078 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
2079 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2082 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
2084 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2086 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
2089 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
2090 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2093 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
2095 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2098 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
2101 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
2102 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
2103 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
2106 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
2108 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2109 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
2111 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
2114 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
2116 qm_info->num_vf_pqs = num_vfs;
2117 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
2118 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
2122 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
2124 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
2125 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2127 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
2130 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
2131 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
2132 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
2136 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
2138 /* rate limited pqs, must come first (FW assumption) */
2139 ecore_init_qm_rl_pqs(p_hwfn);
2141 /* pqs for multi cos */
2142 ecore_init_qm_mcos_pqs(p_hwfn);
2144 /* pure loopback pq */
2145 ecore_init_qm_lb_pq(p_hwfn);
2147 /* out of order pq */
2148 ecore_init_qm_ooo_pq(p_hwfn);
2151 ecore_init_qm_pure_ack_pq(p_hwfn);
2153 /* pq for offloaded protocol */
2154 ecore_init_qm_offload_pq(p_hwfn);
2156 /* done sharing vports */
2157 ecore_init_qm_advance_vport(p_hwfn);
2160 ecore_init_qm_vf_pqs(p_hwfn);
2163 /* compare values of getters against resources amounts */
2164 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
2166 if (ecore_init_qm_get_num_vports(p_hwfn) >
2167 RESC_NUM(p_hwfn, ECORE_VPORT)) {
2168 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
2172 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
2173 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
2177 return ECORE_SUCCESS;
2181 * Function for verbose printing of the qm initialization results
2183 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
2185 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2186 struct init_qm_vport_params *vport;
2187 struct init_qm_port_params *port;
2188 struct init_qm_pq_params *pq;
2191 /* top level params */
2192 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2193 "qm init top level params: start_pq %d, start_vport %d,"
2194 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
2195 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
2196 qm_info->offload_pq, qm_info->pure_ack_pq);
2197 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2198 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
2199 " num_vports %d, max_phys_tcs_per_port %d\n",
2200 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
2201 qm_info->num_vf_pqs, qm_info->num_vports,
2202 qm_info->max_phys_tcs_per_port);
2203 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2204 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
2205 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2206 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
2207 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
2208 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
2211 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
2212 port = &qm_info->qm_port_params[i];
2213 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2214 "port idx %d, active %d, active_phys_tcs %d,"
2215 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
2217 i, port->active, port->active_phys_tcs,
2218 port->num_pbf_cmd_lines, port->num_btb_blocks,
2223 for (i = 0; i < qm_info->num_vports; i++) {
2224 vport = &qm_info->qm_vport_params[i];
2225 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "vport idx %d, wfq %d, first_tx_pq_id [ ",
2226 qm_info->start_vport + i, vport->wfq);
2227 for (tc = 0; tc < NUM_OF_TCS; tc++)
2228 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
2229 vport->first_tx_pq_id[tc]);
2230 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
2234 for (i = 0; i < qm_info->num_pqs; i++) {
2235 pq = &qm_info->qm_pq_params[i];
2236 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2237 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d, rl_id %d\n",
2238 qm_info->start_pq + i, pq->port_id, pq->vport_id,
2239 pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id);
2243 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
2245 /* reset params required for init run */
2246 ecore_init_qm_reset_params(p_hwfn);
2248 /* init QM top level params */
2249 ecore_init_qm_params(p_hwfn);
2251 /* init QM port params */
2252 ecore_init_qm_port_params(p_hwfn);
2254 /* init QM vport params */
2255 ecore_init_qm_vport_params(p_hwfn);
2257 /* init QM physical queue params */
2258 ecore_init_qm_pq_params(p_hwfn);
2260 /* display all that init */
2261 ecore_dp_init_qm_params(p_hwfn);
2264 /* This function reconfigures the QM pf on the fly.
2265 * For this purpose we:
2266 * 1. reconfigure the QM database
2267 * 2. set new values to runtime array
2268 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2269 * 4. activate init tool in QM_PF stage
2270 * 5. send an sdm_qm_cmd through rbc interface to release the QM
2272 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
2273 struct ecore_ptt *p_ptt)
2275 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2277 enum _ecore_status_t rc = ECORE_SUCCESS;
2279 /* multiple flows can issue qm reconf. Need to lock */
2280 OSAL_SPIN_LOCK(&qm_lock);
2282 /* initialize ecore's qm data structure */
2283 ecore_init_qm_info(p_hwfn);
2285 /* stop PF's qm queues */
2286 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2287 qm_info->start_pq, qm_info->num_pqs);
2293 /* clear the QM_PF runtime phase leftovers from previous init */
2294 ecore_init_clear_rt_data(p_hwfn);
2296 /* prepare QM portion of runtime array */
2297 ecore_qm_init_pf(p_hwfn, p_ptt, false);
2299 /* activate init tool on runtime array */
2300 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2301 p_hwfn->hw_info.hw_mode);
2303 /* start PF's qm queues */
2304 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2305 qm_info->start_pq, qm_info->num_pqs);
2310 OSAL_SPIN_UNLOCK(&qm_lock);
2315 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
2317 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2318 enum _ecore_status_t rc;
2320 rc = ecore_init_qm_sanity(p_hwfn);
2321 if (rc != ECORE_SUCCESS)
2324 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2325 sizeof(struct init_qm_pq_params) *
2326 ecore_init_qm_get_num_pqs(p_hwfn));
2327 if (!qm_info->qm_pq_params)
2330 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2331 sizeof(struct init_qm_vport_params) *
2332 ecore_init_qm_get_num_vports(p_hwfn));
2333 if (!qm_info->qm_vport_params)
2336 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2337 sizeof(struct init_qm_port_params) *
2338 p_hwfn->p_dev->num_ports_in_engine);
2339 if (!qm_info->qm_port_params)
2342 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2343 sizeof(struct ecore_wfq_data) *
2344 ecore_init_qm_get_num_vports(p_hwfn));
2345 if (!qm_info->wfq_data)
2348 return ECORE_SUCCESS;
2351 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
2352 ecore_qm_info_free(p_hwfn);
2355 /******************** End QM initialization ***************/
2357 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
2359 enum _ecore_status_t rc = ECORE_SUCCESS;
2363 for_each_hwfn(p_dev, i) {
2364 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
2365 if (rc != ECORE_SUCCESS)
2371 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2372 sizeof(*p_dev->fw_data));
2373 if (!p_dev->fw_data)
2376 for_each_hwfn(p_dev, i) {
2377 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2378 u32 n_eqes, num_cons;
2380 /* initialize the doorbell recovery mechanism */
2381 rc = ecore_db_recovery_setup(p_hwfn);
2385 /* First allocate the context manager structure */
2386 rc = ecore_cxt_mngr_alloc(p_hwfn);
2390 /* Set the HW cid/tid numbers (in the context manager)
2391 * Must be done prior to any further computations.
2393 rc = ecore_cxt_set_pf_params(p_hwfn);
2397 rc = ecore_alloc_qm_data(p_hwfn);
2402 ecore_init_qm_info(p_hwfn);
2404 /* Compute the ILT client partition */
2405 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
2409 /* CID map / ILT shadow table / T2
2410 * The talbes sizes are determined by the computations above
2412 rc = ecore_cxt_tables_alloc(p_hwfn);
2416 /* SPQ, must follow ILT because initializes SPQ context */
2417 rc = ecore_spq_alloc(p_hwfn);
2421 /* SP status block allocation */
2422 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
2425 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2429 rc = ecore_iov_alloc(p_hwfn);
2434 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
2435 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
2436 /* Calculate the EQ size
2437 * ---------------------
2438 * Each ICID may generate up to one event at a time i.e.
2439 * the event must be handled/cleared before a new one
2440 * can be generated. We calculate the sum of events per
2441 * protocol and create an EQ deep enough to handle the
2443 * - Core - according to SPQ.
2444 * - RoCE - per QP there are a couple of ICIDs, one
2445 * responder and one requester, each can
2446 * generate an EQE => n_eqes_qp = 2 * n_qp.
2447 * Each CQ can generate an EQE. There are 2 CQs
2448 * per QP => n_eqes_cq = 2 * n_qp.
2449 * Hence the RoCE total is 4 * n_qp or
2451 * - ENet - There can be up to two events per VF. One
2452 * for VF-PF channel and another for VF FLR
2453 * initial cleanup. The number of VFs is
2454 * bounded by MAX_NUM_VFS_BB, and is much
2455 * smaller than RoCE's so we avoid exact
2458 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
2460 ecore_cxt_get_proto_cid_count(
2466 num_cons = ecore_cxt_get_proto_cid_count(
2471 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
2472 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
2474 ecore_cxt_get_proto_cid_count(p_hwfn,
2477 n_eqes += 2 * num_cons;
2480 if (n_eqes > 0xFFFF) {
2481 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
2482 "The maximum of a u16 chain is 0x%x\n",
2487 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
2491 rc = ecore_consq_alloc(p_hwfn);
2495 rc = ecore_l2_alloc(p_hwfn);
2496 if (rc != ECORE_SUCCESS)
2499 /* DMA info initialization */
2500 rc = ecore_dmae_info_alloc(p_hwfn);
2502 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
2506 /* DCBX initialization */
2507 rc = ecore_dcbx_info_alloc(p_hwfn);
2509 DP_NOTICE(p_hwfn, false,
2510 "Failed to allocate memory for dcbx structure\n");
2514 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
2516 DP_NOTICE(p_hwfn, false,
2517 "Failed to allocate dbg user info structure\n");
2521 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
2523 DP_NOTICE(p_hwfn, false,
2524 "Failed to allocate dbg user info structure\n");
2529 rc = ecore_llh_alloc(p_dev);
2530 if (rc != ECORE_SUCCESS) {
2531 DP_NOTICE(p_dev, true,
2532 "Failed to allocate memory for the llh_info structure\n");
2536 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2537 sizeof(*p_dev->reset_stats));
2538 if (!p_dev->reset_stats) {
2539 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
2543 return ECORE_SUCCESS;
2548 ecore_resc_free(p_dev);
2552 void ecore_resc_setup(struct ecore_dev *p_dev)
2557 for_each_hwfn(p_dev, i)
2558 ecore_l2_setup(&p_dev->hwfns[i]);
2562 for_each_hwfn(p_dev, i) {
2563 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2565 ecore_cxt_mngr_setup(p_hwfn);
2566 ecore_spq_setup(p_hwfn);
2567 ecore_eq_setup(p_hwfn);
2568 ecore_consq_setup(p_hwfn);
2570 /* Read shadow of current MFW mailbox */
2571 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2572 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2573 p_hwfn->mcp_info->mfw_mb_cur,
2574 p_hwfn->mcp_info->mfw_mb_length);
2576 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2578 ecore_l2_setup(p_hwfn);
2579 ecore_iov_setup(p_hwfn);
2583 #define FINAL_CLEANUP_POLL_CNT (100)
2584 #define FINAL_CLEANUP_POLL_TIME (10)
2585 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
2586 struct ecore_ptt *p_ptt,
2589 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2590 enum _ecore_status_t rc = ECORE_TIMEOUT;
2593 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
2594 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2595 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
2596 return ECORE_SUCCESS;
2600 addr = GTT_BAR0_MAP_REG_USDM_RAM +
2601 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2606 command |= X_FINAL_CLEANUP_AGG_INT <<
2607 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2608 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2609 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2610 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2612 /* Make sure notification is not set before initiating final cleanup */
2614 if (REG_RD(p_hwfn, addr)) {
2615 DP_NOTICE(p_hwfn, false,
2616 "Unexpected; Found final cleanup notification");
2617 DP_NOTICE(p_hwfn, false,
2618 " before initiating final cleanup\n");
2619 REG_WR(p_hwfn, addr, 0);
2622 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2623 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2626 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2628 /* Poll until completion */
2629 while (!REG_RD(p_hwfn, addr) && count--)
2630 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
2632 if (REG_RD(p_hwfn, addr))
2635 DP_NOTICE(p_hwfn, true,
2636 "Failed to receive FW final cleanup notification\n");
2638 /* Cleanup afterwards */
2639 REG_WR(p_hwfn, addr, 0);
2644 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
2648 if (ECORE_IS_BB(p_hwfn->p_dev)) {
2649 hw_mode |= 1 << MODE_BB;
2650 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
2651 hw_mode |= 1 << MODE_K2;
2653 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
2654 p_hwfn->p_dev->type);
2658 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
2659 switch (p_hwfn->p_dev->num_ports_in_engine) {
2661 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2664 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2667 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2670 DP_NOTICE(p_hwfn, true,
2671 "num_ports_in_engine = %d not supported\n",
2672 p_hwfn->p_dev->num_ports_in_engine);
2676 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
2677 hw_mode |= 1 << MODE_MF_SD;
2679 hw_mode |= 1 << MODE_MF_SI;
2682 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2683 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2684 hw_mode |= 1 << MODE_FPGA;
2686 if (p_hwfn->p_dev->b_is_emul_full)
2687 hw_mode |= 1 << MODE_EMUL_FULL;
2689 hw_mode |= 1 << MODE_EMUL_REDUCED;
2693 hw_mode |= 1 << MODE_ASIC;
2695 if (ECORE_IS_CMT(p_hwfn->p_dev))
2696 hw_mode |= 1 << MODE_100G;
2698 p_hwfn->hw_info.hw_mode = hw_mode;
2700 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
2701 "Configuring function for hw_mode: 0x%08x\n",
2702 p_hwfn->hw_info.hw_mode);
2704 return ECORE_SUCCESS;
2708 /* MFW-replacement initializations for emulation */
2709 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_dev *p_dev,
2710 struct ecore_ptt *p_ptt)
2712 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2717 if (!CHIP_REV_IS_EMUL(p_dev)) {
2718 DP_NOTICE(p_dev, false,
2719 "ecore_hw_init_chip() shouldn't be called in a non-emulation environment\n");
2723 pl_hv = ECORE_IS_BB(p_dev) ? 0x1 : 0x401;
2724 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
2726 if (ECORE_IS_AH(p_dev))
2727 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2, 0x3ffffff);
2729 /* Initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
2730 if (ECORE_IS_BB(p_dev))
2731 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
2733 if (ECORE_IS_AH(p_dev)) {
2734 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
2735 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
2736 p_dev->num_ports_in_engine >> 1);
2738 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
2739 p_dev->num_ports_in_engine == 4 ? 0 : 3);
2742 /* Signal the PSWRQ block to start initializing internal memories */
2743 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
2744 for (i = 0; i < 100; i++) {
2746 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
2750 DP_NOTICE(p_hwfn, true,
2751 "RBC done failed to complete in PSWRQ2\n");
2752 return ECORE_TIMEOUT;
2755 /* Indicate PSWRQ to initialize steering tag table with zeros */
2756 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RESET_STT, 1);
2757 for (i = 0; i < 100; i++) {
2759 if (!ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_RESET_STT))
2763 DP_NOTICE(p_hwfn, true,
2764 "Steering tag table initialization failed to complete in PSWRQ2\n");
2765 return ECORE_TIMEOUT;
2768 /* Clear a possible PSWRQ2 STT parity which might have been generated by
2769 * a previous MSI-X read.
2771 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_PRTY_STS_WR_H_0, 0x8);
2773 /* Configure PSWRQ2_REG_WR_MBS0 according to the MaxPayloadSize field in
2774 * the PCI configuration space. The value is common for all PFs, so it
2775 * is okay to do it according to the first loading PF.
2777 pos = OSAL_PCI_FIND_CAPABILITY(p_dev, PCI_CAP_ID_EXP);
2779 DP_NOTICE(p_dev, true,
2780 "Failed to find the PCI Express Capability structure in the PCI config space\n");
2784 OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2785 wr_mbs = (ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
2786 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0, wr_mbs);
2788 /* Configure the PGLUE_B to discard mode */
2789 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_DISCARD_NBLOCK, 0x3f);
2791 return ECORE_SUCCESS;
2795 /* Init run time data for all PFs and their VFs on an engine.
2796 * TBD - for VFs - Once we have parent PF info for each VF in
2797 * shmem available as CAU requires knowledge of parent PF for each VF.
2799 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
2801 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2805 for_each_hwfn(p_dev, i) {
2806 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2807 struct ecore_igu_info *p_igu_info;
2808 struct ecore_igu_block *p_block;
2809 struct cau_sb_entry sb_entry;
2811 p_igu_info = p_hwfn->hw_info.p_igu_info;
2814 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
2816 p_block = &p_igu_info->entry[igu_sb_id];
2818 if (!p_block->is_pf)
2821 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
2822 p_block->function_id, 0, 0);
2823 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2829 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
2830 struct ecore_ptt *p_ptt)
2832 u32 val, wr_mbs, cache_line_size;
2834 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2847 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2852 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
2853 switch (cache_line_size) {
2868 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2872 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
2874 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2875 OSAL_CACHE_LINE_SIZE, wr_mbs);
2877 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2879 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2880 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2884 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
2885 struct ecore_ptt *p_ptt,
2888 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2889 struct ecore_dev *p_dev = p_hwfn->p_dev;
2890 u8 vf_id, max_num_vfs;
2893 enum _ecore_status_t rc = ECORE_SUCCESS;
2895 ecore_init_cau_rt_data(p_dev);
2897 /* Program GTT windows */
2898 ecore_gtt_init(p_hwfn);
2901 if (CHIP_REV_IS_EMUL(p_dev) && IS_LEAD_HWFN(p_hwfn)) {
2902 rc = ecore_hw_init_chip(p_dev, p_ptt);
2903 if (rc != ECORE_SUCCESS)
2908 if (p_hwfn->mcp_info) {
2909 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2910 qm_info->pf_rl_en = 1;
2911 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2912 qm_info->pf_wfq_en = 1;
2915 ecore_qm_common_rt_init(p_hwfn,
2916 p_dev->num_ports_in_engine,
2917 qm_info->max_phys_tcs_per_port,
2918 qm_info->pf_rl_en, qm_info->pf_wfq_en,
2919 qm_info->vport_rl_en, qm_info->vport_wfq_en,
2920 qm_info->qm_port_params,
2921 OSAL_NULL /* global RLs are not configured */);
2923 ecore_cxt_hw_init_common(p_hwfn);
2925 ecore_init_cache_line_size(p_hwfn, p_ptt);
2927 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
2929 if (rc != ECORE_SUCCESS)
2932 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
2933 * need to decide with which value, maybe runtime
2935 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2936 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2938 if (ECORE_IS_BB(p_dev)) {
2939 /* Workaround clears ROCE search for all functions to prevent
2940 * involving non initialized function in processing ROCE packet.
2942 num_pfs = (u16)NUM_OF_ENG_PFS(p_dev);
2943 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2944 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
2945 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2946 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2948 /* pretend to original PF */
2949 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2952 /* Workaround for avoiding CCFC execution error when getting packets
2953 * with CRC errors, and allowing instead the invoking of the FW error
2955 * This is not done inside the init tool since it currently can't
2956 * perform a pretending to VFs.
2958 max_num_vfs = (u8)NUM_OF_VFS(p_dev);
2959 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2960 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
2961 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
2962 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2963 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2964 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2965 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2967 /* pretend to original PF */
2968 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2974 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
2975 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
2977 #define PMEG_IF_BYTE_COUNT 8
2979 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
2980 struct ecore_ptt *p_ptt,
2981 u32 addr, u64 data, u8 reg_type, u8 port)
2983 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2984 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
2985 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
2986 (8 << PMEG_IF_BYTE_COUNT),
2987 (reg_type << 25) | (addr << 8) | port,
2988 (u32)((data >> 32) & 0xffffffff),
2989 (u32)(data & 0xffffffff));
2991 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
2992 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
2993 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
2994 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
2995 (reg_type << 25) | (addr << 8) | port);
2996 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
2997 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
2998 (data >> 32) & 0xffffffff);
3001 #define XLPORT_MODE_REG (0x20a)
3002 #define XLPORT_MAC_CONTROL (0x210)
3003 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
3004 #define XLPORT_ENABLE_REG (0x20b)
3006 #define XLMAC_CTRL (0x600)
3007 #define XLMAC_MODE (0x601)
3008 #define XLMAC_RX_MAX_SIZE (0x608)
3009 #define XLMAC_TX_CTRL (0x604)
3010 #define XLMAC_PAUSE_CTRL (0x60d)
3011 #define XLMAC_PFC_CTRL (0x60e)
3013 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
3014 struct ecore_ptt *p_ptt)
3016 u8 loopback = 0, port = p_hwfn->port_id * 2;
3018 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
3019 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
3021 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
3022 /* XLMAC: SOFT RESET */
3023 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
3024 /* XLMAC: Port Speed >= 10Gbps */
3025 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
3026 /* XLMAC: Max Size */
3027 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
3028 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
3029 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
3031 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
3032 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
3033 0x30ffffc000ULL, 0, port);
3034 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
3035 port); /* XLMAC: TX_EN, RX_EN */
3036 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
3037 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
3038 0x1003 | (loopback << 2), 0, port);
3039 /* Enabled Parallel PFC interface */
3040 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
3042 /* XLPORT port enable */
3043 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
3046 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
3047 struct ecore_ptt *p_ptt)
3049 u32 mac_base, mac_config_val = 0xa853;
3050 u8 port = p_hwfn->port_id;
3052 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
3053 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_SHIFT) |
3055 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_SHIFT) |
3056 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_SHIFT));
3058 mac_base = NWM_REG_MAC0_K2 + (port << 2) * NWM_REG_MAC0_SIZE;
3060 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2,
3061 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_SHIFT);
3063 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2,
3064 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_SHIFT);
3066 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2,
3067 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_SHIFT);
3069 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2,
3070 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_SHIFT);
3072 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2,
3074 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_SHIFT) |
3076 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_SHIFT));
3078 /* Strip the CRC field from the frame */
3079 mac_config_val &= ~ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2;
3080 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2,
3084 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
3085 struct ecore_ptt *p_ptt)
3087 u8 port = ECORE_IS_BB(p_hwfn->p_dev) ? p_hwfn->port_id * 2
3090 DP_INFO(p_hwfn->p_dev, "Emulation: Configuring Link [port %02x]\n",
3093 if (ECORE_IS_BB(p_hwfn->p_dev))
3094 ecore_emul_link_init_bb(p_hwfn, p_ptt);
3096 ecore_emul_link_init_ah(p_hwfn, p_ptt);
3101 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
3102 struct ecore_ptt *p_ptt, u8 port)
3104 int port_offset = port ? 0x800 : 0;
3105 u32 xmac_rxctrl = 0;
3108 /* FIXME: move to common start */
3109 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3110 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
3112 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3113 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
3115 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
3117 /* Set the number of ports on the Warp Core to 10G */
3118 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
3120 /* Soft reset of XMAC */
3121 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3122 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3124 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3125 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3127 /* FIXME: move to common end */
3128 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3129 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
3131 /* Set Max packet size: initialize XMAC block register for port 0 */
3132 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
3134 /* CRC append for Tx packets: init XMAC block register for port 1 */
3135 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
3137 /* Enable TX and RX: initialize XMAC block register for port 1 */
3138 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
3139 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
3140 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
3141 XMAC_REG_RX_CTRL_BB + port_offset);
3142 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
3143 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
3147 static u32 ecore_hw_norm_region_conn(struct ecore_hwfn *p_hwfn)
3149 u32 norm_region_conn;
3151 /* The order of CIDs allocation is according to the order of
3152 * 'enum protocol_type'. Therefore, the number of CIDs for the normal
3153 * region is calculated based on the CORE CIDs, in case of non-ETH
3154 * personality, and otherwise - based on the ETH CIDs.
3157 ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
3158 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
3160 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
3163 return norm_region_conn;
3166 static enum _ecore_status_t
3167 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
3168 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
3170 u32 dpi_bit_shift, dpi_count, dpi_page_size;
3174 /* Calculate DPI size
3175 * ------------------
3176 * The PWM region contains Doorbell Pages. The first is reserverd for
3177 * the kernel for, e.g, L2. The others are free to be used by non-
3178 * trusted applications, typically from user space. Each page, called a
3179 * doorbell page is sectioned into windows that allow doorbells to be
3180 * issued in parallel by the kernel/application. The size of such a
3181 * window (a.k.a. WID) is 1kB.
3183 * 1kB WID x N WIDS = DPI page size
3184 * DPI page size x N DPIs = PWM region size
3186 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
3187 * in order to ensure that two applications won't share the same page.
3188 * It also must contain at least one WID per CPU to allow parallelism.
3189 * It also must be a power of 2, since it is stored as a bit shift.
3191 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
3192 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
3193 * containing 4 WIDs.
3195 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
3196 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
3197 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
3198 ~(OSAL_PAGE_SIZE - 1);
3199 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
3200 dpi_count = pwm_region_size / dpi_page_size;
3202 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
3203 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
3206 p_hwfn->dpi_size = dpi_page_size;
3207 p_hwfn->dpi_count = dpi_count;
3209 /* Update registers */
3210 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
3212 if (dpi_count < min_dpis)
3213 return ECORE_NORESOURCES;
3215 return ECORE_SUCCESS;
3218 enum ECORE_ROCE_EDPM_MODE {
3219 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
3220 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
3221 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
3224 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn)
3226 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
3232 static enum _ecore_status_t
3233 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
3234 struct ecore_ptt *p_ptt)
3236 u32 norm_region_conn, min_addr_reg1;
3237 u32 pwm_regsize, norm_regsize;
3238 u32 db_bar_size, n_cpus;
3241 enum _ecore_status_t rc = ECORE_SUCCESS;
3244 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
3245 if (ECORE_IS_CMT(p_hwfn->p_dev))
3248 /* Calculate doorbell regions
3249 * -----------------------------------
3250 * The doorbell BAR is made of two regions. The first is called normal
3251 * region and the second is called PWM region. In the normal region
3252 * each ICID has its own set of addresses so that writing to that
3253 * specific address identifies the ICID. In the Process Window Mode
3254 * region the ICID is given in the data written to the doorbell. The
3255 * above per PF register denotes the offset in the doorbell BAR in which
3256 * the PWM region begins.
3257 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
3258 * non-PWM connection. The calculation below computes the total non-PWM
3259 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
3260 * in units of 4,096 bytes.
3262 norm_region_conn = ecore_hw_norm_region_conn(p_hwfn);
3263 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * norm_region_conn,
3265 min_addr_reg1 = norm_regsize / 4096;
3266 pwm_regsize = db_bar_size - norm_regsize;
3268 /* Check that the normal and PWM sizes are valid */
3269 if (db_bar_size < norm_regsize) {
3270 DP_ERR(p_hwfn->p_dev,
3271 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
3272 db_bar_size, norm_regsize);
3273 return ECORE_NORESOURCES;
3275 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
3276 DP_ERR(p_hwfn->p_dev,
3277 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
3278 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
3280 return ECORE_NORESOURCES;
3283 /* Calculate number of DPIs */
3284 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
3285 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
3286 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
3287 /* Either EDPM is mandatory, or we are attempting to allocate a
3290 n_cpus = OSAL_NUM_CPUS();
3291 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3294 cond = ((rc != ECORE_SUCCESS) &&
3295 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
3296 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
3297 if (cond || p_hwfn->dcbx_no_edpm) {
3298 /* Either EDPM is disabled from user configuration, or it is
3299 * disabled via DCBx, or it is not mandatory and we failed to
3300 * allocated a WID per CPU.
3303 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3305 /* If we entered this flow due to DCBX then the DPM register is
3306 * already configured.
3311 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
3312 norm_regsize, pwm_regsize);
3314 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
3315 p_hwfn->dpi_size, p_hwfn->dpi_count,
3316 (!ecore_edpm_enabled(p_hwfn)) ?
3317 "disabled" : "enabled");
3319 /* Check return codes from above calls */
3320 if (rc != ECORE_SUCCESS) {
3322 "Failed to allocate enough DPIs\n");
3323 return ECORE_NORESOURCES;
3327 p_hwfn->dpi_start_offset = norm_regsize;
3329 /* Update registers */
3330 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
3331 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
3332 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
3333 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
3335 return ECORE_SUCCESS;
3338 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
3339 struct ecore_ptt *p_ptt,
3342 struct ecore_dev *p_dev = p_hwfn->p_dev;
3343 enum _ecore_status_t rc = ECORE_SUCCESS;
3345 /* In CMT the gate should be cleared by the 2nd hwfn */
3346 if (!ECORE_IS_CMT(p_dev) || !IS_LEAD_HWFN(p_hwfn))
3347 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
3349 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
3351 if (rc != ECORE_SUCCESS)
3354 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
3357 if (CHIP_REV_IS_FPGA(p_dev) && ECORE_IS_BB(p_dev))
3358 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
3360 if (CHIP_REV_IS_EMUL(p_dev)) {
3361 if (ECORE_IS_CMT(p_dev)) {
3362 /* Activate OPTE in CMT */
3365 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
3367 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
3368 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
3369 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
3370 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
3371 ecore_wr(p_hwfn, p_ptt,
3372 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
3373 ecore_wr(p_hwfn, p_ptt,
3374 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
3375 ecore_wr(p_hwfn, p_ptt,
3376 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
3380 /* Set the TAGMAC default function on the port if needed.
3381 * The ppfid should be set in the vector, except in BB which has
3382 * a bug in the LLH where the ppfid is actually engine based.
3384 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {
3385 u8 pf_id = p_hwfn->rel_pf_id;
3387 if (!ECORE_IS_BB(p_dev))
3388 pf_id /= p_dev->num_ports_in_engine;
3389 ecore_wr(p_hwfn, p_ptt,
3390 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
3393 ecore_emul_link_init(p_hwfn, p_ptt);
3397 return ECORE_SUCCESS;
3400 static enum _ecore_status_t
3401 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3402 int hw_mode, struct ecore_hw_init_params *p_params)
3404 u8 rel_pf_id = p_hwfn->rel_pf_id;
3406 enum _ecore_status_t rc = ECORE_SUCCESS;
3410 if (p_hwfn->mcp_info) {
3411 struct ecore_mcp_function_info *p_info;
3413 p_info = &p_hwfn->mcp_info->func_info;
3414 if (p_info->bandwidth_min)
3415 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
3417 /* Update rate limit once we'll actually have a link */
3418 p_hwfn->qm_info.pf_rl = 100000;
3420 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
3422 ecore_int_igu_init_rt(p_hwfn);
3424 /* Set VLAN in NIG if needed */
3425 if (hw_mode & (1 << MODE_MF_SD)) {
3426 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
3427 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
3428 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
3429 p_hwfn->hw_info.ovlan);
3431 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3432 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
3433 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
3437 /* Enable classification by MAC if needed */
3438 if (hw_mode & (1 << MODE_MF_SI)) {
3439 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3440 "Configuring TAGMAC_CLS_TYPE\n");
3441 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
3445 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
3446 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
3447 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
3448 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
3449 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
3450 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
3452 /* perform debug configuration when chip is out of reset */
3453 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
3455 /* Sanity check before the PF init sequence that uses DMAE */
3456 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
3460 /* PF Init sequence */
3461 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
3465 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
3466 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
3470 /* Pure runtime initializations - directly to the HW */
3471 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
3473 /* PCI relaxed ordering causes a decrease in the performance on some
3474 * systems. Till a root cause is found, disable this attribute in the
3478 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
3480 * DP_NOTICE(p_hwfn, true,
3481 * "Failed to find the PCIe Cap\n");
3484 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
3485 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
3486 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
3489 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
3490 if (rc != ECORE_SUCCESS)
3493 /* Use the leading hwfn since in CMT only NIG #0 is operational */
3494 if (IS_LEAD_HWFN(p_hwfn)) {
3495 rc = ecore_llh_hw_init_pf(p_hwfn, p_ptt,
3496 p_params->avoid_eng_affin);
3501 if (p_params->b_hw_start) {
3502 /* enable interrupts */
3503 rc = ecore_int_igu_enable(p_hwfn, p_ptt, p_params->int_mode);
3504 if (rc != ECORE_SUCCESS)
3507 /* send function start command */
3508 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_params->p_tunn,
3509 p_params->allow_npar_tx_switch);
3511 DP_NOTICE(p_hwfn, true,
3512 "Function start ramrod failed\n");
3516 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3517 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3518 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3520 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
3521 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
3523 ecore_wr(p_hwfn, p_ptt,
3524 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
3527 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3528 "PRS_REG_SEARCH registers after start PFn\n");
3529 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
3530 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3531 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
3532 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
3533 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3534 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
3535 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
3536 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3537 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
3538 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
3539 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3540 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
3541 prs_reg = ecore_rd(p_hwfn, p_ptt,
3542 PRS_REG_SEARCH_TCP_FIRST_FRAG);
3543 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3544 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
3546 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3547 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3548 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3550 return ECORE_SUCCESS;
3553 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
3554 struct ecore_ptt *p_ptt,
3557 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
3559 /* Configure the PF's internal FID_enable for master transactions */
3560 ecore_wr(p_hwfn, p_ptt,
3561 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
3563 /* Wait until value is set - try for 1 second every 50us */
3564 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
3565 val = ecore_rd(p_hwfn, p_ptt,
3566 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
3573 if (val != set_val) {
3574 DP_NOTICE(p_hwfn, true,
3575 "PFID_ENABLE_MASTER wasn't changed after a second\n");
3576 return ECORE_UNKNOWN_ERROR;
3579 return ECORE_SUCCESS;
3582 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
3583 struct ecore_ptt *p_main_ptt)
3585 /* Read shadow of current MFW mailbox */
3586 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
3587 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
3588 p_hwfn->mcp_info->mfw_mb_cur,
3589 p_hwfn->mcp_info->mfw_mb_length);
3592 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
3593 struct ecore_ptt *p_ptt)
3595 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
3596 1 << p_hwfn->abs_pf_id);
3599 static enum _ecore_status_t
3600 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
3601 struct ecore_load_req_params *p_load_req,
3602 struct ecore_drv_load_params *p_drv_load)
3604 /* Make sure that if ecore-client didn't provide inputs, all the
3605 * expected defaults are indeed zero.
3607 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
3608 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
3609 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
3611 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
3613 if (p_drv_load == OSAL_NULL)
3616 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
3617 ECORE_DRV_ROLE_KDUMP :
3619 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
3620 p_load_req->override_force_load = p_drv_load->override_force_load;
3622 /* Old MFW versions don't support timeout values other than default and
3623 * none, so these values are replaced according to the fall-back action.
3626 if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
3627 p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
3628 (p_hwfn->mcp_info->capabilities &
3629 FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
3630 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
3634 switch (p_drv_load->mfw_timeout_fallback) {
3635 case ECORE_TO_FALLBACK_TO_NONE:
3636 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
3638 case ECORE_TO_FALLBACK_TO_DEFAULT:
3639 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
3641 case ECORE_TO_FALLBACK_FAIL_LOAD:
3642 DP_NOTICE(p_hwfn, false,
3643 "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
3644 p_drv_load->mfw_timeout_val,
3645 ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
3646 ECORE_LOAD_REQ_LOCK_TO_NONE);
3647 return ECORE_ABORTED;
3651 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
3652 p_drv_load->mfw_timeout_val,
3653 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
3655 p_load_req->timeout_val);
3657 return ECORE_SUCCESS;
3660 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
3661 struct ecore_hw_init_params *p_params)
3663 if (p_params->p_tunn) {
3664 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
3665 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
3668 p_hwfn->b_int_enabled = 1;
3670 return ECORE_SUCCESS;
3673 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
3674 struct ecore_hw_init_params *p_params)
3676 struct ecore_load_req_params load_req_params;
3677 u32 load_code, resp, param, drv_mb_param;
3678 bool b_default_mtu = true;
3679 struct ecore_hwfn *p_hwfn;
3680 enum _ecore_status_t rc = ECORE_SUCCESS;
3684 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
3685 DP_NOTICE(p_dev, false,
3686 "MSI mode is not supported for CMT devices\n");
3691 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
3692 if (rc != ECORE_SUCCESS)
3696 for_each_hwfn(p_dev, i) {
3697 p_hwfn = &p_dev->hwfns[i];
3699 /* If management didn't provide a default, set one of our own */
3700 if (!p_hwfn->hw_info.mtu) {
3701 p_hwfn->hw_info.mtu = 1500;
3702 b_default_mtu = false;
3706 ecore_vf_start(p_hwfn, p_params);
3710 rc = ecore_calc_hw_mode(p_hwfn);
3711 if (rc != ECORE_SUCCESS)
3714 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
3716 OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
3717 &p_dev->mf_bits))) {
3718 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
3720 ether_type = ETHER_TYPE_VLAN;
3722 ether_type = ETHER_TYPE_QINQ;
3723 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3725 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3727 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3729 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3733 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
3735 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
3736 p_params->p_drv_load_params);
3737 if (rc != ECORE_SUCCESS)
3740 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3742 if (rc != ECORE_SUCCESS) {
3743 DP_NOTICE(p_hwfn, false,
3744 "Failed sending a LOAD_REQ command\n");
3748 load_code = load_req_params.load_code;
3749 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3750 "Load request was sent. Load code: 0x%x\n",
3753 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3756 * When coming back from hiberbate state, the registers from
3757 * which shadow is read initially are not initialized. It turns
3758 * out that these registers get initialized during the call to
3759 * ecore_mcp_load_req request. So we need to reread them here
3760 * to get the proper shadow register value.
3761 * Note: This is a workaround for the missing MFW
3762 * initialization. It may be removed once the implementation
3765 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3767 /* Only relevant for recovery:
3768 * Clear the indication after the LOAD_REQ command is responded
3771 p_dev->recov_in_prog = false;
3773 p_hwfn->first_on_engine = (load_code ==
3774 FW_MSG_CODE_DRV_LOAD_ENGINE);
3776 if (!qm_lock_ref_cnt) {
3777 #ifdef CONFIG_ECORE_LOCK_ALLOC
3778 rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
3780 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
3784 OSAL_SPIN_LOCK_INIT(&qm_lock);
3788 /* Clean up chip from previous driver if such remains exist.
3789 * This is not needed when the PF is the first one on the
3790 * engine, since afterwards we are going to init the FW.
3792 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3793 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3794 p_hwfn->rel_pf_id, false);
3795 if (rc != ECORE_SUCCESS) {
3796 ecore_hw_err_notify(p_hwfn,
3797 ECORE_HW_ERR_RAMROD_FAIL);
3802 /* Log and clear previous pglue_b errors if such exist */
3803 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
3805 /* Enable the PF's internal FID_enable in the PXP */
3806 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3808 if (rc != ECORE_SUCCESS)
3811 /* Clear the pglue_b was_error indication.
3812 * It must be done after the BME and the internal FID_enable for
3813 * the PF are set, since VDMs may cause the indication to be set
3816 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3818 switch (load_code) {
3819 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3820 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3821 p_hwfn->hw_info.hw_mode);
3822 if (rc != ECORE_SUCCESS)
3825 case FW_MSG_CODE_DRV_LOAD_PORT:
3826 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3827 p_hwfn->hw_info.hw_mode);
3828 if (rc != ECORE_SUCCESS)
3831 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3832 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3833 p_hwfn->hw_info.hw_mode,
3837 DP_NOTICE(p_hwfn, false,
3838 "Unexpected load code [0x%08x]", load_code);
3843 if (rc != ECORE_SUCCESS) {
3844 DP_NOTICE(p_hwfn, false,
3845 "init phase failed for loadcode 0x%x (rc %d)\n",
3850 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3851 if (rc != ECORE_SUCCESS) {
3852 DP_NOTICE(p_hwfn, false,
3853 "Sending load done failed, rc = %d\n", rc);
3854 if (rc == ECORE_NOMEM) {
3855 DP_NOTICE(p_hwfn, false,
3856 "Sending load done was failed due to memory allocation failure\n");
3862 /* send DCBX attention request command */
3863 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
3864 "sending phony dcbx set command to trigger DCBx attention handling\n");
3865 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3866 DRV_MSG_CODE_SET_DCBX,
3867 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
3869 if (rc != ECORE_SUCCESS) {
3870 DP_NOTICE(p_hwfn, false,
3871 "Failed to send DCBX attention request\n");
3875 p_hwfn->hw_init_done = true;
3879 /* Get pre-negotiated values for stag, bandwidth etc. */
3880 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3881 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3882 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3883 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3884 DRV_MSG_CODE_GET_OEM_UPDATES,
3885 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3887 if (rc != ECORE_SUCCESS)
3888 DP_NOTICE(p_hwfn, false,
3889 "Failed to send GET_OEM_UPDATES attention request\n");
3893 /* Get pre-negotiated values for stag, bandwidth etc. */
3894 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3895 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3896 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3897 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3898 DRV_MSG_CODE_GET_OEM_UPDATES,
3899 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3901 if (rc != ECORE_SUCCESS)
3902 DP_NOTICE(p_hwfn, false,
3903 "Failed to send GET_OEM_UPDATES attention request\n");
3907 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3908 drv_mb_param = STORM_FW_VERSION;
3909 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3910 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3911 drv_mb_param, &resp, ¶m);
3912 if (rc != ECORE_SUCCESS)
3913 DP_INFO(p_hwfn, "Failed to update firmware version\n");
3915 if (!b_default_mtu) {
3916 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3917 p_hwfn->hw_info.mtu);
3918 if (rc != ECORE_SUCCESS)
3919 DP_INFO(p_hwfn, "Failed to update default mtu\n");
3922 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
3924 ECORE_OV_DRIVER_STATE_DISABLED);
3925 if (rc != ECORE_SUCCESS)
3926 DP_INFO(p_hwfn, "Failed to update driver state\n");
3928 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3929 ECORE_OV_ESWITCH_NONE);
3930 if (rc != ECORE_SUCCESS)
3931 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3938 #ifdef CONFIG_ECORE_LOCK_ALLOC
3939 if (!qm_lock_ref_cnt)
3940 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
3943 /* The MFW load lock should be released regardless of success or failure
3944 * of initialization.
3945 * TODO: replace this with an attempt to send cancel_load.
3947 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3951 #define ECORE_HW_STOP_RETRY_LIMIT (10)
3952 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
3953 struct ecore_hwfn *p_hwfn,
3954 struct ecore_ptt *p_ptt)
3959 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3960 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3961 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
3963 if ((!ecore_rd(p_hwfn, p_ptt,
3964 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3965 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3968 /* Dependent on number of connection/tasks, possibly
3969 * 1ms sleep is required between polls
3974 if (i < ECORE_HW_STOP_RETRY_LIMIT)
3977 DP_NOTICE(p_hwfn, false,
3978 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3979 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3980 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3983 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
3987 for_each_hwfn(p_dev, j) {
3988 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3989 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3991 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
3995 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
3996 struct ecore_ptt *p_ptt,
3997 u32 addr, u32 expected_val)
3999 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
4001 if (val != expected_val) {
4002 DP_NOTICE(p_hwfn, true,
4003 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
4004 addr, val, expected_val);
4005 return ECORE_UNKNOWN_ERROR;
4008 return ECORE_SUCCESS;
4011 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
4013 struct ecore_hwfn *p_hwfn;
4014 struct ecore_ptt *p_ptt;
4015 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
4018 for_each_hwfn(p_dev, j) {
4019 p_hwfn = &p_dev->hwfns[j];
4020 p_ptt = p_hwfn->p_main_ptt;
4022 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
4025 ecore_vf_pf_int_cleanup(p_hwfn);
4026 rc = ecore_vf_pf_reset(p_hwfn);
4027 if (rc != ECORE_SUCCESS) {
4028 DP_NOTICE(p_hwfn, true,
4029 "ecore_vf_pf_reset failed. rc = %d.\n",
4031 rc2 = ECORE_UNKNOWN_ERROR;
4036 /* mark the hw as uninitialized... */
4037 p_hwfn->hw_init_done = false;
4039 /* Send unload command to MCP */
4040 if (!p_dev->recov_in_prog) {
4041 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
4042 if (rc != ECORE_SUCCESS) {
4043 DP_NOTICE(p_hwfn, false,
4044 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
4046 rc2 = ECORE_UNKNOWN_ERROR;
4050 OSAL_DPC_SYNC(p_hwfn);
4052 /* After this point no MFW attentions are expected, e.g. prevent
4053 * race between pf stop and dcbx pf update.
4056 rc = ecore_sp_pf_stop(p_hwfn);
4057 if (rc != ECORE_SUCCESS) {
4058 DP_NOTICE(p_hwfn, false,
4059 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
4061 rc2 = ECORE_UNKNOWN_ERROR;
4064 OSAL_DPC_SYNC(p_hwfn);
4066 /* After this point we don't expect the FW to send us async
4070 /* perform debug action after PF stop was sent */
4071 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
4073 /* close NIG to BRB gate */
4074 ecore_wr(p_hwfn, p_ptt,
4075 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4078 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4079 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4080 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4081 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4082 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4084 /* @@@TBD - clean transmission queues (5.b) */
4085 /* @@@TBD - clean BTB (5.c) */
4087 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
4089 /* @@@TBD - verify DMAE requests are done (8) */
4091 /* Disable Attention Generation */
4092 ecore_int_igu_disable_int(p_hwfn, p_ptt);
4093 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
4094 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
4095 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
4096 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
4097 if (rc != ECORE_SUCCESS) {
4098 DP_NOTICE(p_hwfn, true,
4099 "Failed to return IGU CAM to default\n");
4100 rc2 = ECORE_UNKNOWN_ERROR;
4103 /* Need to wait 1ms to guarantee SBs are cleared */
4106 if (IS_LEAD_HWFN(p_hwfn) &&
4107 OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
4108 !ECORE_IS_FCOE_PERSONALITY(p_hwfn))
4109 ecore_llh_remove_mac_filter(p_dev, 0,
4110 p_hwfn->hw_info.hw_mac_addr);
4112 if (!p_dev->recov_in_prog) {
4113 ecore_verify_reg_val(p_hwfn, p_ptt,
4114 QM_REG_USG_CNT_PF_TX, 0);
4115 ecore_verify_reg_val(p_hwfn, p_ptt,
4116 QM_REG_USG_CNT_PF_OTHER, 0);
4117 /* @@@TBD - assert on incorrect xCFC values (10.b) */
4120 /* Disable PF in HW blocks */
4121 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
4122 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
4125 #ifdef CONFIG_ECORE_LOCK_ALLOC
4126 if (!qm_lock_ref_cnt)
4127 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
4130 if (!p_dev->recov_in_prog) {
4131 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4132 if (rc == ECORE_NOMEM) {
4133 DP_NOTICE(p_hwfn, false,
4134 "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
4135 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4137 if (rc != ECORE_SUCCESS) {
4138 DP_NOTICE(p_hwfn, false,
4139 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
4141 rc2 = ECORE_UNKNOWN_ERROR;
4146 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
4147 p_hwfn = ECORE_LEADING_HWFN(p_dev);
4148 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
4150 /* Clear the PF's internal FID_enable in the PXP.
4151 * In CMT this should only be done for first hw-function, and
4152 * only after all transactions have stopped for all active
4155 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
4157 if (rc != ECORE_SUCCESS) {
4158 DP_NOTICE(p_hwfn, true,
4159 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
4161 rc2 = ECORE_UNKNOWN_ERROR;
4168 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
4172 for_each_hwfn(p_dev, j) {
4173 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4174 struct ecore_ptt *p_ptt;
4177 ecore_vf_pf_int_cleanup(p_hwfn);
4180 p_ptt = ecore_ptt_acquire(p_hwfn);
4184 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4185 "Shutting down the fastpath\n");
4187 ecore_wr(p_hwfn, p_ptt,
4188 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4190 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4191 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4192 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4193 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4194 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4196 /* @@@TBD - clean transmission queues (5.b) */
4197 /* @@@TBD - clean BTB (5.c) */
4199 /* @@@TBD - verify DMAE requests are done (8) */
4201 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
4202 /* Need to wait 1ms to guarantee SBs are cleared */
4204 ecore_ptt_release(p_hwfn, p_ptt);
4207 return ECORE_SUCCESS;
4210 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
4212 struct ecore_ptt *p_ptt;
4214 if (IS_VF(p_hwfn->p_dev))
4215 return ECORE_SUCCESS;
4217 p_ptt = ecore_ptt_acquire(p_hwfn);
4221 /* If roce info is allocated it means roce is initialized and should
4222 * be enabled in searcher.
4224 if (p_hwfn->p_rdma_info) {
4225 if (p_hwfn->b_rdma_enabled_in_prs)
4226 ecore_wr(p_hwfn, p_ptt,
4227 p_hwfn->rdma_prs_search_reg, 0x1);
4228 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
4231 /* Re-open incoming traffic */
4232 ecore_wr(p_hwfn, p_ptt,
4233 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
4234 ecore_ptt_release(p_hwfn, p_ptt);
4236 return ECORE_SUCCESS;
4239 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
4240 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
4242 ecore_ptt_pool_free(p_hwfn);
4243 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
4246 /* Setup bar access */
4247 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
4249 /* clear indirect access */
4250 if (ECORE_IS_AH(p_hwfn->p_dev)) {
4251 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4252 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
4253 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4254 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
4255 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4256 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
4257 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4258 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
4260 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4261 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
4262 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4263 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
4264 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4265 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
4266 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4267 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
4270 /* Clean previous pglue_b errors if such exist */
4271 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
4273 /* enable internal target-read */
4274 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4275 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
4278 static void get_function_id(struct ecore_hwfn *p_hwfn)
4281 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
4282 PXP_PF_ME_OPAQUE_ADDR);
4284 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
4286 /* Bits 16-19 from the ME registers are the pf_num */
4287 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
4288 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4289 PXP_CONCRETE_FID_PFID);
4290 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4291 PXP_CONCRETE_FID_PORT);
4293 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4294 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
4295 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
4298 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
4300 u32 *feat_num = p_hwfn->hw_info.feat_num;
4301 struct ecore_sb_cnt_info sb_cnt;
4304 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
4305 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
4307 /* L2 Queues require each: 1 status block. 1 L2 queue */
4308 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
4309 /* Start by allocating VF queues, then PF's */
4310 feat_num[ECORE_VF_L2_QUE] =
4312 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
4314 feat_num[ECORE_PF_L2_QUE] =
4316 sb_cnt.cnt - non_l2_sbs,
4317 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
4318 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
4321 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
4322 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) {
4323 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ?
4324 &feat_num[ECORE_FCOE_CQ] :
4325 &feat_num[ECORE_ISCSI_CQ];
4326 u32 limit = sb_cnt.cnt;
4328 /* The number of queues should not exceed the number of FP SBs.
4329 * In storage target, the queues are divided into pairs of a CQ
4330 * and a CmdQ, and each pair uses a single SB. The limit in
4331 * this case should allow a max ratio of 2:1 instead of 1:1.
4333 if (p_hwfn->p_dev->b_is_target)
4335 *p_storage_feat = OSAL_MIN_T(u32, limit,
4336 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
4339 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init
4340 * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2".
4342 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat,
4343 (NUM_OF_GLOBAL_QUEUES / 2));
4346 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4347 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
4348 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
4349 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
4350 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
4351 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
4352 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
4356 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
4359 case ECORE_L2_QUEUE:
4373 case ECORE_RDMA_CNQ_RAM:
4374 return "RDMA_CNQ_RAM";
4377 case ECORE_LL2_QUEUE:
4379 case ECORE_CMDQS_CQS:
4381 case ECORE_RDMA_STATS_QUEUE:
4382 return "RDMA_STATS_QUEUE";
4388 return "UNKNOWN_RESOURCE";
4392 static enum _ecore_status_t
4393 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4394 struct ecore_ptt *p_ptt,
4395 enum ecore_resources res_id,
4399 enum _ecore_status_t rc;
4401 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
4402 resc_max_val, p_mcp_resp);
4403 if (rc != ECORE_SUCCESS) {
4404 DP_NOTICE(p_hwfn, false,
4405 "MFW response failure for a max value setting of resource %d [%s]\n",
4406 res_id, ecore_hw_get_resc_name(res_id));
4410 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
4412 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
4413 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
4415 return ECORE_SUCCESS;
4418 #define RDMA_NUM_STATISTIC_COUNTERS_K2 MAX_NUM_VPORTS_K2
4419 #define RDMA_NUM_STATISTIC_COUNTERS_BB MAX_NUM_VPORTS_BB
4421 static u32 ecore_hsi_def_val[][MAX_CHIP_IDS] = {
4422 {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2},
4423 {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2},
4424 {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2},
4425 {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2, },
4426 {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2},
4427 {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2},
4428 {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2},
4429 {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2},
4430 {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2},
4431 {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2},
4432 {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS},
4433 {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES},
4434 {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2},
4437 u32 ecore_get_hsi_def_val(struct ecore_dev *p_dev, enum ecore_hsi_def_type type)
4439 enum chip_ids chip_id = ECORE_IS_BB(p_dev) ? CHIP_BB : CHIP_K2;
4441 if (type >= ECORE_NUM_HSI_DEFS) {
4442 DP_ERR(p_dev, "Unexpected HSI definition type [%d]\n", type);
4446 return ecore_hsi_def_val[type][chip_id];
4449 static enum _ecore_status_t
4450 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4451 struct ecore_ptt *p_ptt)
4453 u32 resc_max_val, mcp_resp;
4455 enum _ecore_status_t rc;
4457 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4460 case ECORE_LL2_QUEUE:
4461 case ECORE_RDMA_CNQ_RAM:
4462 case ECORE_RDMA_STATS_QUEUE:
4470 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
4471 resc_max_val, &mcp_resp);
4472 if (rc != ECORE_SUCCESS)
4475 /* There's no point to continue to the next resource if the
4476 * command is not supported by the MFW.
4477 * We do continue if the command is supported but the resource
4478 * is unknown to the MFW. Such a resource will be later
4479 * configured with the default allocation values.
4481 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
4482 return ECORE_NOTIMPL;
4485 return ECORE_SUCCESS;
4489 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
4490 enum ecore_resources res_id,
4491 u32 *p_resc_num, u32 *p_resc_start)
4493 u8 num_funcs = p_hwfn->num_funcs_on_engine;
4494 struct ecore_dev *p_dev = p_hwfn->p_dev;
4497 case ECORE_L2_QUEUE:
4498 *p_resc_num = NUM_OF_L2_QUEUES(p_dev) / num_funcs;
4501 *p_resc_num = NUM_OF_VPORTS(p_dev) / num_funcs;
4504 *p_resc_num = NUM_OF_RSS_ENGINES(p_dev) / num_funcs;
4507 *p_resc_num = NUM_OF_QM_TX_QUEUES(p_dev) / num_funcs;
4508 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
4511 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(p_dev) / num_funcs;
4515 /* Each VFC resource can accommodate both a MAC and a VLAN */
4516 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
4519 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(p_dev) / num_funcs;
4521 case ECORE_LL2_QUEUE:
4522 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;
4524 case ECORE_RDMA_CNQ_RAM:
4525 case ECORE_CMDQS_CQS:
4526 /* CNQ/CMDQS are the same resource */
4528 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
4530 case ECORE_RDMA_STATS_QUEUE:
4531 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(p_dev) / num_funcs;
4548 /* Since we want its value to reflect whether MFW supports
4549 * the new scheme, have a default of 0.
4554 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
4558 return ECORE_SUCCESS;
4561 static enum _ecore_status_t
4562 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
4563 bool drv_resc_alloc)
4565 u32 dflt_resc_num = 0, dflt_resc_start = 0;
4566 u32 mcp_resp, *p_resc_num, *p_resc_start;
4567 enum _ecore_status_t rc;
4569 p_resc_num = &RESC_NUM(p_hwfn, res_id);
4570 p_resc_start = &RESC_START(p_hwfn, res_id);
4572 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
4574 if (rc != ECORE_SUCCESS) {
4576 "Failed to get default amount for resource %d [%s]\n",
4577 res_id, ecore_hw_get_resc_name(res_id));
4582 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
4583 *p_resc_num = dflt_resc_num;
4584 *p_resc_start = dflt_resc_start;
4589 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
4590 &mcp_resp, p_resc_num, p_resc_start);
4591 if (rc != ECORE_SUCCESS) {
4592 DP_NOTICE(p_hwfn, true,
4593 "MFW response failure for an allocation request for"
4594 " resource %d [%s]\n",
4595 res_id, ecore_hw_get_resc_name(res_id));
4599 /* Default driver values are applied in the following cases:
4600 * - The resource allocation MB command is not supported by the MFW
4601 * - There is an internal error in the MFW while processing the request
4602 * - The resource ID is unknown to the MFW
4604 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
4606 "Failed to receive allocation info for resource %d [%s]."
4607 " mcp_resp = 0x%x. Applying default values"
4609 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
4610 dflt_resc_num, dflt_resc_start);
4612 *p_resc_num = dflt_resc_num;
4613 *p_resc_start = dflt_resc_start;
4617 if ((*p_resc_num != dflt_resc_num ||
4618 *p_resc_start != dflt_resc_start) &&
4619 res_id != ECORE_SB) {
4621 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
4622 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
4623 *p_resc_start, dflt_resc_num, dflt_resc_start,
4624 drv_resc_alloc ? " - Applying default values" : "");
4625 if (drv_resc_alloc) {
4626 *p_resc_num = dflt_resc_num;
4627 *p_resc_start = dflt_resc_start;
4631 return ECORE_SUCCESS;
4634 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
4635 bool drv_resc_alloc)
4637 enum _ecore_status_t rc;
4640 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4641 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
4642 if (rc != ECORE_SUCCESS)
4646 return ECORE_SUCCESS;
4649 #define ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS 0xaa
4650 #define ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS 0x55
4651 #define ECORE_NONUSED_PPFID_MASK_AH_4P 0xf0
4653 static enum _ecore_status_t ecore_hw_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,
4654 struct ecore_ptt *p_ptt)
4656 u8 native_ppfid_idx = ECORE_PPFID_BY_PFID(p_hwfn), new_bitmap;
4657 struct ecore_dev *p_dev = p_hwfn->p_dev;
4658 enum _ecore_status_t rc;
4660 rc = ecore_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
4661 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL)
4663 else if (rc == ECORE_NOTIMPL)
4664 p_dev->ppfid_bitmap = 0x1 << native_ppfid_idx;
4666 /* 4-ports mode has limitations that should be enforced:
4667 * - BB: the MFW can access only PPFIDs which their corresponding PFIDs
4668 * belong to this certain port.
4669 * - AH: only 4 PPFIDs per port are available.
4671 if (ecore_device_num_ports(p_dev) == 4) {
4674 if (ECORE_IS_BB(p_dev))
4675 mask = MFW_PORT(p_hwfn) > 1 ?
4676 ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS :
4677 ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS;
4679 mask = ECORE_NONUSED_PPFID_MASK_AH_4P;
4681 if (p_dev->ppfid_bitmap & mask) {
4682 new_bitmap = p_dev->ppfid_bitmap & ~mask;
4684 "Fix the PPFID bitmap for 4-ports mode: 0x%hhx -> 0x%hhx\n",
4685 p_dev->ppfid_bitmap, new_bitmap);
4686 p_dev->ppfid_bitmap = new_bitmap;
4690 /* The native PPFID is expected to be part of the allocated bitmap */
4691 if (!(p_dev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
4692 new_bitmap = 0x1 << native_ppfid_idx;
4694 "Fix the PPFID bitmap to inculde the native PPFID: %hhd -> 0x%hhx\n",
4695 p_dev->ppfid_bitmap, new_bitmap);
4696 p_dev->ppfid_bitmap = new_bitmap;
4699 return ECORE_SUCCESS;
4702 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
4703 struct ecore_ptt *p_ptt,
4704 bool drv_resc_alloc)
4706 struct ecore_resc_unlock_params resc_unlock_params;
4707 struct ecore_resc_lock_params resc_lock_params;
4708 struct ecore_dev *p_dev = p_hwfn->p_dev;
4711 enum _ecore_status_t rc;
4713 u32 *resc_start = p_hwfn->hw_info.resc_start;
4714 u32 *resc_num = p_hwfn->hw_info.resc_num;
4715 /* For AH, an equal share of the ILT lines between the maximal number of
4716 * PFs is not enough for RoCE. This would be solved by the future
4717 * resource allocation scheme, but isn't currently present for
4718 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
4719 * to work - the BB number of ILT lines divided by its max PFs number.
4721 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
4724 /* Setting the max values of the soft resources and the following
4725 * resources allocation queries should be atomic. Since several PFs can
4726 * run in parallel - a resource lock is needed.
4727 * If either the resource lock or resource set value commands are not
4728 * supported - skip the max values setting, release the lock if
4729 * needed, and proceed to the queries. Other failures, including a
4730 * failure to acquire the lock, will cause this function to fail.
4731 * Old drivers that don't acquire the lock can run in parallel, and
4732 * their allocation values won't be affected by the updated max values.
4734 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
4735 ECORE_RESC_LOCK_RESC_ALLOC, false);
4737 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
4738 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4740 } else if (rc == ECORE_NOTIMPL) {
4742 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
4743 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
4744 DP_NOTICE(p_hwfn, false,
4745 "Failed to acquire the resource lock for the resource allocation commands\n");
4747 goto unlock_and_exit;
4749 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
4750 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4751 DP_NOTICE(p_hwfn, false,
4752 "Failed to set the max values of the soft resources\n");
4753 goto unlock_and_exit;
4754 } else if (rc == ECORE_NOTIMPL) {
4756 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
4757 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4758 &resc_unlock_params);
4759 if (rc != ECORE_SUCCESS)
4761 "Failed to release the resource lock for the resource allocation commands\n");
4765 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
4766 if (rc != ECORE_SUCCESS)
4767 goto unlock_and_exit;
4769 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
4770 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4771 &resc_unlock_params);
4772 if (rc != ECORE_SUCCESS)
4774 "Failed to release the resource lock for the resource allocation commands\n");
4778 if (IS_LEAD_HWFN(p_hwfn)) {
4779 rc = ecore_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
4780 if (rc != ECORE_SUCCESS)
4785 if (CHIP_REV_IS_EMUL(p_dev)) {
4786 /* Reduced build contains less PQs */
4787 if (!(p_dev->b_is_emul_full)) {
4788 resc_num[ECORE_PQ] = 32;
4789 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
4790 p_hwfn->enabled_func_idx;
4793 /* For AH emulation, since we have a possible maximal number of
4794 * 16 enabled PFs, in case there are not enough ILT lines -
4795 * allocate only first PF as RoCE and have all the other as
4796 * ETH-only with less ILT lines.
4797 * In case we increase the number of ILT lines for PF0, we need
4798 * also to correct the start value for PF1-15.
4800 if (ECORE_IS_AH(p_dev) && p_dev->b_is_emul_full) {
4801 if (!p_hwfn->rel_pf_id) {
4802 resc_num[ECORE_ILT] =
4803 OSAL_MAX_T(u32, resc_num[ECORE_ILT],
4804 roce_min_ilt_lines);
4805 } else if (resc_num[ECORE_ILT] < roce_min_ilt_lines) {
4806 resc_start[ECORE_ILT] += roce_min_ilt_lines -
4807 resc_num[ECORE_ILT];
4813 /* Sanity for ILT */
4814 max_ilt_lines = NUM_OF_PXP_ILT_RECORDS(p_dev);
4815 if (RESC_END(p_hwfn, ECORE_ILT) > max_ilt_lines) {
4816 DP_NOTICE(p_hwfn, true,
4817 "Can't assign ILT pages [%08x,...,%08x]\n",
4818 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
4824 /* This will also learn the number of SBs from MFW */
4825 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
4828 ecore_hw_set_feat(p_hwfn);
4830 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4831 "The numbers for each resource are:\n");
4832 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
4833 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
4834 ecore_hw_get_resc_name(res_id),
4835 RESC_NUM(p_hwfn, res_id),
4836 RESC_START(p_hwfn, res_id));
4838 return ECORE_SUCCESS;
4841 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
4842 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4843 &resc_unlock_params);
4848 static enum _ecore_status_t
4849 ecore_emul_hw_get_nvm_info(struct ecore_hwfn *p_hwfn)
4851 if (IS_LEAD_HWFN(p_hwfn)) {
4852 struct ecore_dev *p_dev = p_hwfn->p_dev;
4854 /* The MF mode on emulation is either default or NPAR 1.0 */
4855 p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
4856 1 << ECORE_MF_LLH_PROTO_CLSS |
4857 1 << ECORE_MF_LL2_NON_UNICAST;
4858 if (p_hwfn->num_funcs_on_port > 1)
4859 p_dev->mf_bits |= 1 << ECORE_MF_INTER_PF_SWITCH |
4860 1 << ECORE_MF_DISABLE_ARFS;
4862 p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
4865 return ECORE_SUCCESS;
4869 static enum _ecore_status_t
4870 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
4871 struct ecore_ptt *p_ptt,
4872 struct ecore_hw_prepare_params *p_params)
4874 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
4875 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
4876 struct ecore_mcp_link_capabilities *p_caps;
4877 struct ecore_mcp_link_params *link;
4878 enum _ecore_status_t rc;
4881 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
4882 return ecore_emul_hw_get_nvm_info(p_hwfn);
4885 /* Read global nvm_cfg address */
4886 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
4888 /* Verify MCP has initialized it */
4889 if (!nvm_cfg_addr) {
4890 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
4891 if (p_params->b_relaxed_probe)
4892 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
4896 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
4898 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
4900 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4901 OFFSETOF(struct nvm_cfg1, glob) +
4902 OFFSETOF(struct nvm_cfg1_glob, core_cfg);
4904 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
4906 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
4907 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
4908 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
4909 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
4911 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4912 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
4914 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4915 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
4917 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4918 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
4920 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4921 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
4923 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4924 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
4926 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4927 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
4929 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4930 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
4932 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4933 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
4935 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4936 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
4938 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4939 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
4942 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
4947 /* Read DCBX configuration */
4948 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4949 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4950 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
4952 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
4953 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
4954 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
4955 switch (dcbx_mode) {
4956 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
4957 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
4959 case NVM_CFG1_PORT_DCBX_MODE_CEE:
4960 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
4962 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
4963 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
4966 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
4969 /* Read default link configuration */
4970 link = &p_hwfn->mcp_info->link_input;
4971 p_caps = &p_hwfn->mcp_info->link_capabilities;
4972 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4973 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4974 link_temp = ecore_rd(p_hwfn, p_ptt,
4976 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
4977 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4978 link->speed.advertised_speeds = link_temp;
4979 p_caps->speed_capabilities = link->speed.advertised_speeds;
4981 link_temp = ecore_rd(p_hwfn, p_ptt,
4983 OFFSETOF(struct nvm_cfg1_port, link_settings));
4984 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
4985 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
4986 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
4987 link->speed.autoneg = true;
4989 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
4990 link->speed.forced_speed = 1000;
4992 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
4993 link->speed.forced_speed = 10000;
4995 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
4996 link->speed.forced_speed = 25000;
4998 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
4999 link->speed.forced_speed = 40000;
5001 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
5002 link->speed.forced_speed = 50000;
5004 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
5005 link->speed.forced_speed = 100000;
5008 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
5011 p_caps->default_speed = link->speed.forced_speed;
5012 p_caps->default_speed_autoneg = link->speed.autoneg;
5014 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
5015 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
5016 link->pause.autoneg = !!(link_temp &
5017 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
5018 link->pause.forced_rx = !!(link_temp &
5019 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
5020 link->pause.forced_tx = !!(link_temp &
5021 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
5022 link->loopback_mode = 0;
5024 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
5025 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
5026 OFFSETOF(struct nvm_cfg1_port, ext_phy));
5027 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
5028 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
5029 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
5030 link->eee.enable = true;
5031 switch (link_temp) {
5032 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
5033 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
5034 link->eee.enable = false;
5036 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
5037 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
5039 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
5040 p_caps->eee_lpi_timer =
5041 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
5043 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
5044 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
5048 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
5049 link->eee.tx_lpi_enable = link->eee.enable;
5050 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
5052 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
5055 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5056 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
5057 link->speed.forced_speed, link->speed.advertised_speeds,
5058 link->speed.autoneg, link->pause.autoneg,
5059 p_caps->default_eee, p_caps->eee_lpi_timer);
5061 /* Read Multi-function information from shmem */
5062 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5063 OFFSETOF(struct nvm_cfg1, glob) +
5064 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
5066 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
5068 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
5069 NVM_CFG1_GLOB_MF_MODE_OFFSET;
5072 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
5073 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
5075 case NVM_CFG1_GLOB_MF_MODE_UFP:
5076 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
5077 1 << ECORE_MF_UFP_SPECIFIC |
5078 1 << ECORE_MF_8021Q_TAGGING;
5080 case NVM_CFG1_GLOB_MF_MODE_BD:
5081 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
5082 1 << ECORE_MF_LLH_PROTO_CLSS |
5083 1 << ECORE_MF_8021AD_TAGGING |
5084 1 << ECORE_MF_FIP_SPECIAL;
5086 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
5087 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
5088 1 << ECORE_MF_LLH_PROTO_CLSS |
5089 1 << ECORE_MF_LL2_NON_UNICAST |
5090 1 << ECORE_MF_INTER_PF_SWITCH |
5091 1 << ECORE_MF_DISABLE_ARFS;
5093 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
5094 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
5095 1 << ECORE_MF_LLH_PROTO_CLSS |
5096 1 << ECORE_MF_LL2_NON_UNICAST;
5097 if (ECORE_IS_BB(p_hwfn->p_dev))
5098 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
5101 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
5102 p_hwfn->p_dev->mf_bits);
5104 if (ECORE_IS_CMT(p_hwfn->p_dev))
5105 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
5107 /* It's funny since we have another switch, but it's easier
5108 * to throw this away in linux this way. Long term, it might be
5109 * better to have have getters for needed ECORE_MF_* fields,
5110 * convert client code and eliminate this.
5113 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
5114 case NVM_CFG1_GLOB_MF_MODE_BD:
5115 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
5117 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
5118 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
5120 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
5121 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
5123 case NVM_CFG1_GLOB_MF_MODE_UFP:
5124 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
5128 /* Read Multi-function information from shmem */
5129 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5130 OFFSETOF(struct nvm_cfg1, glob) +
5131 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
5133 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
5134 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
5135 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
5136 &p_hwfn->hw_info.device_capabilities);
5137 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
5138 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
5139 &p_hwfn->hw_info.device_capabilities);
5140 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
5141 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
5142 &p_hwfn->hw_info.device_capabilities);
5143 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
5144 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
5145 &p_hwfn->hw_info.device_capabilities);
5146 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
5147 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
5148 &p_hwfn->hw_info.device_capabilities);
5150 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
5151 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5153 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5159 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
5160 struct ecore_ptt *p_ptt)
5162 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
5163 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
5164 struct ecore_dev *p_dev = p_hwfn->p_dev;
5166 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
5168 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
5169 * in the other bits are selected.
5170 * Bits 1-15 are for functions 1-15, respectively, and their value is
5171 * '0' only for enabled functions (function 0 always exists and
5173 * In case of CMT in BB, only the "even" functions are enabled, and thus
5174 * the number of functions for both hwfns is learnt from the same bits.
5176 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
5177 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
5178 MISCS_REG_FUNCTION_HIDE_BB_K2);
5180 reg_function_hide = 0;
5183 if (reg_function_hide & 0x1) {
5184 if (ECORE_IS_BB(p_dev)) {
5185 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
5197 /* Get the number of the enabled functions on the engine */
5198 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
5205 /* Get the PF index within the enabled functions */
5206 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
5207 tmp = reg_function_hide & eng_mask & low_pfs_mask;
5215 p_hwfn->num_funcs_on_engine = num_funcs;
5216 p_hwfn->enabled_func_idx = enabled_func_idx;
5219 if (CHIP_REV_IS_FPGA(p_dev)) {
5220 DP_NOTICE(p_hwfn, false,
5221 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
5222 p_hwfn->num_funcs_on_engine = 4;
5226 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
5227 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
5228 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
5229 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
5233 static void ecore_emul_hw_info_port_num(struct ecore_hwfn *p_hwfn,
5234 struct ecore_ptt *p_ptt)
5236 struct ecore_dev *p_dev = p_hwfn->p_dev;
5239 /* MISCS_REG_ECO_RESERVED[15:12]: num of ports in an engine */
5240 eco_reserved = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5242 switch ((eco_reserved & 0xf000) >> 12) {
5244 p_dev->num_ports_in_engine = 1;
5247 p_dev->num_ports_in_engine = 2;
5250 p_dev->num_ports_in_engine = 4;
5253 DP_NOTICE(p_hwfn, false,
5254 "Emulation: Unknown port mode [ECO_RESERVED 0x%08x]\n",
5256 p_dev->num_ports_in_engine = 2; /* Default to something */
5260 p_dev->num_ports = p_dev->num_ports_in_engine *
5261 ecore_device_num_engines(p_dev);
5265 /* Determine the number of ports of the device and per engine */
5266 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
5267 struct ecore_ptt *p_ptt)
5269 struct ecore_dev *p_dev = p_hwfn->p_dev;
5270 u32 addr, global_offsize, global_addr;
5273 if (CHIP_REV_IS_TEDIBEAR(p_dev)) {
5274 p_dev->num_ports_in_engine = 1;
5275 p_dev->num_ports = 2;
5279 if (CHIP_REV_IS_EMUL(p_dev)) {
5280 ecore_emul_hw_info_port_num(p_hwfn, p_ptt);
5285 /* In CMT there is always only one port */
5286 if (ECORE_IS_CMT(p_dev)) {
5287 p_dev->num_ports_in_engine = 1;
5288 p_dev->num_ports = 1;
5292 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
5294 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
5295 global_addr = SECTION_ADDR(global_offsize, 0);
5296 addr = global_addr + OFFSETOF(struct public_global, max_ports);
5297 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
5299 p_dev->num_ports_in_engine = p_dev->num_ports >>
5300 (ecore_device_num_engines(p_dev) - 1);
5303 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
5304 struct ecore_ptt *p_ptt)
5306 struct ecore_mcp_link_capabilities *p_caps;
5309 p_caps = &p_hwfn->mcp_info->link_capabilities;
5310 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
5313 p_caps->eee_speed_caps = 0;
5314 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
5315 OFFSETOF(struct public_port, eee_status));
5316 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
5317 EEE_SUPPORTED_SPEED_OFFSET;
5318 if (eee_status & EEE_1G_SUPPORTED)
5319 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
5320 if (eee_status & EEE_10G_ADV)
5321 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
5324 static enum _ecore_status_t
5325 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
5326 enum ecore_pci_personality personality,
5327 struct ecore_hw_prepare_params *p_params)
5329 bool drv_resc_alloc = p_params->drv_resc_alloc;
5330 enum _ecore_status_t rc;
5332 if (IS_ECORE_PACING(p_hwfn)) {
5333 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV,
5334 "Skipping IOV as packet pacing is requested\n");
5337 /* Since all information is common, only first hwfns should do this */
5338 if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) {
5339 rc = ecore_iov_hw_info(p_hwfn);
5340 if (rc != ECORE_SUCCESS) {
5341 if (p_params->b_relaxed_probe)
5342 p_params->p_relaxed_res =
5343 ECORE_HW_PREPARE_BAD_IOV;
5349 if (IS_LEAD_HWFN(p_hwfn))
5350 ecore_hw_info_port_num(p_hwfn, p_ptt);
5352 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
5354 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
5355 if (rc != ECORE_SUCCESS)
5358 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
5359 if (rc != ECORE_SUCCESS) {
5360 if (p_params->b_relaxed_probe)
5361 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
5367 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
5369 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
5370 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
5373 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
5375 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
5376 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
5380 if (ecore_mcp_is_init(p_hwfn)) {
5381 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
5382 p_hwfn->hw_info.ovlan =
5383 p_hwfn->mcp_info->func_info.ovlan;
5385 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
5387 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
5389 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
5392 if (personality != ECORE_PCI_DEFAULT) {
5393 p_hwfn->hw_info.personality = personality;
5394 } else if (ecore_mcp_is_init(p_hwfn)) {
5395 enum ecore_pci_personality protocol;
5397 protocol = p_hwfn->mcp_info->func_info.protocol;
5398 p_hwfn->hw_info.personality = protocol;
5401 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
5403 * Allow only PF0 to be RoCE to overcome a lack of ILT lines.
5405 if (ECORE_IS_AH(p_hwfn->p_dev) && p_hwfn->rel_pf_id)
5406 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
5408 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
5412 /* although in BB some constellations may support more than 4 tcs,
5413 * that can result in performance penalty in some cases. 4
5414 * represents a good tradeoff between performance and flexibility.
5416 if (IS_ECORE_PACING(p_hwfn))
5417 p_hwfn->hw_info.num_hw_tc = 1;
5419 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
5421 /* start out with a single active tc. This can be increased either
5422 * by dcbx negotiation or by upper layer driver
5424 p_hwfn->hw_info.num_active_tc = 1;
5426 ecore_get_num_funcs(p_hwfn, p_ptt);
5428 if (ecore_mcp_is_init(p_hwfn))
5429 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
5431 /* In case of forcing the driver's default resource allocation, calling
5432 * ecore_hw_get_resc() should come after initializing the personality
5433 * and after getting the number of functions, since the calculation of
5434 * the resources/features depends on them.
5435 * This order is not harmful if not forcing.
5437 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
5438 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5440 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5446 #define ECORE_MAX_DEVICE_NAME_LEN (8)
5448 void ecore_get_dev_name(struct ecore_dev *p_dev, u8 *name, u8 max_chars)
5452 n = OSAL_MIN_T(u8, max_chars, ECORE_MAX_DEVICE_NAME_LEN);
5453 OSAL_SNPRINTF((char *)name, n, "%s %c%d",
5454 ECORE_IS_BB(p_dev) ? "BB" : "AH",
5455 'A' + p_dev->chip_rev, (int)p_dev->chip_metal);
5458 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
5459 struct ecore_ptt *p_ptt)
5461 struct ecore_dev *p_dev = p_hwfn->p_dev;
5465 /* Read Vendor Id / Device Id */
5466 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
5468 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
5471 /* Determine type */
5472 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
5473 switch (device_id_mask) {
5474 case ECORE_DEV_ID_MASK_BB:
5475 p_dev->type = ECORE_DEV_TYPE_BB;
5477 case ECORE_DEV_ID_MASK_AH:
5478 p_dev->type = ECORE_DEV_TYPE_AH;
5481 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
5483 return ECORE_ABORTED;
5486 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
5487 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
5488 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
5489 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
5491 /* Learn number of HW-functions */
5492 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
5494 if (tmp & (1 << p_hwfn->rel_pf_id)) {
5495 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
5496 p_dev->num_hwfns = 2;
5498 p_dev->num_hwfns = 1;
5502 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_BB(p_dev)) {
5503 /* For some reason we have problems with this register
5504 * in BB B0 emulation; Simply assume no CMT
5506 DP_NOTICE(p_dev->hwfns, false,
5507 "device on emul - assume no CMT\n");
5508 p_dev->num_hwfns = 1;
5512 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
5513 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
5514 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
5515 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
5517 DP_INFO(p_dev->hwfns,
5518 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
5519 ECORE_IS_BB(p_dev) ? "BB" : "AH",
5520 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
5521 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
5524 if (ECORE_IS_BB_A0(p_dev)) {
5525 DP_NOTICE(p_dev->hwfns, false,
5526 "The chip type/rev (BB A0) is not supported!\n");
5527 return ECORE_ABORTED;
5530 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
5531 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
5533 if (CHIP_REV_IS_EMUL(p_dev)) {
5534 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5536 /* MISCS_REG_ECO_RESERVED[29]: full/reduced emulation build */
5537 p_dev->b_is_emul_full = !!(tmp & (1 << 29));
5539 /* MISCS_REG_ECO_RESERVED[28]: emulation build w/ or w/o MAC */
5540 p_dev->b_is_emul_mac = !!(tmp & (1 << 28));
5542 DP_NOTICE(p_hwfn, false,
5543 "Emulation: Running on a %s build %s MAC\n",
5544 p_dev->b_is_emul_full ? "full" : "reduced",
5545 p_dev->b_is_emul_mac ? "with" : "without");
5549 return ECORE_SUCCESS;
5552 #ifndef LINUX_REMOVE
5553 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
5560 for_each_hwfn(p_dev, j) {
5561 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
5563 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
5564 "Mark hw/fw uninitialized\n");
5566 p_hwfn->hw_init_done = false;
5568 ecore_ptt_invalidate(p_hwfn);
5573 static enum _ecore_status_t
5574 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
5575 void OSAL_IOMEM *p_doorbells, u64 db_phys_addr,
5576 struct ecore_hw_prepare_params *p_params)
5578 struct ecore_mdump_retain_data mdump_retain;
5579 struct ecore_dev *p_dev = p_hwfn->p_dev;
5580 struct ecore_mdump_info mdump_info;
5581 enum _ecore_status_t rc = ECORE_SUCCESS;
5583 /* Split PCI bars evenly between hwfns */
5584 p_hwfn->regview = p_regview;
5585 p_hwfn->doorbells = p_doorbells;
5586 p_hwfn->db_phys_addr = db_phys_addr;
5589 return ecore_vf_hw_prepare(p_hwfn);
5591 /* Validate that chip access is feasible */
5592 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
5594 "Reading the ME register returns all Fs; Preventing further chip access\n");
5595 if (p_params->b_relaxed_probe)
5596 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
5600 get_function_id(p_hwfn);
5602 /* Allocate PTT pool */
5603 rc = ecore_ptt_pool_alloc(p_hwfn);
5605 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
5606 if (p_params->b_relaxed_probe)
5607 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5611 /* Allocate the main PTT */
5612 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
5614 /* First hwfn learns basic information, e.g., number of hwfns */
5615 if (IS_LEAD_HWFN(p_hwfn)) {
5616 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
5617 if (rc != ECORE_SUCCESS) {
5618 if (p_params->b_relaxed_probe)
5619 p_params->p_relaxed_res =
5620 ECORE_HW_PREPARE_FAILED_DEV;
5626 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) && !b_ptt_gtt_init) {
5627 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
5630 /* Initialize PTT/GTT (done by MFW on ASIC) */
5631 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_START_INIT_PTT_GTT, 1);
5633 ecore_ptt_invalidate(p_hwfn);
5634 val = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_INIT_DONE_PTT_GTT);
5637 "PTT and GTT init in PGLUE_B didn't complete\n");
5641 /* Clear a possible PGLUE_B parity from a previous GRC access */
5642 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_PRTY_STS_WR_H_0, 0x380);
5644 b_ptt_gtt_init = true;
5648 /* Store the precompiled init data ptrs */
5649 if (IS_LEAD_HWFN(p_hwfn))
5650 ecore_init_iro_array(p_hwfn->p_dev);
5652 ecore_hw_hwfn_prepare(p_hwfn);
5654 /* Initialize MCP structure */
5655 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
5657 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
5658 if (p_params->b_relaxed_probe)
5659 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5663 /* Read the device configuration information from the HW and SHMEM */
5664 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
5665 p_params->personality, p_params);
5667 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
5671 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
5672 * called, since among others it sets the ports number in an engine.
5674 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
5675 !p_dev->recov_in_prog) {
5676 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
5677 if (rc != ECORE_SUCCESS)
5678 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
5680 /* Workaround for MFW issue where PF FLR does not cleanup
5683 if (!(p_hwfn->mcp_info->capabilities &
5684 FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
5685 ecore_pf_flr_igu_cleanup(p_hwfn);
5688 /* Check if mdump logs/data are present and update the epoch value */
5689 if (IS_LEAD_HWFN(p_hwfn)) {
5690 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
5692 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
5693 DP_NOTICE(p_hwfn, false,
5694 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
5696 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
5698 if (rc == ECORE_SUCCESS && mdump_retain.valid)
5699 DP_NOTICE(p_hwfn, false,
5700 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
5701 mdump_retain.epoch, mdump_retain.pf,
5702 mdump_retain.status);
5704 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
5708 /* Allocate the init RT array and initialize the init-ops engine */
5709 rc = ecore_init_alloc(p_hwfn);
5711 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
5712 if (p_params->b_relaxed_probe)
5713 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5717 if (CHIP_REV_IS_FPGA(p_dev)) {
5718 if (ECORE_IS_AH(p_dev)) {
5719 DP_NOTICE(p_hwfn, false,
5720 "FPGA: workaround; Prevent DMAE parities\n");
5721 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
5722 PCIE_REG_PRTY_MASK_K2, 7);
5725 DP_NOTICE(p_hwfn, false,
5726 "FPGA: workaround: Set VF bar0 size\n");
5727 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
5728 PGLUE_B_REG_VF_BAR0_SIZE_K2, 4);
5734 if (IS_LEAD_HWFN(p_hwfn))
5735 ecore_iov_free_hw_info(p_dev);
5736 ecore_mcp_free(p_hwfn);
5738 ecore_hw_hwfn_free(p_hwfn);
5743 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
5744 struct ecore_hw_prepare_params *p_params)
5746 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5747 enum _ecore_status_t rc;
5749 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
5750 p_dev->allow_mdump = p_params->allow_mdump;
5751 p_hwfn->b_en_pacing = p_params->b_en_pacing;
5752 p_dev->b_is_target = p_params->b_is_target;
5754 if (p_params->b_relaxed_probe)
5755 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
5757 /* Initialize the first hwfn - will learn number of hwfns */
5758 rc = ecore_hw_prepare_single(p_hwfn, p_dev->regview,
5759 p_dev->doorbells, p_dev->db_phys_addr,
5761 if (rc != ECORE_SUCCESS)
5764 p_params->personality = p_hwfn->hw_info.personality;
5766 /* Initialize 2nd hwfn if necessary */
5767 if (ECORE_IS_CMT(p_dev)) {
5768 void OSAL_IOMEM *p_regview, *p_doorbell;
5769 u8 OSAL_IOMEM *addr;
5773 /* adjust bar offset for second engine */
5774 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
5776 addr = (u8 OSAL_IOMEM *)p_dev->regview + offset;
5777 p_regview = (void OSAL_IOMEM *)addr;
5779 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
5781 addr = (u8 OSAL_IOMEM *)p_dev->doorbells + offset;
5782 p_doorbell = (void OSAL_IOMEM *)addr;
5783 db_phys_addr = p_dev->db_phys_addr + offset;
5785 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;
5786 /* prepare second hw function */
5787 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
5788 p_doorbell, db_phys_addr,
5791 /* in case of error, need to free the previously
5792 * initiliazed hwfn 0.
5794 if (rc != ECORE_SUCCESS) {
5795 if (p_params->b_relaxed_probe)
5796 p_params->p_relaxed_res =
5797 ECORE_HW_PREPARE_FAILED_ENG2;
5800 ecore_init_free(p_hwfn);
5801 ecore_mcp_free(p_hwfn);
5802 ecore_hw_hwfn_free(p_hwfn);
5804 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
5813 void ecore_hw_remove(struct ecore_dev *p_dev)
5815 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5819 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
5820 ECORE_OV_DRIVER_STATE_NOT_LOADED);
5822 for_each_hwfn(p_dev, i) {
5823 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5826 ecore_vf_pf_release(p_hwfn);
5830 ecore_init_free(p_hwfn);
5831 ecore_hw_hwfn_free(p_hwfn);
5832 ecore_mcp_free(p_hwfn);
5834 #ifdef CONFIG_ECORE_LOCK_ALLOC
5835 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
5839 ecore_iov_free_hw_info(p_dev);
5842 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
5843 struct ecore_chain *p_chain)
5845 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
5846 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
5847 struct ecore_chain_next *p_next;
5853 size = p_chain->elem_size * p_chain->usable_per_page;
5855 for (i = 0; i < p_chain->page_cnt; i++) {
5859 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
5860 p_virt_next = p_next->next_virt;
5861 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
5863 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
5864 ECORE_CHAIN_PAGE_SIZE);
5866 p_virt = p_virt_next;
5867 p_phys = p_phys_next;
5871 static void ecore_chain_free_single(struct ecore_dev *p_dev,
5872 struct ecore_chain *p_chain)
5874 if (!p_chain->p_virt_addr)
5877 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
5878 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
5881 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
5882 struct ecore_chain *p_chain)
5884 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
5885 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
5886 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
5888 if (!pp_virt_addr_tbl)
5894 for (i = 0; i < page_cnt; i++) {
5895 if (!pp_virt_addr_tbl[i])
5898 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
5899 *(dma_addr_t *)p_pbl_virt,
5900 ECORE_CHAIN_PAGE_SIZE);
5902 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
5905 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
5907 if (!p_chain->b_external_pbl)
5908 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
5909 p_chain->pbl_sp.p_phys_table, pbl_size);
5911 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
5914 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5916 switch (p_chain->mode) {
5917 case ECORE_CHAIN_MODE_NEXT_PTR:
5918 ecore_chain_free_next_ptr(p_dev, p_chain);
5920 case ECORE_CHAIN_MODE_SINGLE:
5921 ecore_chain_free_single(p_dev, p_chain);
5923 case ECORE_CHAIN_MODE_PBL:
5924 ecore_chain_free_pbl(p_dev, p_chain);
5929 static enum _ecore_status_t
5930 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
5931 enum ecore_chain_cnt_type cnt_type,
5932 osal_size_t elem_size, u32 page_cnt)
5934 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
5936 /* The actual chain size can be larger than the maximal possible value
5937 * after rounding up the requested elements number to pages, and after
5938 * taking into acount the unusuable elements (next-ptr elements).
5939 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
5940 * size/capacity fields are of a u32 type.
5942 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
5943 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
5944 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
5945 chain_size > ECORE_U32_MAX)) {
5946 DP_NOTICE(p_dev, true,
5947 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
5948 (unsigned long)chain_size);
5952 return ECORE_SUCCESS;
5955 static enum _ecore_status_t
5956 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5958 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
5959 dma_addr_t p_phys = 0;
5962 for (i = 0; i < p_chain->page_cnt; i++) {
5963 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
5964 ECORE_CHAIN_PAGE_SIZE);
5966 DP_NOTICE(p_dev, false,
5967 "Failed to allocate chain memory\n");
5972 ecore_chain_init_mem(p_chain, p_virt, p_phys);
5973 ecore_chain_reset(p_chain);
5975 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
5979 p_virt_prev = p_virt;
5981 /* Last page's next element should point to the beginning of the
5984 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
5985 p_chain->p_virt_addr,
5986 p_chain->p_phys_addr);
5988 return ECORE_SUCCESS;
5991 static enum _ecore_status_t
5992 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5994 dma_addr_t p_phys = 0;
5995 void *p_virt = OSAL_NULL;
5997 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
5999 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
6003 ecore_chain_init_mem(p_chain, p_virt, p_phys);
6004 ecore_chain_reset(p_chain);
6006 return ECORE_SUCCESS;
6009 static enum _ecore_status_t
6010 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
6011 struct ecore_chain *p_chain,
6012 struct ecore_chain_ext_pbl *ext_pbl)
6014 u32 page_cnt = p_chain->page_cnt, size, i;
6015 dma_addr_t p_phys = 0, p_pbl_phys = 0;
6016 void **pp_virt_addr_tbl = OSAL_NULL;
6017 u8 *p_pbl_virt = OSAL_NULL;
6018 void *p_virt = OSAL_NULL;
6020 size = page_cnt * sizeof(*pp_virt_addr_tbl);
6021 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
6022 if (!pp_virt_addr_tbl) {
6023 DP_NOTICE(p_dev, false,
6024 "Failed to allocate memory for the chain virtual addresses table\n");
6028 /* The allocation of the PBL table is done with its full size, since it
6029 * is expected to be successive.
6030 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
6031 * failure, since pp_virt_addr_tbl was previously allocated, and it
6032 * should be saved to allow its freeing during the error flow.
6034 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
6036 if (ext_pbl == OSAL_NULL) {
6037 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
6039 p_pbl_virt = ext_pbl->p_pbl_virt;
6040 p_pbl_phys = ext_pbl->p_pbl_phys;
6041 p_chain->b_external_pbl = true;
6044 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
6047 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
6051 for (i = 0; i < page_cnt; i++) {
6052 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
6053 ECORE_CHAIN_PAGE_SIZE);
6055 DP_NOTICE(p_dev, false,
6056 "Failed to allocate chain memory\n");
6061 ecore_chain_init_mem(p_chain, p_virt, p_phys);
6062 ecore_chain_reset(p_chain);
6065 /* Fill the PBL table with the physical address of the page */
6066 *(dma_addr_t *)p_pbl_virt = p_phys;
6067 /* Keep the virtual address of the page */
6068 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
6070 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
6073 return ECORE_SUCCESS;
6076 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
6077 enum ecore_chain_use_mode intended_use,
6078 enum ecore_chain_mode mode,
6079 enum ecore_chain_cnt_type cnt_type,
6080 u32 num_elems, osal_size_t elem_size,
6081 struct ecore_chain *p_chain,
6082 struct ecore_chain_ext_pbl *ext_pbl)
6085 enum _ecore_status_t rc = ECORE_SUCCESS;
6087 if (mode == ECORE_CHAIN_MODE_SINGLE)
6090 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
6092 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
6095 DP_NOTICE(p_dev, false,
6096 "Cannot allocate a chain with the given arguments:\n"
6097 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
6098 intended_use, mode, cnt_type, num_elems, elem_size);
6102 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
6103 mode, cnt_type, p_dev->dp_ctx);
6106 case ECORE_CHAIN_MODE_NEXT_PTR:
6107 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
6109 case ECORE_CHAIN_MODE_SINGLE:
6110 rc = ecore_chain_alloc_single(p_dev, p_chain);
6112 case ECORE_CHAIN_MODE_PBL:
6113 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
6119 return ECORE_SUCCESS;
6122 ecore_chain_free(p_dev, p_chain);
6126 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
6127 u16 src_id, u16 *dst_id)
6129 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
6132 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
6133 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
6134 DP_NOTICE(p_hwfn, true,
6135 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
6141 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
6143 return ECORE_SUCCESS;
6146 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
6147 u8 src_id, u8 *dst_id)
6149 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
6152 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
6153 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
6154 DP_NOTICE(p_hwfn, true,
6155 "vport id [%d] is not valid, available indices [%d - %d]\n",
6161 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
6163 return ECORE_SUCCESS;
6166 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
6167 u8 src_id, u8 *dst_id)
6169 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
6172 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
6173 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
6174 DP_NOTICE(p_hwfn, true,
6175 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
6181 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
6183 return ECORE_SUCCESS;
6186 enum _ecore_status_t
6187 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
6188 struct ecore_ptt *p_ptt)
6190 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
6191 ecore_wr(p_hwfn, p_ptt,
6192 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
6193 1 << p_hwfn->abs_pf_id / 2);
6194 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
6195 return ECORE_SUCCESS;
6198 DP_NOTICE(p_hwfn, false,
6199 "This function can't be set as default\n");
6203 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
6204 struct ecore_ptt *p_ptt,
6205 u32 hw_addr, void *p_eth_qzone,
6206 osal_size_t eth_qzone_size,
6209 struct coalescing_timeset *p_coal_timeset;
6211 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
6212 DP_NOTICE(p_hwfn, true,
6213 "Coalescing configuration not enabled\n");
6217 p_coal_timeset = p_eth_qzone;
6218 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
6219 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
6220 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
6221 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
6223 return ECORE_SUCCESS;
6226 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
6227 u16 rx_coal, u16 tx_coal,
6230 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
6231 enum _ecore_status_t rc = ECORE_SUCCESS;
6232 struct ecore_ptt *p_ptt;
6234 /* TODO - Configuring a single queue's coalescing but
6235 * claiming all queues are abiding same configuration
6236 * for PF and VF both.
6239 if (IS_VF(p_hwfn->p_dev))
6240 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
6243 p_ptt = ecore_ptt_acquire(p_hwfn);
6248 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
6251 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
6255 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
6258 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
6261 ecore_ptt_release(p_hwfn, p_ptt);
6266 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
6267 struct ecore_ptt *p_ptt,
6269 struct ecore_queue_cid *p_cid)
6271 struct ustorm_eth_queue_zone eth_qzone;
6272 u8 timeset, timer_res;
6274 enum _ecore_status_t rc;
6276 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6277 if (coalesce <= 0x7F) {
6279 } else if (coalesce <= 0xFF) {
6281 } else if (coalesce <= 0x1FF) {
6284 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6287 timeset = (u8)(coalesce >> timer_res);
6289 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6290 p_cid->sb_igu_id, false);
6291 if (rc != ECORE_SUCCESS)
6294 address = BAR0_MAP_REG_USDM_RAM +
6295 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6297 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
6298 sizeof(struct ustorm_eth_queue_zone), timeset);
6299 if (rc != ECORE_SUCCESS)
6306 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
6307 struct ecore_ptt *p_ptt,
6309 struct ecore_queue_cid *p_cid)
6311 struct xstorm_eth_queue_zone eth_qzone;
6312 u8 timeset, timer_res;
6314 enum _ecore_status_t rc;
6316 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6317 if (coalesce <= 0x7F) {
6319 } else if (coalesce <= 0xFF) {
6321 } else if (coalesce <= 0x1FF) {
6324 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6328 timeset = (u8)(coalesce >> timer_res);
6330 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6331 p_cid->sb_igu_id, true);
6332 if (rc != ECORE_SUCCESS)
6335 address = BAR0_MAP_REG_XSDM_RAM +
6336 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6338 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
6339 sizeof(struct xstorm_eth_queue_zone), timeset);
6344 /* Calculate final WFQ values for all vports and configure it.
6345 * After this configuration each vport must have
6346 * approx min rate = wfq * min_pf_rate / ECORE_WFQ_UNIT
6348 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6349 struct ecore_ptt *p_ptt,
6352 struct init_qm_vport_params *vport_params;
6355 vport_params = p_hwfn->qm_info.qm_vport_params;
6357 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6358 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6360 vport_params[i].wfq = (wfq_speed * ECORE_WFQ_UNIT) /
6362 ecore_init_vport_wfq(p_hwfn, p_ptt,
6363 vport_params[i].first_tx_pq_id,
6364 vport_params[i].wfq);
6368 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
6372 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
6373 p_hwfn->qm_info.qm_vport_params[i].wfq = 1;
6376 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6377 struct ecore_ptt *p_ptt)
6379 struct init_qm_vport_params *vport_params;
6382 vport_params = p_hwfn->qm_info.qm_vport_params;
6384 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6385 ecore_init_wfq_default_param(p_hwfn);
6386 ecore_init_vport_wfq(p_hwfn, p_ptt,
6387 vport_params[i].first_tx_pq_id,
6388 vport_params[i].wfq);
6392 /* This function performs several validations for WFQ
6393 * configuration and required min rate for a given vport
6394 * 1. req_rate must be greater than one percent of min_pf_rate.
6395 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
6396 * rates to get less than one percent of min_pf_rate.
6397 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
6399 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
6400 u16 vport_id, u32 req_rate,
6403 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
6404 int non_requested_count = 0, req_count = 0, i, num_vports;
6406 num_vports = p_hwfn->qm_info.num_vports;
6408 /* Accounting for the vports which are configured for WFQ explicitly */
6410 for (i = 0; i < num_vports; i++) {
6413 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
6415 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6416 total_req_min_rate += tmp_speed;
6420 /* Include current vport data as well */
6422 total_req_min_rate += req_rate;
6423 non_requested_count = num_vports - req_count;
6425 /* validate possible error cases */
6426 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
6427 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6428 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6429 vport_id, req_rate, min_pf_rate);
6433 /* TBD - for number of vports greater than 100 */
6434 if (num_vports > ECORE_WFQ_UNIT) {
6435 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6436 "Number of vports is greater than %d\n",
6441 if (total_req_min_rate > min_pf_rate) {
6442 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6443 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
6444 total_req_min_rate, min_pf_rate);
6448 /* Data left for non requested vports */
6449 total_left_rate = min_pf_rate - total_req_min_rate;
6450 left_rate_per_vp = total_left_rate / non_requested_count;
6452 /* validate if non requested get < 1% of min bw */
6453 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
6454 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6455 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6456 left_rate_per_vp, min_pf_rate);
6460 /* now req_rate for given vport passes all scenarios.
6461 * assign final wfq rates to all vports.
6463 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
6464 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
6466 for (i = 0; i < num_vports; i++) {
6467 if (p_hwfn->qm_info.wfq_data[i].configured)
6470 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
6473 return ECORE_SUCCESS;
6476 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
6477 struct ecore_ptt *p_ptt,
6478 u16 vp_id, u32 rate)
6480 struct ecore_mcp_link_state *p_link;
6481 int rc = ECORE_SUCCESS;
6483 p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output;
6485 if (!p_link->min_pf_rate) {
6486 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
6487 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
6491 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
6493 if (rc == ECORE_SUCCESS)
6494 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
6495 p_link->min_pf_rate);
6497 DP_NOTICE(p_hwfn, false,
6498 "Validation failed while configuring min rate\n");
6503 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
6504 struct ecore_ptt *p_ptt,
6507 bool use_wfq = false;
6508 int rc = ECORE_SUCCESS;
6511 /* Validate all pre configured vports for wfq */
6512 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6515 if (!p_hwfn->qm_info.wfq_data[i].configured)
6518 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
6521 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
6522 if (rc != ECORE_SUCCESS) {
6523 DP_NOTICE(p_hwfn, false,
6524 "WFQ validation failed while configuring min rate\n");
6529 if (rc == ECORE_SUCCESS && use_wfq)
6530 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
6532 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6537 /* Main API for ecore clients to configure vport min rate.
6538 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
6539 * rate - Speed in Mbps needs to be assigned to a given vport.
6541 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
6543 int i, rc = ECORE_INVAL;
6545 /* TBD - for multiple hardware functions - that is 100 gig */
6546 if (ECORE_IS_CMT(p_dev)) {
6547 DP_NOTICE(p_dev, false,
6548 "WFQ configuration is not supported for this device\n");
6552 for_each_hwfn(p_dev, i) {
6553 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6554 struct ecore_ptt *p_ptt;
6556 p_ptt = ecore_ptt_acquire(p_hwfn);
6558 return ECORE_TIMEOUT;
6560 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
6562 if (rc != ECORE_SUCCESS) {
6563 ecore_ptt_release(p_hwfn, p_ptt);
6567 ecore_ptt_release(p_hwfn, p_ptt);
6573 /* API to configure WFQ from mcp link change */
6574 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
6575 struct ecore_ptt *p_ptt,
6580 /* TBD - for multiple hardware functions - that is 100 gig */
6581 if (ECORE_IS_CMT(p_dev)) {
6582 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
6583 "WFQ configuration is not supported for this device\n");
6587 for_each_hwfn(p_dev, i) {
6588 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6590 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
6595 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
6596 struct ecore_ptt *p_ptt,
6597 struct ecore_mcp_link_state *p_link,
6600 int rc = ECORE_SUCCESS;
6602 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
6604 if (!p_link->line_speed && (max_bw != 100))
6607 p_link->speed = (p_link->line_speed * max_bw) / 100;
6608 p_hwfn->qm_info.pf_rl = p_link->speed;
6610 /* Since the limiter also affects Tx-switched traffic, we don't want it
6611 * to limit such traffic in case there's no actual limit.
6612 * In that case, set limit to imaginary high boundary.
6615 p_hwfn->qm_info.pf_rl = 100000;
6617 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
6618 p_hwfn->qm_info.pf_rl);
6620 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6621 "Configured MAX bandwidth to be %08x Mb/sec\n",
6627 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
6628 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
6630 int i, rc = ECORE_INVAL;
6632 if (max_bw < 1 || max_bw > 100) {
6633 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
6637 for_each_hwfn(p_dev, i) {
6638 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6639 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6640 struct ecore_mcp_link_state *p_link;
6641 struct ecore_ptt *p_ptt;
6643 p_link = &p_lead->mcp_info->link_output;
6645 p_ptt = ecore_ptt_acquire(p_hwfn);
6647 return ECORE_TIMEOUT;
6649 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
6652 ecore_ptt_release(p_hwfn, p_ptt);
6654 if (rc != ECORE_SUCCESS)
6661 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
6662 struct ecore_ptt *p_ptt,
6663 struct ecore_mcp_link_state *p_link,
6666 int rc = ECORE_SUCCESS;
6668 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
6669 p_hwfn->qm_info.pf_wfq = min_bw;
6671 if (!p_link->line_speed)
6674 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
6676 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
6678 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6679 "Configured MIN bandwidth to be %d Mb/sec\n",
6680 p_link->min_pf_rate);
6685 /* Main API to configure PF min bandwidth where bw range is [1-100] */
6686 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
6688 int i, rc = ECORE_INVAL;
6690 if (min_bw < 1 || min_bw > 100) {
6691 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
6695 for_each_hwfn(p_dev, i) {
6696 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6697 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6698 struct ecore_mcp_link_state *p_link;
6699 struct ecore_ptt *p_ptt;
6701 p_link = &p_lead->mcp_info->link_output;
6703 p_ptt = ecore_ptt_acquire(p_hwfn);
6705 return ECORE_TIMEOUT;
6707 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
6709 if (rc != ECORE_SUCCESS) {
6710 ecore_ptt_release(p_hwfn, p_ptt);
6714 if (p_link->min_pf_rate) {
6715 u32 min_rate = p_link->min_pf_rate;
6717 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
6722 ecore_ptt_release(p_hwfn, p_ptt);
6728 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
6730 struct ecore_mcp_link_state *p_link;
6732 p_link = &p_hwfn->mcp_info->link_output;
6734 if (p_link->min_pf_rate)
6735 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6737 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
6738 sizeof(*p_hwfn->qm_info.wfq_data) *
6739 p_hwfn->qm_info.num_vports);
6742 int ecore_device_num_engines(struct ecore_dev *p_dev)
6744 return ECORE_IS_BB(p_dev) ? 2 : 1;
6747 int ecore_device_num_ports(struct ecore_dev *p_dev)
6749 return p_dev->num_ports;
6752 void ecore_set_fw_mac_addr(__le16 *fw_msb,
6757 ((u8 *)fw_msb)[0] = mac[1];
6758 ((u8 *)fw_msb)[1] = mac[0];
6759 ((u8 *)fw_mid)[0] = mac[3];
6760 ((u8 *)fw_mid)[1] = mac[2];
6761 ((u8 *)fw_lsb)[0] = mac[5];
6762 ((u8 *)fw_lsb)[1] = mac[4];
6765 bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
6767 return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);