1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
9 #include "ecore_gtt_reg_addr.h"
11 #include "ecore_chain.h"
12 #include "ecore_status.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_init_ops.h"
16 #include "ecore_int.h"
17 #include "ecore_cxt.h"
18 #include "ecore_spq.h"
19 #include "ecore_init_fw_funcs.h"
20 #include "ecore_sp_commands.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
24 #include "ecore_mcp.h"
25 #include "ecore_hw_defs.h"
26 #include "mcp_public.h"
27 #include "ecore_iro.h"
29 #include "ecore_dcbx.h"
32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
33 * registers involved are not split and thus configuration is a race where
34 * some of the PFs configuration might be lost.
35 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
36 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
37 * there's more than a single compiled ecore component in system].
39 static osal_spinlock_t qm_lock;
40 static u32 qm_lock_ref_cnt;
42 /******************** Doorbell Recovery *******************/
43 /* The doorbell recovery mechanism consists of a list of entries which represent
44 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
45 * entity needs to register with the mechanism and provide the parameters
46 * describing it's doorbell, including a location where last used doorbell data
47 * can be found. The doorbell execute function will traverse the list and
48 * doorbell all of the registered entries.
50 struct ecore_db_recovery_entry {
51 osal_list_entry_t list_entry;
52 void OSAL_IOMEM *db_addr;
54 enum ecore_db_rec_width db_width;
55 enum ecore_db_rec_space db_space;
59 /* display a single doorbell recovery entry */
60 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
61 struct ecore_db_recovery_entry *db_entry,
64 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
65 action, db_entry, db_entry->db_addr, db_entry->db_data,
66 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
67 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
71 /* doorbell address sanity (address within doorbell bar range) */
72 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
75 /* make sure doorbell address is within the doorbell bar */
76 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
77 (u8 *)p_dev->doorbells + p_dev->db_size) {
79 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
80 db_addr, p_dev->doorbells,
81 (u8 *)p_dev->doorbells + p_dev->db_size);
85 /* make sure doorbell data pointer is not null */
87 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
94 /* find hwfn according to the doorbell address */
95 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
96 void OSAL_IOMEM *db_addr)
98 struct ecore_hwfn *p_hwfn;
100 /* In CMT doorbell bar is split down the middle between engine 0 and
103 if (ECORE_IS_CMT(p_dev))
104 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
105 &p_dev->hwfns[0] : &p_dev->hwfns[1];
107 p_hwfn = ECORE_LEADING_HWFN(p_dev);
112 /* add a new entry to the doorbell recovery mechanism */
113 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
114 void OSAL_IOMEM *db_addr,
116 enum ecore_db_rec_width db_width,
117 enum ecore_db_rec_space db_space)
119 struct ecore_db_recovery_entry *db_entry;
120 struct ecore_hwfn *p_hwfn;
122 /* shortcircuit VFs, for now */
124 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
125 return ECORE_SUCCESS;
128 /* sanitize doorbell address */
129 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
132 /* obtain hwfn from doorbell address */
133 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
136 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
138 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
143 db_entry->db_addr = db_addr;
144 db_entry->db_data = db_data;
145 db_entry->db_width = db_width;
146 db_entry->db_space = db_space;
147 db_entry->hwfn_idx = p_hwfn->my_id;
150 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
152 /* protect the list */
153 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
154 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
155 &p_hwfn->db_recovery_info.list);
156 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
158 return ECORE_SUCCESS;
161 /* remove an entry from the doorbell recovery mechanism */
162 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
163 void OSAL_IOMEM *db_addr,
166 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
167 enum _ecore_status_t rc = ECORE_INVAL;
168 struct ecore_hwfn *p_hwfn;
170 /* shortcircuit VFs, for now */
172 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
173 return ECORE_SUCCESS;
176 /* sanitize doorbell address */
177 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
180 /* obtain hwfn from doorbell address */
181 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
183 /* protect the list */
184 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
185 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
186 &p_hwfn->db_recovery_info.list,
188 struct ecore_db_recovery_entry) {
189 /* search according to db_data addr since db_addr is not unique
192 if (db_entry->db_data == db_data) {
193 ecore_db_recovery_dp_entry(p_hwfn, db_entry,
195 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
196 &p_hwfn->db_recovery_info.list);
202 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
204 if (rc == ECORE_INVAL)
206 DP_NOTICE(p_hwfn, false,
207 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
210 OSAL_FREE(p_dev, db_entry);
215 /* initialize the doorbell recovery mechanism */
216 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
218 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
220 /* make sure db_size was set in p_dev */
221 if (!p_hwfn->p_dev->db_size) {
222 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
226 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
227 #ifdef CONFIG_ECORE_LOCK_ALLOC
228 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
231 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
232 p_hwfn->db_recovery_info.db_recovery_counter = 0;
234 return ECORE_SUCCESS;
237 /* destroy the doorbell recovery mechanism */
238 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
240 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
242 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
243 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
244 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
245 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
246 db_entry = OSAL_LIST_FIRST_ENTRY(
247 &p_hwfn->db_recovery_info.list,
248 struct ecore_db_recovery_entry,
250 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
251 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
252 &p_hwfn->db_recovery_info.list);
253 OSAL_FREE(p_hwfn->p_dev, db_entry);
256 #ifdef CONFIG_ECORE_LOCK_ALLOC
257 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
259 p_hwfn->db_recovery_info.db_recovery_counter = 0;
262 /* print the content of the doorbell recovery mechanism */
263 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
265 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
267 DP_NOTICE(p_hwfn, false,
268 "Dispalying doorbell recovery database. Counter was %d\n",
269 p_hwfn->db_recovery_info.db_recovery_counter);
271 /* protect the list */
272 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
273 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
274 &p_hwfn->db_recovery_info.list,
276 struct ecore_db_recovery_entry) {
277 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
280 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
283 /* ring the doorbell of a single doorbell recovery entry */
284 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
285 struct ecore_db_recovery_entry *db_entry,
286 enum ecore_db_rec_exec db_exec)
288 /* Print according to width */
289 if (db_entry->db_width == DB_REC_WIDTH_32B)
290 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
291 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
292 db_entry->db_addr, *(u32 *)db_entry->db_data);
294 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
295 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
297 *(unsigned long *)(db_entry->db_data));
300 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
304 /* Flush the write combined buffer. Since there are multiple doorbelling
305 * entities using the same address, if we don't flush, a transaction
308 OSAL_WMB(p_hwfn->p_dev);
310 /* Ring the doorbell */
311 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
312 if (db_entry->db_width == DB_REC_WIDTH_32B)
313 DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
314 *(u32 *)(db_entry->db_data));
316 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
317 *(u64 *)(db_entry->db_data));
320 /* Flush the write combined buffer. Next doorbell may come from a
321 * different entity to the same address...
323 OSAL_WMB(p_hwfn->p_dev);
326 /* traverse the doorbell recovery entry list and ring all the doorbells */
327 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
328 enum ecore_db_rec_exec db_exec)
330 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
332 if (db_exec != DB_REC_ONCE) {
333 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
334 p_hwfn->db_recovery_info.db_recovery_counter);
336 /* track amount of times recovery was executed */
337 p_hwfn->db_recovery_info.db_recovery_counter++;
340 /* protect the list */
341 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
342 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
343 &p_hwfn->db_recovery_info.list,
345 struct ecore_db_recovery_entry) {
346 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
347 if (db_exec == DB_REC_ONCE)
351 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
353 /******************** Doorbell Recovery end ****************/
356 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
357 * load the driver. The number was
362 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
364 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
365 struct ecore_ptt *p_ptt,
368 u32 bar_reg = (bar_id == BAR_ID_0 ?
369 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
372 if (IS_VF(p_hwfn->p_dev))
373 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
375 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
377 return 1 << (val + 15);
379 /* The above registers were updated in the past only in CMT mode. Since
380 * they were found to be useful MFW started updating them from 8.7.7.0.
381 * In older MFW versions they are set to 0 which means disabled.
383 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
385 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
386 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
389 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
396 void ecore_init_dp(struct ecore_dev *p_dev,
397 u32 dp_module, u8 dp_level, void *dp_ctx)
401 p_dev->dp_level = dp_level;
402 p_dev->dp_module = dp_module;
403 p_dev->dp_ctx = dp_ctx;
404 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
405 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
407 p_hwfn->dp_level = dp_level;
408 p_hwfn->dp_module = dp_module;
409 p_hwfn->dp_ctx = dp_ctx;
413 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
417 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
418 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
420 p_hwfn->p_dev = p_dev;
422 p_hwfn->b_active = false;
424 #ifdef CONFIG_ECORE_LOCK_ALLOC
425 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
428 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
431 /* hwfn 0 is always active */
432 p_dev->hwfns[0].b_active = true;
434 /* set the default cache alignment to 128 (may be overridden later) */
435 p_dev->cache_shift = 7;
436 return ECORE_SUCCESS;
437 #ifdef CONFIG_ECORE_LOCK_ALLOC
440 struct ecore_hwfn *p_hwfn = OSAL_NULL;
442 p_hwfn = &p_dev->hwfns[i];
443 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
449 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
451 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
453 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
454 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
455 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
456 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
459 static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)
461 OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);
462 p_hwfn->dbg_user_info = OSAL_NULL;
465 void ecore_resc_free(struct ecore_dev *p_dev)
470 for_each_hwfn(p_dev, i)
471 ecore_l2_free(&p_dev->hwfns[i]);
475 OSAL_FREE(p_dev, p_dev->fw_data);
477 OSAL_FREE(p_dev, p_dev->reset_stats);
479 for_each_hwfn(p_dev, i) {
480 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
482 ecore_cxt_mngr_free(p_hwfn);
483 ecore_qm_info_free(p_hwfn);
484 ecore_spq_free(p_hwfn);
485 ecore_eq_free(p_hwfn);
486 ecore_consq_free(p_hwfn);
487 ecore_int_free(p_hwfn);
488 ecore_iov_free(p_hwfn);
489 ecore_l2_free(p_hwfn);
490 ecore_dmae_info_free(p_hwfn);
491 ecore_dcbx_info_free(p_hwfn);
492 ecore_dbg_user_data_free(p_hwfn);
493 /* @@@TBD Flush work-queue ? */
495 /* destroy doorbell recovery mechanism */
496 ecore_db_recovery_teardown(p_hwfn);
500 /******************** QM initialization *******************/
502 /* bitmaps for indicating active traffic classes.
503 * Special case for Arrowhead 4 port
505 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
506 #define ACTIVE_TCS_BMAP 0x9f
507 /* 0..3 actually used, OOO and high priority stuff all use 3 */
508 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
510 /* determines the physical queue flags for a given PF. */
511 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
519 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
520 flags |= PQ_FLAGS_VFS;
521 if (IS_ECORE_PACING(p_hwfn))
522 flags |= PQ_FLAGS_RLS;
525 switch (p_hwfn->hw_info.personality) {
527 if (!IS_ECORE_PACING(p_hwfn))
528 flags |= PQ_FLAGS_MCOS;
531 flags |= PQ_FLAGS_OFLD;
533 case ECORE_PCI_ISCSI:
534 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
536 case ECORE_PCI_ETH_ROCE:
537 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
538 if (!IS_ECORE_PACING(p_hwfn))
539 flags |= PQ_FLAGS_MCOS;
541 case ECORE_PCI_ETH_IWARP:
542 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
543 if (!IS_ECORE_PACING(p_hwfn))
544 flags |= PQ_FLAGS_MCOS;
547 DP_ERR(p_hwfn, "unknown personality %d\n",
548 p_hwfn->hw_info.personality);
554 /* Getters for resource amounts necessary for qm initialization */
555 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
557 return p_hwfn->hw_info.num_hw_tc;
560 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
562 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
563 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
566 #define NUM_DEFAULT_RLS 1
568 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
570 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
572 /* num RLs can't exceed resource amount of rls or vports or the
575 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
576 RESC_NUM(p_hwfn, ECORE_VPORT));
578 /* make sure after we reserve the default and VF rls we'll have
581 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
582 DP_NOTICE(p_hwfn, false,
583 "no rate limiters left for PF rate limiting"
584 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
588 /* subtract rls necessary for VFs and one default one for the PF */
589 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
594 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
596 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
598 /* all pqs share the same vport (hence the 1 below), except for vfs
601 return (!!(PQ_FLAGS_RLS & pq_flags)) *
602 ecore_init_qm_get_num_pf_rls(p_hwfn) +
603 (!!(PQ_FLAGS_VFS & pq_flags)) *
604 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
607 /* calc amount of PQs according to the requested flags */
608 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
610 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
612 return (!!(PQ_FLAGS_RLS & pq_flags)) *
613 ecore_init_qm_get_num_pf_rls(p_hwfn) +
614 (!!(PQ_FLAGS_MCOS & pq_flags)) *
615 ecore_init_qm_get_num_tcs(p_hwfn) +
616 (!!(PQ_FLAGS_LB & pq_flags)) +
617 (!!(PQ_FLAGS_OOO & pq_flags)) +
618 (!!(PQ_FLAGS_ACK & pq_flags)) +
619 (!!(PQ_FLAGS_OFLD & pq_flags)) +
620 (!!(PQ_FLAGS_VFS & pq_flags)) *
621 ecore_init_qm_get_num_vfs(p_hwfn);
624 /* initialize the top level QM params */
625 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
627 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
630 /* pq and vport bases for this PF */
631 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
632 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
634 /* rate limiting and weighted fair queueing are always enabled */
635 qm_info->vport_rl_en = 1;
636 qm_info->vport_wfq_en = 1;
638 /* TC config is different for AH 4 port */
639 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
641 /* in AH 4 port we have fewer TCs per port */
642 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
645 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
648 if (!qm_info->ooo_tc)
649 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
653 /* initialize qm vport params */
654 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
656 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
659 /* all vports participate in weighted fair queueing */
660 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
661 qm_info->qm_vport_params[i].vport_wfq = 1;
664 /* initialize qm port params */
665 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
667 /* Initialize qm port parameters */
668 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
670 /* indicate how ooo and high pri traffic is dealt with */
671 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
672 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
674 for (i = 0; i < num_ports; i++) {
675 struct init_qm_port_params *p_qm_port =
676 &p_hwfn->qm_info.qm_port_params[i];
678 p_qm_port->active = 1;
679 p_qm_port->active_phys_tcs = active_phys_tcs;
680 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
681 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
685 /* Reset the params which must be reset for qm init. QM init may be called as
686 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
687 * params may be affected by the init but would simply recalculate to the same
688 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
689 * affected as these amounts stay the same.
691 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
693 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
695 qm_info->num_pqs = 0;
696 qm_info->num_vports = 0;
697 qm_info->num_pf_rls = 0;
698 qm_info->num_vf_pqs = 0;
699 qm_info->first_vf_pq = 0;
700 qm_info->first_mcos_pq = 0;
701 qm_info->first_rl_pq = 0;
704 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
706 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
708 qm_info->num_vports++;
710 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
712 "vport overflow! qm_info->num_vports %d,"
713 " qm_init_get_num_vports() %d\n",
715 ecore_init_qm_get_num_vports(p_hwfn));
718 /* initialize a single pq and manage qm_info resources accounting.
719 * The pq_init_flags param determines whether the PQ is rate limited
721 * and whether a new vport is allocated to the pq or not (i.e. vport will be
725 /* flags for pq init */
726 #define PQ_INIT_SHARE_VPORT (1 << 0)
727 #define PQ_INIT_PF_RL (1 << 1)
728 #define PQ_INIT_VF_RL (1 << 2)
730 /* defines for pq init */
731 #define PQ_INIT_DEFAULT_WRR_GROUP 1
732 #define PQ_INIT_DEFAULT_TC 0
733 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
735 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
736 struct ecore_qm_info *qm_info,
737 u8 tc, u32 pq_init_flags)
739 u16 pq_idx = qm_info->num_pqs, max_pq =
740 ecore_init_qm_get_num_pqs(p_hwfn);
744 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
747 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
748 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
750 qm_info->qm_pq_params[pq_idx].tc_id = tc;
751 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
752 qm_info->qm_pq_params[pq_idx].rl_valid =
753 (pq_init_flags & PQ_INIT_PF_RL ||
754 pq_init_flags & PQ_INIT_VF_RL);
756 /* qm params accounting */
758 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
759 qm_info->num_vports++;
761 if (pq_init_flags & PQ_INIT_PF_RL)
762 qm_info->num_pf_rls++;
764 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
766 "vport overflow! qm_info->num_vports %d,"
767 " qm_init_get_num_vports() %d\n",
769 ecore_init_qm_get_num_vports(p_hwfn));
771 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
772 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
773 " qm_init_get_num_pf_rls() %d\n",
775 ecore_init_qm_get_num_pf_rls(p_hwfn));
778 /* get pq index according to PQ_FLAGS */
779 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
782 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
784 /* Can't have multiple flags set here */
785 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
786 sizeof(pq_flags)) > 1)
791 return &qm_info->first_rl_pq;
793 return &qm_info->first_mcos_pq;
795 return &qm_info->pure_lb_pq;
797 return &qm_info->ooo_pq;
799 return &qm_info->pure_ack_pq;
801 return &qm_info->offload_pq;
803 return &qm_info->first_vf_pq;
809 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
813 /* save pq index in qm info */
814 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
815 u32 pq_flags, u16 pq_val)
817 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
819 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
822 /* get tx pq index, with the PQ TX base already set (ready for context init) */
823 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
825 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
827 return *base_pq_idx + CM_TX_PQ_BASE;
830 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
832 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
835 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
837 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
840 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
842 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
845 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
847 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
850 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
852 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
854 /* for rate limiters, it is okay to use the modulo behavior - no
857 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + (rl % max_rl);
860 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
862 u16 start_pq, pq, qm_pq_idx;
864 pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
865 start_pq = p_hwfn->qm_info.start_pq;
866 qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;
868 if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
870 "qm_pq_idx %d must be smaller than %d\n",
871 qm_pq_idx, p_hwfn->qm_info.num_pqs);
874 return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
877 /* Functions for creating specific types of pqs */
878 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
880 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
882 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
885 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
886 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
889 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
891 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
893 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
896 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
897 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
900 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
902 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
904 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
907 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
908 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
911 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
913 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
915 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
918 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
919 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
922 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
924 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
927 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
930 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
931 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
932 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
935 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
937 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
938 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
940 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
943 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
945 qm_info->num_vf_pqs = num_vfs;
946 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
947 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
951 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
953 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
954 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
956 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
959 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
960 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
961 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
965 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
967 /* rate limited pqs, must come first (FW assumption) */
968 ecore_init_qm_rl_pqs(p_hwfn);
970 /* pqs for multi cos */
971 ecore_init_qm_mcos_pqs(p_hwfn);
973 /* pure loopback pq */
974 ecore_init_qm_lb_pq(p_hwfn);
976 /* out of order pq */
977 ecore_init_qm_ooo_pq(p_hwfn);
980 ecore_init_qm_pure_ack_pq(p_hwfn);
982 /* pq for offloaded protocol */
983 ecore_init_qm_offload_pq(p_hwfn);
985 /* done sharing vports */
986 ecore_init_qm_advance_vport(p_hwfn);
989 ecore_init_qm_vf_pqs(p_hwfn);
992 /* compare values of getters against resources amounts */
993 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
995 if (ecore_init_qm_get_num_vports(p_hwfn) >
996 RESC_NUM(p_hwfn, ECORE_VPORT)) {
997 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1001 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
1002 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1006 return ECORE_SUCCESS;
1010 * Function for verbose printing of the qm initialization results
1012 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
1014 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1015 struct init_qm_vport_params *vport;
1016 struct init_qm_port_params *port;
1017 struct init_qm_pq_params *pq;
1020 /* top level params */
1021 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1022 "qm init top level params: start_pq %d, start_vport %d,"
1023 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
1024 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
1025 qm_info->offload_pq, qm_info->pure_ack_pq);
1026 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1027 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
1028 " num_vports %d, max_phys_tcs_per_port %d\n",
1029 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
1030 qm_info->num_vf_pqs, qm_info->num_vports,
1031 qm_info->max_phys_tcs_per_port);
1032 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1033 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
1034 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1035 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
1036 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
1037 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1040 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1041 port = &qm_info->qm_port_params[i];
1042 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1043 "port idx %d, active %d, active_phys_tcs %d,"
1044 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1046 i, port->active, port->active_phys_tcs,
1047 port->num_pbf_cmd_lines, port->num_btb_blocks,
1052 for (i = 0; i < qm_info->num_vports; i++) {
1053 vport = &qm_info->qm_vport_params[i];
1054 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1055 "vport idx %d, vport_rl %d, wfq %d,"
1056 " first_tx_pq_id [ ",
1057 qm_info->start_vport + i, vport->vport_rl,
1059 for (tc = 0; tc < NUM_OF_TCS; tc++)
1060 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1061 vport->first_tx_pq_id[tc]);
1062 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1066 for (i = 0; i < qm_info->num_pqs; i++) {
1067 pq = &qm_info->qm_pq_params[i];
1068 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1069 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1070 qm_info->start_pq + i, pq->port_id, pq->vport_id,
1071 pq->tc_id, pq->wrr_group, pq->rl_valid);
1075 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1077 /* reset params required for init run */
1078 ecore_init_qm_reset_params(p_hwfn);
1080 /* init QM top level params */
1081 ecore_init_qm_params(p_hwfn);
1083 /* init QM port params */
1084 ecore_init_qm_port_params(p_hwfn);
1086 /* init QM vport params */
1087 ecore_init_qm_vport_params(p_hwfn);
1089 /* init QM physical queue params */
1090 ecore_init_qm_pq_params(p_hwfn);
1092 /* display all that init */
1093 ecore_dp_init_qm_params(p_hwfn);
1096 /* This function reconfigures the QM pf on the fly.
1097 * For this purpose we:
1098 * 1. reconfigure the QM database
1099 * 2. set new values to runtime array
1100 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1101 * 4. activate init tool in QM_PF stage
1102 * 5. send an sdm_qm_cmd through rbc interface to release the QM
1104 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1105 struct ecore_ptt *p_ptt)
1107 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1109 enum _ecore_status_t rc;
1111 /* initialize ecore's qm data structure */
1112 ecore_init_qm_info(p_hwfn);
1114 /* stop PF's qm queues */
1115 OSAL_SPIN_LOCK(&qm_lock);
1116 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1117 qm_info->start_pq, qm_info->num_pqs);
1118 OSAL_SPIN_UNLOCK(&qm_lock);
1122 /* clear the QM_PF runtime phase leftovers from previous init */
1123 ecore_init_clear_rt_data(p_hwfn);
1125 /* prepare QM portion of runtime array */
1126 ecore_qm_init_pf(p_hwfn, p_ptt, false);
1128 /* activate init tool on runtime array */
1129 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1130 p_hwfn->hw_info.hw_mode);
1131 if (rc != ECORE_SUCCESS)
1134 /* start PF's qm queues */
1135 OSAL_SPIN_LOCK(&qm_lock);
1136 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1137 qm_info->start_pq, qm_info->num_pqs);
1138 OSAL_SPIN_UNLOCK(&qm_lock);
1142 return ECORE_SUCCESS;
1145 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1147 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1148 enum _ecore_status_t rc;
1150 rc = ecore_init_qm_sanity(p_hwfn);
1151 if (rc != ECORE_SUCCESS)
1154 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1155 sizeof(struct init_qm_pq_params) *
1156 ecore_init_qm_get_num_pqs(p_hwfn));
1157 if (!qm_info->qm_pq_params)
1160 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1161 sizeof(struct init_qm_vport_params) *
1162 ecore_init_qm_get_num_vports(p_hwfn));
1163 if (!qm_info->qm_vport_params)
1166 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1167 sizeof(struct init_qm_port_params) *
1168 p_hwfn->p_dev->num_ports_in_engine);
1169 if (!qm_info->qm_port_params)
1172 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1173 sizeof(struct ecore_wfq_data) *
1174 ecore_init_qm_get_num_vports(p_hwfn));
1175 if (!qm_info->wfq_data)
1178 return ECORE_SUCCESS;
1181 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1182 ecore_qm_info_free(p_hwfn);
1185 /******************** End QM initialization ***************/
1187 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1189 enum _ecore_status_t rc = ECORE_SUCCESS;
1193 for_each_hwfn(p_dev, i) {
1194 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1195 if (rc != ECORE_SUCCESS)
1201 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1202 sizeof(*p_dev->fw_data));
1203 if (!p_dev->fw_data)
1206 for_each_hwfn(p_dev, i) {
1207 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1208 u32 n_eqes, num_cons;
1210 /* initialize the doorbell recovery mechanism */
1211 rc = ecore_db_recovery_setup(p_hwfn);
1215 /* First allocate the context manager structure */
1216 rc = ecore_cxt_mngr_alloc(p_hwfn);
1220 /* Set the HW cid/tid numbers (in the context manager)
1221 * Must be done prior to any further computations.
1223 rc = ecore_cxt_set_pf_params(p_hwfn);
1227 rc = ecore_alloc_qm_data(p_hwfn);
1232 ecore_init_qm_info(p_hwfn);
1234 /* Compute the ILT client partition */
1235 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1239 /* CID map / ILT shadow table / T2
1240 * The talbes sizes are determined by the computations above
1242 rc = ecore_cxt_tables_alloc(p_hwfn);
1246 /* SPQ, must follow ILT because initializes SPQ context */
1247 rc = ecore_spq_alloc(p_hwfn);
1251 /* SP status block allocation */
1252 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1255 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1259 rc = ecore_iov_alloc(p_hwfn);
1264 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1265 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1266 /* Calculate the EQ size
1267 * ---------------------
1268 * Each ICID may generate up to one event at a time i.e.
1269 * the event must be handled/cleared before a new one
1270 * can be generated. We calculate the sum of events per
1271 * protocol and create an EQ deep enough to handle the
1273 * - Core - according to SPQ.
1274 * - RoCE - per QP there are a couple of ICIDs, one
1275 * responder and one requester, each can
1276 * generate an EQE => n_eqes_qp = 2 * n_qp.
1277 * Each CQ can generate an EQE. There are 2 CQs
1278 * per QP => n_eqes_cq = 2 * n_qp.
1279 * Hence the RoCE total is 4 * n_qp or
1281 * - ENet - There can be up to two events per VF. One
1282 * for VF-PF channel and another for VF FLR
1283 * initial cleanup. The number of VFs is
1284 * bounded by MAX_NUM_VFS_BB, and is much
1285 * smaller than RoCE's so we avoid exact
1288 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1290 ecore_cxt_get_proto_cid_count(
1296 num_cons = ecore_cxt_get_proto_cid_count(
1301 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1302 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1304 ecore_cxt_get_proto_cid_count(p_hwfn,
1307 n_eqes += 2 * num_cons;
1310 if (n_eqes > 0xFFFF) {
1311 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1312 "The maximum of a u16 chain is 0x%x\n",
1317 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1321 rc = ecore_consq_alloc(p_hwfn);
1325 rc = ecore_l2_alloc(p_hwfn);
1326 if (rc != ECORE_SUCCESS)
1329 /* DMA info initialization */
1330 rc = ecore_dmae_info_alloc(p_hwfn);
1332 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
1336 /* DCBX initialization */
1337 rc = ecore_dcbx_info_alloc(p_hwfn);
1339 DP_NOTICE(p_hwfn, false,
1340 "Failed to allocate memory for dcbx structure\n");
1344 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
1346 DP_NOTICE(p_hwfn, false,
1347 "Failed to allocate dbg user info structure\n");
1352 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1353 sizeof(*p_dev->reset_stats));
1354 if (!p_dev->reset_stats) {
1355 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
1359 return ECORE_SUCCESS;
1364 ecore_resc_free(p_dev);
1368 void ecore_resc_setup(struct ecore_dev *p_dev)
1373 for_each_hwfn(p_dev, i)
1374 ecore_l2_setup(&p_dev->hwfns[i]);
1378 for_each_hwfn(p_dev, i) {
1379 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1381 ecore_cxt_mngr_setup(p_hwfn);
1382 ecore_spq_setup(p_hwfn);
1383 ecore_eq_setup(p_hwfn);
1384 ecore_consq_setup(p_hwfn);
1386 /* Read shadow of current MFW mailbox */
1387 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1388 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1389 p_hwfn->mcp_info->mfw_mb_cur,
1390 p_hwfn->mcp_info->mfw_mb_length);
1392 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1394 ecore_l2_setup(p_hwfn);
1395 ecore_iov_setup(p_hwfn);
1399 #define FINAL_CLEANUP_POLL_CNT (100)
1400 #define FINAL_CLEANUP_POLL_TIME (10)
1401 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1402 struct ecore_ptt *p_ptt,
1405 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1406 enum _ecore_status_t rc = ECORE_TIMEOUT;
1409 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1410 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1411 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1412 return ECORE_SUCCESS;
1416 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1417 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1422 command |= X_FINAL_CLEANUP_AGG_INT <<
1423 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1424 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1425 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1426 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1428 /* Make sure notification is not set before initiating final cleanup */
1430 if (REG_RD(p_hwfn, addr)) {
1431 DP_NOTICE(p_hwfn, false,
1432 "Unexpected; Found final cleanup notification");
1433 DP_NOTICE(p_hwfn, false,
1434 " before initiating final cleanup\n");
1435 REG_WR(p_hwfn, addr, 0);
1438 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1439 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1442 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1444 /* Poll until completion */
1445 while (!REG_RD(p_hwfn, addr) && count--)
1446 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1448 if (REG_RD(p_hwfn, addr))
1451 DP_NOTICE(p_hwfn, true,
1452 "Failed to receive FW final cleanup notification\n");
1454 /* Cleanup afterwards */
1455 REG_WR(p_hwfn, addr, 0);
1460 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1464 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1465 hw_mode |= 1 << MODE_BB;
1466 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1467 hw_mode |= 1 << MODE_K2;
1469 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1470 p_hwfn->p_dev->type);
1474 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1475 switch (p_hwfn->p_dev->num_ports_in_engine) {
1477 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1480 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1483 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1486 DP_NOTICE(p_hwfn, true,
1487 "num_ports_in_engine = %d not supported\n",
1488 p_hwfn->p_dev->num_ports_in_engine);
1492 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1493 &p_hwfn->p_dev->mf_bits))
1494 hw_mode |= 1 << MODE_MF_SD;
1496 hw_mode |= 1 << MODE_MF_SI;
1499 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1500 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1501 hw_mode |= 1 << MODE_FPGA;
1503 if (p_hwfn->p_dev->b_is_emul_full)
1504 hw_mode |= 1 << MODE_EMUL_FULL;
1506 hw_mode |= 1 << MODE_EMUL_REDUCED;
1510 hw_mode |= 1 << MODE_ASIC;
1512 if (ECORE_IS_CMT(p_hwfn->p_dev))
1513 hw_mode |= 1 << MODE_100G;
1515 p_hwfn->hw_info.hw_mode = hw_mode;
1517 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1518 "Configuring function for hw_mode: 0x%08x\n",
1519 p_hwfn->hw_info.hw_mode);
1521 return ECORE_SUCCESS;
1525 /* MFW-replacement initializations for non-ASIC */
1526 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1527 struct ecore_ptt *p_ptt)
1529 struct ecore_dev *p_dev = p_hwfn->p_dev;
1533 if (CHIP_REV_IS_EMUL(p_dev)) {
1534 if (ECORE_IS_AH(p_dev))
1538 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1540 if (CHIP_REV_IS_EMUL(p_dev) &&
1541 (ECORE_IS_AH(p_dev)))
1542 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1545 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1546 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1547 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1548 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1550 if (CHIP_REV_IS_EMUL(p_dev)) {
1551 if (ECORE_IS_AH(p_dev)) {
1552 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1553 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1554 (p_dev->num_ports_in_engine >> 1));
1556 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1557 p_dev->num_ports_in_engine == 4 ? 0 : 3);
1562 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1563 for (i = 0; i < 100; i++) {
1565 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1569 DP_NOTICE(p_hwfn, true,
1570 "RBC done failed to complete in PSWRQ2\n");
1572 return ECORE_SUCCESS;
1576 /* Init run time data for all PFs and their VFs on an engine.
1577 * TBD - for VFs - Once we have parent PF info for each VF in
1578 * shmem available as CAU requires knowledge of parent PF for each VF.
1580 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1582 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1585 for_each_hwfn(p_dev, i) {
1586 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1587 struct ecore_igu_info *p_igu_info;
1588 struct ecore_igu_block *p_block;
1589 struct cau_sb_entry sb_entry;
1591 p_igu_info = p_hwfn->hw_info.p_igu_info;
1594 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1596 p_block = &p_igu_info->entry[igu_sb_id];
1598 if (!p_block->is_pf)
1601 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1602 p_block->function_id, 0, 0);
1603 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1609 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1610 struct ecore_ptt *p_ptt)
1612 u32 val, wr_mbs, cache_line_size;
1614 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1627 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1632 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1633 switch (cache_line_size) {
1648 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1652 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1654 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1655 OSAL_CACHE_LINE_SIZE, wr_mbs);
1657 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1659 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1660 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1664 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1665 struct ecore_ptt *p_ptt,
1668 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1669 struct ecore_dev *p_dev = p_hwfn->p_dev;
1670 u8 vf_id, max_num_vfs;
1673 enum _ecore_status_t rc = ECORE_SUCCESS;
1675 ecore_init_cau_rt_data(p_dev);
1677 /* Program GTT windows */
1678 ecore_gtt_init(p_hwfn, p_ptt);
1681 if (CHIP_REV_IS_EMUL(p_dev)) {
1682 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1683 if (rc != ECORE_SUCCESS)
1688 if (p_hwfn->mcp_info) {
1689 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1690 qm_info->pf_rl_en = 1;
1691 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1692 qm_info->pf_wfq_en = 1;
1695 ecore_qm_common_rt_init(p_hwfn,
1696 p_dev->num_ports_in_engine,
1697 qm_info->max_phys_tcs_per_port,
1698 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1699 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1700 qm_info->qm_port_params);
1702 ecore_cxt_hw_init_common(p_hwfn);
1704 ecore_init_cache_line_size(p_hwfn, p_ptt);
1706 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
1708 if (rc != ECORE_SUCCESS)
1711 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1712 * need to decide with which value, maybe runtime
1714 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1715 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1717 if (ECORE_IS_BB(p_dev)) {
1718 /* Workaround clears ROCE search for all functions to prevent
1719 * involving non initialized function in processing ROCE packet.
1721 num_pfs = NUM_OF_ENG_PFS(p_dev);
1722 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1723 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1724 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1725 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1727 /* pretend to original PF */
1728 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1731 /* Workaround for avoiding CCFC execution error when getting packets
1732 * with CRC errors, and allowing instead the invoking of the FW error
1734 * This is not done inside the init tool since it currently can't
1735 * perform a pretending to VFs.
1737 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1738 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1739 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1740 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1741 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1742 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1743 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1744 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1746 /* pretend to original PF */
1747 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1753 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1754 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1756 #define PMEG_IF_BYTE_COUNT 8
1758 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1759 struct ecore_ptt *p_ptt,
1760 u32 addr, u64 data, u8 reg_type, u8 port)
1762 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1763 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1764 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1765 (8 << PMEG_IF_BYTE_COUNT),
1766 (reg_type << 25) | (addr << 8) | port,
1767 (u32)((data >> 32) & 0xffffffff),
1768 (u32)(data & 0xffffffff));
1770 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1771 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1772 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1773 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1774 (reg_type << 25) | (addr << 8) | port);
1775 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1776 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1777 (data >> 32) & 0xffffffff);
1780 #define XLPORT_MODE_REG (0x20a)
1781 #define XLPORT_MAC_CONTROL (0x210)
1782 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1783 #define XLPORT_ENABLE_REG (0x20b)
1785 #define XLMAC_CTRL (0x600)
1786 #define XLMAC_MODE (0x601)
1787 #define XLMAC_RX_MAX_SIZE (0x608)
1788 #define XLMAC_TX_CTRL (0x604)
1789 #define XLMAC_PAUSE_CTRL (0x60d)
1790 #define XLMAC_PFC_CTRL (0x60e)
1792 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1793 struct ecore_ptt *p_ptt)
1795 u8 loopback = 0, port = p_hwfn->port_id * 2;
1797 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1799 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1800 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1802 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1803 /* XLMAC: SOFT RESET */
1804 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1805 /* XLMAC: Port Speed >= 10Gbps */
1806 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1807 /* XLMAC: Max Size */
1808 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1809 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1810 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1812 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1813 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1814 0x30ffffc000ULL, 0, port);
1815 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1816 port); /* XLMAC: TX_EN, RX_EN */
1817 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1818 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1819 0x1003 | (loopback << 2), 0, port);
1820 /* Enabled Parallel PFC interface */
1821 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1823 /* XLPORT port enable */
1824 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1827 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1828 struct ecore_ptt *p_ptt)
1830 u8 port = p_hwfn->port_id;
1831 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1833 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1835 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1836 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1838 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1839 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1841 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1842 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1844 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1845 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1847 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1848 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1850 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1851 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1853 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1855 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1857 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1859 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1863 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1864 struct ecore_ptt *p_ptt)
1866 if (ECORE_IS_AH(p_hwfn->p_dev))
1867 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1869 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1872 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1873 struct ecore_ptt *p_ptt, u8 port)
1875 int port_offset = port ? 0x800 : 0;
1876 u32 xmac_rxctrl = 0;
1879 /* FIXME: move to common start */
1880 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1881 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1883 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1884 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1886 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1888 /* Set the number of ports on the Warp Core to 10G */
1889 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1891 /* Soft reset of XMAC */
1892 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1893 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1895 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1896 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1898 /* FIXME: move to common end */
1899 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1900 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1902 /* Set Max packet size: initialize XMAC block register for port 0 */
1903 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1905 /* CRC append for Tx packets: init XMAC block register for port 1 */
1906 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1908 /* Enable TX and RX: initialize XMAC block register for port 1 */
1909 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1910 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1911 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1912 XMAC_REG_RX_CTRL_BB + port_offset);
1913 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1914 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1918 static enum _ecore_status_t
1919 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1920 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1922 u32 dpi_bit_shift, dpi_count, dpi_page_size;
1926 /* Calculate DPI size
1927 * ------------------
1928 * The PWM region contains Doorbell Pages. The first is reserverd for
1929 * the kernel for, e.g, L2. The others are free to be used by non-
1930 * trusted applications, typically from user space. Each page, called a
1931 * doorbell page is sectioned into windows that allow doorbells to be
1932 * issued in parallel by the kernel/application. The size of such a
1933 * window (a.k.a. WID) is 1kB.
1935 * 1kB WID x N WIDS = DPI page size
1936 * DPI page size x N DPIs = PWM region size
1938 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1939 * in order to ensure that two applications won't share the same page.
1940 * It also must contain at least one WID per CPU to allow parallelism.
1941 * It also must be a power of 2, since it is stored as a bit shift.
1943 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1944 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1945 * containing 4 WIDs.
1947 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1948 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1949 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1950 ~(OSAL_PAGE_SIZE - 1);
1951 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1952 dpi_count = pwm_region_size / dpi_page_size;
1954 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1955 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1958 p_hwfn->dpi_size = dpi_page_size;
1959 p_hwfn->dpi_count = dpi_count;
1961 /* Update registers */
1962 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1964 if (dpi_count < min_dpis)
1965 return ECORE_NORESOURCES;
1967 return ECORE_SUCCESS;
1970 enum ECORE_ROCE_EDPM_MODE {
1971 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1972 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1973 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1976 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn)
1978 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
1984 static enum _ecore_status_t
1985 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1986 struct ecore_ptt *p_ptt)
1988 u32 pwm_regsize, norm_regsize;
1989 u32 non_pwm_conn, min_addr_reg1;
1990 u32 db_bar_size, n_cpus;
1993 enum _ecore_status_t rc = ECORE_SUCCESS;
1996 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1997 if (ECORE_IS_CMT(p_hwfn->p_dev))
2000 /* Calculate doorbell regions
2001 * -----------------------------------
2002 * The doorbell BAR is made of two regions. The first is called normal
2003 * region and the second is called PWM region. In the normal region
2004 * each ICID has its own set of addresses so that writing to that
2005 * specific address identifies the ICID. In the Process Window Mode
2006 * region the ICID is given in the data written to the doorbell. The
2007 * above per PF register denotes the offset in the doorbell BAR in which
2008 * the PWM region begins.
2009 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
2010 * non-PWM connection. The calculation below computes the total non-PWM
2011 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
2012 * in units of 4,096 bytes.
2014 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2015 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2017 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
2018 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
2020 min_addr_reg1 = norm_regsize / 4096;
2021 pwm_regsize = db_bar_size - norm_regsize;
2023 /* Check that the normal and PWM sizes are valid */
2024 if (db_bar_size < norm_regsize) {
2025 DP_ERR(p_hwfn->p_dev,
2026 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2027 db_bar_size, norm_regsize);
2028 return ECORE_NORESOURCES;
2030 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
2031 DP_ERR(p_hwfn->p_dev,
2032 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2033 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
2035 return ECORE_NORESOURCES;
2038 /* Calculate number of DPIs */
2039 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2040 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
2041 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
2042 /* Either EDPM is mandatory, or we are attempting to allocate a
2045 n_cpus = OSAL_NUM_CPUS();
2046 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2049 cond = ((rc != ECORE_SUCCESS) &&
2050 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2051 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2052 if (cond || p_hwfn->dcbx_no_edpm) {
2053 /* Either EDPM is disabled from user configuration, or it is
2054 * disabled via DCBx, or it is not mandatory and we failed to
2055 * allocated a WID per CPU.
2058 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2060 /* If we entered this flow due to DCBX then the DPM register is
2061 * already configured.
2066 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2067 norm_regsize, pwm_regsize);
2069 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2070 p_hwfn->dpi_size, p_hwfn->dpi_count,
2071 (!ecore_edpm_enabled(p_hwfn)) ?
2072 "disabled" : "enabled");
2074 /* Check return codes from above calls */
2075 if (rc != ECORE_SUCCESS) {
2077 "Failed to allocate enough DPIs\n");
2078 return ECORE_NORESOURCES;
2082 p_hwfn->dpi_start_offset = norm_regsize;
2084 /* Update registers */
2085 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2086 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2087 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2088 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2090 return ECORE_SUCCESS;
2093 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2094 struct ecore_ptt *p_ptt,
2097 u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2099 enum _ecore_status_t rc = ECORE_SUCCESS;
2102 /* In CMT for non-RoCE packets - use connection based classification */
2103 val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2104 for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2105 ppf_to_eng_sel[i] = val;
2106 STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2109 /* In CMT the gate should be cleared by the 2nd hwfn */
2110 if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2111 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2113 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2115 if (rc != ECORE_SUCCESS)
2118 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2121 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2122 return ECORE_SUCCESS;
2124 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2125 if (ECORE_IS_AH(p_hwfn->p_dev))
2126 return ECORE_SUCCESS;
2127 else if (ECORE_IS_BB(p_hwfn->p_dev))
2128 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2129 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2130 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2131 /* Activate OPTE in CMT */
2134 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2136 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2137 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2138 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2139 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2140 ecore_wr(p_hwfn, p_ptt,
2141 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2142 ecore_wr(p_hwfn, p_ptt,
2143 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2144 ecore_wr(p_hwfn, p_ptt,
2145 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2149 ecore_emul_link_init(p_hwfn, p_ptt);
2151 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2158 static enum _ecore_status_t
2159 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2160 struct ecore_ptt *p_ptt,
2161 struct ecore_tunnel_info *p_tunn,
2164 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2166 u8 rel_pf_id = p_hwfn->rel_pf_id;
2168 enum _ecore_status_t rc = ECORE_SUCCESS;
2172 if (p_hwfn->mcp_info) {
2173 struct ecore_mcp_function_info *p_info;
2175 p_info = &p_hwfn->mcp_info->func_info;
2176 if (p_info->bandwidth_min)
2177 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2179 /* Update rate limit once we'll actually have a link */
2180 p_hwfn->qm_info.pf_rl = 100000;
2182 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2184 ecore_int_igu_init_rt(p_hwfn);
2186 /* Set VLAN in NIG if needed */
2187 if (hw_mode & (1 << MODE_MF_SD)) {
2188 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2189 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2190 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2191 p_hwfn->hw_info.ovlan);
2193 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2194 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2195 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2199 /* Enable classification by MAC if needed */
2200 if (hw_mode & (1 << MODE_MF_SI)) {
2201 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2202 "Configuring TAGMAC_CLS_TYPE\n");
2203 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2207 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
2208 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2209 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2210 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2211 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2212 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2214 /* perform debug configuration when chip is out of reset */
2215 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2217 /* Sanity check before the PF init sequence that uses DMAE */
2218 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2222 /* PF Init sequence */
2223 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2227 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2228 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2232 /* Pure runtime initializations - directly to the HW */
2233 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2235 /* PCI relaxed ordering causes a decrease in the performance on some
2236 * systems. Till a root cause is found, disable this attribute in the
2240 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2242 * DP_NOTICE(p_hwfn, true,
2243 * "Failed to find the PCIe Cap\n");
2246 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2247 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2248 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2251 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2255 /* enable interrupts */
2256 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2257 if (rc != ECORE_SUCCESS)
2260 /* send function start command */
2261 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2262 allow_npar_tx_switch);
2264 DP_NOTICE(p_hwfn, true,
2265 "Function start ramrod failed\n");
2269 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2270 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2271 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2273 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2274 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2276 ecore_wr(p_hwfn, p_ptt,
2277 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2280 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2281 "PRS_REG_SEARCH registers after start PFn\n");
2282 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2283 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2284 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2285 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2286 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2287 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2288 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2289 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2290 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2291 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2292 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2293 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2294 prs_reg = ecore_rd(p_hwfn, p_ptt,
2295 PRS_REG_SEARCH_TCP_FIRST_FRAG);
2296 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2297 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2299 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2300 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2301 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2303 return ECORE_SUCCESS;
2306 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2307 struct ecore_ptt *p_ptt,
2310 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2312 /* Configure the PF's internal FID_enable for master transactions */
2313 ecore_wr(p_hwfn, p_ptt,
2314 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2316 /* Wait until value is set - try for 1 second every 50us */
2317 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2318 val = ecore_rd(p_hwfn, p_ptt,
2319 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2326 if (val != set_val) {
2327 DP_NOTICE(p_hwfn, true,
2328 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2329 return ECORE_UNKNOWN_ERROR;
2332 return ECORE_SUCCESS;
2335 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2336 struct ecore_ptt *p_main_ptt)
2338 /* Read shadow of current MFW mailbox */
2339 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2340 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2341 p_hwfn->mcp_info->mfw_mb_cur,
2342 p_hwfn->mcp_info->mfw_mb_length);
2345 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2346 struct ecore_ptt *p_ptt)
2348 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2349 1 << p_hwfn->abs_pf_id);
2352 static enum _ecore_status_t
2353 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
2354 struct ecore_load_req_params *p_load_req,
2355 struct ecore_drv_load_params *p_drv_load)
2357 /* Make sure that if ecore-client didn't provide inputs, all the
2358 * expected defaults are indeed zero.
2360 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2361 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2362 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2364 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2366 if (p_drv_load == OSAL_NULL)
2369 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2370 ECORE_DRV_ROLE_KDUMP :
2372 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2373 p_load_req->override_force_load = p_drv_load->override_force_load;
2375 /* Old MFW versions don't support timeout values other than default and
2376 * none, so these values are replaced according to the fall-back action.
2379 if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
2380 p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
2381 (p_hwfn->mcp_info->capabilities &
2382 FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
2383 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2387 switch (p_drv_load->mfw_timeout_fallback) {
2388 case ECORE_TO_FALLBACK_TO_NONE:
2389 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
2391 case ECORE_TO_FALLBACK_TO_DEFAULT:
2392 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
2394 case ECORE_TO_FALLBACK_FAIL_LOAD:
2395 DP_NOTICE(p_hwfn, false,
2396 "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
2397 p_drv_load->mfw_timeout_val,
2398 ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
2399 ECORE_LOAD_REQ_LOCK_TO_NONE);
2400 return ECORE_ABORTED;
2404 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
2405 p_drv_load->mfw_timeout_val,
2406 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
2408 p_load_req->timeout_val);
2410 return ECORE_SUCCESS;
2413 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2414 struct ecore_hw_init_params *p_params)
2416 if (p_params->p_tunn) {
2417 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2418 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2421 p_hwfn->b_int_enabled = 1;
2423 return ECORE_SUCCESS;
2426 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2427 struct ecore_hw_init_params *p_params)
2429 struct ecore_load_req_params load_req_params;
2430 u32 load_code, resp, param, drv_mb_param;
2431 bool b_default_mtu = true;
2432 struct ecore_hwfn *p_hwfn;
2433 enum _ecore_status_t rc = ECORE_SUCCESS;
2437 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2438 DP_NOTICE(p_dev, false,
2439 "MSI mode is not supported for CMT devices\n");
2444 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2445 if (rc != ECORE_SUCCESS)
2449 for_each_hwfn(p_dev, i) {
2450 p_hwfn = &p_dev->hwfns[i];
2452 /* If management didn't provide a default, set one of our own */
2453 if (!p_hwfn->hw_info.mtu) {
2454 p_hwfn->hw_info.mtu = 1500;
2455 b_default_mtu = false;
2459 ecore_vf_start(p_hwfn, p_params);
2463 rc = ecore_calc_hw_mode(p_hwfn);
2464 if (rc != ECORE_SUCCESS)
2467 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
2469 OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
2470 &p_dev->mf_bits))) {
2471 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
2473 ether_type = ETHER_TYPE_VLAN;
2475 ether_type = ETHER_TYPE_QINQ;
2476 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2478 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2480 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2482 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
2486 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
2488 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
2489 p_params->p_drv_load_params);
2490 if (rc != ECORE_SUCCESS)
2493 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2495 if (rc != ECORE_SUCCESS) {
2496 DP_NOTICE(p_hwfn, false,
2497 "Failed sending a LOAD_REQ command\n");
2501 load_code = load_req_params.load_code;
2502 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2503 "Load request was sent. Load code: 0x%x\n",
2506 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2509 * When coming back from hiberbate state, the registers from
2510 * which shadow is read initially are not initialized. It turns
2511 * out that these registers get initialized during the call to
2512 * ecore_mcp_load_req request. So we need to reread them here
2513 * to get the proper shadow register value.
2514 * Note: This is a workaround for the missing MFW
2515 * initialization. It may be removed once the implementation
2518 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2520 /* Only relevant for recovery:
2521 * Clear the indication after the LOAD_REQ command is responded
2524 p_dev->recov_in_prog = false;
2526 p_hwfn->first_on_engine = (load_code ==
2527 FW_MSG_CODE_DRV_LOAD_ENGINE);
2529 if (!qm_lock_ref_cnt) {
2530 #ifdef CONFIG_ECORE_LOCK_ALLOC
2531 rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
2533 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
2537 OSAL_SPIN_LOCK_INIT(&qm_lock);
2541 /* Clean up chip from previous driver if such remains exist.
2542 * This is not needed when the PF is the first one on the
2543 * engine, since afterwards we are going to init the FW.
2545 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2546 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2547 p_hwfn->rel_pf_id, false);
2548 if (rc != ECORE_SUCCESS) {
2549 ecore_hw_err_notify(p_hwfn,
2550 ECORE_HW_ERR_RAMROD_FAIL);
2555 /* Log and clear previous pglue_b errors if such exist */
2556 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
2558 /* Enable the PF's internal FID_enable in the PXP */
2559 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2561 if (rc != ECORE_SUCCESS)
2564 /* Clear the pglue_b was_error indication.
2565 * In E4 it must be done after the BME and the internal
2566 * FID_enable for the PF are set, since VDMs may cause the
2567 * indication to be set again.
2569 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2571 switch (load_code) {
2572 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2573 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2574 p_hwfn->hw_info.hw_mode);
2575 if (rc != ECORE_SUCCESS)
2578 case FW_MSG_CODE_DRV_LOAD_PORT:
2579 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2580 p_hwfn->hw_info.hw_mode);
2581 if (rc != ECORE_SUCCESS)
2584 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2585 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2587 p_hwfn->hw_info.hw_mode,
2588 p_params->b_hw_start,
2590 p_params->allow_npar_tx_switch);
2593 DP_NOTICE(p_hwfn, false,
2594 "Unexpected load code [0x%08x]", load_code);
2599 if (rc != ECORE_SUCCESS) {
2600 DP_NOTICE(p_hwfn, false,
2601 "init phase failed for loadcode 0x%x (rc %d)\n",
2606 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2607 if (rc != ECORE_SUCCESS) {
2608 DP_NOTICE(p_hwfn, false,
2609 "Sending load done failed, rc = %d\n", rc);
2610 if (rc == ECORE_NOMEM) {
2611 DP_NOTICE(p_hwfn, false,
2612 "Sending load done was failed due to memory allocation failure\n");
2618 /* send DCBX attention request command */
2619 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2620 "sending phony dcbx set command to trigger DCBx attention handling\n");
2621 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2622 DRV_MSG_CODE_SET_DCBX,
2623 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2625 if (rc != ECORE_SUCCESS) {
2626 DP_NOTICE(p_hwfn, false,
2627 "Failed to send DCBX attention request\n");
2631 p_hwfn->hw_init_done = true;
2635 /* Get pre-negotiated values for stag, bandwidth etc. */
2636 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2637 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
2638 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
2639 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2640 DRV_MSG_CODE_GET_OEM_UPDATES,
2641 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
2643 if (rc != ECORE_SUCCESS)
2644 DP_NOTICE(p_hwfn, false,
2645 "Failed to send GET_OEM_UPDATES attention request\n");
2649 /* Get pre-negotiated values for stag, bandwidth etc. */
2650 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2651 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
2652 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
2653 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2654 DRV_MSG_CODE_GET_OEM_UPDATES,
2655 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
2657 if (rc != ECORE_SUCCESS)
2658 DP_NOTICE(p_hwfn, false,
2659 "Failed to send GET_OEM_UPDATES attention request\n");
2663 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2664 drv_mb_param = STORM_FW_VERSION;
2665 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2666 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2667 drv_mb_param, &resp, ¶m);
2668 if (rc != ECORE_SUCCESS)
2669 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2671 if (!b_default_mtu) {
2672 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2673 p_hwfn->hw_info.mtu);
2674 if (rc != ECORE_SUCCESS)
2675 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2678 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2680 ECORE_OV_DRIVER_STATE_DISABLED);
2681 if (rc != ECORE_SUCCESS)
2682 DP_INFO(p_hwfn, "Failed to update driver state\n");
2684 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
2685 ECORE_OV_ESWITCH_NONE);
2686 if (rc != ECORE_SUCCESS)
2687 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
2694 #ifdef CONFIG_ECORE_LOCK_ALLOC
2695 if (!qm_lock_ref_cnt)
2696 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2699 /* The MFW load lock should be released regardless of success or failure
2700 * of initialization.
2701 * TODO: replace this with an attempt to send cancel_load.
2703 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2707 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2708 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2709 struct ecore_hwfn *p_hwfn,
2710 struct ecore_ptt *p_ptt)
2715 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2716 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2717 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2719 if ((!ecore_rd(p_hwfn, p_ptt,
2720 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2721 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2724 /* Dependent on number of connection/tasks, possibly
2725 * 1ms sleep is required between polls
2730 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2733 DP_NOTICE(p_hwfn, false,
2734 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
2735 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2736 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2739 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2743 for_each_hwfn(p_dev, j) {
2744 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2745 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2747 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2751 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2752 struct ecore_ptt *p_ptt,
2753 u32 addr, u32 expected_val)
2755 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2757 if (val != expected_val) {
2758 DP_NOTICE(p_hwfn, true,
2759 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2760 addr, val, expected_val);
2761 return ECORE_UNKNOWN_ERROR;
2764 return ECORE_SUCCESS;
2767 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2769 struct ecore_hwfn *p_hwfn;
2770 struct ecore_ptt *p_ptt;
2771 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2774 for_each_hwfn(p_dev, j) {
2775 p_hwfn = &p_dev->hwfns[j];
2776 p_ptt = p_hwfn->p_main_ptt;
2778 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2781 ecore_vf_pf_int_cleanup(p_hwfn);
2782 rc = ecore_vf_pf_reset(p_hwfn);
2783 if (rc != ECORE_SUCCESS) {
2784 DP_NOTICE(p_hwfn, true,
2785 "ecore_vf_pf_reset failed. rc = %d.\n",
2787 rc2 = ECORE_UNKNOWN_ERROR;
2792 /* mark the hw as uninitialized... */
2793 p_hwfn->hw_init_done = false;
2795 /* Send unload command to MCP */
2796 if (!p_dev->recov_in_prog) {
2797 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2798 if (rc != ECORE_SUCCESS) {
2799 DP_NOTICE(p_hwfn, false,
2800 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2802 rc2 = ECORE_UNKNOWN_ERROR;
2806 OSAL_DPC_SYNC(p_hwfn);
2808 /* After this point no MFW attentions are expected, e.g. prevent
2809 * race between pf stop and dcbx pf update.
2812 rc = ecore_sp_pf_stop(p_hwfn);
2813 if (rc != ECORE_SUCCESS) {
2814 DP_NOTICE(p_hwfn, false,
2815 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2817 rc2 = ECORE_UNKNOWN_ERROR;
2820 OSAL_DPC_SYNC(p_hwfn);
2822 /* After this point we don't expect the FW to send us async
2826 /* perform debug action after PF stop was sent */
2827 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2829 /* close NIG to BRB gate */
2830 ecore_wr(p_hwfn, p_ptt,
2831 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2834 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2835 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2836 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2837 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2838 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2840 /* @@@TBD - clean transmission queues (5.b) */
2841 /* @@@TBD - clean BTB (5.c) */
2843 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2845 /* @@@TBD - verify DMAE requests are done (8) */
2847 /* Disable Attention Generation */
2848 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2849 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2850 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2851 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2852 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2853 if (rc != ECORE_SUCCESS) {
2854 DP_NOTICE(p_hwfn, true,
2855 "Failed to return IGU CAM to default\n");
2856 rc2 = ECORE_UNKNOWN_ERROR;
2859 /* Need to wait 1ms to guarantee SBs are cleared */
2862 if (!p_dev->recov_in_prog) {
2863 ecore_verify_reg_val(p_hwfn, p_ptt,
2864 QM_REG_USG_CNT_PF_TX, 0);
2865 ecore_verify_reg_val(p_hwfn, p_ptt,
2866 QM_REG_USG_CNT_PF_OTHER, 0);
2867 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2870 /* Disable PF in HW blocks */
2871 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2872 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2875 #ifdef CONFIG_ECORE_LOCK_ALLOC
2876 if (!qm_lock_ref_cnt)
2877 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2880 if (!p_dev->recov_in_prog) {
2881 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2882 if (rc == ECORE_NOMEM) {
2883 DP_NOTICE(p_hwfn, false,
2884 "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
2885 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2887 if (rc != ECORE_SUCCESS) {
2888 DP_NOTICE(p_hwfn, false,
2889 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2891 rc2 = ECORE_UNKNOWN_ERROR;
2896 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2897 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2898 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2900 /* Clear the PF's internal FID_enable in the PXP.
2901 * In CMT this should only be done for first hw-function, and
2902 * only after all transactions have stopped for all active
2905 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2907 if (rc != ECORE_SUCCESS) {
2908 DP_NOTICE(p_hwfn, true,
2909 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2911 rc2 = ECORE_UNKNOWN_ERROR;
2918 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2922 for_each_hwfn(p_dev, j) {
2923 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2924 struct ecore_ptt *p_ptt;
2927 ecore_vf_pf_int_cleanup(p_hwfn);
2930 p_ptt = ecore_ptt_acquire(p_hwfn);
2934 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2935 "Shutting down the fastpath\n");
2937 ecore_wr(p_hwfn, p_ptt,
2938 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2940 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2941 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2942 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2943 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2944 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2946 /* @@@TBD - clean transmission queues (5.b) */
2947 /* @@@TBD - clean BTB (5.c) */
2949 /* @@@TBD - verify DMAE requests are done (8) */
2951 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2952 /* Need to wait 1ms to guarantee SBs are cleared */
2954 ecore_ptt_release(p_hwfn, p_ptt);
2957 return ECORE_SUCCESS;
2960 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2962 struct ecore_ptt *p_ptt;
2964 if (IS_VF(p_hwfn->p_dev))
2965 return ECORE_SUCCESS;
2967 p_ptt = ecore_ptt_acquire(p_hwfn);
2971 /* If roce info is allocated it means roce is initialized and should
2972 * be enabled in searcher.
2974 if (p_hwfn->p_rdma_info) {
2975 if (p_hwfn->b_rdma_enabled_in_prs)
2976 ecore_wr(p_hwfn, p_ptt,
2977 p_hwfn->rdma_prs_search_reg, 0x1);
2978 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2981 /* Re-open incoming traffic */
2982 ecore_wr(p_hwfn, p_ptt,
2983 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2984 ecore_ptt_release(p_hwfn, p_ptt);
2986 return ECORE_SUCCESS;
2989 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2990 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2992 ecore_ptt_pool_free(p_hwfn);
2993 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2996 /* Setup bar access */
2997 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2999 /* clear indirect access */
3000 if (ECORE_IS_AH(p_hwfn->p_dev)) {
3001 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3002 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
3003 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3004 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
3005 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3006 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
3007 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3008 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
3010 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3011 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
3012 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3013 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
3014 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3015 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
3016 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3017 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
3020 /* Clean previous pglue_b errors if such exist */
3021 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3023 /* enable internal target-read */
3024 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3025 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3028 static void get_function_id(struct ecore_hwfn *p_hwfn)
3031 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
3032 PXP_PF_ME_OPAQUE_ADDR);
3034 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3036 /* Bits 16-19 from the ME registers are the pf_num */
3037 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3038 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3039 PXP_CONCRETE_FID_PFID);
3040 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3041 PXP_CONCRETE_FID_PORT);
3043 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3044 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3045 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3048 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
3050 u32 *feat_num = p_hwfn->hw_info.feat_num;
3051 struct ecore_sb_cnt_info sb_cnt;
3054 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
3055 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
3057 /* L2 Queues require each: 1 status block. 1 L2 queue */
3058 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
3059 /* Start by allocating VF queues, then PF's */
3060 feat_num[ECORE_VF_L2_QUE] =
3062 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
3064 feat_num[ECORE_PF_L2_QUE] =
3066 sb_cnt.cnt - non_l2_sbs,
3067 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
3068 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
3071 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
3072 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) {
3073 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ?
3074 &feat_num[ECORE_FCOE_CQ] :
3075 &feat_num[ECORE_ISCSI_CQ];
3076 u32 limit = sb_cnt.cnt;
3078 /* The number of queues should not exceed the number of FP SBs.
3079 * In storage target, the queues are divided into pairs of a CQ
3080 * and a CmdQ, and each pair uses a single SB. The limit in
3081 * this case should allow a max ratio of 2:1 instead of 1:1.
3083 if (p_hwfn->p_dev->b_is_target)
3085 *p_storage_feat = OSAL_MIN_T(u32, limit,
3086 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
3089 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init
3090 * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2".
3092 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat,
3093 (NUM_OF_GLOBAL_QUEUES / 2));
3096 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3097 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
3098 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
3099 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
3100 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
3101 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
3102 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
3106 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
3109 case ECORE_L2_QUEUE:
3123 case ECORE_RDMA_CNQ_RAM:
3124 return "RDMA_CNQ_RAM";
3127 case ECORE_LL2_QUEUE:
3129 case ECORE_CMDQS_CQS:
3131 case ECORE_RDMA_STATS_QUEUE:
3132 return "RDMA_STATS_QUEUE";
3138 return "UNKNOWN_RESOURCE";
3142 static enum _ecore_status_t
3143 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3144 struct ecore_ptt *p_ptt,
3145 enum ecore_resources res_id,
3149 enum _ecore_status_t rc;
3151 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3152 resc_max_val, p_mcp_resp);
3153 if (rc != ECORE_SUCCESS) {
3154 DP_NOTICE(p_hwfn, false,
3155 "MFW response failure for a max value setting of resource %d [%s]\n",
3156 res_id, ecore_hw_get_resc_name(res_id));
3160 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3162 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3163 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
3165 return ECORE_SUCCESS;
3168 static enum _ecore_status_t
3169 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3170 struct ecore_ptt *p_ptt)
3172 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3173 u32 resc_max_val, mcp_resp;
3175 enum _ecore_status_t rc;
3177 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3180 case ECORE_LL2_QUEUE:
3181 case ECORE_RDMA_CNQ_RAM:
3182 case ECORE_RDMA_STATS_QUEUE:
3190 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3191 resc_max_val, &mcp_resp);
3192 if (rc != ECORE_SUCCESS)
3195 /* There's no point to continue to the next resource if the
3196 * command is not supported by the MFW.
3197 * We do continue if the command is supported but the resource
3198 * is unknown to the MFW. Such a resource will be later
3199 * configured with the default allocation values.
3201 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3202 return ECORE_NOTIMPL;
3205 return ECORE_SUCCESS;
3209 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3210 enum ecore_resources res_id,
3211 u32 *p_resc_num, u32 *p_resc_start)
3213 u8 num_funcs = p_hwfn->num_funcs_on_engine;
3214 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3217 case ECORE_L2_QUEUE:
3218 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3219 MAX_NUM_L2_QUEUES_BB) / num_funcs;
3222 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3223 MAX_NUM_VPORTS_BB) / num_funcs;
3226 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3227 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3230 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3231 MAX_QM_TX_QUEUES_BB) / num_funcs;
3234 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3238 /* Each VFC resource can accommodate both a MAC and a VLAN */
3239 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3242 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3243 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3245 case ECORE_LL2_QUEUE:
3246 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3248 case ECORE_RDMA_CNQ_RAM:
3249 case ECORE_CMDQS_CQS:
3250 /* CNQ/CMDQS are the same resource */
3252 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3254 case ECORE_RDMA_STATS_QUEUE:
3256 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3257 MAX_NUM_VPORTS_BB) / num_funcs;
3274 /* Since we want its value to reflect whether MFW supports
3275 * the new scheme, have a default of 0.
3280 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3284 return ECORE_SUCCESS;
3287 static enum _ecore_status_t
3288 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3289 bool drv_resc_alloc)
3291 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3292 u32 mcp_resp, *p_resc_num, *p_resc_start;
3293 enum _ecore_status_t rc;
3295 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3296 p_resc_start = &RESC_START(p_hwfn, res_id);
3298 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3300 if (rc != ECORE_SUCCESS) {
3302 "Failed to get default amount for resource %d [%s]\n",
3303 res_id, ecore_hw_get_resc_name(res_id));
3308 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3309 *p_resc_num = dflt_resc_num;
3310 *p_resc_start = dflt_resc_start;
3315 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3316 &mcp_resp, p_resc_num, p_resc_start);
3317 if (rc != ECORE_SUCCESS) {
3318 DP_NOTICE(p_hwfn, true,
3319 "MFW response failure for an allocation request for"
3320 " resource %d [%s]\n",
3321 res_id, ecore_hw_get_resc_name(res_id));
3325 /* Default driver values are applied in the following cases:
3326 * - The resource allocation MB command is not supported by the MFW
3327 * - There is an internal error in the MFW while processing the request
3328 * - The resource ID is unknown to the MFW
3330 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3332 "Failed to receive allocation info for resource %d [%s]."
3333 " mcp_resp = 0x%x. Applying default values"
3335 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3336 dflt_resc_num, dflt_resc_start);
3338 *p_resc_num = dflt_resc_num;
3339 *p_resc_start = dflt_resc_start;
3343 if ((*p_resc_num != dflt_resc_num ||
3344 *p_resc_start != dflt_resc_start) &&
3345 res_id != ECORE_SB) {
3347 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3348 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3349 *p_resc_start, dflt_resc_num, dflt_resc_start,
3350 drv_resc_alloc ? " - Applying default values" : "");
3351 if (drv_resc_alloc) {
3352 *p_resc_num = dflt_resc_num;
3353 *p_resc_start = dflt_resc_start;
3357 return ECORE_SUCCESS;
3360 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3361 bool drv_resc_alloc)
3363 enum _ecore_status_t rc;
3366 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3367 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3368 if (rc != ECORE_SUCCESS)
3372 return ECORE_SUCCESS;
3375 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3376 struct ecore_ptt *p_ptt,
3377 bool drv_resc_alloc)
3379 struct ecore_resc_unlock_params resc_unlock_params;
3380 struct ecore_resc_lock_params resc_lock_params;
3381 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3383 enum _ecore_status_t rc;
3385 u32 *resc_start = p_hwfn->hw_info.resc_start;
3386 u32 *resc_num = p_hwfn->hw_info.resc_num;
3387 /* For AH, an equal share of the ILT lines between the maximal number of
3388 * PFs is not enough for RoCE. This would be solved by the future
3389 * resource allocation scheme, but isn't currently present for
3390 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3391 * to work - the BB number of ILT lines divided by its max PFs number.
3393 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3396 /* Setting the max values of the soft resources and the following
3397 * resources allocation queries should be atomic. Since several PFs can
3398 * run in parallel - a resource lock is needed.
3399 * If either the resource lock or resource set value commands are not
3400 * supported - skip the max values setting, release the lock if
3401 * needed, and proceed to the queries. Other failures, including a
3402 * failure to acquire the lock, will cause this function to fail.
3403 * Old drivers that don't acquire the lock can run in parallel, and
3404 * their allocation values won't be affected by the updated max values.
3406 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3407 ECORE_RESC_LOCK_RESC_ALLOC, false);
3409 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3410 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3412 } else if (rc == ECORE_NOTIMPL) {
3414 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3415 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3416 DP_NOTICE(p_hwfn, false,
3417 "Failed to acquire the resource lock for the resource allocation commands\n");
3419 goto unlock_and_exit;
3421 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3422 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3423 DP_NOTICE(p_hwfn, false,
3424 "Failed to set the max values of the soft resources\n");
3425 goto unlock_and_exit;
3426 } else if (rc == ECORE_NOTIMPL) {
3428 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3429 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3430 &resc_unlock_params);
3431 if (rc != ECORE_SUCCESS)
3433 "Failed to release the resource lock for the resource allocation commands\n");
3437 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3438 if (rc != ECORE_SUCCESS)
3439 goto unlock_and_exit;
3441 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3442 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3443 &resc_unlock_params);
3444 if (rc != ECORE_SUCCESS)
3446 "Failed to release the resource lock for the resource allocation commands\n");
3450 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3451 /* Reduced build contains less PQs */
3452 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3453 resc_num[ECORE_PQ] = 32;
3454 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3455 p_hwfn->enabled_func_idx;
3458 /* For AH emulation, since we have a possible maximal number of
3459 * 16 enabled PFs, in case there are not enough ILT lines -
3460 * allocate only first PF as RoCE and have all the other ETH
3461 * only with less ILT lines.
3463 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3464 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3465 resc_num[ECORE_ILT],
3466 roce_min_ilt_lines);
3469 /* Correct the common ILT calculation if PF0 has more */
3470 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3471 p_hwfn->p_dev->b_is_emul_full &&
3472 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3473 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3474 resc_num[ECORE_ILT];
3477 /* Sanity for ILT */
3478 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3479 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3480 DP_NOTICE(p_hwfn, true,
3481 "Can't assign ILT pages [%08x,...,%08x]\n",
3482 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3488 /* This will also learn the number of SBs from MFW */
3489 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3492 ecore_hw_set_feat(p_hwfn);
3494 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3495 "The numbers for each resource are:\n");
3496 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3497 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3498 ecore_hw_get_resc_name(res_id),
3499 RESC_NUM(p_hwfn, res_id),
3500 RESC_START(p_hwfn, res_id));
3502 return ECORE_SUCCESS;
3505 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3506 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3507 &resc_unlock_params);
3511 static enum _ecore_status_t
3512 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3513 struct ecore_ptt *p_ptt,
3514 struct ecore_hw_prepare_params *p_params)
3516 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3517 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3518 struct ecore_mcp_link_capabilities *p_caps;
3519 struct ecore_mcp_link_params *link;
3520 enum _ecore_status_t rc;
3522 /* Read global nvm_cfg address */
3523 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3525 /* Verify MCP has initialized it */
3526 if (!nvm_cfg_addr) {
3527 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3528 if (p_params->b_relaxed_probe)
3529 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3533 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
3535 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3537 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3538 OFFSETOF(struct nvm_cfg1, glob) +
3539 OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3541 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3543 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3544 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3545 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3546 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3548 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3549 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3551 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3552 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3554 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3555 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3557 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3558 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3560 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3561 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3563 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3564 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3566 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3567 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3569 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3570 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3572 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3573 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3575 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3576 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3579 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3584 /* Read DCBX configuration */
3585 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3586 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3587 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3589 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3590 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3591 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3592 switch (dcbx_mode) {
3593 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3594 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3596 case NVM_CFG1_PORT_DCBX_MODE_CEE:
3597 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3599 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3600 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3603 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3606 /* Read default link configuration */
3607 link = &p_hwfn->mcp_info->link_input;
3608 p_caps = &p_hwfn->mcp_info->link_capabilities;
3609 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3610 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3611 link_temp = ecore_rd(p_hwfn, p_ptt,
3613 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3614 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3615 link->speed.advertised_speeds = link_temp;
3616 p_caps->speed_capabilities = link->speed.advertised_speeds;
3618 link_temp = ecore_rd(p_hwfn, p_ptt,
3620 OFFSETOF(struct nvm_cfg1_port, link_settings));
3621 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3622 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3623 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3624 link->speed.autoneg = true;
3626 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3627 link->speed.forced_speed = 1000;
3629 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3630 link->speed.forced_speed = 10000;
3632 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3633 link->speed.forced_speed = 25000;
3635 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3636 link->speed.forced_speed = 40000;
3638 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3639 link->speed.forced_speed = 50000;
3641 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3642 link->speed.forced_speed = 100000;
3645 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3648 p_caps->default_speed = link->speed.forced_speed;
3649 p_caps->default_speed_autoneg = link->speed.autoneg;
3651 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3652 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3653 link->pause.autoneg = !!(link_temp &
3654 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3655 link->pause.forced_rx = !!(link_temp &
3656 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3657 link->pause.forced_tx = !!(link_temp &
3658 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3659 link->loopback_mode = 0;
3661 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3662 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3663 OFFSETOF(struct nvm_cfg1_port, ext_phy));
3664 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3665 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3666 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3667 link->eee.enable = true;
3668 switch (link_temp) {
3669 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3670 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3671 link->eee.enable = false;
3673 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3674 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3676 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3677 p_caps->eee_lpi_timer =
3678 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3680 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3681 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3685 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3686 link->eee.tx_lpi_enable = link->eee.enable;
3687 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3689 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3692 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3693 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3694 link->speed.forced_speed, link->speed.advertised_speeds,
3695 link->speed.autoneg, link->pause.autoneg,
3696 p_caps->default_eee, p_caps->eee_lpi_timer);
3698 /* Read Multi-function information from shmem */
3699 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3700 OFFSETOF(struct nvm_cfg1, glob) +
3701 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3703 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3705 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3706 NVM_CFG1_GLOB_MF_MODE_OFFSET;
3709 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3710 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3712 case NVM_CFG1_GLOB_MF_MODE_UFP:
3713 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3714 1 << ECORE_MF_UFP_SPECIFIC |
3715 1 << ECORE_MF_8021Q_TAGGING;
3717 case NVM_CFG1_GLOB_MF_MODE_BD:
3718 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3719 1 << ECORE_MF_LLH_PROTO_CLSS |
3720 1 << ECORE_MF_8021AD_TAGGING |
3721 1 << ECORE_MF_FIP_SPECIAL;
3723 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3724 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3725 1 << ECORE_MF_LLH_PROTO_CLSS |
3726 1 << ECORE_MF_LL2_NON_UNICAST |
3727 1 << ECORE_MF_INTER_PF_SWITCH |
3728 1 << ECORE_MF_DISABLE_ARFS;
3730 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3731 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3732 1 << ECORE_MF_LLH_PROTO_CLSS |
3733 1 << ECORE_MF_LL2_NON_UNICAST;
3734 if (ECORE_IS_BB(p_hwfn->p_dev))
3735 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3738 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3739 p_hwfn->p_dev->mf_bits);
3741 if (ECORE_IS_CMT(p_hwfn->p_dev))
3742 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3744 /* It's funny since we have another switch, but it's easier
3745 * to throw this away in linux this way. Long term, it might be
3746 * better to have have getters for needed ECORE_MF_* fields,
3747 * convert client code and eliminate this.
3750 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3751 case NVM_CFG1_GLOB_MF_MODE_BD:
3752 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3754 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3755 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3757 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3758 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3760 case NVM_CFG1_GLOB_MF_MODE_UFP:
3761 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3765 /* Read Multi-function information from shmem */
3766 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3767 OFFSETOF(struct nvm_cfg1, glob) +
3768 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3770 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3771 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3772 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3773 &p_hwfn->hw_info.device_capabilities);
3774 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3775 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3776 &p_hwfn->hw_info.device_capabilities);
3777 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3778 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3779 &p_hwfn->hw_info.device_capabilities);
3780 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3781 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3782 &p_hwfn->hw_info.device_capabilities);
3783 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3784 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3785 &p_hwfn->hw_info.device_capabilities);
3787 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3788 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3790 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3796 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3797 struct ecore_ptt *p_ptt)
3799 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3800 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3801 struct ecore_dev *p_dev = p_hwfn->p_dev;
3803 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3805 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3806 * in the other bits are selected.
3807 * Bits 1-15 are for functions 1-15, respectively, and their value is
3808 * '0' only for enabled functions (function 0 always exists and
3810 * In case of CMT in BB, only the "even" functions are enabled, and thus
3811 * the number of functions for both hwfns is learnt from the same bits.
3813 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3814 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3815 MISCS_REG_FUNCTION_HIDE_BB_K2);
3817 reg_function_hide = 0;
3820 if (reg_function_hide & 0x1) {
3821 if (ECORE_IS_BB(p_dev)) {
3822 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3834 /* Get the number of the enabled functions on the engine */
3835 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3842 /* Get the PF index within the enabled functions */
3843 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3844 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3852 p_hwfn->num_funcs_on_engine = num_funcs;
3853 p_hwfn->enabled_func_idx = enabled_func_idx;
3856 if (CHIP_REV_IS_FPGA(p_dev)) {
3857 DP_NOTICE(p_hwfn, false,
3858 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3859 p_hwfn->num_funcs_on_engine = 4;
3863 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3864 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3865 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3866 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3869 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3870 struct ecore_ptt *p_ptt)
3872 struct ecore_dev *p_dev = p_hwfn->p_dev;
3876 /* Read the port mode */
3877 if (CHIP_REV_IS_FPGA(p_dev))
3879 else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3880 /* In CMT on emulation, assume 1 port */
3884 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3886 if (port_mode < 3) {
3887 p_dev->num_ports_in_engine = 1;
3888 } else if (port_mode <= 5) {
3889 p_dev->num_ports_in_engine = 2;
3891 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3892 p_dev->num_ports_in_engine);
3894 /* Default num_ports_in_engine to something */
3895 p_dev->num_ports_in_engine = 1;
3899 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3900 struct ecore_ptt *p_ptt)
3902 struct ecore_dev *p_dev = p_hwfn->p_dev;
3906 p_dev->num_ports_in_engine = 0;
3909 if (CHIP_REV_IS_EMUL(p_dev)) {
3910 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3911 switch ((port & 0xf000) >> 12) {
3913 p_dev->num_ports_in_engine = 1;
3916 p_dev->num_ports_in_engine = 2;
3919 p_dev->num_ports_in_engine = 4;
3922 DP_NOTICE(p_hwfn, false,
3923 "Unknown port mode in ECO_RESERVED %08x\n",
3928 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3929 port = ecore_rd(p_hwfn, p_ptt,
3930 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3933 p_dev->num_ports_in_engine++;
3936 if (!p_dev->num_ports_in_engine) {
3937 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3939 /* Default num_ports_in_engine to something */
3940 p_dev->num_ports_in_engine = 1;
3944 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3945 struct ecore_ptt *p_ptt)
3947 struct ecore_dev *p_dev = p_hwfn->p_dev;
3949 /* Determine the number of ports per engine */
3950 if (ECORE_IS_BB(p_dev))
3951 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3953 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3955 /* Get the total number of ports of the device */
3956 if (ECORE_IS_CMT(p_dev)) {
3957 /* In CMT there is always only one port */
3958 p_dev->num_ports = 1;
3960 } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3961 p_dev->num_ports = p_dev->num_ports_in_engine *
3962 ecore_device_num_engines(p_dev);
3965 u32 addr, global_offsize, global_addr;
3967 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3969 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3970 global_addr = SECTION_ADDR(global_offsize, 0);
3971 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3972 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3976 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3977 struct ecore_ptt *p_ptt)
3979 struct ecore_mcp_link_capabilities *p_caps;
3982 p_caps = &p_hwfn->mcp_info->link_capabilities;
3983 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3986 p_caps->eee_speed_caps = 0;
3987 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3988 OFFSETOF(struct public_port, eee_status));
3989 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3990 EEE_SUPPORTED_SPEED_OFFSET;
3991 if (eee_status & EEE_1G_SUPPORTED)
3992 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3993 if (eee_status & EEE_10G_ADV)
3994 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3997 static enum _ecore_status_t
3998 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3999 enum ecore_pci_personality personality,
4000 struct ecore_hw_prepare_params *p_params)
4002 bool drv_resc_alloc = p_params->drv_resc_alloc;
4003 enum _ecore_status_t rc;
4005 if (IS_ECORE_PACING(p_hwfn)) {
4006 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV,
4007 "Skipping IOV as packet pacing is requested\n");
4010 /* Since all information is common, only first hwfns should do this */
4011 if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) {
4012 rc = ecore_iov_hw_info(p_hwfn);
4013 if (rc != ECORE_SUCCESS) {
4014 if (p_params->b_relaxed_probe)
4015 p_params->p_relaxed_res =
4016 ECORE_HW_PREPARE_BAD_IOV;
4022 if (IS_LEAD_HWFN(p_hwfn))
4023 ecore_hw_info_port_num(p_hwfn, p_ptt);
4025 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
4028 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
4030 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
4031 if (rc != ECORE_SUCCESS)
4037 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
4038 if (rc != ECORE_SUCCESS) {
4039 if (p_params->b_relaxed_probe)
4040 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
4046 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
4048 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
4049 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
4052 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
4054 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
4055 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
4059 if (ecore_mcp_is_init(p_hwfn)) {
4060 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
4061 p_hwfn->hw_info.ovlan =
4062 p_hwfn->mcp_info->func_info.ovlan;
4064 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
4066 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
4068 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
4071 if (personality != ECORE_PCI_DEFAULT) {
4072 p_hwfn->hw_info.personality = personality;
4073 } else if (ecore_mcp_is_init(p_hwfn)) {
4074 enum ecore_pci_personality protocol;
4076 protocol = p_hwfn->mcp_info->func_info.protocol;
4077 p_hwfn->hw_info.personality = protocol;
4081 /* To overcome ILT lack for emulation, until at least until we'll have
4082 * a definite answer from system about it, allow only PF0 to be RoCE.
4084 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
4085 if (!p_hwfn->rel_pf_id)
4086 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
4088 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
4092 /* although in BB some constellations may support more than 4 tcs,
4093 * that can result in performance penalty in some cases. 4
4094 * represents a good tradeoff between performance and flexibility.
4096 if (IS_ECORE_PACING(p_hwfn))
4097 p_hwfn->hw_info.num_hw_tc = 1;
4099 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4101 /* start out with a single active tc. This can be increased either
4102 * by dcbx negotiation or by upper layer driver
4104 p_hwfn->hw_info.num_active_tc = 1;
4106 ecore_get_num_funcs(p_hwfn, p_ptt);
4108 if (ecore_mcp_is_init(p_hwfn))
4109 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4111 /* In case of forcing the driver's default resource allocation, calling
4112 * ecore_hw_get_resc() should come after initializing the personality
4113 * and after getting the number of functions, since the calculation of
4114 * the resources/features depends on them.
4115 * This order is not harmful if not forcing.
4117 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
4118 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
4120 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
4126 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
4127 struct ecore_ptt *p_ptt)
4129 struct ecore_dev *p_dev = p_hwfn->p_dev;
4133 /* Read Vendor Id / Device Id */
4134 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
4136 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
4139 /* Determine type */
4140 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
4141 switch (device_id_mask) {
4142 case ECORE_DEV_ID_MASK_BB:
4143 p_dev->type = ECORE_DEV_TYPE_BB;
4145 case ECORE_DEV_ID_MASK_AH:
4146 p_dev->type = ECORE_DEV_TYPE_AH;
4149 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
4151 return ECORE_ABORTED;
4154 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4155 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
4156 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4157 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
4159 /* Learn number of HW-functions */
4160 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4162 if (tmp & (1 << p_hwfn->rel_pf_id)) {
4163 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
4164 p_dev->num_hwfns = 2;
4166 p_dev->num_hwfns = 1;
4170 if (CHIP_REV_IS_EMUL(p_dev)) {
4171 /* For some reason we have problems with this register
4172 * in B0 emulation; Simply assume no CMT
4174 DP_NOTICE(p_dev->hwfns, false,
4175 "device on emul - assume no CMT\n");
4176 p_dev->num_hwfns = 1;
4180 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
4181 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
4182 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4183 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
4185 DP_INFO(p_dev->hwfns,
4186 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
4187 ECORE_IS_BB(p_dev) ? "BB" : "AH",
4188 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
4189 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
4192 if (ECORE_IS_BB_A0(p_dev)) {
4193 DP_NOTICE(p_dev->hwfns, false,
4194 "The chip type/rev (BB A0) is not supported!\n");
4195 return ECORE_ABORTED;
4198 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
4199 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
4201 if (CHIP_REV_IS_EMUL(p_dev)) {
4202 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
4203 if (tmp & (1 << 29)) {
4204 DP_NOTICE(p_hwfn, false,
4205 "Emulation: Running on a FULL build\n");
4206 p_dev->b_is_emul_full = true;
4208 DP_NOTICE(p_hwfn, false,
4209 "Emulation: Running on a REDUCED build\n");
4214 return ECORE_SUCCESS;
4217 #ifndef LINUX_REMOVE
4218 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
4225 for_each_hwfn(p_dev, j) {
4226 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4228 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4229 "Mark hw/fw uninitialized\n");
4231 p_hwfn->hw_init_done = false;
4233 ecore_ptt_invalidate(p_hwfn);
4238 static enum _ecore_status_t
4239 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4240 void OSAL_IOMEM * p_regview,
4241 void OSAL_IOMEM * p_doorbells,
4242 struct ecore_hw_prepare_params *p_params)
4244 struct ecore_mdump_retain_data mdump_retain;
4245 struct ecore_dev *p_dev = p_hwfn->p_dev;
4246 struct ecore_mdump_info mdump_info;
4247 enum _ecore_status_t rc = ECORE_SUCCESS;
4249 /* Split PCI bars evenly between hwfns */
4250 p_hwfn->regview = p_regview;
4251 p_hwfn->doorbells = p_doorbells;
4254 return ecore_vf_hw_prepare(p_hwfn);
4256 /* Validate that chip access is feasible */
4257 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4259 "Reading the ME register returns all Fs; Preventing further chip access\n");
4260 if (p_params->b_relaxed_probe)
4261 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4265 get_function_id(p_hwfn);
4267 /* Allocate PTT pool */
4268 rc = ecore_ptt_pool_alloc(p_hwfn);
4270 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
4271 if (p_params->b_relaxed_probe)
4272 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4276 /* Allocate the main PTT */
4277 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4279 /* First hwfn learns basic information, e.g., number of hwfns */
4280 if (!p_hwfn->my_id) {
4281 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4282 if (rc != ECORE_SUCCESS) {
4283 if (p_params->b_relaxed_probe)
4284 p_params->p_relaxed_res =
4285 ECORE_HW_PREPARE_FAILED_DEV;
4290 ecore_hw_hwfn_prepare(p_hwfn);
4292 /* Initialize MCP structure */
4293 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4295 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
4296 if (p_params->b_relaxed_probe)
4297 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4301 /* Read the device configuration information from the HW and SHMEM */
4302 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4303 p_params->personality, p_params);
4305 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
4309 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4310 * called, since among others it sets the ports number in an engine.
4312 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4313 !p_dev->recov_in_prog) {
4314 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4315 if (rc != ECORE_SUCCESS)
4316 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4318 /* Workaround for MFW issue where PF FLR does not cleanup
4321 if (!(p_hwfn->mcp_info->capabilities &
4322 FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
4323 ecore_pf_flr_igu_cleanup(p_hwfn);
4326 /* Check if mdump logs/data are present and update the epoch value */
4327 if (IS_LEAD_HWFN(p_hwfn)) {
4329 if (!CHIP_REV_IS_EMUL(p_dev)) {
4331 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4333 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4334 DP_NOTICE(p_hwfn, false,
4335 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4337 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4339 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4340 DP_NOTICE(p_hwfn, false,
4341 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4342 mdump_retain.epoch, mdump_retain.pf,
4343 mdump_retain.status);
4345 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4352 /* Allocate the init RT array and initialize the init-ops engine */
4353 rc = ecore_init_alloc(p_hwfn);
4355 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
4356 if (p_params->b_relaxed_probe)
4357 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4361 if (CHIP_REV_IS_FPGA(p_dev)) {
4362 DP_NOTICE(p_hwfn, false,
4363 "FPGA: workaround; Prevent DMAE parities\n");
4364 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4367 DP_NOTICE(p_hwfn, false,
4368 "FPGA: workaround: Set VF bar0 size\n");
4369 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4370 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4376 if (IS_LEAD_HWFN(p_hwfn))
4377 ecore_iov_free_hw_info(p_dev);
4378 ecore_mcp_free(p_hwfn);
4380 ecore_hw_hwfn_free(p_hwfn);
4385 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4386 struct ecore_hw_prepare_params *p_params)
4388 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4389 enum _ecore_status_t rc;
4391 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4392 p_dev->allow_mdump = p_params->allow_mdump;
4393 p_hwfn->b_en_pacing = p_params->b_en_pacing;
4394 p_dev->b_is_target = p_params->b_is_target;
4396 if (p_params->b_relaxed_probe)
4397 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4399 /* Store the precompiled init data ptrs */
4401 ecore_init_iro_array(p_dev);
4403 /* Initialize the first hwfn - will learn number of hwfns */
4404 rc = ecore_hw_prepare_single(p_hwfn,
4406 p_dev->doorbells, p_params);
4407 if (rc != ECORE_SUCCESS)
4410 p_params->personality = p_hwfn->hw_info.personality;
4412 /* initilalize 2nd hwfn if necessary */
4413 if (ECORE_IS_CMT(p_dev)) {
4414 void OSAL_IOMEM *p_regview, *p_doorbell;
4415 u8 OSAL_IOMEM *addr;
4417 /* adjust bar offset for second engine */
4418 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4419 ecore_hw_bar_size(p_hwfn,
4422 p_regview = (void OSAL_IOMEM *)addr;
4424 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4425 ecore_hw_bar_size(p_hwfn,
4428 p_doorbell = (void OSAL_IOMEM *)addr;
4430 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;
4431 /* prepare second hw function */
4432 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4433 p_doorbell, p_params);
4435 /* in case of error, need to free the previously
4436 * initiliazed hwfn 0.
4438 if (rc != ECORE_SUCCESS) {
4439 if (p_params->b_relaxed_probe)
4440 p_params->p_relaxed_res =
4441 ECORE_HW_PREPARE_FAILED_ENG2;
4444 ecore_init_free(p_hwfn);
4445 ecore_mcp_free(p_hwfn);
4446 ecore_hw_hwfn_free(p_hwfn);
4448 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
4457 void ecore_hw_remove(struct ecore_dev *p_dev)
4459 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4463 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4464 ECORE_OV_DRIVER_STATE_NOT_LOADED);
4466 for_each_hwfn(p_dev, i) {
4467 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4470 ecore_vf_pf_release(p_hwfn);
4474 ecore_init_free(p_hwfn);
4475 ecore_hw_hwfn_free(p_hwfn);
4476 ecore_mcp_free(p_hwfn);
4478 #ifdef CONFIG_ECORE_LOCK_ALLOC
4479 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
4483 ecore_iov_free_hw_info(p_dev);
4486 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4487 struct ecore_chain *p_chain)
4489 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4490 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4491 struct ecore_chain_next *p_next;
4497 size = p_chain->elem_size * p_chain->usable_per_page;
4499 for (i = 0; i < p_chain->page_cnt; i++) {
4503 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4504 p_virt_next = p_next->next_virt;
4505 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4507 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4508 ECORE_CHAIN_PAGE_SIZE);
4510 p_virt = p_virt_next;
4511 p_phys = p_phys_next;
4515 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4516 struct ecore_chain *p_chain)
4518 if (!p_chain->p_virt_addr)
4521 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4522 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4525 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4526 struct ecore_chain *p_chain)
4528 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4529 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4530 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4532 if (!pp_virt_addr_tbl)
4538 for (i = 0; i < page_cnt; i++) {
4539 if (!pp_virt_addr_tbl[i])
4542 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4543 *(dma_addr_t *)p_pbl_virt,
4544 ECORE_CHAIN_PAGE_SIZE);
4546 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4549 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4551 if (!p_chain->b_external_pbl)
4552 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4553 p_chain->pbl_sp.p_phys_table, pbl_size);
4555 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4558 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4560 switch (p_chain->mode) {
4561 case ECORE_CHAIN_MODE_NEXT_PTR:
4562 ecore_chain_free_next_ptr(p_dev, p_chain);
4564 case ECORE_CHAIN_MODE_SINGLE:
4565 ecore_chain_free_single(p_dev, p_chain);
4567 case ECORE_CHAIN_MODE_PBL:
4568 ecore_chain_free_pbl(p_dev, p_chain);
4573 static enum _ecore_status_t
4574 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4575 enum ecore_chain_cnt_type cnt_type,
4576 osal_size_t elem_size, u32 page_cnt)
4578 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4580 /* The actual chain size can be larger than the maximal possible value
4581 * after rounding up the requested elements number to pages, and after
4582 * taking into acount the unusuable elements (next-ptr elements).
4583 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4584 * size/capacity fields are of a u32 type.
4586 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4587 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4588 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4589 chain_size > ECORE_U32_MAX)) {
4590 DP_NOTICE(p_dev, true,
4591 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4592 (unsigned long)chain_size);
4596 return ECORE_SUCCESS;
4599 static enum _ecore_status_t
4600 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4602 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4603 dma_addr_t p_phys = 0;
4606 for (i = 0; i < p_chain->page_cnt; i++) {
4607 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4608 ECORE_CHAIN_PAGE_SIZE);
4610 DP_NOTICE(p_dev, false,
4611 "Failed to allocate chain memory\n");
4616 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4617 ecore_chain_reset(p_chain);
4619 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4623 p_virt_prev = p_virt;
4625 /* Last page's next element should point to the beginning of the
4628 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4629 p_chain->p_virt_addr,
4630 p_chain->p_phys_addr);
4632 return ECORE_SUCCESS;
4635 static enum _ecore_status_t
4636 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4638 dma_addr_t p_phys = 0;
4639 void *p_virt = OSAL_NULL;
4641 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4643 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
4647 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4648 ecore_chain_reset(p_chain);
4650 return ECORE_SUCCESS;
4653 static enum _ecore_status_t
4654 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4655 struct ecore_chain *p_chain,
4656 struct ecore_chain_ext_pbl *ext_pbl)
4658 u32 page_cnt = p_chain->page_cnt, size, i;
4659 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4660 void **pp_virt_addr_tbl = OSAL_NULL;
4661 u8 *p_pbl_virt = OSAL_NULL;
4662 void *p_virt = OSAL_NULL;
4664 size = page_cnt * sizeof(*pp_virt_addr_tbl);
4665 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4666 if (!pp_virt_addr_tbl) {
4667 DP_NOTICE(p_dev, false,
4668 "Failed to allocate memory for the chain virtual addresses table\n");
4672 /* The allocation of the PBL table is done with its full size, since it
4673 * is expected to be successive.
4674 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4675 * failure, since pp_virt_addr_tbl was previously allocated, and it
4676 * should be saved to allow its freeing during the error flow.
4678 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4680 if (ext_pbl == OSAL_NULL) {
4681 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4683 p_pbl_virt = ext_pbl->p_pbl_virt;
4684 p_pbl_phys = ext_pbl->p_pbl_phys;
4685 p_chain->b_external_pbl = true;
4688 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4691 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
4695 for (i = 0; i < page_cnt; i++) {
4696 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4697 ECORE_CHAIN_PAGE_SIZE);
4699 DP_NOTICE(p_dev, false,
4700 "Failed to allocate chain memory\n");
4705 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4706 ecore_chain_reset(p_chain);
4709 /* Fill the PBL table with the physical address of the page */
4710 *(dma_addr_t *)p_pbl_virt = p_phys;
4711 /* Keep the virtual address of the page */
4712 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4714 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4717 return ECORE_SUCCESS;
4720 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4721 enum ecore_chain_use_mode intended_use,
4722 enum ecore_chain_mode mode,
4723 enum ecore_chain_cnt_type cnt_type,
4724 u32 num_elems, osal_size_t elem_size,
4725 struct ecore_chain *p_chain,
4726 struct ecore_chain_ext_pbl *ext_pbl)
4729 enum _ecore_status_t rc = ECORE_SUCCESS;
4731 if (mode == ECORE_CHAIN_MODE_SINGLE)
4734 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4736 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4739 DP_NOTICE(p_dev, false,
4740 "Cannot allocate a chain with the given arguments:\n"
4741 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4742 intended_use, mode, cnt_type, num_elems, elem_size);
4746 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4747 mode, cnt_type, p_dev->dp_ctx);
4750 case ECORE_CHAIN_MODE_NEXT_PTR:
4751 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4753 case ECORE_CHAIN_MODE_SINGLE:
4754 rc = ecore_chain_alloc_single(p_dev, p_chain);
4756 case ECORE_CHAIN_MODE_PBL:
4757 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4763 return ECORE_SUCCESS;
4766 ecore_chain_free(p_dev, p_chain);
4770 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4771 u16 src_id, u16 *dst_id)
4773 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4776 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4777 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4778 DP_NOTICE(p_hwfn, true,
4779 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4785 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4787 return ECORE_SUCCESS;
4790 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4791 u8 src_id, u8 *dst_id)
4793 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4796 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4797 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4798 DP_NOTICE(p_hwfn, true,
4799 "vport id [%d] is not valid, available indices [%d - %d]\n",
4805 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4807 return ECORE_SUCCESS;
4810 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4811 u8 src_id, u8 *dst_id)
4813 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4816 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4817 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4818 DP_NOTICE(p_hwfn, true,
4819 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4825 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4827 return ECORE_SUCCESS;
4830 static enum _ecore_status_t
4831 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4832 struct ecore_ptt *p_ptt, u32 high, u32 low,
4838 /* Find a free entry and utilize it */
4839 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4840 en = ecore_rd(p_hwfn, p_ptt,
4841 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4845 ecore_wr(p_hwfn, p_ptt,
4846 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4847 2 * i * sizeof(u32), low);
4848 ecore_wr(p_hwfn, p_ptt,
4849 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4850 (2 * i + 1) * sizeof(u32), high);
4851 ecore_wr(p_hwfn, p_ptt,
4852 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4853 i * sizeof(u32), 0);
4854 ecore_wr(p_hwfn, p_ptt,
4855 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4856 i * sizeof(u32), 0);
4857 ecore_wr(p_hwfn, p_ptt,
4858 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4859 i * sizeof(u32), 1);
4863 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4864 return ECORE_NORESOURCES;
4868 return ECORE_SUCCESS;
4871 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4872 struct ecore_ptt *p_ptt, u8 *p_filter)
4874 u32 high, low, entry_num;
4875 enum _ecore_status_t rc = ECORE_SUCCESS;
4877 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4878 &p_hwfn->p_dev->mf_bits))
4879 return ECORE_SUCCESS;
4881 high = p_filter[1] | (p_filter[0] << 8);
4882 low = p_filter[5] | (p_filter[4] << 8) |
4883 (p_filter[3] << 16) | (p_filter[2] << 24);
4885 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4886 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4888 if (rc != ECORE_SUCCESS) {
4889 DP_NOTICE(p_hwfn, false,
4890 "Failed to find an empty LLH filter to utilize\n");
4894 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4895 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4896 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4897 p_filter[4], p_filter[5], entry_num);
4902 static enum _ecore_status_t
4903 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4904 struct ecore_ptt *p_ptt, u32 high, u32 low,
4909 /* Find the entry and clean it */
4910 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4911 if (ecore_rd(p_hwfn, p_ptt,
4912 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4913 2 * i * sizeof(u32)) != low)
4915 if (ecore_rd(p_hwfn, p_ptt,
4916 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4917 (2 * i + 1) * sizeof(u32)) != high)
4920 ecore_wr(p_hwfn, p_ptt,
4921 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4922 ecore_wr(p_hwfn, p_ptt,
4923 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4924 2 * i * sizeof(u32), 0);
4925 ecore_wr(p_hwfn, p_ptt,
4926 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4927 (2 * i + 1) * sizeof(u32), 0);
4931 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4936 return ECORE_SUCCESS;
4939 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4940 struct ecore_ptt *p_ptt, u8 *p_filter)
4942 u32 high, low, entry_num;
4943 enum _ecore_status_t rc = ECORE_SUCCESS;
4945 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4946 &p_hwfn->p_dev->mf_bits))
4949 high = p_filter[1] | (p_filter[0] << 8);
4950 low = p_filter[5] | (p_filter[4] << 8) |
4951 (p_filter[3] << 16) | (p_filter[2] << 24);
4953 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4954 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4956 if (rc != ECORE_SUCCESS) {
4957 DP_NOTICE(p_hwfn, false,
4958 "Tried to remove a non-configured filter\n");
4963 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4964 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4965 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4966 p_filter[4], p_filter[5], entry_num);
4969 static enum _ecore_status_t
4970 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4971 struct ecore_ptt *p_ptt,
4972 enum ecore_llh_port_filter_type_t type,
4973 u32 high, u32 low, u32 *p_entry_num)
4978 /* Find a free entry and utilize it */
4979 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4980 en = ecore_rd(p_hwfn, p_ptt,
4981 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4985 ecore_wr(p_hwfn, p_ptt,
4986 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4987 2 * i * sizeof(u32), low);
4988 ecore_wr(p_hwfn, p_ptt,
4989 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4990 (2 * i + 1) * sizeof(u32), high);
4991 ecore_wr(p_hwfn, p_ptt,
4992 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4993 i * sizeof(u32), 1);
4994 ecore_wr(p_hwfn, p_ptt,
4995 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4996 i * sizeof(u32), 1 << type);
4997 ecore_wr(p_hwfn, p_ptt,
4998 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
5002 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
5003 return ECORE_NORESOURCES;
5007 return ECORE_SUCCESS;
5010 enum _ecore_status_t
5011 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
5012 struct ecore_ptt *p_ptt,
5013 u16 source_port_or_eth_type,
5015 enum ecore_llh_port_filter_type_t type)
5017 u32 high, low, entry_num;
5018 enum _ecore_status_t rc = ECORE_SUCCESS;
5020 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5021 &p_hwfn->p_dev->mf_bits))
5028 case ECORE_LLH_FILTER_ETHERTYPE:
5029 high = source_port_or_eth_type;
5031 case ECORE_LLH_FILTER_TCP_SRC_PORT:
5032 case ECORE_LLH_FILTER_UDP_SRC_PORT:
5033 low = source_port_or_eth_type << 16;
5035 case ECORE_LLH_FILTER_TCP_DEST_PORT:
5036 case ECORE_LLH_FILTER_UDP_DEST_PORT:
5039 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5040 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5041 low = (source_port_or_eth_type << 16) | dest_port;
5044 DP_NOTICE(p_hwfn, true,
5045 "Non valid LLH protocol filter type %d\n", type);
5049 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5050 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5051 high, low, &entry_num);
5052 if (rc != ECORE_SUCCESS) {
5053 DP_NOTICE(p_hwfn, false,
5054 "Failed to find an empty LLH filter to utilize\n");
5058 case ECORE_LLH_FILTER_ETHERTYPE:
5059 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5060 "ETH type %x is added at %d\n",
5061 source_port_or_eth_type, entry_num);
5063 case ECORE_LLH_FILTER_TCP_SRC_PORT:
5064 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5065 "TCP src port %x is added at %d\n",
5066 source_port_or_eth_type, entry_num);
5068 case ECORE_LLH_FILTER_UDP_SRC_PORT:
5069 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5070 "UDP src port %x is added at %d\n",
5071 source_port_or_eth_type, entry_num);
5073 case ECORE_LLH_FILTER_TCP_DEST_PORT:
5074 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5075 "TCP dst port %x is added at %d\n", dest_port,
5078 case ECORE_LLH_FILTER_UDP_DEST_PORT:
5079 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5080 "UDP dst port %x is added at %d\n", dest_port,
5083 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5084 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5085 "TCP src/dst ports %x/%x are added at %d\n",
5086 source_port_or_eth_type, dest_port, entry_num);
5088 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5089 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5090 "UDP src/dst ports %x/%x are added at %d\n",
5091 source_port_or_eth_type, dest_port, entry_num);
5098 static enum _ecore_status_t
5099 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
5100 struct ecore_ptt *p_ptt,
5101 enum ecore_llh_port_filter_type_t type,
5102 u32 high, u32 low, u32 *p_entry_num)
5106 /* Find the entry and clean it */
5107 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5108 if (!ecore_rd(p_hwfn, p_ptt,
5109 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
5112 if (!ecore_rd(p_hwfn, p_ptt,
5113 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
5116 if (!(ecore_rd(p_hwfn, p_ptt,
5117 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
5118 i * sizeof(u32)) & (1 << type)))
5120 if (ecore_rd(p_hwfn, p_ptt,
5121 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5122 2 * i * sizeof(u32)) != low)
5124 if (ecore_rd(p_hwfn, p_ptt,
5125 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5126 (2 * i + 1) * sizeof(u32)) != high)
5129 ecore_wr(p_hwfn, p_ptt,
5130 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
5131 ecore_wr(p_hwfn, p_ptt,
5132 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
5133 i * sizeof(u32), 0);
5134 ecore_wr(p_hwfn, p_ptt,
5135 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
5136 i * sizeof(u32), 0);
5137 ecore_wr(p_hwfn, p_ptt,
5138 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5139 2 * i * sizeof(u32), 0);
5140 ecore_wr(p_hwfn, p_ptt,
5141 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5142 (2 * i + 1) * sizeof(u32), 0);
5146 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
5151 return ECORE_SUCCESS;
5155 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
5156 struct ecore_ptt *p_ptt,
5157 u16 source_port_or_eth_type,
5159 enum ecore_llh_port_filter_type_t type)
5161 u32 high, low, entry_num;
5162 enum _ecore_status_t rc = ECORE_SUCCESS;
5164 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5165 &p_hwfn->p_dev->mf_bits))
5172 case ECORE_LLH_FILTER_ETHERTYPE:
5173 high = source_port_or_eth_type;
5175 case ECORE_LLH_FILTER_TCP_SRC_PORT:
5176 case ECORE_LLH_FILTER_UDP_SRC_PORT:
5177 low = source_port_or_eth_type << 16;
5179 case ECORE_LLH_FILTER_TCP_DEST_PORT:
5180 case ECORE_LLH_FILTER_UDP_DEST_PORT:
5183 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5184 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5185 low = (source_port_or_eth_type << 16) | dest_port;
5188 DP_NOTICE(p_hwfn, true,
5189 "Non valid LLH protocol filter type %d\n", type);
5193 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5194 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5197 if (rc != ECORE_SUCCESS) {
5198 DP_NOTICE(p_hwfn, false,
5199 "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
5200 type, source_port_or_eth_type, dest_port);
5204 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5205 "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
5206 type, source_port_or_eth_type, dest_port, entry_num);
5209 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
5210 struct ecore_ptt *p_ptt)
5214 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
5217 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5218 ecore_wr(p_hwfn, p_ptt,
5219 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
5220 i * sizeof(u32), 0);
5221 ecore_wr(p_hwfn, p_ptt,
5222 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5223 2 * i * sizeof(u32), 0);
5224 ecore_wr(p_hwfn, p_ptt,
5225 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5226 (2 * i + 1) * sizeof(u32), 0);
5230 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
5231 struct ecore_ptt *p_ptt)
5233 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5234 &p_hwfn->p_dev->mf_bits) &&
5235 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5236 &p_hwfn->p_dev->mf_bits))
5239 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5240 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5243 enum _ecore_status_t
5244 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5245 struct ecore_ptt *p_ptt)
5247 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5248 ecore_wr(p_hwfn, p_ptt,
5249 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5250 1 << p_hwfn->abs_pf_id / 2);
5251 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5252 return ECORE_SUCCESS;
5255 DP_NOTICE(p_hwfn, false,
5256 "This function can't be set as default\n");
5260 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5261 struct ecore_ptt *p_ptt,
5262 u32 hw_addr, void *p_eth_qzone,
5263 osal_size_t eth_qzone_size,
5266 struct coalescing_timeset *p_coal_timeset;
5268 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5269 DP_NOTICE(p_hwfn, true,
5270 "Coalescing configuration not enabled\n");
5274 p_coal_timeset = p_eth_qzone;
5275 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5276 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5277 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5278 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5280 return ECORE_SUCCESS;
5283 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5284 u16 rx_coal, u16 tx_coal,
5287 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5288 enum _ecore_status_t rc = ECORE_SUCCESS;
5289 struct ecore_ptt *p_ptt;
5291 /* TODO - Configuring a single queue's coalescing but
5292 * claiming all queues are abiding same configuration
5293 * for PF and VF both.
5296 if (IS_VF(p_hwfn->p_dev))
5297 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5300 p_ptt = ecore_ptt_acquire(p_hwfn);
5305 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5308 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5312 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5315 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5318 ecore_ptt_release(p_hwfn, p_ptt);
5323 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5324 struct ecore_ptt *p_ptt,
5326 struct ecore_queue_cid *p_cid)
5328 struct ustorm_eth_queue_zone eth_qzone;
5329 u8 timeset, timer_res;
5331 enum _ecore_status_t rc;
5333 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5334 if (coalesce <= 0x7F) {
5336 } else if (coalesce <= 0xFF) {
5338 } else if (coalesce <= 0x1FF) {
5341 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5344 timeset = (u8)(coalesce >> timer_res);
5346 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5347 p_cid->sb_igu_id, false);
5348 if (rc != ECORE_SUCCESS)
5351 address = BAR0_MAP_REG_USDM_RAM +
5352 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5354 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5355 sizeof(struct ustorm_eth_queue_zone), timeset);
5356 if (rc != ECORE_SUCCESS)
5363 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5364 struct ecore_ptt *p_ptt,
5366 struct ecore_queue_cid *p_cid)
5368 struct xstorm_eth_queue_zone eth_qzone;
5369 u8 timeset, timer_res;
5371 enum _ecore_status_t rc;
5373 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5374 if (coalesce <= 0x7F) {
5376 } else if (coalesce <= 0xFF) {
5378 } else if (coalesce <= 0x1FF) {
5381 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5385 timeset = (u8)(coalesce >> timer_res);
5387 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5388 p_cid->sb_igu_id, true);
5389 if (rc != ECORE_SUCCESS)
5392 address = BAR0_MAP_REG_XSDM_RAM +
5393 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5395 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5396 sizeof(struct xstorm_eth_queue_zone), timeset);
5401 /* Calculate final WFQ values for all vports and configure it.
5402 * After this configuration each vport must have
5403 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5405 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5406 struct ecore_ptt *p_ptt,
5409 struct init_qm_vport_params *vport_params;
5412 vport_params = p_hwfn->qm_info.qm_vport_params;
5414 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5415 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5417 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5419 ecore_init_vport_wfq(p_hwfn, p_ptt,
5420 vport_params[i].first_tx_pq_id,
5421 vport_params[i].vport_wfq);
5425 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5429 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5430 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5433 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5434 struct ecore_ptt *p_ptt)
5436 struct init_qm_vport_params *vport_params;
5439 vport_params = p_hwfn->qm_info.qm_vport_params;
5441 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5442 ecore_init_wfq_default_param(p_hwfn);
5443 ecore_init_vport_wfq(p_hwfn, p_ptt,
5444 vport_params[i].first_tx_pq_id,
5445 vport_params[i].vport_wfq);
5449 /* This function performs several validations for WFQ
5450 * configuration and required min rate for a given vport
5451 * 1. req_rate must be greater than one percent of min_pf_rate.
5452 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5453 * rates to get less than one percent of min_pf_rate.
5454 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5456 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5457 u16 vport_id, u32 req_rate,
5460 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5461 int non_requested_count = 0, req_count = 0, i, num_vports;
5463 num_vports = p_hwfn->qm_info.num_vports;
5465 /* Accounting for the vports which are configured for WFQ explicitly */
5467 for (i = 0; i < num_vports; i++) {
5470 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5472 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5473 total_req_min_rate += tmp_speed;
5477 /* Include current vport data as well */
5479 total_req_min_rate += req_rate;
5480 non_requested_count = num_vports - req_count;
5482 /* validate possible error cases */
5483 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5484 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5485 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5486 vport_id, req_rate, min_pf_rate);
5490 /* TBD - for number of vports greater than 100 */
5491 if (num_vports > ECORE_WFQ_UNIT) {
5492 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5493 "Number of vports is greater than %d\n",
5498 if (total_req_min_rate > min_pf_rate) {
5499 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5500 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5501 total_req_min_rate, min_pf_rate);
5505 /* Data left for non requested vports */
5506 total_left_rate = min_pf_rate - total_req_min_rate;
5507 left_rate_per_vp = total_left_rate / non_requested_count;
5509 /* validate if non requested get < 1% of min bw */
5510 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5511 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5512 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5513 left_rate_per_vp, min_pf_rate);
5517 /* now req_rate for given vport passes all scenarios.
5518 * assign final wfq rates to all vports.
5520 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5521 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5523 for (i = 0; i < num_vports; i++) {
5524 if (p_hwfn->qm_info.wfq_data[i].configured)
5527 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5530 return ECORE_SUCCESS;
5533 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5534 struct ecore_ptt *p_ptt,
5535 u16 vp_id, u32 rate)
5537 struct ecore_mcp_link_state *p_link;
5538 int rc = ECORE_SUCCESS;
5540 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5542 if (!p_link->min_pf_rate) {
5543 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5544 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5548 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5550 if (rc == ECORE_SUCCESS)
5551 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5552 p_link->min_pf_rate);
5554 DP_NOTICE(p_hwfn, false,
5555 "Validation failed while configuring min rate\n");
5560 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5561 struct ecore_ptt *p_ptt,
5564 bool use_wfq = false;
5565 int rc = ECORE_SUCCESS;
5568 /* Validate all pre configured vports for wfq */
5569 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5572 if (!p_hwfn->qm_info.wfq_data[i].configured)
5575 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5578 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5579 if (rc != ECORE_SUCCESS) {
5580 DP_NOTICE(p_hwfn, false,
5581 "WFQ validation failed while configuring min rate\n");
5586 if (rc == ECORE_SUCCESS && use_wfq)
5587 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5589 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5594 /* Main API for ecore clients to configure vport min rate.
5595 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5596 * rate - Speed in Mbps needs to be assigned to a given vport.
5598 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5600 int i, rc = ECORE_INVAL;
5602 /* TBD - for multiple hardware functions - that is 100 gig */
5603 if (ECORE_IS_CMT(p_dev)) {
5604 DP_NOTICE(p_dev, false,
5605 "WFQ configuration is not supported for this device\n");
5609 for_each_hwfn(p_dev, i) {
5610 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5611 struct ecore_ptt *p_ptt;
5613 p_ptt = ecore_ptt_acquire(p_hwfn);
5615 return ECORE_TIMEOUT;
5617 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5619 if (rc != ECORE_SUCCESS) {
5620 ecore_ptt_release(p_hwfn, p_ptt);
5624 ecore_ptt_release(p_hwfn, p_ptt);
5630 /* API to configure WFQ from mcp link change */
5631 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5632 struct ecore_ptt *p_ptt,
5637 /* TBD - for multiple hardware functions - that is 100 gig */
5638 if (ECORE_IS_CMT(p_dev)) {
5639 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5640 "WFQ configuration is not supported for this device\n");
5644 for_each_hwfn(p_dev, i) {
5645 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5647 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5652 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5653 struct ecore_ptt *p_ptt,
5654 struct ecore_mcp_link_state *p_link,
5657 int rc = ECORE_SUCCESS;
5659 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5661 if (!p_link->line_speed && (max_bw != 100))
5664 p_link->speed = (p_link->line_speed * max_bw) / 100;
5665 p_hwfn->qm_info.pf_rl = p_link->speed;
5667 /* Since the limiter also affects Tx-switched traffic, we don't want it
5668 * to limit such traffic in case there's no actual limit.
5669 * In that case, set limit to imaginary high boundary.
5672 p_hwfn->qm_info.pf_rl = 100000;
5674 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5675 p_hwfn->qm_info.pf_rl);
5677 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5678 "Configured MAX bandwidth to be %08x Mb/sec\n",
5684 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5685 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5687 int i, rc = ECORE_INVAL;
5689 if (max_bw < 1 || max_bw > 100) {
5690 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5694 for_each_hwfn(p_dev, i) {
5695 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5696 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5697 struct ecore_mcp_link_state *p_link;
5698 struct ecore_ptt *p_ptt;
5700 p_link = &p_lead->mcp_info->link_output;
5702 p_ptt = ecore_ptt_acquire(p_hwfn);
5704 return ECORE_TIMEOUT;
5706 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5709 ecore_ptt_release(p_hwfn, p_ptt);
5711 if (rc != ECORE_SUCCESS)
5718 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5719 struct ecore_ptt *p_ptt,
5720 struct ecore_mcp_link_state *p_link,
5723 int rc = ECORE_SUCCESS;
5725 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5726 p_hwfn->qm_info.pf_wfq = min_bw;
5728 if (!p_link->line_speed)
5731 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5733 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5735 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5736 "Configured MIN bandwidth to be %d Mb/sec\n",
5737 p_link->min_pf_rate);
5742 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5743 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5745 int i, rc = ECORE_INVAL;
5747 if (min_bw < 1 || min_bw > 100) {
5748 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5752 for_each_hwfn(p_dev, i) {
5753 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5754 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5755 struct ecore_mcp_link_state *p_link;
5756 struct ecore_ptt *p_ptt;
5758 p_link = &p_lead->mcp_info->link_output;
5760 p_ptt = ecore_ptt_acquire(p_hwfn);
5762 return ECORE_TIMEOUT;
5764 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5766 if (rc != ECORE_SUCCESS) {
5767 ecore_ptt_release(p_hwfn, p_ptt);
5771 if (p_link->min_pf_rate) {
5772 u32 min_rate = p_link->min_pf_rate;
5774 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5779 ecore_ptt_release(p_hwfn, p_ptt);
5785 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5787 struct ecore_mcp_link_state *p_link;
5789 p_link = &p_hwfn->mcp_info->link_output;
5791 if (p_link->min_pf_rate)
5792 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5794 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5795 sizeof(*p_hwfn->qm_info.wfq_data) *
5796 p_hwfn->qm_info.num_vports);
5799 int ecore_device_num_engines(struct ecore_dev *p_dev)
5801 return ECORE_IS_BB(p_dev) ? 2 : 1;
5804 int ecore_device_num_ports(struct ecore_dev *p_dev)
5806 return p_dev->num_ports;
5809 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5814 ((u8 *)fw_msb)[0] = mac[1];
5815 ((u8 *)fw_msb)[1] = mac[0];
5816 ((u8 *)fw_mid)[0] = mac[3];
5817 ((u8 *)fw_mid)[1] = mac[2];
5818 ((u8 *)fw_lsb)[0] = mac[5];
5819 ((u8 *)fw_lsb)[1] = mac[4];
5822 bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
5824 return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);