2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
36 * registers involved are not split and thus configuration is a race where
37 * some of the PFs configuration might be lost.
38 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
39 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
40 * there's more than a single compiled ecore component in system].
42 static osal_spinlock_t qm_lock;
43 static bool qm_lock_init;
46 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
47 * load the driver. The number was
52 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
55 BAR_ID_0, /* used for GRC */
56 BAR_ID_1 /* Used for doorbells */
59 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
61 u32 bar_reg = (bar_id == BAR_ID_0 ?
62 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
65 if (IS_VF(p_hwfn->p_dev)) {
66 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
67 * read from actual register, but we're currently not using
68 * it for actual doorbelling.
73 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
75 return 1 << (val + 15);
77 /* The above registers were updated in the past only in CMT mode. Since
78 * they were found to be useful MFW started updating them from 8.7.7.0.
79 * In older MFW versions they are set to 0 which means disabled.
81 if (p_hwfn->p_dev->num_hwfns > 1) {
82 DP_NOTICE(p_hwfn, false,
83 "BAR size not configured. Assuming BAR size of 256kB"
84 " for GRC and 512kB for DB\n");
85 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
87 DP_NOTICE(p_hwfn, false,
88 "BAR size not configured. Assuming BAR size of 512kB"
89 " for GRC and 512kB for DB\n");
96 void ecore_init_dp(struct ecore_dev *p_dev,
97 u32 dp_module, u8 dp_level, void *dp_ctx)
101 p_dev->dp_level = dp_level;
102 p_dev->dp_module = dp_module;
103 p_dev->dp_ctx = dp_ctx;
104 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
105 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
107 p_hwfn->dp_level = dp_level;
108 p_hwfn->dp_module = dp_module;
109 p_hwfn->dp_ctx = dp_ctx;
113 void ecore_init_struct(struct ecore_dev *p_dev)
117 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
118 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
120 p_hwfn->p_dev = p_dev;
122 p_hwfn->b_active = false;
124 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
125 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
128 /* hwfn 0 is always active */
129 p_dev->hwfns[0].b_active = true;
131 /* set the default cache alignment to 128 (may be overridden later) */
132 p_dev->cache_shift = 7;
135 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
137 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
139 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
141 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
142 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
145 void ecore_resc_free(struct ecore_dev *p_dev)
152 OSAL_FREE(p_dev, p_dev->fw_data);
154 OSAL_FREE(p_dev, p_dev->reset_stats);
156 for_each_hwfn(p_dev, i) {
157 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
159 ecore_cxt_mngr_free(p_hwfn);
160 ecore_qm_info_free(p_hwfn);
161 ecore_spq_free(p_hwfn);
162 ecore_eq_free(p_hwfn);
163 ecore_consq_free(p_hwfn);
164 ecore_int_free(p_hwfn);
165 ecore_iov_free(p_hwfn);
166 ecore_dmae_info_free(p_hwfn);
167 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
168 /* @@@TBD Flush work-queue ? */
172 /******************** QM initialization *******************/
174 /* bitmaps for indicating active traffic classes.
175 * Special case for Arrowhead 4 port
177 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
178 #define ACTIVE_TCS_BMAP 0x9f
179 /* 0..3 actually used, OOO and high priority stuff all use 3 */
180 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
182 /* determines the physical queue flags for a given PF. */
183 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
191 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
192 flags |= PQ_FLAGS_VFS;
195 switch (p_hwfn->hw_info.personality) {
197 flags |= PQ_FLAGS_MCOS;
200 flags |= PQ_FLAGS_OFLD;
202 case ECORE_PCI_ISCSI:
203 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
205 case ECORE_PCI_ETH_ROCE:
206 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
208 case ECORE_PCI_ETH_IWARP:
209 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
213 DP_ERR(p_hwfn, "unknown personality %d\n",
214 p_hwfn->hw_info.personality);
220 /* Getters for resource amounts necessary for qm initialization */
221 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
223 return p_hwfn->hw_info.num_hw_tc;
226 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
228 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
229 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
232 #define NUM_DEFAULT_RLS 1
234 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
236 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
239 /* num RLs can't exceed resource amount of rls or vports or the
242 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
243 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
245 /* make sure after we reserve the default and VF rls we'll have
248 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
249 DP_NOTICE(p_hwfn, false,
250 "no rate limiters left for PF rate limiting"
251 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
255 /* subtract rls necessary for VFs and one default one for the PF */
256 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
261 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
263 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
265 /* all pqs share the same vport (hence the 1 below), except for vfs
268 return (!!(PQ_FLAGS_RLS & pq_flags)) *
269 ecore_init_qm_get_num_pf_rls(p_hwfn) +
270 (!!(PQ_FLAGS_VFS & pq_flags)) *
271 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
274 /* calc amount of PQs according to the requested flags */
275 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
277 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
279 return (!!(PQ_FLAGS_RLS & pq_flags)) *
280 ecore_init_qm_get_num_pf_rls(p_hwfn) +
281 (!!(PQ_FLAGS_MCOS & pq_flags)) *
282 ecore_init_qm_get_num_tcs(p_hwfn) +
283 (!!(PQ_FLAGS_LB & pq_flags)) +
284 (!!(PQ_FLAGS_OOO & pq_flags)) +
285 (!!(PQ_FLAGS_ACK & pq_flags)) +
286 (!!(PQ_FLAGS_OFLD & pq_flags)) +
287 (!!(PQ_FLAGS_VFS & pq_flags)) *
288 ecore_init_qm_get_num_vfs(p_hwfn);
291 /* initialize the top level QM params */
292 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
294 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
297 /* pq and vport bases for this PF */
298 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
299 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
301 /* rate limiting and weighted fair queueing are always enabled */
302 qm_info->vport_rl_en = 1;
303 qm_info->vport_wfq_en = 1;
305 /* TC config is different for AH 4 port */
306 four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
308 /* in AH 4 port we have fewer TCs per port */
309 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
312 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
315 if (!qm_info->ooo_tc)
316 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
320 /* initialize qm vport params */
321 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
323 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
326 /* all vports participate in weighted fair queueing */
327 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
328 qm_info->qm_vport_params[i].vport_wfq = 1;
331 /* initialize qm port params */
332 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
334 /* Initialize qm port parameters */
335 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
337 /* indicate how ooo and high pri traffic is dealt with */
338 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
339 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
341 for (i = 0; i < num_ports; i++) {
342 struct init_qm_port_params *p_qm_port =
343 &p_hwfn->qm_info.qm_port_params[i];
345 p_qm_port->active = 1;
346 p_qm_port->active_phys_tcs = active_phys_tcs;
347 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
348 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
352 /* Reset the params which must be reset for qm init. QM init may be called as
353 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
354 * params may be affected by the init but would simply recalculate to the same
355 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
356 * affected as these amounts stay the same.
358 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
360 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
362 qm_info->num_pqs = 0;
363 qm_info->num_vports = 0;
364 qm_info->num_pf_rls = 0;
365 qm_info->num_vf_pqs = 0;
366 qm_info->first_vf_pq = 0;
367 qm_info->first_mcos_pq = 0;
368 qm_info->first_rl_pq = 0;
371 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
373 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
375 qm_info->num_vports++;
377 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
379 "vport overflow! qm_info->num_vports %d,"
380 " qm_init_get_num_vports() %d\n",
382 ecore_init_qm_get_num_vports(p_hwfn));
385 /* initialize a single pq and manage qm_info resources accounting.
386 * The pq_init_flags param determines whether the PQ is rate limited
388 * and whether a new vport is allocated to the pq or not (i.e. vport will be
392 /* flags for pq init */
393 #define PQ_INIT_SHARE_VPORT (1 << 0)
394 #define PQ_INIT_PF_RL (1 << 1)
395 #define PQ_INIT_VF_RL (1 << 2)
397 /* defines for pq init */
398 #define PQ_INIT_DEFAULT_WRR_GROUP 1
399 #define PQ_INIT_DEFAULT_TC 0
400 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
402 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
403 struct ecore_qm_info *qm_info,
404 u8 tc, u32 pq_init_flags)
406 u16 pq_idx = qm_info->num_pqs, max_pq =
407 ecore_init_qm_get_num_pqs(p_hwfn);
411 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
414 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
416 qm_info->qm_pq_params[pq_idx].tc_id = tc;
417 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
418 qm_info->qm_pq_params[pq_idx].rl_valid =
419 (pq_init_flags & PQ_INIT_PF_RL ||
420 pq_init_flags & PQ_INIT_VF_RL);
422 /* qm params accounting */
424 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
425 qm_info->num_vports++;
427 if (pq_init_flags & PQ_INIT_PF_RL)
428 qm_info->num_pf_rls++;
430 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
432 "vport overflow! qm_info->num_vports %d,"
433 " qm_init_get_num_vports() %d\n",
435 ecore_init_qm_get_num_vports(p_hwfn));
437 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
438 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
439 " qm_init_get_num_pf_rls() %d\n",
441 ecore_init_qm_get_num_pf_rls(p_hwfn));
444 /* get pq index according to PQ_FLAGS */
445 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
448 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
450 /* Can't have multiple flags set here */
451 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
452 sizeof(pq_flags)) > 1)
457 return &qm_info->first_rl_pq;
459 return &qm_info->first_mcos_pq;
461 return &qm_info->pure_lb_pq;
463 return &qm_info->ooo_pq;
465 return &qm_info->pure_ack_pq;
467 return &qm_info->offload_pq;
469 return &qm_info->first_vf_pq;
475 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
479 /* save pq index in qm info */
480 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
481 u32 pq_flags, u16 pq_val)
483 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
485 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
488 /* get tx pq index, with the PQ TX base already set (ready for context init) */
489 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
491 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
493 return *base_pq_idx + CM_TX_PQ_BASE;
496 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
498 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
501 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
503 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
506 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
508 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
511 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
513 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
516 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
518 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
521 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
523 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
526 /* Functions for creating specific types of pqs */
527 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
529 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
531 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
534 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
535 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
538 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
540 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
542 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
545 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
546 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
549 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
551 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
553 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
556 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
557 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
560 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
562 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
564 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
567 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
568 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
571 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
573 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
576 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
579 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
580 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
581 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
584 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
586 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
587 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
589 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
592 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
594 qm_info->num_vf_pqs = num_vfs;
595 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
596 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
600 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
602 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
603 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
605 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
608 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
609 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
610 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
614 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
616 /* rate limited pqs, must come first (FW assumption) */
617 ecore_init_qm_rl_pqs(p_hwfn);
619 /* pqs for multi cos */
620 ecore_init_qm_mcos_pqs(p_hwfn);
622 /* pure loopback pq */
623 ecore_init_qm_lb_pq(p_hwfn);
625 /* out of order pq */
626 ecore_init_qm_ooo_pq(p_hwfn);
629 ecore_init_qm_pure_ack_pq(p_hwfn);
631 /* pq for offloaded protocol */
632 ecore_init_qm_offload_pq(p_hwfn);
634 /* done sharing vports */
635 ecore_init_qm_advance_vport(p_hwfn);
638 ecore_init_qm_vf_pqs(p_hwfn);
641 /* compare values of getters against resources amounts */
642 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
644 if (ecore_init_qm_get_num_vports(p_hwfn) >
645 RESC_NUM(p_hwfn, ECORE_VPORT)) {
646 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
650 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
651 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
655 return ECORE_SUCCESS;
659 * Function for verbose printing of the qm initialization results
661 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
663 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
664 struct init_qm_vport_params *vport;
665 struct init_qm_port_params *port;
666 struct init_qm_pq_params *pq;
669 /* top level params */
670 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
671 "qm init top level params: start_pq %d, start_vport %d,"
672 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
673 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
674 qm_info->offload_pq, qm_info->pure_ack_pq);
675 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
676 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
677 " num_vports %d, max_phys_tcs_per_port %d\n",
678 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
679 qm_info->num_vf_pqs, qm_info->num_vports,
680 qm_info->max_phys_tcs_per_port);
681 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
682 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
683 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
684 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
685 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
686 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
689 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
690 port = &qm_info->qm_port_params[i];
691 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
692 "port idx %d, active %d, active_phys_tcs %d,"
693 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
695 i, port->active, port->active_phys_tcs,
696 port->num_pbf_cmd_lines, port->num_btb_blocks,
701 for (i = 0; i < qm_info->num_vports; i++) {
702 vport = &qm_info->qm_vport_params[i];
703 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
704 "vport idx %d, vport_rl %d, wfq %d,"
705 " first_tx_pq_id [ ",
706 qm_info->start_vport + i, vport->vport_rl,
708 for (tc = 0; tc < NUM_OF_TCS; tc++)
709 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
710 vport->first_tx_pq_id[tc]);
711 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
715 for (i = 0; i < qm_info->num_pqs; i++) {
716 pq = &qm_info->qm_pq_params[i];
717 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
718 "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
720 qm_info->start_pq + i, pq->vport_id, pq->tc_id,
721 pq->wrr_group, pq->rl_valid);
725 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
727 /* reset params required for init run */
728 ecore_init_qm_reset_params(p_hwfn);
730 /* init QM top level params */
731 ecore_init_qm_params(p_hwfn);
733 /* init QM port params */
734 ecore_init_qm_port_params(p_hwfn);
736 /* init QM vport params */
737 ecore_init_qm_vport_params(p_hwfn);
739 /* init QM physical queue params */
740 ecore_init_qm_pq_params(p_hwfn);
742 /* display all that init */
743 ecore_dp_init_qm_params(p_hwfn);
746 /* This function reconfigures the QM pf on the fly.
747 * For this purpose we:
748 * 1. reconfigure the QM database
749 * 2. set new values to runtime array
750 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
751 * 4. activate init tool in QM_PF stage
752 * 5. send an sdm_qm_cmd through rbc interface to release the QM
754 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
755 struct ecore_ptt *p_ptt)
757 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
758 enum _ecore_status_t rc;
761 /* initialize ecore's qm data structure */
762 ecore_init_qm_info(p_hwfn);
764 /* stop PF's qm queues */
765 OSAL_SPIN_LOCK(&qm_lock);
766 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
767 qm_info->start_pq, qm_info->num_pqs);
768 OSAL_SPIN_UNLOCK(&qm_lock);
772 /* clear the QM_PF runtime phase leftovers from previous init */
773 ecore_init_clear_rt_data(p_hwfn);
775 /* prepare QM portion of runtime array */
776 ecore_qm_init_pf(p_hwfn);
778 /* activate init tool on runtime array */
779 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
780 p_hwfn->hw_info.hw_mode);
781 if (rc != ECORE_SUCCESS)
784 /* start PF's qm queues */
785 OSAL_SPIN_LOCK(&qm_lock);
786 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
787 qm_info->start_pq, qm_info->num_pqs);
788 OSAL_SPIN_UNLOCK(&qm_lock);
792 return ECORE_SUCCESS;
795 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
797 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
798 enum _ecore_status_t rc;
800 rc = ecore_init_qm_sanity(p_hwfn);
801 if (rc != ECORE_SUCCESS)
804 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
805 sizeof(struct init_qm_pq_params) *
806 ecore_init_qm_get_num_pqs(p_hwfn));
807 if (!qm_info->qm_pq_params)
810 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
811 sizeof(struct init_qm_vport_params) *
812 ecore_init_qm_get_num_vports(p_hwfn));
813 if (!qm_info->qm_vport_params)
816 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
817 sizeof(struct init_qm_port_params) *
818 p_hwfn->p_dev->num_ports_in_engines);
819 if (!qm_info->qm_port_params)
822 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
823 sizeof(struct ecore_wfq_data) *
824 ecore_init_qm_get_num_vports(p_hwfn));
825 if (!qm_info->wfq_data)
828 return ECORE_SUCCESS;
831 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
832 ecore_qm_info_free(p_hwfn);
835 /******************** End QM initialization ***************/
837 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
839 enum _ecore_status_t rc = ECORE_SUCCESS;
845 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
846 sizeof(*p_dev->fw_data));
850 for_each_hwfn(p_dev, i) {
851 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
852 u32 n_eqes, num_cons;
854 /* First allocate the context manager structure */
855 rc = ecore_cxt_mngr_alloc(p_hwfn);
859 /* Set the HW cid/tid numbers (in the contest manager)
860 * Must be done prior to any further computations.
862 rc = ecore_cxt_set_pf_params(p_hwfn);
866 rc = ecore_alloc_qm_data(p_hwfn);
871 ecore_init_qm_info(p_hwfn);
873 /* Compute the ILT client partition */
874 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
878 /* CID map / ILT shadow table / T2
879 * The talbes sizes are determined by the computations above
881 rc = ecore_cxt_tables_alloc(p_hwfn);
885 /* SPQ, must follow ILT because initializes SPQ context */
886 rc = ecore_spq_alloc(p_hwfn);
890 /* SP status block allocation */
891 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
894 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
898 rc = ecore_iov_alloc(p_hwfn);
903 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
904 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
905 /* Calculate the EQ size
906 * ---------------------
907 * Each ICID may generate up to one event at a time i.e.
908 * the event must be handled/cleared before a new one
909 * can be generated. We calculate the sum of events per
910 * protocol and create an EQ deep enough to handle the
912 * - Core - according to SPQ.
913 * - RoCE - per QP there are a couple of ICIDs, one
914 * responder and one requester, each can
915 * generate an EQE => n_eqes_qp = 2 * n_qp.
916 * Each CQ can generate an EQE. There are 2 CQs
917 * per QP => n_eqes_cq = 2 * n_qp.
918 * Hence the RoCE total is 4 * n_qp or
920 * - ENet - There can be up to two events per VF. One
921 * for VF-PF channel and another for VF FLR
922 * initial cleanup. The number of VFs is
923 * bounded by MAX_NUM_VFS_BB, and is much
924 * smaller than RoCE's so we avoid exact
927 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
929 ecore_cxt_get_proto_cid_count(
935 num_cons = ecore_cxt_get_proto_cid_count(
940 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
941 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
943 ecore_cxt_get_proto_cid_count(p_hwfn,
946 n_eqes += 2 * num_cons;
949 if (n_eqes > 0xFFFF) {
950 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
951 "The maximum of a u16 chain is 0x%x\n",
956 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
960 rc = ecore_consq_alloc(p_hwfn);
964 /* DMA info initialization */
965 rc = ecore_dmae_info_alloc(p_hwfn);
967 DP_NOTICE(p_hwfn, true,
968 "Failed to allocate memory for dmae_info"
973 /* DCBX initialization */
974 rc = ecore_dcbx_info_alloc(p_hwfn);
976 DP_NOTICE(p_hwfn, true,
977 "Failed to allocate memory for dcbx structure\n");
982 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
983 sizeof(*p_dev->reset_stats));
984 if (!p_dev->reset_stats) {
985 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
989 return ECORE_SUCCESS;
994 ecore_resc_free(p_dev);
998 void ecore_resc_setup(struct ecore_dev *p_dev)
1005 for_each_hwfn(p_dev, i) {
1006 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1008 ecore_cxt_mngr_setup(p_hwfn);
1009 ecore_spq_setup(p_hwfn);
1010 ecore_eq_setup(p_hwfn);
1011 ecore_consq_setup(p_hwfn);
1013 /* Read shadow of current MFW mailbox */
1014 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1015 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1016 p_hwfn->mcp_info->mfw_mb_cur,
1017 p_hwfn->mcp_info->mfw_mb_length);
1019 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1021 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1025 #define FINAL_CLEANUP_POLL_CNT (100)
1026 #define FINAL_CLEANUP_POLL_TIME (10)
1027 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1028 struct ecore_ptt *p_ptt,
1031 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1032 enum _ecore_status_t rc = ECORE_TIMEOUT;
1035 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1036 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1037 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1038 return ECORE_SUCCESS;
1042 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1043 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1048 command |= X_FINAL_CLEANUP_AGG_INT <<
1049 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1050 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1051 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1052 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1054 /* Make sure notification is not set before initiating final cleanup */
1056 if (REG_RD(p_hwfn, addr)) {
1057 DP_NOTICE(p_hwfn, false,
1058 "Unexpected; Found final cleanup notification");
1059 DP_NOTICE(p_hwfn, false,
1060 " before initiating final cleanup\n");
1061 REG_WR(p_hwfn, addr, 0);
1064 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1065 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1068 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1070 /* Poll until completion */
1071 while (!REG_RD(p_hwfn, addr) && count--)
1072 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1074 if (REG_RD(p_hwfn, addr))
1077 DP_NOTICE(p_hwfn, true,
1078 "Failed to receive FW final cleanup notification\n");
1080 /* Cleanup afterwards */
1081 REG_WR(p_hwfn, addr, 0);
1086 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1090 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1091 hw_mode |= 1 << MODE_BB;
1092 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1093 hw_mode |= 1 << MODE_K2;
1095 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1096 p_hwfn->p_dev->type);
1100 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1101 switch (p_hwfn->p_dev->num_ports_in_engines) {
1103 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1106 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1109 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1112 DP_NOTICE(p_hwfn, true,
1113 "num_ports_in_engine = %d not supported\n",
1114 p_hwfn->p_dev->num_ports_in_engines);
1118 switch (p_hwfn->p_dev->mf_mode) {
1119 case ECORE_MF_DEFAULT:
1121 hw_mode |= 1 << MODE_MF_SI;
1123 case ECORE_MF_OVLAN:
1124 hw_mode |= 1 << MODE_MF_SD;
1127 DP_NOTICE(p_hwfn, true,
1128 "Unsupported MF mode, init as DEFAULT\n");
1129 hw_mode |= 1 << MODE_MF_SI;
1133 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1134 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1135 hw_mode |= 1 << MODE_FPGA;
1137 if (p_hwfn->p_dev->b_is_emul_full)
1138 hw_mode |= 1 << MODE_EMUL_FULL;
1140 hw_mode |= 1 << MODE_EMUL_REDUCED;
1144 hw_mode |= 1 << MODE_ASIC;
1146 if (p_hwfn->p_dev->num_hwfns > 1)
1147 hw_mode |= 1 << MODE_100G;
1149 p_hwfn->hw_info.hw_mode = hw_mode;
1151 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1152 "Configuring function for hw_mode: 0x%08x\n",
1153 p_hwfn->hw_info.hw_mode);
1155 return ECORE_SUCCESS;
1159 /* MFW-replacement initializations for non-ASIC */
1160 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1161 struct ecore_ptt *p_ptt)
1163 struct ecore_dev *p_dev = p_hwfn->p_dev;
1167 if (CHIP_REV_IS_EMUL(p_dev)) {
1168 if (ECORE_IS_AH(p_dev))
1172 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1174 if (CHIP_REV_IS_EMUL(p_dev) &&
1175 (ECORE_IS_AH(p_dev)))
1176 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1179 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1180 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1181 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1182 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1184 if (CHIP_REV_IS_EMUL(p_dev)) {
1185 if (ECORE_IS_AH(p_dev)) {
1186 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1187 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1188 (p_dev->num_ports_in_engines >> 1));
1190 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1191 p_dev->num_ports_in_engines == 4 ? 0 : 3);
1196 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1197 for (i = 0; i < 100; i++) {
1199 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1203 DP_NOTICE(p_hwfn, true,
1204 "RBC done failed to complete in PSWRQ2\n");
1206 return ECORE_SUCCESS;
1210 /* Init run time data for all PFs and their VFs on an engine.
1211 * TBD - for VFs - Once we have parent PF info for each VF in
1212 * shmem available as CAU requires knowledge of parent PF for each VF.
1214 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1216 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1219 for_each_hwfn(p_dev, i) {
1220 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1221 struct ecore_igu_info *p_igu_info;
1222 struct ecore_igu_block *p_block;
1223 struct cau_sb_entry sb_entry;
1225 p_igu_info = p_hwfn->hw_info.p_igu_info;
1227 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1229 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1231 if (!p_block->is_pf)
1234 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1235 p_block->function_id, 0, 0);
1236 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1241 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1242 struct ecore_ptt *p_ptt,
1245 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1246 struct ecore_dev *p_dev = p_hwfn->p_dev;
1247 u8 vf_id, max_num_vfs;
1250 enum _ecore_status_t rc = ECORE_SUCCESS;
1252 ecore_init_cau_rt_data(p_dev);
1254 /* Program GTT windows */
1255 ecore_gtt_init(p_hwfn);
1258 if (CHIP_REV_IS_EMUL(p_dev)) {
1259 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1260 if (rc != ECORE_SUCCESS)
1265 if (p_hwfn->mcp_info) {
1266 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1267 qm_info->pf_rl_en = 1;
1268 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1269 qm_info->pf_wfq_en = 1;
1272 ecore_qm_common_rt_init(p_hwfn,
1273 p_dev->num_ports_in_engines,
1274 qm_info->max_phys_tcs_per_port,
1275 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1276 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1277 qm_info->qm_port_params);
1279 ecore_cxt_hw_init_common(p_hwfn);
1281 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1282 if (rc != ECORE_SUCCESS)
1285 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1286 * need to decide with which value, maybe runtime
1288 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1289 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1291 if (ECORE_IS_BB(p_dev)) {
1292 /* Workaround clears ROCE search for all functions to prevent
1293 * involving non initialized function in processing ROCE packet.
1295 num_pfs = NUM_OF_ENG_PFS(p_dev);
1296 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1297 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1298 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1299 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1301 /* pretend to original PF */
1302 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1305 /* Workaround for avoiding CCFC execution error when getting packets
1306 * with CRC errors, and allowing instead the invoking of the FW error
1308 * This is not done inside the init tool since it currently can't
1309 * perform a pretending to VFs.
1311 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1312 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1313 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1314 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1315 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1316 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1317 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1318 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1320 /* pretend to original PF */
1321 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1327 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1328 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1330 #define PMEG_IF_BYTE_COUNT 8
1332 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1333 struct ecore_ptt *p_ptt,
1334 u32 addr, u64 data, u8 reg_type, u8 port)
1336 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1337 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1338 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1339 (8 << PMEG_IF_BYTE_COUNT),
1340 (reg_type << 25) | (addr << 8) | port,
1341 (u32)((data >> 32) & 0xffffffff),
1342 (u32)(data & 0xffffffff));
1344 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1345 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1346 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1347 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1348 (reg_type << 25) | (addr << 8) | port);
1349 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1350 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1351 (data >> 32) & 0xffffffff);
1354 #define XLPORT_MODE_REG (0x20a)
1355 #define XLPORT_MAC_CONTROL (0x210)
1356 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1357 #define XLPORT_ENABLE_REG (0x20b)
1359 #define XLMAC_CTRL (0x600)
1360 #define XLMAC_MODE (0x601)
1361 #define XLMAC_RX_MAX_SIZE (0x608)
1362 #define XLMAC_TX_CTRL (0x604)
1363 #define XLMAC_PAUSE_CTRL (0x60d)
1364 #define XLMAC_PFC_CTRL (0x60e)
1366 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1367 struct ecore_ptt *p_ptt)
1369 u8 loopback = 0, port = p_hwfn->port_id * 2;
1371 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1373 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1374 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1376 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1377 /* XLMAC: SOFT RESET */
1378 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1379 /* XLMAC: Port Speed >= 10Gbps */
1380 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1381 /* XLMAC: Max Size */
1382 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1383 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1384 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1386 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1387 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1388 0x30ffffc000ULL, 0, port);
1389 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1390 port); /* XLMAC: TX_EN, RX_EN */
1391 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1392 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1393 0x1003 | (loopback << 2), 0, port);
1394 /* Enabled Parallel PFC interface */
1395 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1397 /* XLPORT port enable */
1398 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1401 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1402 struct ecore_ptt *p_ptt)
1404 u8 port = p_hwfn->port_id;
1405 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1407 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1409 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1410 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1412 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1413 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1415 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1416 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1418 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1419 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1421 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1422 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1424 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1425 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1427 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1429 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1431 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1433 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1437 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1438 struct ecore_ptt *p_ptt)
1440 if (ECORE_IS_AH(p_hwfn->p_dev))
1441 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1443 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1446 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1447 struct ecore_ptt *p_ptt, u8 port)
1449 int port_offset = port ? 0x800 : 0;
1450 u32 xmac_rxctrl = 0;
1453 /* FIXME: move to common start */
1454 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1455 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1457 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1458 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1460 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1462 /* Set the number of ports on the Warp Core to 10G */
1463 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1465 /* Soft reset of XMAC */
1466 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1467 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1469 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1470 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1472 /* FIXME: move to common end */
1473 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1474 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1476 /* Set Max packet size: initialize XMAC block register for port 0 */
1477 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1479 /* CRC append for Tx packets: init XMAC block register for port 1 */
1480 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1482 /* Enable TX and RX: initialize XMAC block register for port 1 */
1483 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1484 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1485 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1486 XMAC_REG_RX_CTRL_BB + port_offset);
1487 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1488 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1492 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1493 struct ecore_ptt *p_ptt,
1496 enum _ecore_status_t rc = ECORE_SUCCESS;
1498 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1500 if (rc != ECORE_SUCCESS)
1503 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1504 return ECORE_SUCCESS;
1506 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1507 if (ECORE_IS_AH(p_hwfn->p_dev))
1508 return ECORE_SUCCESS;
1509 else if (ECORE_IS_BB(p_hwfn->p_dev))
1510 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1511 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1512 if (p_hwfn->p_dev->num_hwfns > 1) {
1513 /* Activate OPTE in CMT */
1516 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1518 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1519 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1520 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1521 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1522 ecore_wr(p_hwfn, p_ptt,
1523 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1524 ecore_wr(p_hwfn, p_ptt,
1525 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1526 ecore_wr(p_hwfn, p_ptt,
1527 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1531 ecore_emul_link_init(p_hwfn, p_ptt);
1533 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1540 static enum _ecore_status_t
1541 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1542 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1544 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1545 u32 dpi_bit_shift, dpi_count;
1548 /* Calculate DPI size
1549 * ------------------
1550 * The PWM region contains Doorbell Pages. The first is reserverd for
1551 * the kernel for, e.g, L2. The others are free to be used by non-
1552 * trusted applications, typically from user space. Each page, called a
1553 * doorbell page is sectioned into windows that allow doorbells to be
1554 * issued in parallel by the kernel/application. The size of such a
1555 * window (a.k.a. WID) is 1kB.
1557 * 1kB WID x N WIDS = DPI page size
1558 * DPI page size x N DPIs = PWM region size
1560 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1561 * in order to ensure that two applications won't share the same page.
1562 * It also must contain at least one WID per CPU to allow parallelism.
1563 * It also must be a power of 2, since it is stored as a bit shift.
1565 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1566 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1567 * containing 4 WIDs.
1569 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1570 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1571 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1572 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1573 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1575 dpi_count = pwm_region_size / dpi_page_size;
1577 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1578 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1581 p_hwfn->dpi_size = dpi_page_size;
1582 p_hwfn->dpi_count = dpi_count;
1584 /* Update registers */
1585 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1587 if (dpi_count < min_dpis)
1588 return ECORE_NORESOURCES;
1590 return ECORE_SUCCESS;
1593 enum ECORE_ROCE_EDPM_MODE {
1594 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1595 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1596 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1599 static enum _ecore_status_t
1600 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1601 struct ecore_ptt *p_ptt)
1603 u32 pwm_regsize, norm_regsize;
1604 u32 non_pwm_conn, min_addr_reg1;
1605 u32 db_bar_size, n_cpus;
1608 int rc = ECORE_SUCCESS;
1611 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1612 if (p_hwfn->p_dev->num_hwfns > 1)
1615 /* Calculate doorbell regions
1616 * -----------------------------------
1617 * The doorbell BAR is made of two regions. The first is called normal
1618 * region and the second is called PWM region. In the normal region
1619 * each ICID has its own set of addresses so that writing to that
1620 * specific address identifies the ICID. In the Process Window Mode
1621 * region the ICID is given in the data written to the doorbell. The
1622 * above per PF register denotes the offset in the doorbell BAR in which
1623 * the PWM region begins.
1624 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1625 * non-PWM connection. The calculation below computes the total non-PWM
1626 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1627 * in units of 4,096 bytes.
1629 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1630 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1632 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1633 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1634 min_addr_reg1 = norm_regsize / 4096;
1635 pwm_regsize = db_bar_size - norm_regsize;
1637 /* Check that the normal and PWM sizes are valid */
1638 if (db_bar_size < norm_regsize) {
1639 DP_ERR(p_hwfn->p_dev,
1640 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1641 db_bar_size, norm_regsize);
1642 return ECORE_NORESOURCES;
1644 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1645 DP_ERR(p_hwfn->p_dev,
1646 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1647 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1649 return ECORE_NORESOURCES;
1652 /* Calculate number of DPIs */
1653 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1654 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1655 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1656 /* Either EDPM is mandatory, or we are attempting to allocate a
1659 n_cpus = OSAL_NUM_ACTIVE_CPU();
1660 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1663 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1664 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1665 if (cond || p_hwfn->dcbx_no_edpm) {
1666 /* Either EDPM is disabled from user configuration, or it is
1667 * disabled via DCBx, or it is not mandatory and we failed to
1668 * allocated a WID per CPU.
1671 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1673 /* If we entered this flow due to DCBX then the DPM register is
1674 * already configured.
1679 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1680 norm_regsize, pwm_regsize);
1682 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1683 p_hwfn->dpi_size, p_hwfn->dpi_count,
1684 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1685 "disabled" : "enabled");
1687 /* Check return codes from above calls */
1690 "Failed to allocate enough DPIs\n");
1691 return ECORE_NORESOURCES;
1695 p_hwfn->dpi_start_offset = norm_regsize;
1697 /* Update registers */
1698 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1699 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1700 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1701 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1703 return ECORE_SUCCESS;
1706 static enum _ecore_status_t
1707 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1708 struct ecore_ptt *p_ptt,
1709 struct ecore_tunnel_info *p_tunn,
1712 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1714 u8 rel_pf_id = p_hwfn->rel_pf_id;
1716 enum _ecore_status_t rc = ECORE_SUCCESS;
1720 if (p_hwfn->mcp_info) {
1721 struct ecore_mcp_function_info *p_info;
1723 p_info = &p_hwfn->mcp_info->func_info;
1724 if (p_info->bandwidth_min)
1725 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1727 /* Update rate limit once we'll actually have a link */
1728 p_hwfn->qm_info.pf_rl = 100000;
1730 ecore_cxt_hw_init_pf(p_hwfn);
1732 ecore_int_igu_init_rt(p_hwfn);
1734 /* Set VLAN in NIG if needed */
1735 if (hw_mode & (1 << MODE_MF_SD)) {
1736 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1737 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1738 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1739 p_hwfn->hw_info.ovlan);
1742 /* Enable classification by MAC if needed */
1743 if (hw_mode & (1 << MODE_MF_SI)) {
1744 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1745 "Configuring TAGMAC_CLS_TYPE\n");
1746 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1750 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1751 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1752 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1753 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1754 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1755 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1757 /* perform debug configuration when chip is out of reset */
1758 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1760 /* Cleanup chip from previous driver if such remains exist */
1761 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1762 if (rc != ECORE_SUCCESS) {
1763 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1767 /* PF Init sequence */
1768 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1772 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1773 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1777 /* Pure runtime initializations - directly to the HW */
1778 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1780 /* PCI relaxed ordering causes a decrease in the performance on some
1781 * systems. Till a root cause is found, disable this attribute in the
1785 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1787 * DP_NOTICE(p_hwfn, true,
1788 * "Failed to find the PCIe Cap\n");
1791 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1792 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1793 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1796 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1800 /* enable interrupts */
1801 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1802 if (rc != ECORE_SUCCESS)
1805 /* send function start command */
1806 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1807 allow_npar_tx_switch);
1809 DP_NOTICE(p_hwfn, true,
1810 "Function start ramrod failed\n");
1812 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1813 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1814 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1816 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1817 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1819 ecore_wr(p_hwfn, p_ptt,
1820 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1823 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1824 "PRS_REG_SEARCH registers after start PFn\n");
1825 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1826 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1827 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1828 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1829 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1830 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1831 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1832 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1833 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1834 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1835 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1836 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1837 prs_reg = ecore_rd(p_hwfn, p_ptt,
1838 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1839 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1840 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1842 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1843 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1844 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1850 static enum _ecore_status_t
1851 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1852 struct ecore_ptt *p_ptt, u8 enable)
1854 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1856 /* Change PF in PXP */
1857 ecore_wr(p_hwfn, p_ptt,
1858 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1860 /* wait until value is set - try for 1 second every 50us */
1861 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1862 val = ecore_rd(p_hwfn, p_ptt,
1863 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1870 if (val != set_val) {
1871 DP_NOTICE(p_hwfn, true,
1872 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1873 return ECORE_UNKNOWN_ERROR;
1876 return ECORE_SUCCESS;
1879 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1880 struct ecore_ptt *p_main_ptt)
1882 /* Read shadow of current MFW mailbox */
1883 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1884 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1885 p_hwfn->mcp_info->mfw_mb_cur,
1886 p_hwfn->mcp_info->mfw_mb_length);
1889 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1890 struct ecore_hw_init_params *p_params)
1892 if (p_params->p_tunn) {
1893 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1894 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1897 p_hwfn->b_int_enabled = 1;
1899 return ECORE_SUCCESS;
1902 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1903 struct ecore_hw_init_params *p_params)
1905 struct ecore_load_req_params load_req_params;
1906 u32 load_code, param, drv_mb_param;
1907 struct ecore_hwfn *p_hwfn;
1908 bool b_default_mtu = true;
1909 enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1912 if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1913 (p_dev->num_hwfns > 1)) {
1914 DP_NOTICE(p_dev, false,
1915 "MSI mode is not supported for CMT devices\n");
1920 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1921 if (rc != ECORE_SUCCESS)
1925 for_each_hwfn(p_dev, i) {
1926 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1928 /* If management didn't provide a default, set one of our own */
1929 if (!p_hwfn->hw_info.mtu) {
1930 p_hwfn->hw_info.mtu = 1500;
1931 b_default_mtu = false;
1935 ecore_vf_start(p_hwfn, p_params);
1939 /* Enable DMAE in PXP */
1940 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1941 if (rc != ECORE_SUCCESS)
1944 rc = ecore_calc_hw_mode(p_hwfn);
1945 if (rc != ECORE_SUCCESS)
1948 OSAL_MEM_ZERO(&load_req_params, sizeof(load_req_params));
1949 load_req_params.drv_role = p_params->is_crash_kernel ?
1950 ECORE_DRV_ROLE_KDUMP :
1952 load_req_params.timeout_val = p_params->mfw_timeout_val;
1953 load_req_params.avoid_eng_reset = p_params->avoid_eng_reset;
1954 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1956 if (rc != ECORE_SUCCESS) {
1957 DP_NOTICE(p_hwfn, true,
1958 "Failed sending a LOAD_REQ command\n");
1962 load_code = load_req_params.load_code;
1963 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1964 "Load request was sent. Load code: 0x%x\n",
1968 * When coming back from hiberbate state, the registers from
1969 * which shadow is read initially are not initialized. It turns
1970 * out that these registers get initialized during the call to
1971 * ecore_mcp_load_req request. So we need to reread them here
1972 * to get the proper shadow register value.
1973 * Note: This is a workaround for the missing MFW
1974 * initialization. It may be removed once the implementation
1977 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1979 /* Only relevant for recovery:
1980 * Clear the indication after the LOAD_REQ command is responded
1983 p_dev->recov_in_prog = false;
1985 p_hwfn->first_on_engine = (load_code ==
1986 FW_MSG_CODE_DRV_LOAD_ENGINE);
1988 if (!qm_lock_init) {
1989 OSAL_SPIN_LOCK_INIT(&qm_lock);
1990 qm_lock_init = true;
1993 switch (load_code) {
1994 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1995 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1996 p_hwfn->hw_info.hw_mode);
1997 if (rc != ECORE_SUCCESS)
2000 case FW_MSG_CODE_DRV_LOAD_PORT:
2001 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2002 p_hwfn->hw_info.hw_mode);
2003 if (rc != ECORE_SUCCESS)
2006 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2007 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2009 p_hwfn->hw_info.hw_mode,
2010 p_params->b_hw_start,
2012 p_params->allow_npar_tx_switch);
2015 DP_NOTICE(p_hwfn, false,
2016 "Unexpected load code [0x%08x]", load_code);
2021 if (rc != ECORE_SUCCESS)
2022 DP_NOTICE(p_hwfn, true,
2023 "init phase failed for loadcode 0x%x (rc %d)\n",
2026 /* ACK mfw regardless of success or failure of initialization */
2027 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2028 DRV_MSG_CODE_LOAD_DONE,
2029 0, &load_code, ¶m);
2030 if (rc != ECORE_SUCCESS)
2033 if (mfw_rc != ECORE_SUCCESS) {
2034 DP_NOTICE(p_hwfn, true,
2035 "Failed sending LOAD_DONE command\n");
2039 /* send DCBX attention request command */
2040 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2041 "sending phony dcbx set command to trigger DCBx attention handling\n");
2042 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2043 DRV_MSG_CODE_SET_DCBX,
2044 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2045 &load_code, ¶m);
2046 if (mfw_rc != ECORE_SUCCESS) {
2047 DP_NOTICE(p_hwfn, true,
2048 "Failed to send DCBX attention request\n");
2052 p_hwfn->hw_init_done = true;
2056 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2057 drv_mb_param = STORM_FW_VERSION;
2058 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2059 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2060 drv_mb_param, &load_code, ¶m);
2061 if (rc != ECORE_SUCCESS)
2062 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2065 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2066 p_hwfn->hw_info.mtu);
2067 if (rc != ECORE_SUCCESS)
2068 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2070 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2072 ECORE_OV_DRIVER_STATE_DISABLED);
2073 if (rc != ECORE_SUCCESS)
2074 DP_INFO(p_hwfn, "Failed to update driver state\n");
2080 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2081 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2082 struct ecore_hwfn *p_hwfn,
2083 struct ecore_ptt *p_ptt)
2088 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2089 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2090 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2092 if ((!ecore_rd(p_hwfn, p_ptt,
2093 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2094 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2097 /* Dependent on number of connection/tasks, possibly
2098 * 1ms sleep is required between polls
2103 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2106 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2107 " [Connection %02x Tasks %02x]\n",
2108 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2109 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2112 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2116 for_each_hwfn(p_dev, j) {
2117 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2118 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2120 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2124 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2126 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
2129 for_each_hwfn(p_dev, j) {
2130 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2131 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2133 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2136 ecore_vf_pf_int_cleanup(p_hwfn);
2140 /* mark the hw as uninitialized... */
2141 p_hwfn->hw_init_done = false;
2143 rc = ecore_sp_pf_stop(p_hwfn);
2145 DP_NOTICE(p_hwfn, true,
2146 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
2148 /* perform debug action after PF stop was sent */
2149 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
2151 /* close NIG to BRB gate */
2152 ecore_wr(p_hwfn, p_ptt,
2153 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2156 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2157 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2158 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2159 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2160 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2162 /* @@@TBD - clean transmission queues (5.b) */
2163 /* @@@TBD - clean BTB (5.c) */
2165 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2167 /* @@@TBD - verify DMAE requests are done (8) */
2169 /* Disable Attention Generation */
2170 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2171 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2172 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2173 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2174 /* Need to wait 1ms to guarantee SBs are cleared */
2179 /* Disable DMAE in PXP - in CMT, this should only be done for
2180 * first hw-function, and only after all transactions have
2181 * stopped for all active hw-functions.
2183 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
2184 p_dev->hwfns[0].p_main_ptt, false);
2185 if (t_rc != ECORE_SUCCESS)
2192 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2196 for_each_hwfn(p_dev, j) {
2197 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2198 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2201 ecore_vf_pf_int_cleanup(p_hwfn);
2205 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2206 "Shutting down the fastpath\n");
2208 ecore_wr(p_hwfn, p_ptt,
2209 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2211 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2212 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2213 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2214 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2215 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2217 /* @@@TBD - clean transmission queues (5.b) */
2218 /* @@@TBD - clean BTB (5.c) */
2220 /* @@@TBD - verify DMAE requests are done (8) */
2222 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2223 /* Need to wait 1ms to guarantee SBs are cleared */
2228 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2230 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2232 if (IS_VF(p_hwfn->p_dev))
2235 /* If roce info is allocated it means roce is initialized and should
2236 * be enabled in searcher.
2238 if (p_hwfn->p_rdma_info) {
2239 if (p_hwfn->b_rdma_enabled_in_prs)
2240 ecore_wr(p_hwfn, p_ptt,
2241 p_hwfn->rdma_prs_search_reg, 0x1);
2242 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2245 /* Re-open incoming traffic */
2246 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2247 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2250 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
2251 struct ecore_ptt *p_ptt, u32 reg,
2254 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
2256 if (assert_val != expected) {
2257 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
2259 return ECORE_UNKNOWN_ERROR;
2265 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
2267 enum _ecore_status_t rc = ECORE_SUCCESS;
2268 u32 unload_resp, unload_param;
2271 for_each_hwfn(p_dev, i) {
2272 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2275 rc = ecore_vf_pf_reset(p_hwfn);
2281 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
2283 /* Check for incorrect states */
2284 if (!p_dev->recov_in_prog) {
2285 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2286 QM_REG_USG_CNT_PF_TX, 0);
2287 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2288 QM_REG_USG_CNT_PF_OTHER, 0);
2289 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2292 /* Disable PF in HW blocks */
2293 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2294 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2296 if (p_dev->recov_in_prog) {
2297 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2298 "Recovery is in progress -> skip sending unload_req/done\n");
2302 /* Send unload command to MCP */
2303 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2304 DRV_MSG_CODE_UNLOAD_REQ,
2305 DRV_MB_PARAM_UNLOAD_WOL_MCP,
2306 &unload_resp, &unload_param);
2307 if (rc != ECORE_SUCCESS) {
2308 DP_NOTICE(p_hwfn, true,
2309 "ecore_hw_reset: UNLOAD_REQ failed\n");
2310 /* @@TBD - what to do? for now, assume ENG. */
2311 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2314 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2315 DRV_MSG_CODE_UNLOAD_DONE,
2316 0, &unload_resp, &unload_param);
2317 if (rc != ECORE_SUCCESS) {
2319 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2320 /* @@@TBD - Should it really ASSERT here ? */
2328 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2329 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2331 ecore_ptt_pool_free(p_hwfn);
2332 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2335 /* Setup bar access */
2336 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2338 /* clear indirect access */
2339 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2340 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2341 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2342 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2343 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2344 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2345 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2346 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2347 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2349 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2350 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2351 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2352 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2353 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2354 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2355 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2356 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2359 /* Clean Previous errors if such exist */
2360 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2361 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2363 /* enable internal target-read */
2364 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2365 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2368 static void get_function_id(struct ecore_hwfn *p_hwfn)
2371 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2372 PXP_PF_ME_OPAQUE_ADDR);
2374 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2376 /* Bits 16-19 from the ME registers are the pf_num */
2377 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2378 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2379 PXP_CONCRETE_FID_PFID);
2380 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2381 PXP_CONCRETE_FID_PORT);
2383 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2384 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2385 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2388 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2390 u32 *feat_num = p_hwfn->hw_info.feat_num;
2391 struct ecore_sb_cnt_info sb_cnt_info;
2392 int num_features = 1;
2394 /* L2 Queues require each: 1 status block. 1 L2 queue */
2395 feat_num[ECORE_PF_L2_QUE] =
2397 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2398 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2400 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2401 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2402 feat_num[ECORE_VF_L2_QUE] =
2404 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2405 FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2406 sb_cnt_info.sb_iov_cnt);
2408 feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2409 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2410 feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2411 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2413 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2414 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2415 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2416 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2417 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2418 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2419 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2420 RESC_NUM(p_hwfn, ECORE_SB));
2423 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2428 case ECORE_L2_QUEUE:
2442 case ECORE_RDMA_CNQ_RAM:
2443 return "RDMA_CNQ_RAM";
2446 case ECORE_LL2_QUEUE:
2448 case ECORE_CMDQS_CQS:
2450 case ECORE_RDMA_STATS_QUEUE:
2451 return "RDMA_STATS_QUEUE";
2455 return "UNKNOWN_RESOURCE";
2459 static enum _ecore_status_t
2460 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2461 enum ecore_resources res_id, u32 resc_max_val,
2464 enum _ecore_status_t rc;
2466 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_hwfn->p_main_ptt, res_id,
2467 resc_max_val, p_mcp_resp);
2468 if (rc != ECORE_SUCCESS) {
2469 DP_NOTICE(p_hwfn, true,
2470 "MFW response failure for a max value setting of resource %d [%s]\n",
2471 res_id, ecore_hw_get_resc_name(res_id));
2475 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2477 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2478 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2480 return ECORE_SUCCESS;
2483 static enum _ecore_status_t
2484 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn)
2486 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2487 u32 resc_max_val, mcp_resp;
2489 enum _ecore_status_t rc;
2491 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2494 case ECORE_LL2_QUEUE:
2495 case ECORE_RDMA_CNQ_RAM:
2496 case ECORE_RDMA_STATS_QUEUE:
2504 rc = __ecore_hw_set_soft_resc_size(p_hwfn, res_id,
2505 resc_max_val, &mcp_resp);
2506 if (rc != ECORE_SUCCESS)
2509 /* There's no point to continue to the next resource if the
2510 * command is not supported by the MFW.
2511 * We do continue if the command is supported but the resource
2512 * is unknown to the MFW. Such a resource will be later
2513 * configured with the default allocation values.
2515 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2516 return ECORE_NOTIMPL;
2519 return ECORE_SUCCESS;
2523 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2524 enum ecore_resources res_id,
2525 u32 *p_resc_num, u32 *p_resc_start)
2527 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2528 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2529 struct ecore_sb_cnt_info sb_cnt_info;
2533 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2534 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2535 *p_resc_num = sb_cnt_info.sb_cnt;
2537 case ECORE_L2_QUEUE:
2538 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2539 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2542 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2543 MAX_NUM_VPORTS_BB) / num_funcs;
2546 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2547 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2550 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2551 MAX_QM_TX_QUEUES_BB) / num_funcs;
2554 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2558 /* Each VFC resource can accommodate both a MAC and a VLAN */
2559 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2562 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2563 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2565 case ECORE_LL2_QUEUE:
2566 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2568 case ECORE_RDMA_CNQ_RAM:
2569 case ECORE_CMDQS_CQS:
2570 /* CNQ/CMDQS are the same resource */
2572 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2574 case ECORE_RDMA_STATS_QUEUE:
2576 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2577 MAX_NUM_VPORTS_BB) / num_funcs;
2594 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2598 return ECORE_SUCCESS;
2601 static enum _ecore_status_t
2602 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
2603 bool drv_resc_alloc)
2605 u32 dflt_resc_num = 0, dflt_resc_start = 0;
2606 u32 mcp_resp, *p_resc_num, *p_resc_start;
2607 enum _ecore_status_t rc;
2609 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2610 p_resc_start = &RESC_START(p_hwfn, res_id);
2612 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2614 if (rc != ECORE_SUCCESS) {
2616 "Failed to get default amount for resource %d [%s]\n",
2617 res_id, ecore_hw_get_resc_name(res_id));
2622 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2623 *p_resc_num = dflt_resc_num;
2624 *p_resc_start = dflt_resc_start;
2629 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2630 &mcp_resp, p_resc_num, p_resc_start);
2631 if (rc != ECORE_SUCCESS) {
2632 DP_NOTICE(p_hwfn, true,
2633 "MFW response failure for an allocation request for"
2634 " resource %d [%s]\n",
2635 res_id, ecore_hw_get_resc_name(res_id));
2639 /* Default driver values are applied in the following cases:
2640 * - The resource allocation MB command is not supported by the MFW
2641 * - There is an internal error in the MFW while processing the request
2642 * - The resource ID is unknown to the MFW
2644 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2646 "Failed to receive allocation info for resource %d [%s]."
2647 " mcp_resp = 0x%x. Applying default values"
2649 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2650 dflt_resc_num, dflt_resc_start);
2652 *p_resc_num = dflt_resc_num;
2653 *p_resc_start = dflt_resc_start;
2657 /* TBD - remove this when revising the handling of the SB resource */
2658 if (res_id == ECORE_SB) {
2659 /* Excluding the slowpath SB */
2661 *p_resc_start -= p_hwfn->enabled_func_idx;
2664 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2666 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
2667 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2668 *p_resc_start, dflt_resc_num, dflt_resc_start,
2669 drv_resc_alloc ? " - Applying default values" : "");
2670 if (drv_resc_alloc) {
2671 *p_resc_num = dflt_resc_num;
2672 *p_resc_start = dflt_resc_start;
2676 return ECORE_SUCCESS;
2679 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2680 bool drv_resc_alloc)
2682 enum _ecore_status_t rc;
2685 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2686 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2687 if (rc != ECORE_SUCCESS)
2691 return ECORE_SUCCESS;
2694 #define ECORE_RESC_ALLOC_LOCK_RETRY_CNT 10
2695 #define ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US 10000 /* 10 msec */
2697 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2698 bool drv_resc_alloc)
2700 struct ecore_resc_unlock_params resc_unlock_params;
2701 struct ecore_resc_lock_params resc_lock_params;
2702 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2704 enum _ecore_status_t rc;
2706 u32 *resc_start = p_hwfn->hw_info.resc_start;
2707 u32 *resc_num = p_hwfn->hw_info.resc_num;
2708 /* For AH, an equal share of the ILT lines between the maximal number of
2709 * PFs is not enough for RoCE. This would be solved by the future
2710 * resource allocation scheme, but isn't currently present for
2711 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2712 * to work - the BB number of ILT lines divided by its max PFs number.
2714 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2717 /* Setting the max values of the soft resources and the following
2718 * resources allocation queries should be atomic. Since several PFs can
2719 * run in parallel - a resource lock is needed.
2720 * If either the resource lock or resource set value commands are not
2721 * supported - skip the the max values setting, release the lock if
2722 * needed, and proceed to the queries. Other failures, including a
2723 * failure to acquire the lock, will cause this function to fail.
2724 * Old drivers that don't acquire the lock can run in parallel, and
2725 * their allocation values won't be affected by the updated max values.
2727 OSAL_MEM_ZERO(&resc_lock_params, sizeof(resc_lock_params));
2728 resc_lock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2729 resc_lock_params.retry_num = ECORE_RESC_ALLOC_LOCK_RETRY_CNT;
2730 resc_lock_params.retry_interval = ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2731 resc_lock_params.sleep_b4_retry = true;
2732 OSAL_MEM_ZERO(&resc_unlock_params, sizeof(resc_unlock_params));
2733 resc_unlock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2735 rc = ecore_mcp_resc_lock(p_hwfn, p_hwfn->p_main_ptt, &resc_lock_params);
2736 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2738 } else if (rc == ECORE_NOTIMPL) {
2740 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2741 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
2742 DP_NOTICE(p_hwfn, false,
2743 "Failed to acquire the resource lock for the resource allocation commands\n");
2745 goto unlock_and_exit;
2747 rc = ecore_hw_set_soft_resc_size(p_hwfn);
2748 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2749 DP_NOTICE(p_hwfn, false,
2750 "Failed to set the max values of the soft resources\n");
2751 goto unlock_and_exit;
2752 } else if (rc == ECORE_NOTIMPL) {
2754 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2755 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2756 &resc_unlock_params);
2757 if (rc != ECORE_SUCCESS)
2759 "Failed to release the resource lock for the resource allocation commands\n");
2763 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
2764 if (rc != ECORE_SUCCESS)
2765 goto unlock_and_exit;
2767 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2768 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2769 &resc_unlock_params);
2770 if (rc != ECORE_SUCCESS)
2772 "Failed to release the resource lock for the resource allocation commands\n");
2776 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2777 /* Reduced build contains less PQs */
2778 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2779 resc_num[ECORE_PQ] = 32;
2780 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2781 p_hwfn->enabled_func_idx;
2784 /* For AH emulation, since we have a possible maximal number of
2785 * 16 enabled PFs, in case there are not enough ILT lines -
2786 * allocate only first PF as RoCE and have all the other ETH
2787 * only with less ILT lines.
2789 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2790 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2791 resc_num[ECORE_ILT],
2792 roce_min_ilt_lines);
2795 /* Correct the common ILT calculation if PF0 has more */
2796 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2797 p_hwfn->p_dev->b_is_emul_full &&
2798 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2799 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2800 resc_num[ECORE_ILT];
2803 /* Sanity for ILT */
2804 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2805 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2806 DP_NOTICE(p_hwfn, true,
2807 "Can't assign ILT pages [%08x,...,%08x]\n",
2808 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2814 ecore_hw_set_feat(p_hwfn);
2816 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2817 "The numbers for each resource are:\n");
2818 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2819 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2820 ecore_hw_get_resc_name(res_id),
2821 RESC_NUM(p_hwfn, res_id),
2822 RESC_START(p_hwfn, res_id));
2824 return ECORE_SUCCESS;
2827 ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt, &resc_unlock_params);
2831 static enum _ecore_status_t
2832 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2833 struct ecore_ptt *p_ptt,
2834 struct ecore_hw_prepare_params *p_params)
2836 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2837 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2838 struct ecore_mcp_link_params *link;
2839 enum _ecore_status_t rc;
2841 /* Read global nvm_cfg address */
2842 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2844 /* Verify MCP has initialized it */
2845 if (!nvm_cfg_addr) {
2846 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2847 if (p_params->b_relaxed_probe)
2848 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2852 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2854 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2856 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2857 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2860 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2862 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2863 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2864 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2865 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2867 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2868 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2870 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2871 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2873 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2874 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2876 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2877 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2879 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2880 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2882 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2883 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2885 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2886 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2888 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2889 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2891 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2892 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2894 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2895 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2898 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2903 /* Read DCBX configuration */
2904 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2905 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2906 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2908 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2909 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2910 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2911 switch (dcbx_mode) {
2912 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2913 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2915 case NVM_CFG1_PORT_DCBX_MODE_CEE:
2916 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2918 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2919 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2922 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2925 /* Read default link configuration */
2926 link = &p_hwfn->mcp_info->link_input;
2927 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2928 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2929 link_temp = ecore_rd(p_hwfn, p_ptt,
2931 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2932 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2933 link->speed.advertised_speeds = link_temp;
2935 link_temp = link->speed.advertised_speeds;
2936 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2938 link_temp = ecore_rd(p_hwfn, p_ptt,
2940 OFFSETOF(struct nvm_cfg1_port, link_settings));
2941 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2942 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2943 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2944 link->speed.autoneg = true;
2946 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2947 link->speed.forced_speed = 1000;
2949 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2950 link->speed.forced_speed = 10000;
2952 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2953 link->speed.forced_speed = 25000;
2955 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2956 link->speed.forced_speed = 40000;
2958 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2959 link->speed.forced_speed = 50000;
2961 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2962 link->speed.forced_speed = 100000;
2965 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2968 p_hwfn->mcp_info->link_capabilities.default_speed =
2969 link->speed.forced_speed;
2970 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2971 link->speed.autoneg;
2973 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2974 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2975 link->pause.autoneg = !!(link_temp &
2976 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2977 link->pause.forced_rx = !!(link_temp &
2978 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2979 link->pause.forced_tx = !!(link_temp &
2980 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2981 link->loopback_mode = 0;
2983 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2984 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2985 link->speed.forced_speed, link->speed.advertised_speeds,
2986 link->speed.autoneg, link->pause.autoneg);
2988 /* Read Multi-function information from shmem */
2989 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2990 OFFSETOF(struct nvm_cfg1, glob) +
2991 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2993 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2995 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2996 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2999 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3000 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3002 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3003 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3005 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3006 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3009 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3010 p_hwfn->p_dev->mf_mode);
3012 /* Read Multi-function information from shmem */
3013 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3014 OFFSETOF(struct nvm_cfg1, glob) +
3015 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3017 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3018 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3019 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3020 &p_hwfn->hw_info.device_capabilities);
3021 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3022 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3023 &p_hwfn->hw_info.device_capabilities);
3024 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3025 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3026 &p_hwfn->hw_info.device_capabilities);
3027 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3028 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3029 &p_hwfn->hw_info.device_capabilities);
3030 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3031 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3032 &p_hwfn->hw_info.device_capabilities);
3034 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3035 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3037 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3043 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3044 struct ecore_ptt *p_ptt)
3046 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3047 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3048 struct ecore_dev *p_dev = p_hwfn->p_dev;
3050 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3052 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3053 * in the other bits are selected.
3054 * Bits 1-15 are for functions 1-15, respectively, and their value is
3055 * '0' only for enabled functions (function 0 always exists and
3057 * In case of CMT in BB, only the "even" functions are enabled, and thus
3058 * the number of functions for both hwfns is learnt from the same bits.
3060 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3061 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3062 MISCS_REG_FUNCTION_HIDE_BB_K2);
3064 reg_function_hide = 0;
3067 if (reg_function_hide & 0x1) {
3068 if (ECORE_IS_BB(p_dev)) {
3069 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3081 /* Get the number of the enabled functions on the engine */
3082 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3089 /* Get the PF index within the enabled functions */
3090 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3091 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3099 p_hwfn->num_funcs_on_engine = num_funcs;
3100 p_hwfn->enabled_func_idx = enabled_func_idx;
3103 if (CHIP_REV_IS_FPGA(p_dev)) {
3104 DP_NOTICE(p_hwfn, false,
3105 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3106 p_hwfn->num_funcs_on_engine = 4;
3110 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3111 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3112 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3113 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3116 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3117 struct ecore_ptt *p_ptt)
3122 /* Read the port mode */
3123 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3125 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3126 (p_hwfn->p_dev->num_hwfns > 1))
3127 /* In CMT on emulation, assume 1 port */
3131 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3133 if (port_mode < 3) {
3134 p_hwfn->p_dev->num_ports_in_engines = 1;
3135 } else if (port_mode <= 5) {
3136 p_hwfn->p_dev->num_ports_in_engines = 2;
3138 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3139 p_hwfn->p_dev->num_ports_in_engines);
3141 /* Default num_ports_in_engines to something */
3142 p_hwfn->p_dev->num_ports_in_engines = 1;
3146 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3147 struct ecore_ptt *p_ptt)
3152 p_hwfn->p_dev->num_ports_in_engines = 0;
3155 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3156 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3157 switch ((port & 0xf000) >> 12) {
3159 p_hwfn->p_dev->num_ports_in_engines = 1;
3162 p_hwfn->p_dev->num_ports_in_engines = 2;
3165 p_hwfn->p_dev->num_ports_in_engines = 4;
3168 DP_NOTICE(p_hwfn, false,
3169 "Unknown port mode in ECO_RESERVED %08x\n",
3174 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3175 port = ecore_rd(p_hwfn, p_ptt,
3176 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3179 p_hwfn->p_dev->num_ports_in_engines++;
3183 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3184 struct ecore_ptt *p_ptt)
3186 if (ECORE_IS_BB(p_hwfn->p_dev))
3187 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3189 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3192 static enum _ecore_status_t
3193 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3194 enum ecore_pci_personality personality,
3195 struct ecore_hw_prepare_params *p_params)
3197 bool drv_resc_alloc = p_params->drv_resc_alloc;
3198 enum _ecore_status_t rc;
3200 /* Since all information is common, only first hwfns should do this */
3201 if (IS_LEAD_HWFN(p_hwfn)) {
3202 rc = ecore_iov_hw_info(p_hwfn);
3203 if (rc != ECORE_SUCCESS) {
3204 if (p_params->b_relaxed_probe)
3205 p_params->p_relaxed_res =
3206 ECORE_HW_PREPARE_BAD_IOV;
3212 /* TODO In get_hw_info, amoungst others:
3213 * Get MCP FW revision and determine according to it the supported
3214 * featrues (e.g. DCB)
3216 * ecore_get_pcie_width_speed, WOL capability.
3217 * Number of global CQ-s (for storage
3219 ecore_hw_info_port_num(p_hwfn, p_ptt);
3222 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3224 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3225 if (rc != ECORE_SUCCESS)
3231 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3232 if (rc != ECORE_SUCCESS) {
3233 if (p_params->b_relaxed_probe)
3234 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3240 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3242 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3243 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3246 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3248 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3249 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3253 if (ecore_mcp_is_init(p_hwfn)) {
3254 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3255 p_hwfn->hw_info.ovlan =
3256 p_hwfn->mcp_info->func_info.ovlan;
3258 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3261 if (personality != ECORE_PCI_DEFAULT) {
3262 p_hwfn->hw_info.personality = personality;
3263 } else if (ecore_mcp_is_init(p_hwfn)) {
3264 enum ecore_pci_personality protocol;
3266 protocol = p_hwfn->mcp_info->func_info.protocol;
3267 p_hwfn->hw_info.personality = protocol;
3271 /* To overcome ILT lack for emulation, until at least until we'll have
3272 * a definite answer from system about it, allow only PF0 to be RoCE.
3274 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3275 if (!p_hwfn->rel_pf_id)
3276 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3278 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3282 /* although in BB some constellations may support more than 4 tcs,
3283 * that can result in performance penalty in some cases. 4
3284 * represents a good tradeoff between performance and flexibility.
3286 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3288 /* start out with a single active tc. This can be increased either
3289 * by dcbx negotiation or by upper layer driver
3291 p_hwfn->hw_info.num_active_tc = 1;
3293 ecore_get_num_funcs(p_hwfn, p_ptt);
3295 if (ecore_mcp_is_init(p_hwfn))
3296 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3298 /* In case of forcing the driver's default resource allocation, calling
3299 * ecore_hw_get_resc() should come after initializing the personality
3300 * and after getting the number of functions, since the calculation of
3301 * the resources/features depends on them.
3302 * This order is not harmful if not forcing.
3304 rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3305 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3307 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3313 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3315 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3318 /* Read Vendor Id / Device Id */
3319 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3321 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3324 /* Determine type */
3325 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
3326 p_dev->type = ECORE_DEV_TYPE_AH;
3328 p_dev->type = ECORE_DEV_TYPE_BB;
3330 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3331 MISCS_REG_CHIP_NUM);
3332 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3333 MISCS_REG_CHIP_REV);
3335 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3337 /* Learn number of HW-functions */
3338 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3339 MISCS_REG_CMT_ENABLED_FOR_PAIR);
3341 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3342 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3343 p_dev->num_hwfns = 2;
3345 p_dev->num_hwfns = 1;
3349 if (CHIP_REV_IS_EMUL(p_dev)) {
3350 /* For some reason we have problems with this register
3351 * in B0 emulation; Simply assume no CMT
3353 DP_NOTICE(p_dev->hwfns, false,
3354 "device on emul - assume no CMT\n");
3355 p_dev->num_hwfns = 1;
3359 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3360 MISCS_REG_CHIP_TEST_REG) >> 4;
3361 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3362 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3363 MISCS_REG_CHIP_METAL);
3364 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3365 DP_INFO(p_dev->hwfns,
3366 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3367 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3368 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3369 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3372 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3373 DP_NOTICE(p_dev->hwfns, false,
3374 "The chip type/rev (BB A0) is not supported!\n");
3375 return ECORE_ABORTED;
3378 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3379 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3380 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3382 if (CHIP_REV_IS_EMUL(p_dev)) {
3383 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3384 MISCS_REG_ECO_RESERVED);
3385 if (tmp & (1 << 29)) {
3386 DP_NOTICE(p_hwfn, false,
3387 "Emulation: Running on a FULL build\n");
3388 p_dev->b_is_emul_full = true;
3390 DP_NOTICE(p_hwfn, false,
3391 "Emulation: Running on a REDUCED build\n");
3396 return ECORE_SUCCESS;
3399 #ifndef LINUX_REMOVE
3400 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3407 for_each_hwfn(p_dev, j) {
3408 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3410 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3411 "Mark hw/fw uninitialized\n");
3413 p_hwfn->hw_init_done = false;
3414 p_hwfn->first_on_engine = false;
3416 ecore_ptt_invalidate(p_hwfn);
3421 static enum _ecore_status_t
3422 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3423 void OSAL_IOMEM * p_regview,
3424 void OSAL_IOMEM * p_doorbells,
3425 struct ecore_hw_prepare_params *p_params)
3427 struct ecore_dev *p_dev = p_hwfn->p_dev;
3428 struct ecore_mdump_info mdump_info;
3429 enum _ecore_status_t rc = ECORE_SUCCESS;
3431 /* Split PCI bars evenly between hwfns */
3432 p_hwfn->regview = p_regview;
3433 p_hwfn->doorbells = p_doorbells;
3436 return ecore_vf_hw_prepare(p_hwfn);
3438 /* Validate that chip access is feasible */
3439 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3441 "Reading the ME register returns all Fs; Preventing further chip access\n");
3442 if (p_params->b_relaxed_probe)
3443 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3447 get_function_id(p_hwfn);
3449 /* Allocate PTT pool */
3450 rc = ecore_ptt_pool_alloc(p_hwfn);
3452 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3453 if (p_params->b_relaxed_probe)
3454 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3458 /* Allocate the main PTT */
3459 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3461 /* First hwfn learns basic information, e.g., number of hwfns */
3462 if (!p_hwfn->my_id) {
3463 rc = ecore_get_dev_info(p_dev);
3464 if (rc != ECORE_SUCCESS) {
3465 if (p_params->b_relaxed_probe)
3466 p_params->p_relaxed_res =
3467 ECORE_HW_PREPARE_FAILED_DEV;
3472 ecore_hw_hwfn_prepare(p_hwfn);
3474 /* Initialize MCP structure */
3475 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3477 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3478 if (p_params->b_relaxed_probe)
3479 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3483 /* Read the device configuration information from the HW and SHMEM */
3484 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3485 p_params->personality, p_params);
3487 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3491 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3492 * called, since among others it sets the ports number in an engine.
3494 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3495 !p_dev->recov_in_prog) {
3496 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3497 if (rc != ECORE_SUCCESS)
3498 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3501 /* Check if mdump logs are present and update the epoch value */
3502 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3503 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3505 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3506 DP_NOTICE(p_hwfn, false,
3507 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3510 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3514 /* Allocate the init RT array and initialize the init-ops engine */
3515 rc = ecore_init_alloc(p_hwfn);
3517 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3518 if (p_params->b_relaxed_probe)
3519 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3523 if (CHIP_REV_IS_FPGA(p_dev)) {
3524 DP_NOTICE(p_hwfn, false,
3525 "FPGA: workaround; Prevent DMAE parities\n");
3526 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3529 DP_NOTICE(p_hwfn, false,
3530 "FPGA: workaround: Set VF bar0 size\n");
3531 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3532 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3538 if (IS_LEAD_HWFN(p_hwfn))
3539 ecore_iov_free_hw_info(p_dev);
3540 ecore_mcp_free(p_hwfn);
3542 ecore_hw_hwfn_free(p_hwfn);
3547 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3548 struct ecore_hw_prepare_params *p_params)
3550 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3551 enum _ecore_status_t rc;
3553 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3555 if (p_params->b_relaxed_probe)
3556 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3558 /* Store the precompiled init data ptrs */
3560 ecore_init_iro_array(p_dev);
3562 /* Initialize the first hwfn - will learn number of hwfns */
3563 rc = ecore_hw_prepare_single(p_hwfn,
3565 p_dev->doorbells, p_params);
3566 if (rc != ECORE_SUCCESS)
3569 p_params->personality = p_hwfn->hw_info.personality;
3571 /* initilalize 2nd hwfn if necessary */
3572 if (p_dev->num_hwfns > 1) {
3573 void OSAL_IOMEM *p_regview, *p_doorbell;
3574 u8 OSAL_IOMEM *addr;
3576 /* adjust bar offset for second engine */
3577 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3578 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3579 p_regview = (void OSAL_IOMEM *)addr;
3581 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3582 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3583 p_doorbell = (void OSAL_IOMEM *)addr;
3585 /* prepare second hw function */
3586 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3587 p_doorbell, p_params);
3589 /* in case of error, need to free the previously
3590 * initiliazed hwfn 0.
3592 if (rc != ECORE_SUCCESS) {
3593 if (p_params->b_relaxed_probe)
3594 p_params->p_relaxed_res =
3595 ECORE_HW_PREPARE_FAILED_ENG2;
3598 ecore_init_free(p_hwfn);
3599 ecore_mcp_free(p_hwfn);
3600 ecore_hw_hwfn_free(p_hwfn);
3602 DP_NOTICE(p_dev, true,
3603 "What do we need to free when VF hwfn1 init fails\n");
3612 void ecore_hw_remove(struct ecore_dev *p_dev)
3614 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3618 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3619 ECORE_OV_DRIVER_STATE_NOT_LOADED);
3621 for_each_hwfn(p_dev, i) {
3622 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3625 ecore_vf_pf_release(p_hwfn);
3629 ecore_init_free(p_hwfn);
3630 ecore_hw_hwfn_free(p_hwfn);
3631 ecore_mcp_free(p_hwfn);
3633 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3636 ecore_iov_free_hw_info(p_dev);
3639 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3640 struct ecore_chain *p_chain)
3642 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3643 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3644 struct ecore_chain_next *p_next;
3650 size = p_chain->elem_size * p_chain->usable_per_page;
3652 for (i = 0; i < p_chain->page_cnt; i++) {
3656 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3657 p_virt_next = p_next->next_virt;
3658 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3660 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3661 ECORE_CHAIN_PAGE_SIZE);
3663 p_virt = p_virt_next;
3664 p_phys = p_phys_next;
3668 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3669 struct ecore_chain *p_chain)
3671 if (!p_chain->p_virt_addr)
3674 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3675 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3678 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3679 struct ecore_chain *p_chain)
3681 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3682 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3683 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3685 if (!pp_virt_addr_tbl)
3691 for (i = 0; i < page_cnt; i++) {
3692 if (!pp_virt_addr_tbl[i])
3695 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3696 *(dma_addr_t *)p_pbl_virt,
3697 ECORE_CHAIN_PAGE_SIZE);
3699 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3702 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3704 if (!p_chain->b_external_pbl)
3705 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3706 p_chain->pbl_sp.p_phys_table, pbl_size);
3708 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3711 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3713 switch (p_chain->mode) {
3714 case ECORE_CHAIN_MODE_NEXT_PTR:
3715 ecore_chain_free_next_ptr(p_dev, p_chain);
3717 case ECORE_CHAIN_MODE_SINGLE:
3718 ecore_chain_free_single(p_dev, p_chain);
3720 case ECORE_CHAIN_MODE_PBL:
3721 ecore_chain_free_pbl(p_dev, p_chain);
3726 static enum _ecore_status_t
3727 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3728 enum ecore_chain_cnt_type cnt_type,
3729 osal_size_t elem_size, u32 page_cnt)
3731 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3733 /* The actual chain size can be larger than the maximal possible value
3734 * after rounding up the requested elements number to pages, and after
3735 * taking into acount the unusuable elements (next-ptr elements).
3736 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3737 * size/capacity fields are of a u32 type.
3739 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3740 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3741 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3742 chain_size > ECORE_U32_MAX)) {
3743 DP_NOTICE(p_dev, true,
3744 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3745 (unsigned long)chain_size);
3749 return ECORE_SUCCESS;
3752 static enum _ecore_status_t
3753 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3755 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3756 dma_addr_t p_phys = 0;
3759 for (i = 0; i < p_chain->page_cnt; i++) {
3760 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3761 ECORE_CHAIN_PAGE_SIZE);
3763 DP_NOTICE(p_dev, true,
3764 "Failed to allocate chain memory\n");
3769 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3770 ecore_chain_reset(p_chain);
3772 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3776 p_virt_prev = p_virt;
3778 /* Last page's next element should point to the beginning of the
3781 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3782 p_chain->p_virt_addr,
3783 p_chain->p_phys_addr);
3785 return ECORE_SUCCESS;
3788 static enum _ecore_status_t
3789 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3791 dma_addr_t p_phys = 0;
3792 void *p_virt = OSAL_NULL;
3794 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3796 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3800 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3801 ecore_chain_reset(p_chain);
3803 return ECORE_SUCCESS;
3806 static enum _ecore_status_t
3807 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3808 struct ecore_chain *p_chain,
3809 struct ecore_chain_ext_pbl *ext_pbl)
3811 void *p_virt = OSAL_NULL;
3812 u8 *p_pbl_virt = OSAL_NULL;
3813 void **pp_virt_addr_tbl = OSAL_NULL;
3814 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3815 u32 page_cnt = p_chain->page_cnt, size, i;
3817 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3818 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
3819 if (!pp_virt_addr_tbl) {
3820 DP_NOTICE(p_dev, true,
3821 "Failed to allocate memory for the chain virtual addresses table\n");
3825 /* The allocation of the PBL table is done with its full size, since it
3826 * is expected to be successive.
3827 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3828 * failure, since pp_virt_addr_tbl was previously allocated, and it
3829 * should be saved to allow its freeing during the error flow.
3831 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3833 if (ext_pbl == OSAL_NULL) {
3834 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3836 p_pbl_virt = ext_pbl->p_pbl_virt;
3837 p_pbl_phys = ext_pbl->p_pbl_phys;
3838 p_chain->b_external_pbl = true;
3841 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3844 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3848 for (i = 0; i < page_cnt; i++) {
3849 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3850 ECORE_CHAIN_PAGE_SIZE);
3852 DP_NOTICE(p_dev, true,
3853 "Failed to allocate chain memory\n");
3858 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3859 ecore_chain_reset(p_chain);
3862 /* Fill the PBL table with the physical address of the page */
3863 *(dma_addr_t *)p_pbl_virt = p_phys;
3864 /* Keep the virtual address of the page */
3865 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3867 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3870 return ECORE_SUCCESS;
3873 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3874 enum ecore_chain_use_mode intended_use,
3875 enum ecore_chain_mode mode,
3876 enum ecore_chain_cnt_type cnt_type,
3877 u32 num_elems, osal_size_t elem_size,
3878 struct ecore_chain *p_chain,
3879 struct ecore_chain_ext_pbl *ext_pbl)
3882 enum _ecore_status_t rc = ECORE_SUCCESS;
3884 if (mode == ECORE_CHAIN_MODE_SINGLE)
3887 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3889 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3892 DP_NOTICE(p_dev, true,
3893 "Cannot allocate a chain with the given arguments:\n"
3894 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3895 intended_use, mode, cnt_type, num_elems, elem_size);
3899 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3900 mode, cnt_type, p_dev->dp_ctx);
3903 case ECORE_CHAIN_MODE_NEXT_PTR:
3904 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3906 case ECORE_CHAIN_MODE_SINGLE:
3907 rc = ecore_chain_alloc_single(p_dev, p_chain);
3909 case ECORE_CHAIN_MODE_PBL:
3910 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3916 return ECORE_SUCCESS;
3919 ecore_chain_free(p_dev, p_chain);
3923 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3924 u16 src_id, u16 *dst_id)
3926 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3929 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3930 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3931 DP_NOTICE(p_hwfn, true,
3932 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3938 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3940 return ECORE_SUCCESS;
3943 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3944 u8 src_id, u8 *dst_id)
3946 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3949 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3950 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3951 DP_NOTICE(p_hwfn, true,
3952 "vport id [%d] is not valid, available indices [%d - %d]\n",
3958 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3960 return ECORE_SUCCESS;
3963 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3964 u8 src_id, u8 *dst_id)
3966 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3969 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3970 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3971 DP_NOTICE(p_hwfn, true,
3972 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3978 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3980 return ECORE_SUCCESS;
3983 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3984 struct ecore_ptt *p_ptt,
3990 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3991 return ECORE_SUCCESS;
3993 high = p_filter[1] | (p_filter[0] << 8);
3994 low = p_filter[5] | (p_filter[4] << 8) |
3995 (p_filter[3] << 16) | (p_filter[2] << 24);
3997 /* Find a free entry and utilize it */
3998 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3999 en = ecore_rd(p_hwfn, p_ptt,
4000 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4003 ecore_wr(p_hwfn, p_ptt,
4004 NIG_REG_LLH_FUNC_FILTER_VALUE +
4005 2 * i * sizeof(u32), low);
4006 ecore_wr(p_hwfn, p_ptt,
4007 NIG_REG_LLH_FUNC_FILTER_VALUE +
4008 (2 * i + 1) * sizeof(u32), high);
4009 ecore_wr(p_hwfn, p_ptt,
4010 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4011 ecore_wr(p_hwfn, p_ptt,
4012 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4013 i * sizeof(u32), 0);
4014 ecore_wr(p_hwfn, p_ptt,
4015 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4018 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4019 DP_NOTICE(p_hwfn, false,
4020 "Failed to find an empty LLH filter to utilize\n");
4024 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4025 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
4026 p_filter[0], p_filter[1], p_filter[2],
4027 p_filter[3], p_filter[4], p_filter[5], i);
4029 return ECORE_SUCCESS;
4032 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4033 struct ecore_ptt *p_ptt, u8 *p_filter)
4038 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4041 high = p_filter[1] | (p_filter[0] << 8);
4042 low = p_filter[5] | (p_filter[4] << 8) |
4043 (p_filter[3] << 16) | (p_filter[2] << 24);
4045 /* Find the entry and clean it */
4046 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4047 if (ecore_rd(p_hwfn, p_ptt,
4048 NIG_REG_LLH_FUNC_FILTER_VALUE +
4049 2 * i * sizeof(u32)) != low)
4051 if (ecore_rd(p_hwfn, p_ptt,
4052 NIG_REG_LLH_FUNC_FILTER_VALUE +
4053 (2 * i + 1) * sizeof(u32)) != high)
4056 ecore_wr(p_hwfn, p_ptt,
4057 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4058 ecore_wr(p_hwfn, p_ptt,
4059 NIG_REG_LLH_FUNC_FILTER_VALUE +
4060 2 * i * sizeof(u32), 0);
4061 ecore_wr(p_hwfn, p_ptt,
4062 NIG_REG_LLH_FUNC_FILTER_VALUE +
4063 (2 * i + 1) * sizeof(u32), 0);
4066 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4067 DP_NOTICE(p_hwfn, false,
4068 "Tried to remove a non-configured filter\n");
4071 enum _ecore_status_t
4072 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4073 struct ecore_ptt *p_ptt,
4074 u16 source_port_or_eth_type,
4076 enum ecore_llh_port_filter_type_t type)
4081 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4082 return ECORE_SUCCESS;
4087 case ECORE_LLH_FILTER_ETHERTYPE:
4088 high = source_port_or_eth_type;
4090 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4091 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4092 low = source_port_or_eth_type << 16;
4094 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4095 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4098 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4099 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4100 low = (source_port_or_eth_type << 16) | dest_port;
4103 DP_NOTICE(p_hwfn, true,
4104 "Non valid LLH protocol filter type %d\n", type);
4107 /* Find a free entry and utilize it */
4108 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4109 en = ecore_rd(p_hwfn, p_ptt,
4110 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4113 ecore_wr(p_hwfn, p_ptt,
4114 NIG_REG_LLH_FUNC_FILTER_VALUE +
4115 2 * i * sizeof(u32), low);
4116 ecore_wr(p_hwfn, p_ptt,
4117 NIG_REG_LLH_FUNC_FILTER_VALUE +
4118 (2 * i + 1) * sizeof(u32), high);
4119 ecore_wr(p_hwfn, p_ptt,
4120 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4121 ecore_wr(p_hwfn, p_ptt,
4122 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4123 i * sizeof(u32), 1 << type);
4124 ecore_wr(p_hwfn, p_ptt,
4125 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4128 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4129 DP_NOTICE(p_hwfn, false,
4130 "Failed to find an empty LLH filter to utilize\n");
4131 return ECORE_NORESOURCES;
4134 case ECORE_LLH_FILTER_ETHERTYPE:
4135 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4136 "ETH type %x is added at %d\n",
4137 source_port_or_eth_type, i);
4139 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4140 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4141 "TCP src port %x is added at %d\n",
4142 source_port_or_eth_type, i);
4144 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4145 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4146 "UDP src port %x is added at %d\n",
4147 source_port_or_eth_type, i);
4149 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4150 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4151 "TCP dst port %x is added at %d\n", dest_port, i);
4153 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4154 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4155 "UDP dst port %x is added at %d\n", dest_port, i);
4157 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4158 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4159 "TCP src/dst ports %x/%x are added at %d\n",
4160 source_port_or_eth_type, dest_port, i);
4162 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4163 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4164 "UDP src/dst ports %x/%x are added at %d\n",
4165 source_port_or_eth_type, dest_port, i);
4168 return ECORE_SUCCESS;
4172 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4173 struct ecore_ptt *p_ptt,
4174 u16 source_port_or_eth_type,
4176 enum ecore_llh_port_filter_type_t type)
4181 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4187 case ECORE_LLH_FILTER_ETHERTYPE:
4188 high = source_port_or_eth_type;
4190 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4191 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4192 low = source_port_or_eth_type << 16;
4194 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4195 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4198 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4199 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4200 low = (source_port_or_eth_type << 16) | dest_port;
4203 DP_NOTICE(p_hwfn, true,
4204 "Non valid LLH protocol filter type %d\n", type);
4208 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4209 if (!ecore_rd(p_hwfn, p_ptt,
4210 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4212 if (!ecore_rd(p_hwfn, p_ptt,
4213 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4215 if (!(ecore_rd(p_hwfn, p_ptt,
4216 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4217 i * sizeof(u32)) & (1 << type)))
4219 if (ecore_rd(p_hwfn, p_ptt,
4220 NIG_REG_LLH_FUNC_FILTER_VALUE +
4221 2 * i * sizeof(u32)) != low)
4223 if (ecore_rd(p_hwfn, p_ptt,
4224 NIG_REG_LLH_FUNC_FILTER_VALUE +
4225 (2 * i + 1) * sizeof(u32)) != high)
4228 ecore_wr(p_hwfn, p_ptt,
4229 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4230 ecore_wr(p_hwfn, p_ptt,
4231 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4232 ecore_wr(p_hwfn, p_ptt,
4233 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4234 i * sizeof(u32), 0);
4235 ecore_wr(p_hwfn, p_ptt,
4236 NIG_REG_LLH_FUNC_FILTER_VALUE +
4237 2 * i * sizeof(u32), 0);
4238 ecore_wr(p_hwfn, p_ptt,
4239 NIG_REG_LLH_FUNC_FILTER_VALUE +
4240 (2 * i + 1) * sizeof(u32), 0);
4244 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4245 DP_NOTICE(p_hwfn, false,
4246 "Tried to remove a non-configured filter\n");
4249 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4250 struct ecore_ptt *p_ptt)
4254 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4257 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4258 ecore_wr(p_hwfn, p_ptt,
4259 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4260 ecore_wr(p_hwfn, p_ptt,
4261 NIG_REG_LLH_FUNC_FILTER_VALUE +
4262 2 * i * sizeof(u32), 0);
4263 ecore_wr(p_hwfn, p_ptt,
4264 NIG_REG_LLH_FUNC_FILTER_VALUE +
4265 (2 * i + 1) * sizeof(u32), 0);
4269 enum _ecore_status_t
4270 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4271 struct ecore_ptt *p_ptt)
4273 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4274 ecore_wr(p_hwfn, p_ptt,
4275 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4276 1 << p_hwfn->abs_pf_id / 2);
4277 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4278 return ECORE_SUCCESS;
4281 DP_NOTICE(p_hwfn, false,
4282 "This function can't be set as default\n");
4286 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4287 struct ecore_ptt *p_ptt,
4288 u32 hw_addr, void *p_eth_qzone,
4289 osal_size_t eth_qzone_size,
4292 struct coalescing_timeset *p_coal_timeset;
4294 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4295 DP_NOTICE(p_hwfn, true,
4296 "Coalescing configuration not enabled\n");
4300 p_coal_timeset = p_eth_qzone;
4301 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4302 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4303 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4304 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4306 return ECORE_SUCCESS;
4309 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4310 u16 rx_coal, u16 tx_coal,
4313 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
4314 enum _ecore_status_t rc = ECORE_SUCCESS;
4315 struct ecore_ptt *p_ptt;
4317 /* TODO - Configuring a single queue's coalescing but
4318 * claiming all queues are abiding same configuration
4319 * for PF and VF both.
4322 if (IS_VF(p_hwfn->p_dev))
4323 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
4326 p_ptt = ecore_ptt_acquire(p_hwfn);
4331 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4334 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
4338 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4341 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
4344 ecore_ptt_release(p_hwfn, p_ptt);
4349 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4350 struct ecore_ptt *p_ptt,
4352 struct ecore_queue_cid *p_cid)
4354 struct ustorm_eth_queue_zone eth_qzone;
4355 u8 timeset, timer_res;
4357 enum _ecore_status_t rc;
4359 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4360 if (coalesce <= 0x7F) {
4362 } else if (coalesce <= 0xFF) {
4364 } else if (coalesce <= 0x1FF) {
4367 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4370 timeset = (u8)(coalesce >> timer_res);
4372 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4373 p_cid->abs.sb_idx, false);
4374 if (rc != ECORE_SUCCESS)
4377 address = BAR0_MAP_REG_USDM_RAM +
4378 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4380 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4381 sizeof(struct ustorm_eth_queue_zone), timeset);
4382 if (rc != ECORE_SUCCESS)
4389 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4390 struct ecore_ptt *p_ptt,
4392 struct ecore_queue_cid *p_cid)
4394 struct xstorm_eth_queue_zone eth_qzone;
4395 u8 timeset, timer_res;
4397 enum _ecore_status_t rc;
4399 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4400 if (coalesce <= 0x7F) {
4402 } else if (coalesce <= 0xFF) {
4404 } else if (coalesce <= 0x1FF) {
4407 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4411 timeset = (u8)(coalesce >> timer_res);
4413 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4414 p_cid->abs.sb_idx, true);
4415 if (rc != ECORE_SUCCESS)
4418 address = BAR0_MAP_REG_XSDM_RAM +
4419 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4421 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4422 sizeof(struct xstorm_eth_queue_zone), timeset);
4427 /* Calculate final WFQ values for all vports and configure it.
4428 * After this configuration each vport must have
4429 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4431 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4432 struct ecore_ptt *p_ptt,
4435 struct init_qm_vport_params *vport_params;
4438 vport_params = p_hwfn->qm_info.qm_vport_params;
4440 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4441 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4443 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4445 ecore_init_vport_wfq(p_hwfn, p_ptt,
4446 vport_params[i].first_tx_pq_id,
4447 vport_params[i].vport_wfq);
4452 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4456 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4457 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4460 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4461 struct ecore_ptt *p_ptt,
4464 struct init_qm_vport_params *vport_params;
4467 vport_params = p_hwfn->qm_info.qm_vport_params;
4469 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4470 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4471 ecore_init_vport_wfq(p_hwfn, p_ptt,
4472 vport_params[i].first_tx_pq_id,
4473 vport_params[i].vport_wfq);
4477 /* This function performs several validations for WFQ
4478 * configuration and required min rate for a given vport
4479 * 1. req_rate must be greater than one percent of min_pf_rate.
4480 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4481 * rates to get less than one percent of min_pf_rate.
4482 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4484 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4485 u16 vport_id, u32 req_rate,
4488 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4489 int non_requested_count = 0, req_count = 0, i, num_vports;
4491 num_vports = p_hwfn->qm_info.num_vports;
4493 /* Accounting for the vports which are configured for WFQ explicitly */
4495 for (i = 0; i < num_vports; i++) {
4498 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4500 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4501 total_req_min_rate += tmp_speed;
4505 /* Include current vport data as well */
4507 total_req_min_rate += req_rate;
4508 non_requested_count = num_vports - req_count;
4510 /* validate possible error cases */
4511 if (req_rate > min_pf_rate) {
4512 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4513 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4514 vport_id, req_rate, min_pf_rate);
4518 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4519 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4520 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4521 vport_id, req_rate, min_pf_rate);
4525 /* TBD - for number of vports greater than 100 */
4526 if (num_vports > ECORE_WFQ_UNIT) {
4527 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4528 "Number of vports is greater than %d\n",
4533 if (total_req_min_rate > min_pf_rate) {
4534 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4535 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4536 total_req_min_rate, min_pf_rate);
4540 /* Data left for non requested vports */
4541 total_left_rate = min_pf_rate - total_req_min_rate;
4542 left_rate_per_vp = total_left_rate / non_requested_count;
4544 /* validate if non requested get < 1% of min bw */
4545 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4546 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4547 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4548 left_rate_per_vp, min_pf_rate);
4552 /* now req_rate for given vport passes all scenarios.
4553 * assign final wfq rates to all vports.
4555 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4556 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4558 for (i = 0; i < num_vports; i++) {
4559 if (p_hwfn->qm_info.wfq_data[i].configured)
4562 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4565 return ECORE_SUCCESS;
4568 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4569 struct ecore_ptt *p_ptt,
4570 u16 vp_id, u32 rate)
4572 struct ecore_mcp_link_state *p_link;
4573 int rc = ECORE_SUCCESS;
4575 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4577 if (!p_link->min_pf_rate) {
4578 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4579 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4583 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4585 if (rc == ECORE_SUCCESS)
4586 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4587 p_link->min_pf_rate);
4589 DP_NOTICE(p_hwfn, false,
4590 "Validation failed while configuring min rate\n");
4595 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4596 struct ecore_ptt *p_ptt,
4599 bool use_wfq = false;
4600 int rc = ECORE_SUCCESS;
4603 /* Validate all pre configured vports for wfq */
4604 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4607 if (!p_hwfn->qm_info.wfq_data[i].configured)
4610 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4613 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4614 if (rc != ECORE_SUCCESS) {
4615 DP_NOTICE(p_hwfn, false,
4616 "WFQ validation failed while configuring min rate\n");
4621 if (rc == ECORE_SUCCESS && use_wfq)
4622 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4624 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4629 /* Main API for ecore clients to configure vport min rate.
4630 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4631 * rate - Speed in Mbps needs to be assigned to a given vport.
4633 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4635 int i, rc = ECORE_INVAL;
4637 /* TBD - for multiple hardware functions - that is 100 gig */
4638 if (p_dev->num_hwfns > 1) {
4639 DP_NOTICE(p_dev, false,
4640 "WFQ configuration is not supported for this device\n");
4644 for_each_hwfn(p_dev, i) {
4645 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4646 struct ecore_ptt *p_ptt;
4648 p_ptt = ecore_ptt_acquire(p_hwfn);
4650 return ECORE_TIMEOUT;
4652 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4654 if (rc != ECORE_SUCCESS) {
4655 ecore_ptt_release(p_hwfn, p_ptt);
4659 ecore_ptt_release(p_hwfn, p_ptt);
4665 /* API to configure WFQ from mcp link change */
4666 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4671 /* TBD - for multiple hardware functions - that is 100 gig */
4672 if (p_dev->num_hwfns > 1) {
4673 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4674 "WFQ configuration is not supported for this device\n");
4678 for_each_hwfn(p_dev, i) {
4679 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4681 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4687 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4688 struct ecore_ptt *p_ptt,
4689 struct ecore_mcp_link_state *p_link,
4692 int rc = ECORE_SUCCESS;
4694 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4696 if (!p_link->line_speed && (max_bw != 100))
4699 p_link->speed = (p_link->line_speed * max_bw) / 100;
4700 p_hwfn->qm_info.pf_rl = p_link->speed;
4702 /* Since the limiter also affects Tx-switched traffic, we don't want it
4703 * to limit such traffic in case there's no actual limit.
4704 * In that case, set limit to imaginary high boundary.
4707 p_hwfn->qm_info.pf_rl = 100000;
4709 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4710 p_hwfn->qm_info.pf_rl);
4712 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4713 "Configured MAX bandwidth to be %08x Mb/sec\n",
4719 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4720 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4722 int i, rc = ECORE_INVAL;
4724 if (max_bw < 1 || max_bw > 100) {
4725 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4729 for_each_hwfn(p_dev, i) {
4730 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4731 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4732 struct ecore_mcp_link_state *p_link;
4733 struct ecore_ptt *p_ptt;
4735 p_link = &p_lead->mcp_info->link_output;
4737 p_ptt = ecore_ptt_acquire(p_hwfn);
4739 return ECORE_TIMEOUT;
4741 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4744 ecore_ptt_release(p_hwfn, p_ptt);
4746 if (rc != ECORE_SUCCESS)
4753 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4754 struct ecore_ptt *p_ptt,
4755 struct ecore_mcp_link_state *p_link,
4758 int rc = ECORE_SUCCESS;
4760 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4761 p_hwfn->qm_info.pf_wfq = min_bw;
4763 if (!p_link->line_speed)
4766 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4768 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4770 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4771 "Configured MIN bandwidth to be %d Mb/sec\n",
4772 p_link->min_pf_rate);
4777 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4778 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4780 int i, rc = ECORE_INVAL;
4782 if (min_bw < 1 || min_bw > 100) {
4783 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4787 for_each_hwfn(p_dev, i) {
4788 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4789 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4790 struct ecore_mcp_link_state *p_link;
4791 struct ecore_ptt *p_ptt;
4793 p_link = &p_lead->mcp_info->link_output;
4795 p_ptt = ecore_ptt_acquire(p_hwfn);
4797 return ECORE_TIMEOUT;
4799 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4801 if (rc != ECORE_SUCCESS) {
4802 ecore_ptt_release(p_hwfn, p_ptt);
4806 if (p_link->min_pf_rate) {
4807 u32 min_rate = p_link->min_pf_rate;
4809 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4814 ecore_ptt_release(p_hwfn, p_ptt);
4820 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4822 struct ecore_mcp_link_state *p_link;
4824 p_link = &p_hwfn->mcp_info->link_output;
4826 if (p_link->min_pf_rate)
4827 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4828 p_link->min_pf_rate);
4830 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4831 sizeof(*p_hwfn->qm_info.wfq_data) *
4832 p_hwfn->qm_info.num_vports);
4835 int ecore_device_num_engines(struct ecore_dev *p_dev)
4837 return ECORE_IS_BB(p_dev) ? 2 : 1;
4840 int ecore_device_num_ports(struct ecore_dev *p_dev)
4842 /* in CMT always only one port */
4843 if (p_dev->num_hwfns > 1)
4846 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4849 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4854 ((u8 *)fw_msb)[0] = mac[1];
4855 ((u8 *)fw_msb)[1] = mac[0];
4856 ((u8 *)fw_mid)[0] = mac[3];
4857 ((u8 *)fw_mid)[1] = mac[2];
4858 ((u8 *)fw_lsb)[0] = mac[5];
4859 ((u8 *)fw_lsb)[1] = mac[4];