drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /* Configurable */
  45 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  46                                          * load the driver. The number was
  47                                          * arbitrarily set.
  48                                          */
  49
  50 /* Derived */
  51 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  52
  53 enum BAR_ID {
  54         BAR_ID_0,               /* used for GRC */
  55         BAR_ID_1                /* Used for doorbells */
  56 };
  57
  58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  59 {
  60         u32 bar_reg = (bar_id == BAR_ID_0 ?
  61                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  62         u32 val;
  63
  64         if (IS_VF(p_hwfn->p_dev)) {
  65                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  66                  * read from actual register, but we're currently not using
  67                  * it for actual doorbelling.
  68                  */
  69                 return 1 << 17;
  70         }
  71
  72         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  73
  74         /* The above registers were updated in the past only in CMT mode. Since
  75          * they were found to be useful MFW started updating them from 8.7.7.0.
  76          * In older MFW versions they are set to 0 which means disabled.
  77          */
  78         if (!val) {
  79                 if (p_hwfn->p_dev->num_hwfns > 1) {
  80                         DP_NOTICE(p_hwfn, false,
  81                                   "BAR size not configured. Assuming BAR size");
  82                         DP_NOTICE(p_hwfn, false,
  83                                   "of 256kB for GRC and 512kB for DB\n");
  84                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  85                 } else {
  86                         DP_NOTICE(p_hwfn, false,
  87                                   "BAR size not configured. Assuming BAR size");
  88                         DP_NOTICE(p_hwfn, false,
  89                                   "of 512kB for GRC and 512kB for DB\n");
  90                         return 512 * 1024;
  91                 }
  92         }
  93
  94         return 1 << (val + 15);
  95 }
  96
  97 void ecore_init_dp(struct ecore_dev *p_dev,
  98                    u32 dp_module, u8 dp_level, void *dp_ctx)
  99 {
 100         u32 i;
 101
 102         p_dev->dp_level = dp_level;
 103         p_dev->dp_module = dp_module;
 104         p_dev->dp_ctx = dp_ctx;
 105         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 106                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 107
 108                 p_hwfn->dp_level = dp_level;
 109                 p_hwfn->dp_module = dp_module;
 110                 p_hwfn->dp_ctx = dp_ctx;
 111         }
 112 }
 113
 114 void ecore_init_struct(struct ecore_dev *p_dev)
 115 {
 116         u8 i;
 117
 118         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 119                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 120
 121                 p_hwfn->p_dev = p_dev;
 122                 p_hwfn->my_id = i;
 123                 p_hwfn->b_active = false;
 124
 125                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 126                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 127         }
 128
 129         /* hwfn 0 is always active */
 130         p_dev->hwfns[0].b_active = true;
 131
 132         /* set the default cache alignment to 128 (may be overridden later) */
 133         p_dev->cache_shift = 7;
 134 }
 135
 136 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 137 {
 138         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 139
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 141         qm_info->qm_pq_params = OSAL_NULL;
 142         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 143         qm_info->qm_vport_params = OSAL_NULL;
 144         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 145         qm_info->qm_port_params = OSAL_NULL;
 146         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 147         qm_info->wfq_data = OSAL_NULL;
 148 }
 149
 150 void ecore_resc_free(struct ecore_dev *p_dev)
 151 {
 152         int i;
 153
 154         if (IS_VF(p_dev))
 155                 return;
 156
 157         OSAL_FREE(p_dev, p_dev->fw_data);
 158         p_dev->fw_data = OSAL_NULL;
 159
 160         OSAL_FREE(p_dev, p_dev->reset_stats);
 161
 162         for_each_hwfn(p_dev, i) {
 163                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 164
 165                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 166                 p_hwfn->p_tx_cids = OSAL_NULL;
 167                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 168                 p_hwfn->p_rx_cids = OSAL_NULL;
 169         }
 170
 171         for_each_hwfn(p_dev, i) {
 172                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 173
 174                 ecore_cxt_mngr_free(p_hwfn);
 175                 ecore_qm_info_free(p_hwfn);
 176                 ecore_spq_free(p_hwfn);
 177                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 178                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 179                 ecore_int_free(p_hwfn);
 180 #ifdef CONFIG_ECORE_LL2
 181                 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 182 #endif
 183                 ecore_iov_free(p_hwfn);
 184                 ecore_dmae_info_free(p_hwfn);
 185                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 186                 /* @@@TBD Flush work-queue ? */
 187         }
 188 }
 189
 190 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
 191                                                bool b_sleepable)
 192 {
 193         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
 194         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 195         struct init_qm_port_params *p_qm_port;
 196         bool init_rdma_offload_pq = false;
 197         bool init_pure_ack_pq = false;
 198         bool init_ooo_pq = false;
 199         u16 num_pqs, protocol_pqs;
 200         u16 num_pf_rls = 0;
 201         u16 num_vfs = 0;
 202         u32 pf_rl;
 203         u8 pf_wfq;
 204
 205         /* @TMP - saving the existing min/max bw config before resetting the
 206          * qm_info to restore them.
 207          */
 208         pf_rl = qm_info->pf_rl;
 209         pf_wfq = qm_info->pf_wfq;
 210
 211 #ifdef CONFIG_ECORE_SRIOV
 212         if (p_hwfn->p_dev->p_iov_info)
 213                 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
 214 #endif
 215         OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
 216
 217 #ifndef ASIC_ONLY
 218         /* @TMP - Don't allocate QM queues for VFs on emulation */
 219         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 220                 DP_NOTICE(p_hwfn, false,
 221                           "Emulation - skip configuring QM queues for VFs\n");
 222                 num_vfs = 0;
 223         }
 224 #endif
 225
 226         /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
 227          * active, we want physical queues allocated for all of them, since we
 228          * don't have a good recycle flow. Non ethernet PFs require only a
 229          * single physical queue.
 230          */
 231         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 232             p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 233             p_hwfn->hw_info.personality == ECORE_PCI_ETH)
 234                 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
 235         else
 236                 protocol_pqs = 1;
 237
 238         num_pqs = protocol_pqs + num_vfs + 1;   /* The '1' is for pure-LB */
 239         num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
 240
 241         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 242                 num_pqs++;      /* for RoCE queue */
 243                 init_rdma_offload_pq = true;
 244                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
 245                         /* Due to FW assumption that rl==vport, we limit the
 246                          * number of rate limiters by the minimum between its
 247                          * allocated number and the allocated number of vports.
 248                          * Another limitation is the number of supported qps
 249                          * with rate limiters in FW.
 250                          */
 251                         num_pf_rls =
 252                             (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 253                                              RESC_NUM(p_hwfn, ECORE_VPORT));
 254
 255                         /* we subtract num_vfs because each one requires a rate
 256                          * limiter, and one default rate limiter.
 257                          */
 258                         if (num_pf_rls < num_vfs + 1) {
 259                                 DP_ERR(p_hwfn, "No RL for DCQCN");
 260                                 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
 261                                        num_pf_rls, num_vfs);
 262                                 return ECORE_INVAL;
 263                         }
 264                         num_pf_rls -= num_vfs + 1;
 265                 }
 266
 267                 num_pqs += num_pf_rls;
 268                 qm_info->num_pf_rls = (u8)num_pf_rls;
 269         }
 270
 271         if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
 272                 num_pqs += 3;   /* for iwarp queue / pure-ack / ooo */
 273                 init_rdma_offload_pq = true;
 274                 init_pure_ack_pq = true;
 275                 init_ooo_pq = true;
 276         }
 277
 278         if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 279                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 280                 init_pure_ack_pq = true;
 281                 init_ooo_pq = true;
 282         }
 283
 284         /* Sanity checking that setup requires legal number of resources */
 285         if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
 286                 DP_ERR(p_hwfn,
 287                        "Need too many Physical queues - 0x%04x avail %04x",
 288                        num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
 289                 return ECORE_INVAL;
 290         }
 291
 292         /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
 293          * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
 294          */
 295         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
 296                                             b_sleepable ? GFP_KERNEL :
 297                                             GFP_ATOMIC,
 298                                             sizeof(struct init_qm_pq_params) *
 299                                             num_pqs);
 300         if (!qm_info->qm_pq_params)
 301                 goto alloc_err;
 302
 303         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
 304                                                b_sleepable ? GFP_KERNEL :
 305                                                GFP_ATOMIC,
 306                                                sizeof(struct
 307                                                       init_qm_vport_params) *
 308                                                num_vports);
 309         if (!qm_info->qm_vport_params)
 310                 goto alloc_err;
 311
 312         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
 313                                               b_sleepable ? GFP_KERNEL :
 314                                               GFP_ATOMIC,
 315                                               sizeof(struct init_qm_port_params)
 316                                               * MAX_NUM_PORTS);
 317         if (!qm_info->qm_port_params)
 318                 goto alloc_err;
 319
 320         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
 321                                         b_sleepable ? GFP_KERNEL :
 322                                         GFP_ATOMIC,
 323                                         sizeof(struct ecore_wfq_data) *
 324                                         num_vports);
 325
 326         if (!qm_info->wfq_data)
 327                 goto alloc_err;
 328
 329         vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 330
 331         /* First init rate limited queues ( Due to RoCE assumption of
 332          * qpid=rlid )
 333          */
 334         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 335                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 336                 qm_info->qm_pq_params[curr_queue].tc_id =
 337                     p_hwfn->hw_info.offload_tc;
 338                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 339                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 340         };
 341
 342         /* Protocol PQs */
 343         for (i = 0; i < protocol_pqs; i++) {
 344                 struct init_qm_pq_params *params =
 345                     &qm_info->qm_pq_params[curr_queue++];
 346
 347                 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 348                     p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 349                     p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
 350                         params->vport_id = vport_id;
 351                         params->tc_id = i;
 352                         /* Note: this assumes that if we had a configuration
 353                          * with N tcs and subsequently another configuration
 354                          * With Fewer TCs, the in flight traffic (in QM queues,
 355                          * in FW, from driver to FW) will still trickle out and
 356                          * not get "stuck" in the QM. This is determined by the
 357                          * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
 358                          * supposed to be cleared in this map, allowing traffic
 359                          * to flush out. If this is not the case, we would need
 360                          * to set the TC of unused queues to 0, and reconfigure
 361                          * QM every time num of TCs changes. Unused queues in
 362                          * this context would mean those intended for TCs where
 363                          * tc_id > hw_info.num_active_tcs.
 364                          */
 365                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 366                 } else {
 367                         params->vport_id = vport_id;
 368                         params->tc_id = p_hwfn->hw_info.offload_tc;
 369                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 370                 }
 371         }
 372
 373         /* Then init pure-LB PQ */
 374         qm_info->pure_lb_pq = curr_queue;
 375         qm_info->qm_pq_params[curr_queue].vport_id =
 376             (u8)RESC_START(p_hwfn, ECORE_VPORT);
 377         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 378         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 379         curr_queue++;
 380
 381         qm_info->offload_pq = 0;        /* Already initialized for iSCSI/FCoE */
 382         if (init_rdma_offload_pq) {
 383                 qm_info->offload_pq = curr_queue;
 384                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 385                 qm_info->qm_pq_params[curr_queue].tc_id =
 386                     p_hwfn->hw_info.offload_tc;
 387                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 388                 curr_queue++;
 389         }
 390
 391         if (init_pure_ack_pq) {
 392                 qm_info->pure_ack_pq = curr_queue;
 393                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 394                 qm_info->qm_pq_params[curr_queue].tc_id =
 395                     p_hwfn->hw_info.offload_tc;
 396                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 397                 curr_queue++;
 398         }
 399
 400         if (init_ooo_pq) {
 401                 qm_info->ooo_pq = curr_queue;
 402                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 403                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 404                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 405                 curr_queue++;
 406         }
 407
 408         /* Then init per-VF PQs */
 409         vf_offset = curr_queue;
 410         for (i = 0; i < num_vfs; i++) {
 411                 /* First vport is used by the PF */
 412                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 413                 /* @@@TBD VF Multi-cos */
 414                 qm_info->qm_pq_params[curr_queue].tc_id = 0;
 415                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 416                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 417                 curr_queue++;
 418         };
 419
 420         qm_info->vf_queues_offset = vf_offset;
 421         qm_info->num_pqs = num_pqs;
 422         qm_info->num_vports = num_vports;
 423
 424         /* Initialize qm port parameters */
 425         num_ports = p_hwfn->p_dev->num_ports_in_engines;
 426         for (i = 0; i < num_ports; i++) {
 427                 p_qm_port = &qm_info->qm_port_params[i];
 428                 p_qm_port->active = 1;
 429                 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
 430                  * be in place
 431                  */
 432                 if (num_ports == 4)
 433                         p_qm_port->active_phys_tcs = 0xf;
 434                 else
 435                         p_qm_port->active_phys_tcs = 0x9f;
 436                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 437                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 438         }
 439
 440         if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
 441                 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
 442         else
 443                 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 444
 445         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 446
 447         qm_info->num_vf_pqs = num_vfs;
 448         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 449
 450         for (i = 0; i < qm_info->num_vports; i++)
 451                 qm_info->qm_vport_params[i].vport_wfq = 1;
 452
 453         qm_info->vport_rl_en = 1;
 454         qm_info->vport_wfq_en = 1;
 455         qm_info->pf_rl = pf_rl;
 456         qm_info->pf_wfq = pf_wfq;
 457
 458         return ECORE_SUCCESS;
 459
 460  alloc_err:
 461         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 462         ecore_qm_info_free(p_hwfn);
 463         return ECORE_NOMEM;
 464 }
 465
 466 /* This function reconfigures the QM pf on the fly.
 467  * For this purpose we:
 468  * 1. reconfigure the QM database
 469  * 2. set new values to runtime arrat
 470  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 471  * 4. activate init tool in QM_PF stage
 472  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 473  */
 474 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 475                                      struct ecore_ptt *p_ptt)
 476 {
 477         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 478         bool b_rc;
 479         enum _ecore_status_t rc;
 480
 481         /* qm_info is allocated in ecore_init_qm_info() which is already called
 482          * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
 483          * The allocated size may change each init, so we free it before next
 484          * allocation.
 485          */
 486         ecore_qm_info_free(p_hwfn);
 487
 488         /* initialize ecore's qm data structure */
 489         rc = ecore_init_qm_info(p_hwfn, false);
 490         if (rc != ECORE_SUCCESS)
 491                 return rc;
 492
 493         /* stop PF's qm queues */
 494         OSAL_SPIN_LOCK(&qm_lock);
 495         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 496                                       qm_info->start_pq, qm_info->num_pqs);
 497         OSAL_SPIN_UNLOCK(&qm_lock);
 498         if (!b_rc)
 499                 return ECORE_INVAL;
 500
 501         /* clear the QM_PF runtime phase leftovers from previous init */
 502         ecore_init_clear_rt_data(p_hwfn);
 503
 504         /* prepare QM portion of runtime array */
 505         ecore_qm_init_pf(p_hwfn);
 506
 507         /* activate init tool on runtime array */
 508         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 509                             p_hwfn->hw_info.hw_mode);
 510         if (rc != ECORE_SUCCESS)
 511                 return rc;
 512
 513         /* start PF's qm queues */
 514         OSAL_SPIN_LOCK(&qm_lock);
 515         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 516                                       qm_info->start_pq, qm_info->num_pqs);
 517         OSAL_SPIN_UNLOCK(&qm_lock);
 518         if (!b_rc)
 519                 return ECORE_INVAL;
 520
 521         return ECORE_SUCCESS;
 522 }
 523
 524 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 525 {
 526         struct ecore_consq *p_consq;
 527         struct ecore_eq *p_eq;
 528 #ifdef  CONFIG_ECORE_LL2
 529         struct ecore_ll2_info *p_ll2_info;
 530 #endif
 531         enum _ecore_status_t rc = ECORE_SUCCESS;
 532         int i;
 533
 534         if (IS_VF(p_dev))
 535                 return rc;
 536
 537         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 538                                      sizeof(*p_dev->fw_data));
 539         if (!p_dev->fw_data)
 540                 return ECORE_NOMEM;
 541
 542         /* Allocate Memory for the Queue->CID mapping */
 543         for_each_hwfn(p_dev, i) {
 544                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 545
 546                 /* @@@TMP - resc management, change to actual required size */
 547                 int tx_size = sizeof(struct ecore_hw_cid_data) *
 548                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 549                 int rx_size = sizeof(struct ecore_hw_cid_data) *
 550                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 551
 552                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 553                                                 tx_size);
 554                 if (!p_hwfn->p_tx_cids) {
 555                         DP_NOTICE(p_hwfn, true,
 556                                   "Failed to allocate memory for Tx Cids\n");
 557                         goto alloc_no_mem;
 558                 }
 559
 560                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 561                                                 rx_size);
 562                 if (!p_hwfn->p_rx_cids) {
 563                         DP_NOTICE(p_hwfn, true,
 564                                   "Failed to allocate memory for Rx Cids\n");
 565                         goto alloc_no_mem;
 566                 }
 567         }
 568
 569         for_each_hwfn(p_dev, i) {
 570                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 571                 u32 n_eqes, num_cons;
 572
 573                 /* First allocate the context manager structure */
 574                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 575                 if (rc)
 576                         goto alloc_err;
 577
 578                 /* Set the HW cid/tid numbers (in the contest manager)
 579                  * Must be done prior to any further computations.
 580                  */
 581                 rc = ecore_cxt_set_pf_params(p_hwfn);
 582                 if (rc)
 583                         goto alloc_err;
 584
 585                 /* Prepare and process QM requirements */
 586                 rc = ecore_init_qm_info(p_hwfn, true);
 587                 if (rc)
 588                         goto alloc_err;
 589
 590                 /* Compute the ILT client partition */
 591                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 592                 if (rc)
 593                         goto alloc_err;
 594
 595                 /* CID map / ILT shadow table / T2
 596                  * The talbes sizes are determined by the computations above
 597                  */
 598                 rc = ecore_cxt_tables_alloc(p_hwfn);
 599                 if (rc)
 600                         goto alloc_err;
 601
 602                 /* SPQ, must follow ILT because initializes SPQ context */
 603                 rc = ecore_spq_alloc(p_hwfn);
 604                 if (rc)
 605                         goto alloc_err;
 606
 607                 /* SP status block allocation */
 608                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 609                                                            RESERVED_PTT_DPC);
 610
 611                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 612                 if (rc)
 613                         goto alloc_err;
 614
 615                 rc = ecore_iov_alloc(p_hwfn);
 616                 if (rc)
 617                         goto alloc_err;
 618
 619                 /* EQ */
 620                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 621                 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
 622                     (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
 623                         /* Calculate the EQ size
 624                          * ---------------------
 625                          * Each ICID may generate up to one event at a time i.e.
 626                          * the event must be handled/cleared before a new one
 627                          * can be generated. We calculate the sum of events per
 628                          * protocol and create an EQ deep enough to handle the
 629                          * worst case:
 630                          * - Core - according to SPQ.
 631                          * - RoCE - per QP there are a couple of ICIDs, one
 632                          *          responder and one requester, each can
 633                          *          generate an EQE => n_eqes_qp = 2 * n_qp.
 634                          *          Each CQ can generate an EQE. There are 2 CQs
 635                          *          per QP => n_eqes_cq = 2 * n_qp.
 636                          *          Hence the RoCE total is 4 * n_qp or
 637                          *          2 * num_cons.
 638                          * - ENet - There can be up to two events per VF. One
 639                          *          for VF-PF channel and another for VF FLR
 640                          *          initial cleanup. The number of VFs is
 641                          *          bounded by MAX_NUM_VFS_BB, and is much
 642                          *          smaller than RoCE's so we avoid exact
 643                          *          calculation.
 644                          */
 645                         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 646                                 num_cons =
 647                                     ecore_cxt_get_proto_cid_count(
 648                                                 p_hwfn,
 649                                                 PROTOCOLID_ROCE,
 650                                                 0);
 651                                 num_cons *= 2;
 652                         } else {
 653                                 num_cons = ecore_cxt_get_proto_cid_count(
 654                                                 p_hwfn,
 655                                                 PROTOCOLID_IWARP,
 656                                                 0);
 657                         }
 658                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 659                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 660                         num_cons =
 661                             ecore_cxt_get_proto_cid_count(p_hwfn,
 662                                                           PROTOCOLID_ISCSI, 0);
 663                         n_eqes += 2 * num_cons;
 664                 }
 665
 666                 if (n_eqes > 0xFFFF) {
 667                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 668                                        "The maximum of a u16 chain is 0x%x\n",
 669                                n_eqes, 0xFFFF);
 670                         goto alloc_err;
 671                 }
 672
 673                 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 674                 if (!p_eq)
 675                         goto alloc_no_mem;
 676                 p_hwfn->p_eq = p_eq;
 677
 678                 p_consq = ecore_consq_alloc(p_hwfn);
 679                 if (!p_consq)
 680                         goto alloc_no_mem;
 681                 p_hwfn->p_consq = p_consq;
 682
 683 #ifdef CONFIG_ECORE_LL2
 684                 if (p_hwfn->using_ll2) {
 685                         p_ll2_info = ecore_ll2_alloc(p_hwfn);
 686                         if (!p_ll2_info)
 687                                 goto alloc_no_mem;
 688                         p_hwfn->p_ll2_info = p_ll2_info;
 689                 }
 690 #endif
 691
 692                 /* DMA info initialization */
 693                 rc = ecore_dmae_info_alloc(p_hwfn);
 694                 if (rc) {
 695                         DP_NOTICE(p_hwfn, true,
 696                                   "Failed to allocate memory for dmae_info structure\n");
 697                         goto alloc_err;
 698                 }
 699
 700                 /* DCBX initialization */
 701                 rc = ecore_dcbx_info_alloc(p_hwfn);
 702                 if (rc) {
 703                         DP_NOTICE(p_hwfn, true,
 704                                   "Failed to allocate memory for dcbx structure\n");
 705                         goto alloc_err;
 706                 }
 707         }
 708
 709         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 710                                          sizeof(struct ecore_eth_stats));
 711         if (!p_dev->reset_stats) {
 712                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 713                 goto alloc_no_mem;
 714         }
 715
 716         return ECORE_SUCCESS;
 717
 718  alloc_no_mem:
 719         rc = ECORE_NOMEM;
 720  alloc_err:
 721         ecore_resc_free(p_dev);
 722         return rc;
 723 }
 724
 725 void ecore_resc_setup(struct ecore_dev *p_dev)
 726 {
 727         int i;
 728
 729         if (IS_VF(p_dev))
 730                 return;
 731
 732         for_each_hwfn(p_dev, i) {
 733                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 734
 735                 ecore_cxt_mngr_setup(p_hwfn);
 736                 ecore_spq_setup(p_hwfn);
 737                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
 738                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
 739
 740                 /* Read shadow of current MFW mailbox */
 741                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 742                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
 743                             p_hwfn->mcp_info->mfw_mb_cur,
 744                             p_hwfn->mcp_info->mfw_mb_length);
 745
 746                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 747
 748                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 749 #ifdef CONFIG_ECORE_LL2
 750                 if (p_hwfn->using_ll2)
 751                         ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
 752 #endif
 753         }
 754 }
 755
 756 #define FINAL_CLEANUP_POLL_CNT  (100)
 757 #define FINAL_CLEANUP_POLL_TIME (10)
 758 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
 759                                          struct ecore_ptt *p_ptt,
 760                                          u16 id, bool is_vf)
 761 {
 762         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 763         enum _ecore_status_t rc = ECORE_TIMEOUT;
 764
 765 #ifndef ASIC_ONLY
 766         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
 767             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 768                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
 769                 return ECORE_SUCCESS;
 770         }
 771 #endif
 772
 773         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 774             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 775
 776         if (is_vf)
 777                 id += 0x10;
 778
 779         command |= X_FINAL_CLEANUP_AGG_INT <<
 780             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 781         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 782         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 783         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 784
 785 /* Make sure notification is not set before initiating final cleanup */
 786
 787         if (REG_RD(p_hwfn, addr)) {
 788                 DP_NOTICE(p_hwfn, false,
 789                           "Unexpected; Found final cleanup notification");
 790                 DP_NOTICE(p_hwfn, false,
 791                           " before initiating final cleanup\n");
 792                 REG_WR(p_hwfn, addr, 0);
 793         }
 794
 795         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
 796                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 797                    id, OSAL_CPU_TO_LE32(command));
 798
 799         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
 800                  OSAL_CPU_TO_LE32(command));
 801
 802         /* Poll until completion */
 803         while (!REG_RD(p_hwfn, addr) && count--)
 804                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
 805
 806         if (REG_RD(p_hwfn, addr))
 807                 rc = ECORE_SUCCESS;
 808         else
 809                 DP_NOTICE(p_hwfn, true,
 810                           "Failed to receive FW final cleanup notification\n");
 811
 812         /* Cleanup afterwards */
 813         REG_WR(p_hwfn, addr, 0);
 814
 815         return rc;
 816 }
 817
 818 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
 819 {
 820         int hw_mode = 0;
 821
 822         if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
 823                 hw_mode |= 1 << MODE_BB_A0;
 824         } else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
 825                 hw_mode |= 1 << MODE_BB_B0;
 826         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
 827                 hw_mode |= 1 << MODE_K2;
 828         } else {
 829                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
 830                           p_hwfn->p_dev->type);
 831                 return ECORE_INVAL;
 832         }
 833
 834         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
 835         switch (p_hwfn->p_dev->num_ports_in_engines) {
 836         case 1:
 837                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 838                 break;
 839         case 2:
 840                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 841                 break;
 842         case 4:
 843                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 844                 break;
 845         default:
 846                 DP_NOTICE(p_hwfn, true,
 847                           "num_ports_in_engine = %d not supported\n",
 848                           p_hwfn->p_dev->num_ports_in_engines);
 849                 return ECORE_INVAL;
 850         }
 851
 852         switch (p_hwfn->p_dev->mf_mode) {
 853         case ECORE_MF_DEFAULT:
 854         case ECORE_MF_NPAR:
 855                 hw_mode |= 1 << MODE_MF_SI;
 856                 break;
 857         case ECORE_MF_OVLAN:
 858                 hw_mode |= 1 << MODE_MF_SD;
 859                 break;
 860         default:
 861                 DP_NOTICE(p_hwfn, true,
 862                           "Unsupported MF mode, init as DEFAULT\n");
 863                 hw_mode |= 1 << MODE_MF_SI;
 864         }
 865
 866 #ifndef ASIC_ONLY
 867         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 868                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 869                         hw_mode |= 1 << MODE_FPGA;
 870                 } else {
 871                         if (p_hwfn->p_dev->b_is_emul_full)
 872                                 hw_mode |= 1 << MODE_EMUL_FULL;
 873                         else
 874                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
 875                 }
 876         } else
 877 #endif
 878                 hw_mode |= 1 << MODE_ASIC;
 879
 880 #ifndef REAL_ASIC_ONLY
 881         if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn))
 882                 hw_mode |= 1 << MODE_EAGLE_ENG1_WORKAROUND;
 883 #endif
 884
 885         if (p_hwfn->p_dev->num_hwfns > 1)
 886                 hw_mode |= 1 << MODE_100G;
 887
 888         p_hwfn->hw_info.hw_mode = hw_mode;
 889
 890         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
 891                    "Configuring function for hw_mode: 0x%08x\n",
 892                    p_hwfn->hw_info.hw_mode);
 893
 894         return ECORE_SUCCESS;
 895 }
 896
 897 #ifndef ASIC_ONLY
 898 /* MFW-replacement initializations for non-ASIC */
 899 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
 900                                                struct ecore_ptt *p_ptt)
 901 {
 902         u32 pl_hv = 1;
 903         int i;
 904
 905         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 906                 pl_hv |= 0x600;
 907
 908         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
 909
 910         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 911                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
 912
 913         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
 914         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
 915         if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
 916                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
 917
 918         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
 919                 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
 920                 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
 921                          (p_hwfn->p_dev->num_ports_in_engines >> 1));
 922
 923                 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
 924                          p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
 925         }
 926
 927         /* Poll on RBC */
 928         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
 929         for (i = 0; i < 100; i++) {
 930                 OSAL_UDELAY(50);
 931                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
 932                         break;
 933         }
 934         if (i == 100)
 935                 DP_NOTICE(p_hwfn, true,
 936                           "RBC done failed to complete in PSWRQ2\n");
 937
 938         return ECORE_SUCCESS;
 939 }
 940 #endif
 941
 942 /* Init run time data for all PFs and their VFs on an engine.
 943  * TBD - for VFs - Once we have parent PF info for each VF in
 944  * shmem available as CAU requires knowledge of parent PF for each VF.
 945  */
 946 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
 947 {
 948         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 949         int i, sb_id;
 950
 951         for_each_hwfn(p_dev, i) {
 952                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 953                 struct ecore_igu_info *p_igu_info;
 954                 struct ecore_igu_block *p_block;
 955                 struct cau_sb_entry sb_entry;
 956
 957                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 958
 959                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
 960                      sb_id++) {
 961                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 962
 963                         if (!p_block->is_pf)
 964                                 continue;
 965
 966                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
 967                                                 p_block->function_id, 0, 0);
 968                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 969                 }
 970         }
 971 }
 972
 973 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
 974                                                  struct ecore_ptt *p_ptt,
 975                                                  int hw_mode)
 976 {
 977         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 978         struct ecore_dev *p_dev = p_hwfn->p_dev;
 979         u8 vf_id, max_num_vfs;
 980         u16 num_pfs, pf_id;
 981         u32 concrete_fid;
 982         enum _ecore_status_t rc = ECORE_SUCCESS;
 983
 984         ecore_init_cau_rt_data(p_dev);
 985
 986         /* Program GTT windows */
 987         ecore_gtt_init(p_hwfn);
 988
 989 #ifndef ASIC_ONLY
 990         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 991                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
 992                 if (rc != ECORE_SUCCESS)
 993                         return rc;
 994         }
 995 #endif
 996
 997         if (p_hwfn->mcp_info) {
 998                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 999                         qm_info->pf_rl_en = 1;
1000                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1001                         qm_info->pf_wfq_en = 1;
1002         }
1003
1004         ecore_qm_common_rt_init(p_hwfn,
1005                                 p_hwfn->p_dev->num_ports_in_engines,
1006                                 qm_info->max_phys_tcs_per_port,
1007                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1008                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1009                                 qm_info->qm_port_params);
1010
1011         ecore_cxt_hw_init_common(p_hwfn);
1012
1013         /* Close gate from NIG to BRB/Storm; By default they are open, but
1014          * we close them to prevent NIG from passing data to reset blocks.
1015          * Should have been done in the ENGINE phase, but init-tool lacks
1016          * proper port-pretend capabilities.
1017          */
1018         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1019         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1020         ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1021         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1022         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1023         ecore_port_unpretend(p_hwfn, p_ptt);
1024
1025         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1026         if (rc != ECORE_SUCCESS)
1027                 return rc;
1028
1029         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1030          * need to decide with which value, maybe runtime
1031          */
1032         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1033         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1034
1035         if (ECORE_IS_BB(p_hwfn->p_dev)) {
1036                 /* Workaround clears ROCE search for all functions to prevent
1037                  * involving non initialized function in processing ROCE packet.
1038                  */
1039                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1040                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1041                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1042                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1043                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1044                 }
1045                 /* pretend to original PF */
1046                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1047         }
1048
1049         /* Workaround for avoiding CCFC execution error when getting packets
1050          * with CRC errors, and allowing instead the invoking of the FW error
1051          * handler.
1052          * This is not done inside the init tool since it currently can't
1053          * perform a pretending to VFs.
1054          */
1055         max_num_vfs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_VFS_K2
1056             : MAX_NUM_VFS_BB;
1057         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1058                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1059                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1060                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1061                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1062                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1063                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1064         }
1065         /* pretend to original PF */
1066         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1067
1068         return rc;
1069 }
1070
1071 #ifndef ASIC_ONLY
1072 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1073 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1074
1075 #define PMEG_IF_BYTE_COUNT      8
1076
1077 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1078                              struct ecore_ptt *p_ptt,
1079                              u32 addr, u64 data, u8 reg_type, u8 port)
1080 {
1081         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1082                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1083                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
1084                    (8 << PMEG_IF_BYTE_COUNT),
1085                    (reg_type << 25) | (addr << 8) | port,
1086                    (u32)((data >> 32) & 0xffffffff),
1087                    (u32)(data & 0xffffffff));
1088
1089         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
1090                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
1091                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1092         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
1093                  (reg_type << 25) | (addr << 8) | port);
1094         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1095                  data & 0xffffffff);
1096         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1097                  (data >> 32) & 0xffffffff);
1098 }
1099
1100 #define XLPORT_MODE_REG (0x20a)
1101 #define XLPORT_MAC_CONTROL (0x210)
1102 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1103 #define XLPORT_ENABLE_REG (0x20b)
1104
1105 #define XLMAC_CTRL (0x600)
1106 #define XLMAC_MODE (0x601)
1107 #define XLMAC_RX_MAX_SIZE (0x608)
1108 #define XLMAC_TX_CTRL (0x604)
1109 #define XLMAC_PAUSE_CTRL (0x60d)
1110 #define XLMAC_PFC_CTRL (0x60e)
1111
1112 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
1113                                     struct ecore_ptt *p_ptt)
1114 {
1115         u8 port = p_hwfn->port_id;
1116         u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
1117
1118         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
1119                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
1120                  (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
1121                  | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
1122
1123         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
1124                  1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
1125
1126         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
1127                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
1128
1129         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
1130                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
1131
1132         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
1133                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
1134
1135         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
1136                  (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
1137                  (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
1138
1139         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
1140 }
1141
1142 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1143                                  struct ecore_ptt *p_ptt)
1144 {
1145         u8 loopback = 0, port = p_hwfn->port_id * 2;
1146
1147         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1148
1149         if (ECORE_IS_AH(p_hwfn->p_dev)) {
1150                 ecore_emul_link_init_ah(p_hwfn, p_ptt);
1151                 return;
1152         }
1153
1154         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1155         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1156                          port);
1157         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1158         /* XLMAC: SOFT RESET */
1159         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1160         /* XLMAC: Port Speed >= 10Gbps */
1161         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1162         /* XLMAC: Max Size */
1163         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1164         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1165                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1166                          0, port);
1167         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1168         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1169                          0x30ffffc000ULL, 0, port);
1170         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1171                          port); /* XLMAC: TX_EN, RX_EN */
1172         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1173         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1174                          0x1003 | (loopback << 2), 0, port);
1175         /* Enabled Parallel PFC interface */
1176         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1177
1178         /* XLPORT port enable */
1179         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1180 }
1181
1182 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
1183                             struct ecore_ptt *p_ptt, u8 port)
1184 {
1185         int port_offset = port ? 0x800 : 0;
1186         u32 xmac_rxctrl = 0;
1187
1188         /* Reset of XMAC */
1189         /* FIXME: move to common start */
1190         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1191                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1192         OSAL_MSLEEP(1);
1193         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1194                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1195
1196         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1197
1198         /* Set the number of ports on the Warp Core to 10G */
1199         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1200
1201         /* Soft reset of XMAC */
1202         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1203                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1204         OSAL_MSLEEP(1);
1205         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1206                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1207
1208         /* FIXME: move to common end */
1209         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1210                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
1211
1212         /* Set Max packet size: initialize XMAC block register for port 0 */
1213         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
1214
1215         /* CRC append for Tx packets: init XMAC block register for port 1 */
1216         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
1217
1218         /* Enable TX and RX: initialize XMAC block register for port 1 */
1219         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
1220                  XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
1221         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
1222         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
1223         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
1224 }
1225 #endif
1226
1227 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1228                                                struct ecore_ptt *p_ptt,
1229                                                int hw_mode)
1230 {
1231         enum _ecore_status_t rc = ECORE_SUCCESS;
1232
1233         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1234                             hw_mode);
1235         if (rc != ECORE_SUCCESS)
1236                 return rc;
1237 #ifndef ASIC_ONLY
1238         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1239                 return ECORE_SUCCESS;
1240
1241         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1242                 if (ECORE_IS_AH(p_hwfn->p_dev))
1243                         return ECORE_SUCCESS;
1244                 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1245         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1246                 if (p_hwfn->p_dev->num_hwfns > 1) {
1247                         /* Activate OPTE in CMT */
1248                         u32 val;
1249
1250                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1251                         val |= 0x10;
1252                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1253                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1254                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1255                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1256                         ecore_wr(p_hwfn, p_ptt,
1257                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1258                         ecore_wr(p_hwfn, p_ptt,
1259                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1260                         ecore_wr(p_hwfn, p_ptt,
1261                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1262                                  0x55555555);
1263                 }
1264
1265                 ecore_emul_link_init(p_hwfn, p_ptt);
1266         } else {
1267                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1268         }
1269 #endif
1270
1271         return rc;
1272 }
1273
1274 static enum _ecore_status_t
1275 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1276                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1277 {
1278         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1279         u32 dpi_bit_shift, dpi_count;
1280         u32 min_dpis;
1281
1282         /* Calculate DPI size
1283          * ------------------
1284          * The PWM region contains Doorbell Pages. The first is reserverd for
1285          * the kernel for, e.g, L2. The others are free to be used by non-
1286          * trusted applications, typically from user space. Each page, called a
1287          * doorbell page is sectioned into windows that allow doorbells to be
1288          * issued in parallel by the kernel/application. The size of such a
1289          * window (a.k.a. WID) is 1kB.
1290          * Summary:
1291          *    1kB WID x N WIDS = DPI page size
1292          *    DPI page size x N DPIs = PWM region size
1293          * Notes:
1294          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1295          * in order to ensure that two applications won't share the same page.
1296          * It also must contain at least one WID per CPU to allow parallelism.
1297          * It also must be a power of 2, since it is stored as a bit shift.
1298          *
1299          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1300          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1301          * containing 4 WIDs.
1302          */
1303         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1304         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1305         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1306         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1307         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1308
1309         dpi_count = pwm_region_size / dpi_page_size;
1310
1311         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1312         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1313
1314         /* Update hwfn */
1315         p_hwfn->dpi_size = dpi_page_size;
1316         p_hwfn->dpi_count = dpi_count;
1317
1318         /* Update registers */
1319         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1320
1321         if (dpi_count < min_dpis)
1322                 return ECORE_NORESOURCES;
1323
1324         return ECORE_SUCCESS;
1325 }
1326
1327 enum ECORE_ROCE_EDPM_MODE {
1328         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1329         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1330         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1331 };
1332
1333 static enum _ecore_status_t
1334 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1335                               struct ecore_ptt *p_ptt)
1336 {
1337         u32 pwm_regsize, norm_regsize;
1338         u32 non_pwm_conn, min_addr_reg1;
1339         u32 db_bar_size, n_cpus;
1340         u32 roce_edpm_mode;
1341         u32 pf_dems_shift;
1342         int rc = ECORE_SUCCESS;
1343         u8 cond;
1344
1345         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1346         if (p_hwfn->p_dev->num_hwfns > 1)
1347                 db_bar_size /= 2;
1348
1349         /* Calculate doorbell regions
1350          * -----------------------------------
1351          * The doorbell BAR is made of two regions. The first is called normal
1352          * region and the second is called PWM region. In the normal region
1353          * each ICID has its own set of addresses so that writing to that
1354          * specific address identifies the ICID. In the Process Window Mode
1355          * region the ICID is given in the data written to the doorbell. The
1356          * above per PF register denotes the offset in the doorbell BAR in which
1357          * the PWM region begins.
1358          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1359          * non-PWM connection. The calculation below computes the total non-PWM
1360          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1361          * in units of 4,096 bytes.
1362          */
1363         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1364             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1365                                           OSAL_NULL) +
1366             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1367         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1368         min_addr_reg1 = norm_regsize / 4096;
1369         pwm_regsize = db_bar_size - norm_regsize;
1370
1371         /* Check that the normal and PWM sizes are valid */
1372         if (db_bar_size < norm_regsize) {
1373                 DP_ERR(p_hwfn->p_dev,
1374                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1375                        db_bar_size, norm_regsize);
1376                 return ECORE_NORESOURCES;
1377         }
1378         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1379                 DP_ERR(p_hwfn->p_dev,
1380                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1381                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1382                        norm_regsize);
1383                 return ECORE_NORESOURCES;
1384         }
1385
1386         /* Calculate number of DPIs */
1387         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1388         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1389             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1390                 /* Either EDPM is mandatory, or we are attempting to allocate a
1391                  * WID per CPU.
1392                  */
1393                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1394                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1395         }
1396
1397         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1398             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1399         if (cond || p_hwfn->dcbx_no_edpm) {
1400                 /* Either EDPM is disabled from user configuration, or it is
1401                  * disabled via DCBx, or it is not mandatory and we failed to
1402                  * allocated a WID per CPU.
1403                  */
1404                 n_cpus = 1;
1405                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1406
1407                 /* If we entered this flow due to DCBX then the DPM register is
1408                  * already configured.
1409                  */
1410         }
1411
1412         DP_INFO(p_hwfn,
1413                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1414                 norm_regsize, pwm_regsize);
1415         DP_INFO(p_hwfn,
1416                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1417                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1418                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1419                 "disabled" : "enabled");
1420
1421         /* Check return codes from above calls */
1422         if (rc) {
1423                 DP_ERR(p_hwfn,
1424                        "Failed to allocate enough DPIs\n");
1425                 return ECORE_NORESOURCES;
1426         }
1427
1428         /* Update hwfn */
1429         p_hwfn->dpi_start_offset = norm_regsize;
1430
1431         /* Update registers */
1432         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1433         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1434         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1435         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1436
1437         return ECORE_SUCCESS;
1438 }
1439
1440 static enum _ecore_status_t
1441 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1442                  struct ecore_ptt *p_ptt,
1443                  struct ecore_tunn_start_params *p_tunn,
1444                  int hw_mode,
1445                  bool b_hw_start,
1446                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1447 {
1448         u8 rel_pf_id = p_hwfn->rel_pf_id;
1449         u32 prs_reg;
1450         enum _ecore_status_t rc = ECORE_SUCCESS;
1451         u16 ctrl;
1452         int pos;
1453
1454         if (p_hwfn->mcp_info) {
1455                 struct ecore_mcp_function_info *p_info;
1456
1457                 p_info = &p_hwfn->mcp_info->func_info;
1458                 if (p_info->bandwidth_min)
1459                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1460
1461                 /* Update rate limit once we'll actually have a link */
1462                 p_hwfn->qm_info.pf_rl = 100000;
1463         }
1464         ecore_cxt_hw_init_pf(p_hwfn);
1465
1466         ecore_int_igu_init_rt(p_hwfn);
1467
1468         /* Set VLAN in NIG if needed */
1469         if (hw_mode & (1 << MODE_MF_SD)) {
1470                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1471                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1472                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1473                              p_hwfn->hw_info.ovlan);
1474         }
1475
1476         /* Enable classification by MAC if needed */
1477         if (hw_mode & (1 << MODE_MF_SI)) {
1478                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1479                            "Configuring TAGMAC_CLS_TYPE\n");
1480                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1481                              1);
1482         }
1483
1484         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1485         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1486                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1487         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1488                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1489         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1490
1491         /* perform debug configuration when chip is out of reset */
1492         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1493
1494         /* Cleanup chip from previous driver if such remains exist */
1495         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1496         if (rc != ECORE_SUCCESS) {
1497                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1498                 return rc;
1499         }
1500
1501         /* PF Init sequence */
1502         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1503         if (rc)
1504                 return rc;
1505
1506         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1507         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1508         if (rc)
1509                 return rc;
1510
1511         /* Pure runtime initializations - directly to the HW  */
1512         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1513
1514         /* PCI relaxed ordering causes a decrease in the performance on some
1515          * systems. Till a root cause is found, disable this attribute in the
1516          * PCI config space.
1517          */
1518         /* Not in use @DPDK
1519         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1520         * if (!pos) {
1521         *       DP_NOTICE(p_hwfn, true,
1522         *                 "Failed to find the PCIe Cap\n");
1523         *       return ECORE_IO;
1524         * }
1525         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1526         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1527         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1528         */
1529
1530         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1531         if (rc)
1532                 return rc;
1533         if (b_hw_start) {
1534                 /* enable interrupts */
1535                 ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1536
1537                 /* send function start command */
1538                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1539                                        allow_npar_tx_switch);
1540                 if (rc) {
1541                         DP_NOTICE(p_hwfn, true,
1542                                   "Function start ramrod failed\n");
1543                 } else {
1544                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1545                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1546                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1547
1548                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1549                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1550                                          (1 << 2));
1551                                 ecore_wr(p_hwfn, p_ptt,
1552                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1553                                     0x100);
1554                         }
1555                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1556                                    "PRS_REG_SEARCH registers after start PFn\n");
1557                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1558                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1559                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1560                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1561                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1562                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1563                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1564                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1565                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1566                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1567                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1568                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1569                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1570                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1571                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1572                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1573                                    prs_reg);
1574                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1575                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1576                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1577                 }
1578         }
1579         return rc;
1580 }
1581
1582 static enum _ecore_status_t
1583 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1584                       struct ecore_ptt *p_ptt, u8 enable)
1585 {
1586         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1587
1588         /* Change PF in PXP */
1589         ecore_wr(p_hwfn, p_ptt,
1590                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1591
1592         /* wait until value is set - try for 1 second every 50us */
1593         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1594                 val = ecore_rd(p_hwfn, p_ptt,
1595                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1596                 if (val == set_val)
1597                         break;
1598
1599                 OSAL_UDELAY(50);
1600         }
1601
1602         if (val != set_val) {
1603                 DP_NOTICE(p_hwfn, true,
1604                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1605                 return ECORE_UNKNOWN_ERROR;
1606         }
1607
1608         return ECORE_SUCCESS;
1609 }
1610
1611 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1612                                   struct ecore_ptt *p_main_ptt)
1613 {
1614         /* Read shadow of current MFW mailbox */
1615         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1616         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1617                     p_hwfn->mcp_info->mfw_mb_cur,
1618                     p_hwfn->mcp_info->mfw_mb_length);
1619 }
1620
1621 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1622                                    struct ecore_tunn_start_params *p_tunn,
1623                                    bool b_hw_start,
1624                                    enum ecore_int_mode int_mode,
1625                                    bool allow_npar_tx_switch,
1626                                    const u8 *bin_fw_data)
1627 {
1628         enum _ecore_status_t rc, mfw_rc;
1629         u32 load_code, param;
1630         int i, j;
1631
1632         if ((int_mode == ECORE_INT_MODE_MSI) && (p_dev->num_hwfns > 1)) {
1633                 DP_NOTICE(p_dev, false,
1634                           "MSI mode is not supported for CMT devices\n");
1635                 return ECORE_INVAL;
1636         }
1637
1638         if (IS_PF(p_dev)) {
1639                 rc = ecore_init_fw_data(p_dev, bin_fw_data);
1640                 if (rc != ECORE_SUCCESS)
1641                         return rc;
1642         }
1643
1644         for_each_hwfn(p_dev, i) {
1645                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1646
1647                 if (IS_VF(p_dev)) {
1648                         p_hwfn->b_int_enabled = 1;
1649                         continue;
1650                 }
1651
1652                 /* Enable DMAE in PXP */
1653                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1654                 if (rc != ECORE_SUCCESS)
1655                         return rc;
1656
1657                 rc = ecore_calc_hw_mode(p_hwfn);
1658                 if (rc != ECORE_SUCCESS)
1659                         return rc;
1660
1661                 /* @@@TBD need to add here:
1662                  * Check for fan failure
1663                  * Prev_unload
1664                  */
1665                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1666                 if (rc) {
1667                         DP_NOTICE(p_hwfn, true,
1668                                   "Failed sending LOAD_REQ command\n");
1669                         return rc;
1670                 }
1671
1672                 /* CQ75580:
1673                  * When coming back from hiberbate state, the registers from
1674                  * which shadow is read initially are not initialized. It turns
1675                  * out that these registers get initialized during the call to
1676                  * ecore_mcp_load_req request. So we need to reread them here
1677                  * to get the proper shadow register value.
1678                  * Note: This is a workaround for the missinginig MFW
1679                  * initialization. It may be removed once the implementation
1680                  * is done.
1681                  */
1682                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1683
1684                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1685                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1686                            rc, load_code);
1687
1688                 /* Only relevant for recovery:
1689                  * Clear the indication after the LOAD_REQ command is responded
1690                  * by the MFW.
1691                  */
1692                 p_dev->recov_in_prog = false;
1693
1694                 p_hwfn->first_on_engine = (load_code ==
1695                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1696
1697                 if (!qm_lock_init) {
1698                         OSAL_SPIN_LOCK_INIT(&qm_lock);
1699                         qm_lock_init = true;
1700                 }
1701
1702                 switch (load_code) {
1703                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1704                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1705                                                   p_hwfn->hw_info.hw_mode);
1706                         if (rc)
1707                                 break;
1708                         /* Fall into */
1709                 case FW_MSG_CODE_DRV_LOAD_PORT:
1710                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1711                                                 p_hwfn->hw_info.hw_mode);
1712                         if (rc)
1713                                 break;
1714
1715 #ifndef REAL_ASIC_ONLY
1716                         if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
1717                                 struct init_nig_pri_tc_map_req tc_map;
1718
1719                                 OSAL_MEM_ZERO(&tc_map, sizeof(tc_map));
1720
1721                                 /* remove this once flow control is
1722                                  * implemented
1723                                  */
1724                                 for (j = 0; j < NUM_OF_VLAN_PRIORITIES; j++) {
1725                                         tc_map.pri[j].tc_id = 0;
1726                                         tc_map.pri[j].valid = 1;
1727                                 }
1728                                 ecore_init_nig_pri_tc_map(p_hwfn,
1729                                                           p_hwfn->p_main_ptt,
1730                                                           &tc_map);
1731                         }
1732 #endif
1733                         /* Fall into */
1734                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1735                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1736                                               p_tunn, p_hwfn->hw_info.hw_mode,
1737                                               b_hw_start, int_mode,
1738                                               allow_npar_tx_switch);
1739                         break;
1740                 default:
1741                         rc = ECORE_NOTIMPL;
1742                         break;
1743                 }
1744
1745                 if (rc != ECORE_SUCCESS)
1746                         DP_NOTICE(p_hwfn, true,
1747                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1748                                   load_code, rc);
1749
1750                 /* ACK mfw regardless of success or failure of initialization */
1751                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1752                                        DRV_MSG_CODE_LOAD_DONE,
1753                                        0, &load_code, &param);
1754                 if (rc != ECORE_SUCCESS)
1755                         return rc;
1756                 if (mfw_rc != ECORE_SUCCESS) {
1757                         DP_NOTICE(p_hwfn, true,
1758                                   "Failed sending LOAD_DONE command\n");
1759                         return mfw_rc;
1760                 }
1761
1762                 /* send DCBX attention request command */
1763                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1764                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1765                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1766                                        DRV_MSG_CODE_SET_DCBX,
1767                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1768                                        &load_code, &param);
1769                 if (mfw_rc != ECORE_SUCCESS) {
1770                         DP_NOTICE(p_hwfn, true,
1771                                   "Failed to send DCBX attention request\n");
1772                         return mfw_rc;
1773                 }
1774
1775                 p_hwfn->hw_init_done = true;
1776         }
1777
1778         return ECORE_SUCCESS;
1779 }
1780
1781 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
1782 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1783                                  struct ecore_hwfn *p_hwfn,
1784                                  struct ecore_ptt *p_ptt)
1785 {
1786         int i;
1787
1788         /* close timers */
1789         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1790         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1791         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1792                                                                         i++) {
1793                 if ((!ecore_rd(p_hwfn, p_ptt,
1794                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1795                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1796                         break;
1797
1798                 /* Dependent on number of connection/tasks, possibly
1799                  * 1ms sleep is required between polls
1800                  */
1801                 OSAL_MSLEEP(1);
1802         }
1803         if (i == ECORE_HW_STOP_RETRY_LIMIT)
1804                 DP_NOTICE(p_hwfn, true,
1805                           "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1806                           (u8)ecore_rd(p_hwfn, p_ptt,
1807                                         TM_REG_PF_SCAN_ACTIVE_CONN),
1808                           (u8)ecore_rd(p_hwfn, p_ptt,
1809                                         TM_REG_PF_SCAN_ACTIVE_TASK));
1810 }
1811
1812 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1813 {
1814         int j;
1815
1816         for_each_hwfn(p_dev, j) {
1817                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1818                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1819
1820                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1821         }
1822 }
1823
1824 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1825 {
1826         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1827         int j;
1828
1829         for_each_hwfn(p_dev, j) {
1830                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1831                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1832
1833                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1834
1835                 if (IS_VF(p_dev)) {
1836                         ecore_vf_pf_int_cleanup(p_hwfn);
1837                         continue;
1838                 }
1839
1840                 /* mark the hw as uninitialized... */
1841                 p_hwfn->hw_init_done = false;
1842
1843                 rc = ecore_sp_pf_stop(p_hwfn);
1844                 if (rc)
1845                         DP_NOTICE(p_hwfn, true,
1846                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1847
1848                 /* perform debug action after PF stop was sent */
1849                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1850
1851                 /* close NIG to BRB gate */
1852                 ecore_wr(p_hwfn, p_ptt,
1853                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1854
1855                 /* close parser */
1856                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1857                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1858                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1859                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1860                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1861
1862                 /* @@@TBD - clean transmission queues (5.b) */
1863                 /* @@@TBD - clean BTB (5.c) */
1864
1865                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1866
1867                 /* @@@TBD - verify DMAE requests are done (8) */
1868
1869                 /* Disable Attention Generation */
1870                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1871                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1872                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1873                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1874                 /* Need to wait 1ms to guarantee SBs are cleared */
1875                 OSAL_MSLEEP(1);
1876         }
1877
1878         if (IS_PF(p_dev)) {
1879                 /* Disable DMAE in PXP - in CMT, this should only be done for
1880                  * first hw-function, and only after all transactions have
1881                  * stopped for all active hw-functions.
1882                  */
1883                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1884                                              p_dev->hwfns[0].p_main_ptt, false);
1885                 if (t_rc != ECORE_SUCCESS)
1886                         rc = t_rc;
1887         }
1888
1889         return rc;
1890 }
1891
1892 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1893 {
1894         int j;
1895
1896         for_each_hwfn(p_dev, j) {
1897                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1898                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1899
1900                 if (IS_VF(p_dev)) {
1901                         ecore_vf_pf_int_cleanup(p_hwfn);
1902                         continue;
1903                 }
1904
1905                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1906                            "Shutting down the fastpath\n");
1907
1908                 ecore_wr(p_hwfn, p_ptt,
1909                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1910
1911                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1912                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1913                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1914                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1915                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1916
1917                 /* @@@TBD - clean transmission queues (5.b) */
1918                 /* @@@TBD - clean BTB (5.c) */
1919
1920                 /* @@@TBD - verify DMAE requests are done (8) */
1921
1922                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1923                 /* Need to wait 1ms to guarantee SBs are cleared */
1924                 OSAL_MSLEEP(1);
1925         }
1926 }
1927
1928 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1929 {
1930         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1931
1932         if (IS_VF(p_hwfn->p_dev))
1933                 return;
1934
1935         /* If roce info is allocated it means roce is initialized and should
1936          * be enabled in searcher.
1937          */
1938         if (p_hwfn->p_rdma_info) {
1939                 if (p_hwfn->b_rdma_enabled_in_prs)
1940                         ecore_wr(p_hwfn, p_ptt,
1941                                  p_hwfn->rdma_prs_search_reg, 0x1);
1942                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1943         }
1944
1945         /* Re-open incoming traffic */
1946         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1947                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1948 }
1949
1950 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1951                                              struct ecore_ptt *p_ptt, u32 reg,
1952                                              bool expected)
1953 {
1954         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1955
1956         if (assert_val != expected) {
1957                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1958                           reg, expected);
1959                 return ECORE_UNKNOWN_ERROR;
1960         }
1961
1962         return 0;
1963 }
1964
1965 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1966 {
1967         enum _ecore_status_t rc = ECORE_SUCCESS;
1968         u32 unload_resp, unload_param;
1969         int i;
1970
1971         for_each_hwfn(p_dev, i) {
1972                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1973
1974                 if (IS_VF(p_dev)) {
1975                         rc = ecore_vf_pf_reset(p_hwfn);
1976                         if (rc)
1977                                 return rc;
1978                         continue;
1979                 }
1980
1981                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1982
1983                 /* Check for incorrect states */
1984                 if (!p_dev->recov_in_prog) {
1985                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1986                                          QM_REG_USG_CNT_PF_TX, 0);
1987                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1988                                          QM_REG_USG_CNT_PF_OTHER, 0);
1989                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
1990                 }
1991
1992                 /* Disable PF in HW blocks */
1993                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1994                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1995
1996                 if (p_dev->recov_in_prog) {
1997                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1998                                    "Recovery is in progress -> skip sending unload_req/done\n");
1999                         break;
2000                 }
2001
2002                 /* Send unload command to MCP */
2003                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2004                                    DRV_MSG_CODE_UNLOAD_REQ,
2005                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
2006                                    &unload_resp, &unload_param);
2007                 if (rc != ECORE_SUCCESS) {
2008                         DP_NOTICE(p_hwfn, true,
2009                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
2010                         /* @@TBD - what to do? for now, assume ENG. */
2011                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2012                 }
2013
2014                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2015                                    DRV_MSG_CODE_UNLOAD_DONE,
2016                                    0, &unload_resp, &unload_param);
2017                 if (rc != ECORE_SUCCESS) {
2018                         DP_NOTICE(p_hwfn,
2019                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2020                         /* @@@TBD - Should it really ASSERT here ? */
2021                         return rc;
2022                 }
2023         }
2024
2025         return rc;
2026 }
2027
2028 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2029 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2030 {
2031         ecore_ptt_pool_free(p_hwfn);
2032         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2033 }
2034
2035 /* Setup bar access */
2036 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2037 {
2038         /* clear indirect access */
2039         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2040                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2041                          PGLUE_B_REG_PGL_ADDR_E8_F0, 0);
2042                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2043                          PGLUE_B_REG_PGL_ADDR_EC_F0, 0);
2044                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2045                          PGLUE_B_REG_PGL_ADDR_F0_F0, 0);
2046                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2047                          PGLUE_B_REG_PGL_ADDR_F4_F0, 0);
2048         } else {
2049                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2050                          PGLUE_B_REG_PGL_ADDR_88_F0, 0);
2051                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2052                          PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
2053                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2054                          PGLUE_B_REG_PGL_ADDR_90_F0, 0);
2055                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2056                          PGLUE_B_REG_PGL_ADDR_94_F0, 0);
2057         }
2058
2059         /* Clean Previous errors if such exist */
2060         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2061                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2062
2063         /* enable internal target-read */
2064         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2065                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2066 }
2067
2068 static void get_function_id(struct ecore_hwfn *p_hwfn)
2069 {
2070         /* ME Register */
2071         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2072                                                   PXP_PF_ME_OPAQUE_ADDR);
2073
2074         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2075
2076         /* Bits 16-19 from the ME registers are the pf_num */
2077         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2078         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2079                                       PXP_CONCRETE_FID_PFID);
2080         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2081                                     PXP_CONCRETE_FID_PORT);
2082
2083         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2084                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2085                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2086 }
2087
2088 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2089 {
2090         u32 *feat_num = p_hwfn->hw_info.feat_num;
2091         int num_features = 1;
2092
2093         /* L2 Queues require each: 1 status block. 1 L2 queue */
2094         feat_num[ECORE_PF_L2_QUE] =
2095             OSAL_MIN_T(u32,
2096                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2097                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2098
2099         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2100                    "#PF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2101                    feat_num[ECORE_PF_L2_QUE],
2102                    feat_num[ECORE_RDMA_CNQ],
2103                    RESC_NUM(p_hwfn, ECORE_SB), num_features);
2104 }
2105
2106 static enum resource_id_enum
2107 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2108 {
2109         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2110
2111         switch (res_id) {
2112         case ECORE_SB:
2113                 mfw_res_id = RESOURCE_NUM_SB_E;
2114                 break;
2115         case ECORE_L2_QUEUE:
2116                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2117                 break;
2118         case ECORE_VPORT:
2119                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2120                 break;
2121         case ECORE_RSS_ENG:
2122                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2123                 break;
2124         case ECORE_PQ:
2125                 mfw_res_id = RESOURCE_NUM_PQ_E;
2126                 break;
2127         case ECORE_RL:
2128                 mfw_res_id = RESOURCE_NUM_RL_E;
2129                 break;
2130         case ECORE_MAC:
2131         case ECORE_VLAN:
2132                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2133                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2134                 break;
2135         case ECORE_ILT:
2136                 mfw_res_id = RESOURCE_ILT_E;
2137                 break;
2138         case ECORE_LL2_QUEUE:
2139                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2140                 break;
2141         case ECORE_RDMA_CNQ_RAM:
2142         case ECORE_CMDQS_CQS:
2143                 /* CNQ/CMDQS are the same resource */
2144                 mfw_res_id = RESOURCE_CQS_E;
2145                 break;
2146         case ECORE_RDMA_STATS_QUEUE:
2147                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2148                 break;
2149         default:
2150                 break;
2151         }
2152
2153         return mfw_res_id;
2154 }
2155
2156 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2157                                       enum ecore_resources res_id)
2158 {
2159         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2160         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2161         struct ecore_sb_cnt_info sb_cnt_info;
2162         u32 dflt_resc_num = 0;
2163
2164         switch (res_id) {
2165         case ECORE_SB:
2166                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2167                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2168                 dflt_resc_num = sb_cnt_info.sb_cnt;
2169                 break;
2170         case ECORE_L2_QUEUE:
2171                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2172                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2173                 break;
2174         case ECORE_VPORT:
2175                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2176                                  MAX_NUM_VPORTS_BB) / num_funcs;
2177                 break;
2178         case ECORE_RSS_ENG:
2179                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2180                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2181                 break;
2182         case ECORE_PQ:
2183                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2184                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2185                 break;
2186         case ECORE_RL:
2187                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2188                 break;
2189         case ECORE_MAC:
2190         case ECORE_VLAN:
2191                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2192                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2193                 break;
2194         case ECORE_ILT:
2195                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2196                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2197                 break;
2198         case ECORE_LL2_QUEUE:
2199                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2200                 break;
2201         case ECORE_RDMA_CNQ_RAM:
2202         case ECORE_CMDQS_CQS:
2203                 /* CNQ/CMDQS are the same resource */
2204                 /* @DPDK */
2205                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2206                 break;
2207         case ECORE_RDMA_STATS_QUEUE:
2208                 /* @DPDK */
2209                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2210                                  MAX_NUM_VPORTS_BB) / num_funcs;
2211                 break;
2212         default:
2213                 break;
2214         }
2215
2216         return dflt_resc_num;
2217 }
2218
2219 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2220                                                    enum ecore_resources res_id,
2221                                                    bool drv_resc_alloc)
2222 {
2223         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2224         u32 *p_resc_num, *p_resc_start;
2225         struct resource_info resc_info;
2226         enum _ecore_status_t rc;
2227
2228         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2229         p_resc_start = &RESC_START(p_hwfn, res_id);
2230
2231         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2232         if (!dflt_resc_num) {
2233                 DP_ERR(p_hwfn, "Failed to get default amount for resource %d\n",
2234                        res_id);
2235                 return ECORE_INVAL;
2236         }
2237         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2238
2239 #ifndef ASIC_ONLY
2240         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2241                 *p_resc_num = dflt_resc_num;
2242                 *p_resc_start = dflt_resc_start;
2243                 goto out;
2244         }
2245 #endif
2246
2247         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2248         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2249         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2250                 DP_ERR(p_hwfn,
2251                        "Failed to match resource %d with MFW resources\n",
2252                        res_id);
2253                 return ECORE_INVAL;
2254         }
2255
2256         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2257                                      &mcp_resp, &mcp_param);
2258         if (rc != ECORE_SUCCESS) {
2259                 DP_NOTICE(p_hwfn, true,
2260                           "MFW resp failure for a resc alloc req [res_id %d]\n",
2261                           res_id);
2262                 return rc;
2263         }
2264
2265         /* Default driver values are applied in the following cases:
2266          * - The resource allocation MB command is not supported by the MFW
2267          * - There is an internal error in the MFW while processing the request
2268          * - The resource ID is unknown to the MFW
2269          */
2270         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2271             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2272                 /* @DPDK */
2273                 DP_INFO(p_hwfn,
2274                           "No allocation info for resc %d [mcp_resp 0x%x].",
2275                           res_id, mcp_resp);
2276                 DP_INFO(p_hwfn,
2277                           "Applying default values [num %d, start %d].\n",
2278                           dflt_resc_num, dflt_resc_start);
2279
2280                 *p_resc_num = dflt_resc_num;
2281                 *p_resc_start = dflt_resc_start;
2282                 goto out;
2283         }
2284
2285         /* TBD - remove this when revising the handling of the SB resource */
2286         if (res_id == ECORE_SB) {
2287                 /* Excluding the slowpath SB */
2288                 resc_info.size -= 1;
2289                 resc_info.offset -= p_hwfn->enabled_func_idx;
2290         }
2291
2292         *p_resc_num = resc_info.size;
2293         *p_resc_start = resc_info.offset;
2294
2295         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2296                 DP_NOTICE(p_hwfn, false,
2297                           "Resource %d: MFW allocation [num %d, start %d]",
2298                           res_id, *p_resc_num, *p_resc_start);
2299                 DP_NOTICE(p_hwfn, false,
2300                           "differs from default values [num %d, start %d]%s\n",
2301                           dflt_resc_num,
2302                           dflt_resc_start,
2303                           drv_resc_alloc ? " - applying default values" : "");
2304                 if (drv_resc_alloc) {
2305                         *p_resc_num = dflt_resc_num;
2306                         *p_resc_start = dflt_resc_start;
2307                 }
2308         }
2309  out:
2310         return ECORE_SUCCESS;
2311 }
2312
2313 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2314 {
2315         switch (res_id) {
2316         case ECORE_SB:
2317                 return "SB";
2318         case ECORE_L2_QUEUE:
2319                 return "L2_QUEUE";
2320         case ECORE_VPORT:
2321                 return "VPORT";
2322         case ECORE_RSS_ENG:
2323                 return "RSS_ENG";
2324         case ECORE_PQ:
2325                 return "PQ";
2326         case ECORE_RL:
2327                 return "RL";
2328         case ECORE_MAC:
2329                 return "MAC";
2330         case ECORE_VLAN:
2331                 return "VLAN";
2332         case ECORE_RDMA_CNQ_RAM:
2333                 return "RDMA_CNQ_RAM";
2334         case ECORE_ILT:
2335                 return "ILT";
2336         case ECORE_LL2_QUEUE:
2337                 return "LL2_QUEUE";
2338         case ECORE_CMDQS_CQS:
2339                 return "CMDQS_CQS";
2340         case ECORE_RDMA_STATS_QUEUE:
2341                 return "RDMA_STATS_QUEUE";
2342         default:
2343                 return "UNKNOWN_RESOURCE";
2344         }
2345 }
2346
2347 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2348                                               bool drv_resc_alloc)
2349 {
2350         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2351         enum _ecore_status_t rc;
2352         u8 res_id;
2353 #ifndef ASIC_ONLY
2354         u32 *resc_start = p_hwfn->hw_info.resc_start;
2355         u32 *resc_num = p_hwfn->hw_info.resc_num;
2356         /* For AH, an equal share of the ILT lines between the maximal number of
2357          * PFs is not enough for RoCE. This would be solved by the future
2358          * resource allocation scheme, but isn't currently present for
2359          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2360          * to work - the BB number of ILT lines divided by its max PFs number.
2361          */
2362         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2363 #endif
2364
2365         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2366                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2367                 if (rc != ECORE_SUCCESS)
2368                         return rc;
2369         }
2370
2371 #ifndef ASIC_ONLY
2372         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2373                 /* Reduced build contains less PQs */
2374                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2375                         resc_num[ECORE_PQ] = 32;
2376                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2377                             p_hwfn->enabled_func_idx;
2378                 }
2379
2380                 /* For AH emulation, since we have a possible maximal number of
2381                  * 16 enabled PFs, in case there are not enough ILT lines -
2382                  * allocate only first PF as RoCE and have all the other ETH
2383                  * only with less ILT lines.
2384                  */
2385                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2386                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2387                                                          resc_num[ECORE_ILT],
2388                                                          roce_min_ilt_lines);
2389         }
2390
2391         /* Correct the common ILT calculation if PF0 has more */
2392         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2393             p_hwfn->p_dev->b_is_emul_full &&
2394             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2395                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2396                     resc_num[ECORE_ILT];
2397 #endif
2398
2399         /* Sanity for ILT */
2400         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2401             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2402                 DP_NOTICE(p_hwfn, true,
2403                           "Can't assign ILT pages [%08x,...,%08x]\n",
2404                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2405                                                                   ECORE_ILT) -
2406                           1);
2407                 return ECORE_INVAL;
2408         }
2409
2410         ecore_hw_set_feat(p_hwfn);
2411
2412         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2413                    "The numbers for each resource are:\n");
2414         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2415                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2416                            ecore_hw_get_resc_name(res_id),
2417                            RESC_NUM(p_hwfn, res_id),
2418                            RESC_START(p_hwfn, res_id));
2419
2420         return ECORE_SUCCESS;
2421 }
2422
2423 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2424                                                   struct ecore_ptt *p_ptt)
2425 {
2426         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2427         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2428         struct ecore_mcp_link_params *link;
2429
2430         /* Read global nvm_cfg address */
2431         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2432
2433         /* Verify MCP has initialized it */
2434         if (!nvm_cfg_addr) {
2435                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2436                 return ECORE_INVAL;
2437         }
2438
2439 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2440
2441         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2442
2443         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2444             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2445                                                        core_cfg);
2446
2447         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2448
2449         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2450                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2451         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2452                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2453                 break;
2454         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2455                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2456                 break;
2457         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2458                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2459                 break;
2460         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2461                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2462                 break;
2463         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2464                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2465                 break;
2466         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2467                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2468                 break;
2469         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2470                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2471                 break;
2472         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2473                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2474                 break;
2475         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2476                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2477                 break;
2478         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2479                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2480                 break;
2481         default:
2482                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2483                           core_cfg);
2484                 break;
2485         }
2486
2487         /* Read default link configuration */
2488         link = &p_hwfn->mcp_info->link_input;
2489         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2490             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2491         link_temp = ecore_rd(p_hwfn, p_ptt,
2492                              port_cfg_addr +
2493                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2494         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2495         link->speed.advertised_speeds = link_temp;
2496
2497         link_temp = link->speed.advertised_speeds;
2498         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2499
2500         link_temp = ecore_rd(p_hwfn, p_ptt,
2501                              port_cfg_addr +
2502                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2503         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2504                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2505         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2506                 link->speed.autoneg = true;
2507                 break;
2508         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2509                 link->speed.forced_speed = 1000;
2510                 break;
2511         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2512                 link->speed.forced_speed = 10000;
2513                 break;
2514         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2515                 link->speed.forced_speed = 25000;
2516                 break;
2517         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2518                 link->speed.forced_speed = 40000;
2519                 break;
2520         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2521                 link->speed.forced_speed = 50000;
2522                 break;
2523         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2524                 link->speed.forced_speed = 100000;
2525                 break;
2526         default:
2527                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2528         }
2529
2530         p_hwfn->mcp_info->link_capabilities.default_speed =
2531             link->speed.forced_speed;
2532         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2533             link->speed.autoneg;
2534
2535         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2536         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2537         link->pause.autoneg = !!(link_temp &
2538                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2539         link->pause.forced_rx = !!(link_temp &
2540                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2541         link->pause.forced_tx = !!(link_temp &
2542                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2543         link->loopback_mode = 0;
2544
2545         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2546                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2547                    link->speed.forced_speed, link->speed.advertised_speeds,
2548                    link->speed.autoneg, link->pause.autoneg);
2549
2550         /* Read Multi-function information from shmem */
2551         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2552             OFFSETOF(struct nvm_cfg1, glob) +
2553             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2554
2555         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2556
2557         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2558             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2559
2560         switch (mf_mode) {
2561         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2562                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2563                 break;
2564         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2565                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2566                 break;
2567         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2568                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2569                 break;
2570         }
2571         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2572                 p_hwfn->p_dev->mf_mode);
2573
2574         /* Read Multi-function information from shmem */
2575         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2576             OFFSETOF(struct nvm_cfg1, glob) +
2577             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2578
2579         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2580         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2581                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2582                              &p_hwfn->hw_info.device_capabilities);
2583         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2584                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2585                              &p_hwfn->hw_info.device_capabilities);
2586         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2587                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2588                              &p_hwfn->hw_info.device_capabilities);
2589         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2590                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2591                              &p_hwfn->hw_info.device_capabilities);
2592         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2593                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2594                              &p_hwfn->hw_info.device_capabilities);
2595
2596         return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2597 }
2598
2599 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2600                                 struct ecore_ptt *p_ptt)
2601 {
2602         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2603         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2604         struct ecore_dev *p_dev = p_hwfn->p_dev;
2605
2606         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2607
2608         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2609          * in the other bits are selected.
2610          * Bits 1-15 are for functions 1-15, respectively, and their value is
2611          * '0' only for enabled functions (function 0 always exists and
2612          * enabled).
2613          * In case of CMT in BB, only the "even" functions are enabled, and thus
2614          * the number of functions for both hwfns is learnt from the same bits.
2615          */
2616         reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2617
2618         if (reg_function_hide & 0x1) {
2619                 if (ECORE_IS_BB(p_dev)) {
2620                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2621                                 num_funcs = 0;
2622                                 eng_mask = 0xaaaa;
2623                         } else {
2624                                 num_funcs = 1;
2625                                 eng_mask = 0x5554;
2626                         }
2627                 } else {
2628                         num_funcs = 1;
2629                         eng_mask = 0xfffe;
2630                 }
2631
2632                 /* Get the number of the enabled functions on the engine */
2633                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2634                 while (tmp) {
2635                         if (tmp & 0x1)
2636                                 num_funcs++;
2637                         tmp >>= 0x1;
2638                 }
2639
2640                 /* Get the PF index within the enabled functions */
2641                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2642                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2643                 while (tmp) {
2644                         if (tmp & 0x1)
2645                                 enabled_func_idx--;
2646                         tmp >>= 0x1;
2647                 }
2648         }
2649
2650         p_hwfn->num_funcs_on_engine = num_funcs;
2651         p_hwfn->enabled_func_idx = enabled_func_idx;
2652
2653 #ifndef ASIC_ONLY
2654         if (CHIP_REV_IS_FPGA(p_dev)) {
2655                 DP_NOTICE(p_hwfn, false,
2656                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2657                 p_hwfn->num_funcs_on_engine = 4;
2658         }
2659 #endif
2660
2661         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2662                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2663                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2664                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2665 }
2666
2667 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2668                                       struct ecore_ptt *p_ptt)
2669 {
2670         u32 port_mode;
2671
2672 #ifndef ASIC_ONLY
2673         /* Read the port mode */
2674         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2675                 port_mode = 4;
2676         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2677                  (p_hwfn->p_dev->num_hwfns > 1))
2678                 /* In CMT on emulation, assume 1 port */
2679                 port_mode = 1;
2680         else
2681 #endif
2682                 port_mode = ecore_rd(p_hwfn, p_ptt,
2683                                      CNIG_REG_NW_PORT_MODE_BB_B0);
2684
2685         if (port_mode < 3) {
2686                 p_hwfn->p_dev->num_ports_in_engines = 1;
2687         } else if (port_mode <= 5) {
2688                 p_hwfn->p_dev->num_ports_in_engines = 2;
2689         } else {
2690                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2691                           p_hwfn->p_dev->num_ports_in_engines);
2692
2693                 /* Default num_ports_in_engines to something */
2694                 p_hwfn->p_dev->num_ports_in_engines = 1;
2695         }
2696 }
2697
2698 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2699                                       struct ecore_ptt *p_ptt)
2700 {
2701         u32 port;
2702         int i;
2703
2704         p_hwfn->p_dev->num_ports_in_engines = 0;
2705
2706 #ifndef ASIC_ONLY
2707         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2708                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2709                 switch ((port & 0xf000) >> 12) {
2710                 case 1:
2711                         p_hwfn->p_dev->num_ports_in_engines = 1;
2712                         break;
2713                 case 3:
2714                         p_hwfn->p_dev->num_ports_in_engines = 2;
2715                         break;
2716                 case 0xf:
2717                         p_hwfn->p_dev->num_ports_in_engines = 4;
2718                         break;
2719                 default:
2720                         DP_NOTICE(p_hwfn, false,
2721                                   "Unknown port mode in ECO_RESERVED %08x\n",
2722                                   port);
2723                 }
2724         } else
2725 #endif
2726                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2727                         port = ecore_rd(p_hwfn, p_ptt,
2728                                         CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2729                         if (port & 1)
2730                                 p_hwfn->p_dev->num_ports_in_engines++;
2731                 }
2732 }
2733
2734 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2735                                    struct ecore_ptt *p_ptt)
2736 {
2737         if (ECORE_IS_BB(p_hwfn->p_dev))
2738                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2739         else
2740                 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2741 }
2742
2743 static enum _ecore_status_t
2744 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2745                   enum ecore_pci_personality personality, bool drv_resc_alloc)
2746 {
2747         enum _ecore_status_t rc;
2748
2749         /* Since all information is common, only first hwfns should do this */
2750         if (IS_LEAD_HWFN(p_hwfn)) {
2751                 rc = ecore_iov_hw_info(p_hwfn);
2752                 if (rc)
2753                         return rc;
2754         }
2755
2756         /* TODO In get_hw_info, amoungst others:
2757          * Get MCP FW revision and determine according to it the supported
2758          * featrues (e.g. DCB)
2759          * Get boot mode
2760          * ecore_get_pcie_width_speed, WOL capability.
2761          * Number of global CQ-s (for storage
2762          */
2763         ecore_hw_info_port_num(p_hwfn, p_ptt);
2764
2765 #ifndef ASIC_ONLY
2766         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2767 #endif
2768                 ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2769
2770         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2771         if (rc)
2772                 return rc;
2773
2774 #ifndef ASIC_ONLY
2775         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2776 #endif
2777                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2778                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2779 #ifndef ASIC_ONLY
2780         } else {
2781                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2782
2783                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2784                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2785         }
2786 #endif
2787
2788         if (ecore_mcp_is_init(p_hwfn)) {
2789                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2790                         p_hwfn->hw_info.ovlan =
2791                             p_hwfn->mcp_info->func_info.ovlan;
2792
2793                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2794         }
2795
2796         if (personality != ECORE_PCI_DEFAULT)
2797                 p_hwfn->hw_info.personality = personality;
2798         else if (ecore_mcp_is_init(p_hwfn))
2799                 p_hwfn->hw_info.personality =
2800                     p_hwfn->mcp_info->func_info.protocol;
2801
2802 #ifndef ASIC_ONLY
2803         /* To overcome ILT lack for emulation, until at least until we'll have
2804          * a definite answer from system about it, allow only PF0 to be RoCE.
2805          */
2806         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2807                 if (!p_hwfn->rel_pf_id)
2808                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2809                 else
2810                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2811         }
2812 #endif
2813
2814         /* although in BB some constellations may support more than 4 tcs,
2815          * that can result in performance penalty in some cases. 4
2816          * represents a good tradeoff between performance and flexibility.
2817          */
2818         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2819
2820         /* start out with a single active tc. This can be increased either
2821          * by dcbx negotiation or by upper layer driver
2822          */
2823         p_hwfn->hw_info.num_active_tc = 1;
2824
2825         ecore_get_num_funcs(p_hwfn, p_ptt);
2826
2827         /* In case of forcing the driver's default resource allocation, calling
2828          * ecore_hw_get_resc() should come after initializing the personality
2829          * and after getting the number of functions, since the calculation of
2830          * the resources/features depends on them.
2831          * This order is not harmful if not forcing.
2832          */
2833         return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2834 }
2835
2836 #define ECORE_DEV_ID_MASK       0xff00
2837 #define ECORE_DEV_ID_MASK_BB    0x1600
2838 #define ECORE_DEV_ID_MASK_AH    0x8000
2839
2840 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2841 {
2842         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2843         u32 tmp;
2844
2845         /* Read Vendor Id / Device Id */
2846         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2847                                   &p_dev->vendor_id);
2848         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2849                                   &p_dev->device_id);
2850
2851         /* Determine type */
2852         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2853                 p_dev->type = ECORE_DEV_TYPE_AH;
2854         else
2855                 p_dev->type = ECORE_DEV_TYPE_BB;
2856
2857         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2858                                          MISCS_REG_CHIP_NUM);
2859         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2860                                          MISCS_REG_CHIP_REV);
2861
2862         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2863
2864         /* Learn number of HW-functions */
2865         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2866                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
2867
2868         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2869                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2870                 p_dev->num_hwfns = 2;
2871         } else {
2872                 p_dev->num_hwfns = 1;
2873         }
2874
2875 #ifndef ASIC_ONLY
2876         if (CHIP_REV_IS_EMUL(p_dev)) {
2877                 /* For some reason we have problems with this register
2878                  * in B0 emulation; Simply assume no CMT
2879                  */
2880                 DP_NOTICE(p_dev->hwfns, false,
2881                           "device on emul - assume no CMT\n");
2882                 p_dev->num_hwfns = 1;
2883         }
2884 #endif
2885
2886         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2887                                        MISCS_REG_CHIP_TEST_REG) >> 4;
2888         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2889         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2890                                            MISCS_REG_CHIP_METAL);
2891         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2892         DP_INFO(p_dev->hwfns,
2893                 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2894                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2895                 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2896                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2897                 p_dev->chip_metal);
2898
2899         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2900                 DP_NOTICE(p_dev->hwfns, false,
2901                           "The chip type/rev (BB A0) is not supported!\n");
2902                 return ECORE_ABORTED;
2903         }
2904 #ifndef ASIC_ONLY
2905         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2906                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2907                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2908
2909         if (CHIP_REV_IS_EMUL(p_dev)) {
2910                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2911                                MISCS_REG_ECO_RESERVED);
2912                 if (tmp & (1 << 29)) {
2913                         DP_NOTICE(p_hwfn, false,
2914                                   "Emulation: Running on a FULL build\n");
2915                         p_dev->b_is_emul_full = true;
2916                 } else {
2917                         DP_NOTICE(p_hwfn, false,
2918                                   "Emulation: Running on a REDUCED build\n");
2919                 }
2920         }
2921 #endif
2922
2923         return ECORE_SUCCESS;
2924 }
2925
2926 #ifndef LINUX_REMOVE
2927 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2928 {
2929         int j;
2930
2931         if (IS_VF(p_dev))
2932                 return;
2933
2934         for_each_hwfn(p_dev, j) {
2935                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2936
2937                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2938                            "Mark hw/fw uninitialized\n");
2939
2940                 p_hwfn->hw_init_done = false;
2941                 p_hwfn->first_on_engine = false;
2942
2943                 ecore_ptt_invalidate(p_hwfn);
2944         }
2945 }
2946 #endif
2947
2948 static enum _ecore_status_t
2949 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
2950                         void OSAL_IOMEM *p_doorbells,
2951                         struct ecore_hw_prepare_params *p_params)
2952 {
2953         enum _ecore_status_t rc = ECORE_SUCCESS;
2954
2955         /* Split PCI bars evenly between hwfns */
2956         p_hwfn->regview = p_regview;
2957         p_hwfn->doorbells = p_doorbells;
2958
2959         if (IS_VF(p_hwfn->p_dev))
2960                 return ecore_vf_hw_prepare(p_hwfn);
2961
2962         /* Validate that chip access is feasible */
2963         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2964                 DP_ERR(p_hwfn,
2965                        "Reading the ME register returns all Fs; Preventing further chip access\n");
2966                 return ECORE_INVAL;
2967         }
2968
2969         get_function_id(p_hwfn);
2970
2971         /* Allocate PTT pool */
2972         rc = ecore_ptt_pool_alloc(p_hwfn);
2973         if (rc) {
2974                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2975                 goto err0;
2976         }
2977
2978         /* Allocate the main PTT */
2979         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2980
2981         /* First hwfn learns basic information, e.g., number of hwfns */
2982         if (!p_hwfn->my_id) {
2983                 rc = ecore_get_dev_info(p_hwfn->p_dev);
2984                 if (rc != ECORE_SUCCESS)
2985                         goto err1;
2986         }
2987
2988         ecore_hw_hwfn_prepare(p_hwfn);
2989
2990         /* Initialize MCP structure */
2991         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2992         if (rc) {
2993                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
2994                 goto err1;
2995         }
2996
2997         /* Read the device configuration information from the HW and SHMEM */
2998         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
2999                                p_params->personality, p_params->drv_resc_alloc);
3000         if (rc) {
3001                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3002                 goto err2;
3003         }
3004
3005         /* Allocate the init RT array and initialize the init-ops engine */
3006         rc = ecore_init_alloc(p_hwfn);
3007         if (rc) {
3008                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3009                 goto err2;
3010         }
3011 #ifndef ASIC_ONLY
3012         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
3013                 DP_NOTICE(p_hwfn, false,
3014                           "FPGA: workaround; Prevent DMAE parities\n");
3015                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
3016
3017                 DP_NOTICE(p_hwfn, false,
3018                           "FPGA: workaround: Set VF bar0 size\n");
3019                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3020                          PGLUE_B_REG_VF_BAR0_SIZE, 4);
3021         }
3022 #endif
3023
3024         return rc;
3025  err2:
3026         if (IS_LEAD_HWFN(p_hwfn))
3027                 ecore_iov_free_hw_info(p_hwfn->p_dev);
3028         ecore_mcp_free(p_hwfn);
3029  err1:
3030         ecore_hw_hwfn_free(p_hwfn);
3031  err0:
3032         return rc;
3033 }
3034
3035 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3036                                       struct ecore_hw_prepare_params *p_params)
3037 {
3038         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3039         enum _ecore_status_t rc;
3040
3041         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3042
3043         /* Store the precompiled init data ptrs */
3044         if (IS_PF(p_dev))
3045                 ecore_init_iro_array(p_dev);
3046
3047         /* Initialize the first hwfn - will learn number of hwfns */
3048         rc = ecore_hw_prepare_single(p_hwfn,
3049                                      p_dev->regview,
3050                                      p_dev->doorbells, p_params);
3051         if (rc != ECORE_SUCCESS)
3052                 return rc;
3053
3054         p_params->personality = p_hwfn->hw_info.personality;
3055
3056         /* initilalize 2nd hwfn if necessary */
3057         if (p_dev->num_hwfns > 1) {
3058                 void OSAL_IOMEM *p_regview, *p_doorbell;
3059                 u8 OSAL_IOMEM *addr;
3060
3061                 /* adjust bar offset for second engine */
3062                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3063                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3064                 p_regview = (void OSAL_IOMEM *)addr;
3065
3066                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3067                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3068                 p_doorbell = (void OSAL_IOMEM *)addr;
3069
3070                 /* prepare second hw function */
3071                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3072                                              p_doorbell, p_params);
3073
3074                 /* in case of error, need to free the previously
3075                  * initiliazed hwfn 0.
3076                  */
3077                 if (rc != ECORE_SUCCESS) {
3078                         if (IS_PF(p_dev)) {
3079                                 ecore_init_free(p_hwfn);
3080                                 ecore_mcp_free(p_hwfn);
3081                                 ecore_hw_hwfn_free(p_hwfn);
3082                         } else {
3083                                 DP_NOTICE(p_dev, true,
3084                                           "What do we need to free when VF hwfn1 init fails\n");
3085                         }
3086                         return rc;
3087                 }
3088         }
3089
3090         return ECORE_SUCCESS;
3091 }
3092
3093 void ecore_hw_remove(struct ecore_dev *p_dev)
3094 {
3095         int i;
3096
3097         for_each_hwfn(p_dev, i) {
3098                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3099
3100                 if (IS_VF(p_dev)) {
3101                         ecore_vf_pf_release(p_hwfn);
3102                         continue;
3103                 }
3104
3105                 ecore_init_free(p_hwfn);
3106                 ecore_hw_hwfn_free(p_hwfn);
3107                 ecore_mcp_free(p_hwfn);
3108
3109                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3110         }
3111
3112         ecore_iov_free_hw_info(p_dev);
3113 }
3114
3115 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3116                                       struct ecore_chain *p_chain)
3117 {
3118         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3119         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3120         struct ecore_chain_next *p_next;
3121         u32 size, i;
3122
3123         if (!p_virt)
3124                 return;
3125
3126         size = p_chain->elem_size * p_chain->usable_per_page;
3127
3128         for (i = 0; i < p_chain->page_cnt; i++) {
3129                 if (!p_virt)
3130                         break;
3131
3132                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3133                 p_virt_next = p_next->next_virt;
3134                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3135
3136                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3137                                        ECORE_CHAIN_PAGE_SIZE);
3138
3139                 p_virt = p_virt_next;
3140                 p_phys = p_phys_next;
3141         }
3142 }
3143
3144 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3145                                     struct ecore_chain *p_chain)
3146 {
3147         if (!p_chain->p_virt_addr)
3148                 return;
3149
3150         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3151                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3152 }
3153
3154 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3155                                  struct ecore_chain *p_chain)
3156 {
3157         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3158         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3159         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3160
3161         if (!pp_virt_addr_tbl)
3162                 return;
3163
3164         if (!p_chain->pbl.p_virt_table)
3165                 goto out;
3166
3167         for (i = 0; i < page_cnt; i++) {
3168                 if (!pp_virt_addr_tbl[i])
3169                         break;
3170
3171                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3172                                        *(dma_addr_t *)p_pbl_virt,
3173                                        ECORE_CHAIN_PAGE_SIZE);
3174
3175                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3176         }
3177
3178         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3179         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3180                                p_chain->pbl.p_phys_table, pbl_size);
3181  out:
3182         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3183 }
3184
3185 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3186 {
3187         switch (p_chain->mode) {
3188         case ECORE_CHAIN_MODE_NEXT_PTR:
3189                 ecore_chain_free_next_ptr(p_dev, p_chain);
3190                 break;
3191         case ECORE_CHAIN_MODE_SINGLE:
3192                 ecore_chain_free_single(p_dev, p_chain);
3193                 break;
3194         case ECORE_CHAIN_MODE_PBL:
3195                 ecore_chain_free_pbl(p_dev, p_chain);
3196                 break;
3197         }
3198 }
3199
3200 static enum _ecore_status_t
3201 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3202                                enum ecore_chain_cnt_type cnt_type,
3203                                osal_size_t elem_size, u32 page_cnt)
3204 {
3205         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3206
3207         /* The actual chain size can be larger than the maximal possible value
3208          * after rounding up the requested elements number to pages, and after
3209          * taking into acount the unusuable elements (next-ptr elements).
3210          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3211          * size/capacity fields are of a u32 type.
3212          */
3213         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3214              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3215             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3216              chain_size > ECORE_U32_MAX)) {
3217                 DP_NOTICE(p_dev, true,
3218                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3219                           (unsigned long)chain_size);
3220                 return ECORE_INVAL;
3221         }
3222
3223         return ECORE_SUCCESS;
3224 }
3225
3226 static enum _ecore_status_t
3227 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3228 {
3229         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3230         dma_addr_t p_phys = 0;
3231         u32 i;
3232
3233         for (i = 0; i < p_chain->page_cnt; i++) {
3234                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3235                                                  ECORE_CHAIN_PAGE_SIZE);
3236                 if (!p_virt) {
3237                         DP_NOTICE(p_dev, true,
3238                                   "Failed to allocate chain memory\n");
3239                         return ECORE_NOMEM;
3240                 }
3241
3242                 if (i == 0) {
3243                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3244                         ecore_chain_reset(p_chain);
3245                 } else {
3246                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3247                                                        p_virt, p_phys);
3248                 }
3249
3250                 p_virt_prev = p_virt;
3251         }
3252         /* Last page's next element should point to the beginning of the
3253          * chain.
3254          */
3255         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3256                                        p_chain->p_virt_addr,
3257                                        p_chain->p_phys_addr);
3258
3259         return ECORE_SUCCESS;
3260 }
3261
3262 static enum _ecore_status_t
3263 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3264 {
3265         void *p_virt = OSAL_NULL;
3266         dma_addr_t p_phys = 0;
3267
3268         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3269         if (!p_virt) {
3270                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3271                 return ECORE_NOMEM;
3272         }
3273
3274         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3275         ecore_chain_reset(p_chain);
3276
3277         return ECORE_SUCCESS;
3278 }
3279
3280 static enum _ecore_status_t ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3281                                                   struct ecore_chain *p_chain)
3282 {
3283         void *p_virt = OSAL_NULL;
3284         u8 *p_pbl_virt = OSAL_NULL;
3285         void **pp_virt_addr_tbl = OSAL_NULL;
3286         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3287         u32 page_cnt = p_chain->page_cnt, size, i;
3288
3289         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3290         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3291         if (!pp_virt_addr_tbl) {
3292                 DP_NOTICE(p_dev, true,
3293                           "Failed to allocate memory for the chain virtual addresses table\n");
3294                 return ECORE_NOMEM;
3295         }
3296         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3297
3298         /* The allocation of the PBL table is done with its full size, since it
3299          * is expected to be successive.
3300          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3301          * failure, since pp_virt_addr_tbl was previously allocated, and it
3302          * should be saved to allow its freeing during the error flow.
3303          */
3304         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3305         p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3306         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3307                                  pp_virt_addr_tbl);
3308         if (!p_pbl_virt) {
3309                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3310                 return ECORE_NOMEM;
3311         }
3312
3313         for (i = 0; i < page_cnt; i++) {
3314                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3315                                                  ECORE_CHAIN_PAGE_SIZE);
3316                 if (!p_virt) {
3317                         DP_NOTICE(p_dev, true,
3318                                   "Failed to allocate chain memory\n");
3319                         return ECORE_NOMEM;
3320                 }
3321
3322                 if (i == 0) {
3323                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3324                         ecore_chain_reset(p_chain);
3325                 }
3326
3327                 /* Fill the PBL table with the physical address of the page */
3328                 *(dma_addr_t *)p_pbl_virt = p_phys;
3329                 /* Keep the virtual address of the page */
3330                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3331
3332                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3333         }
3334
3335         return ECORE_SUCCESS;
3336 }
3337
3338 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3339                                        enum ecore_chain_use_mode intended_use,
3340                                        enum ecore_chain_mode mode,
3341                                        enum ecore_chain_cnt_type cnt_type,
3342                                        u32 num_elems, osal_size_t elem_size,
3343                                        struct ecore_chain *p_chain)
3344 {
3345         u32 page_cnt;
3346         enum _ecore_status_t rc = ECORE_SUCCESS;
3347
3348         if (mode == ECORE_CHAIN_MODE_SINGLE)
3349                 page_cnt = 1;
3350         else
3351                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3352
3353         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3354                                             page_cnt);
3355         if (rc) {
3356                 DP_NOTICE(p_dev, true,
3357                           "Cannot allocate a chain with the given arguments:\n"
3358                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3359                           intended_use, mode, cnt_type, num_elems, elem_size);
3360                 return rc;
3361         }
3362
3363         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3364                                 mode, cnt_type, p_dev->dp_ctx);
3365
3366         switch (mode) {
3367         case ECORE_CHAIN_MODE_NEXT_PTR:
3368                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3369                 break;
3370         case ECORE_CHAIN_MODE_SINGLE:
3371                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3372                 break;
3373         case ECORE_CHAIN_MODE_PBL:
3374                 rc = ecore_chain_alloc_pbl(p_dev, p_chain);
3375                 break;
3376         }
3377         if (rc)
3378                 goto nomem;
3379
3380         return ECORE_SUCCESS;
3381
3382  nomem:
3383         ecore_chain_free(p_dev, p_chain);
3384         return rc;
3385 }
3386
3387 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3388                                        u16 src_id, u16 *dst_id)
3389 {
3390         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3391                 u16 min, max;
3392
3393                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3394                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3395                 DP_NOTICE(p_hwfn, true,
3396                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3397                           src_id, min, max);
3398
3399                 return ECORE_INVAL;
3400         }
3401
3402         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3403
3404         return ECORE_SUCCESS;
3405 }
3406
3407 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3408                                     u8 src_id, u8 *dst_id)
3409 {
3410         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3411                 u8 min, max;
3412
3413                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3414                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3415                 DP_NOTICE(p_hwfn, true,
3416                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3417                           src_id, min, max);
3418
3419                 return ECORE_INVAL;
3420         }
3421
3422         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3423
3424         return ECORE_SUCCESS;
3425 }
3426
3427 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3428                                       u8 src_id, u8 *dst_id)
3429 {
3430         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3431                 u8 min, max;
3432
3433                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3434                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3435                 DP_NOTICE(p_hwfn, true,
3436                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3437                           src_id, min, max);
3438
3439                 return ECORE_INVAL;
3440         }
3441
3442         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3443
3444         return ECORE_SUCCESS;
3445 }
3446
3447 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3448                                               struct ecore_ptt *p_ptt,
3449                                               u8 *p_filter)
3450 {
3451         u32 high, low, en;
3452         int i;
3453
3454         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3455                 return ECORE_SUCCESS;
3456
3457         high = p_filter[1] | (p_filter[0] << 8);
3458         low = p_filter[5] | (p_filter[4] << 8) |
3459             (p_filter[3] << 16) | (p_filter[2] << 24);
3460
3461         /* Find a free entry and utilize it */
3462         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3463                 en = ecore_rd(p_hwfn, p_ptt,
3464                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3465                 if (en)
3466                         continue;
3467                 ecore_wr(p_hwfn, p_ptt,
3468                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3469                          2 * i * sizeof(u32), low);
3470                 ecore_wr(p_hwfn, p_ptt,
3471                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3472                          (2 * i + 1) * sizeof(u32), high);
3473                 ecore_wr(p_hwfn, p_ptt,
3474                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3475                 ecore_wr(p_hwfn, p_ptt,
3476                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3477                          i * sizeof(u32), 0);
3478                 ecore_wr(p_hwfn, p_ptt,
3479                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3480                 break;
3481         }
3482         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3483                 DP_NOTICE(p_hwfn, false,
3484                           "Failed to find an empty LLH filter to utilize\n");
3485                 return ECORE_INVAL;
3486         }
3487
3488         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3489                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3490                    p_filter[0], p_filter[1], p_filter[2],
3491                    p_filter[3], p_filter[4], p_filter[5], i);
3492
3493         return ECORE_SUCCESS;
3494 }
3495
3496 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3497                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3498 {
3499         u32 high, low;
3500         int i;
3501
3502         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3503                 return;
3504
3505         high = p_filter[1] | (p_filter[0] << 8);
3506         low = p_filter[5] | (p_filter[4] << 8) |
3507             (p_filter[3] << 16) | (p_filter[2] << 24);
3508
3509         /* Find the entry and clean it */
3510         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3511                 if (ecore_rd(p_hwfn, p_ptt,
3512                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3513                              2 * i * sizeof(u32)) != low)
3514                         continue;
3515                 if (ecore_rd(p_hwfn, p_ptt,
3516                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3517                              (2 * i + 1) * sizeof(u32)) != high)
3518                         continue;
3519
3520                 ecore_wr(p_hwfn, p_ptt,
3521                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3522                 ecore_wr(p_hwfn, p_ptt,
3523                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3524                          2 * i * sizeof(u32), 0);
3525                 ecore_wr(p_hwfn, p_ptt,
3526                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3527                          (2 * i + 1) * sizeof(u32), 0);
3528                 break;
3529         }
3530         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3531                 DP_NOTICE(p_hwfn, false,
3532                           "Tried to remove a non-configured filter\n");
3533 }
3534
3535 enum _ecore_status_t
3536 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3537                               struct ecore_ptt *p_ptt,
3538                               u16 source_port_or_eth_type,
3539                               u16 dest_port,
3540                               enum ecore_llh_port_filter_type_t type)
3541 {
3542         u32 high, low, en;
3543         int i;
3544
3545         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3546                 return ECORE_SUCCESS;
3547
3548         high = 0;
3549         low = 0;
3550         switch (type) {
3551         case ECORE_LLH_FILTER_ETHERTYPE:
3552                 high = source_port_or_eth_type;
3553                 break;
3554         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3555         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3556                 low = source_port_or_eth_type << 16;
3557                 break;
3558         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3559         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3560                 low = dest_port;
3561                 break;
3562         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3563         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3564                 low = (source_port_or_eth_type << 16) | dest_port;
3565                 break;
3566         default:
3567                 DP_NOTICE(p_hwfn, true,
3568                           "Non valid LLH protocol filter type %d\n", type);
3569                 return ECORE_INVAL;
3570         }
3571         /* Find a free entry and utilize it */
3572         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3573                 en = ecore_rd(p_hwfn, p_ptt,
3574                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3575                 if (en)
3576                         continue;
3577                 ecore_wr(p_hwfn, p_ptt,
3578                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3579                          2 * i * sizeof(u32), low);
3580                 ecore_wr(p_hwfn, p_ptt,
3581                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3582                          (2 * i + 1) * sizeof(u32), high);
3583                 ecore_wr(p_hwfn, p_ptt,
3584                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3585                 ecore_wr(p_hwfn, p_ptt,
3586                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3587                          i * sizeof(u32), 1 << type);
3588                 ecore_wr(p_hwfn, p_ptt,
3589                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3590                 break;
3591         }
3592         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3593                 DP_NOTICE(p_hwfn, false,
3594                           "Failed to find an empty LLH filter to utilize\n");
3595                 return ECORE_NORESOURCES;
3596         }
3597         switch (type) {
3598         case ECORE_LLH_FILTER_ETHERTYPE:
3599                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3600                            "ETH type %x is added at %d\n",
3601                            source_port_or_eth_type, i);
3602                 break;
3603         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3604                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3605                            "TCP src port %x is added at %d\n",
3606                            source_port_or_eth_type, i);
3607                 break;
3608         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3609                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3610                            "UDP src port %x is added at %d\n",
3611                            source_port_or_eth_type, i);
3612                 break;
3613         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3614                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3615                            "TCP dst port %x is added at %d\n", dest_port, i);
3616                 break;
3617         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3618                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3619                            "UDP dst port %x is added at %d\n", dest_port, i);
3620                 break;
3621         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3622                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3623                            "TCP src/dst ports %x/%x are added at %d\n",
3624                            source_port_or_eth_type, dest_port, i);
3625                 break;
3626         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3627                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3628                            "UDP src/dst ports %x/%x are added at %d\n",
3629                            source_port_or_eth_type, dest_port, i);
3630                 break;
3631         }
3632         return ECORE_SUCCESS;
3633 }
3634
3635 void
3636 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3637                                  struct ecore_ptt *p_ptt,
3638                                  u16 source_port_or_eth_type,
3639                                  u16 dest_port,
3640                                  enum ecore_llh_port_filter_type_t type)
3641 {
3642         u32 high, low;
3643         int i;
3644
3645         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3646                 return;
3647
3648         high = 0;
3649         low = 0;
3650         switch (type) {
3651         case ECORE_LLH_FILTER_ETHERTYPE:
3652                 high = source_port_or_eth_type;
3653                 break;
3654         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3655         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3656                 low = source_port_or_eth_type << 16;
3657                 break;
3658         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3659         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3660                 low = dest_port;
3661                 break;
3662         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3663         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3664                 low = (source_port_or_eth_type << 16) | dest_port;
3665                 break;
3666         default:
3667                 DP_NOTICE(p_hwfn, true,
3668                           "Non valid LLH protocol filter type %d\n", type);
3669                 return;
3670         }
3671
3672         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3673                 if (!ecore_rd(p_hwfn, p_ptt,
3674                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3675                         continue;
3676                 if (!ecore_rd(p_hwfn, p_ptt,
3677                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3678                         continue;
3679                 if (!(ecore_rd(p_hwfn, p_ptt,
3680                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3681                                i * sizeof(u32)) & (1 << type)))
3682                         continue;
3683                 if (ecore_rd(p_hwfn, p_ptt,
3684                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3685                              2 * i * sizeof(u32)) != low)
3686                         continue;
3687                 if (ecore_rd(p_hwfn, p_ptt,
3688                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3689                              (2 * i + 1) * sizeof(u32)) != high)
3690                         continue;
3691
3692                 ecore_wr(p_hwfn, p_ptt,
3693                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3694                 ecore_wr(p_hwfn, p_ptt,
3695                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3696                 ecore_wr(p_hwfn, p_ptt,
3697                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3698                          i * sizeof(u32), 0);
3699                 ecore_wr(p_hwfn, p_ptt,
3700                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3701                          2 * i * sizeof(u32), 0);
3702                 ecore_wr(p_hwfn, p_ptt,
3703                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3704                          (2 * i + 1) * sizeof(u32), 0);
3705                 break;
3706         }
3707
3708         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3709                 DP_NOTICE(p_hwfn, false,
3710                           "Tried to remove a non-configured filter\n");
3711 }
3712
3713 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3714                                  struct ecore_ptt *p_ptt)
3715 {
3716         int i;
3717
3718         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3719                 return;
3720
3721         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3722                 ecore_wr(p_hwfn, p_ptt,
3723                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3724                 ecore_wr(p_hwfn, p_ptt,
3725                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3726                          2 * i * sizeof(u32), 0);
3727                 ecore_wr(p_hwfn, p_ptt,
3728                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3729                          (2 * i + 1) * sizeof(u32), 0);
3730         }
3731 }
3732
3733 enum _ecore_status_t
3734 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3735                                   struct ecore_ptt *p_ptt)
3736 {
3737         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3738                 ecore_wr(p_hwfn, p_ptt,
3739                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3740                          1 << p_hwfn->abs_pf_id / 2);
3741                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3742                 return ECORE_SUCCESS;
3743         }
3744
3745         DP_NOTICE(p_hwfn, false,
3746                   "This function can't be set as default\n");
3747         return ECORE_INVAL;
3748 }
3749
3750 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3751                                                struct ecore_ptt *p_ptt,
3752                                                u32 hw_addr, void *p_eth_qzone,
3753                                                osal_size_t eth_qzone_size,
3754                                                u8 timeset)
3755 {
3756         struct coalescing_timeset *p_coal_timeset;
3757
3758         if (IS_VF(p_hwfn->p_dev)) {
3759                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3760                 return ECORE_INVAL;
3761         }
3762
3763         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3764                 DP_NOTICE(p_hwfn, true,
3765                           "Coalescing configuration not enabled\n");
3766                 return ECORE_INVAL;
3767         }
3768
3769         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3770         p_coal_timeset = p_eth_qzone;
3771         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3772         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3773         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3774
3775         return ECORE_SUCCESS;
3776 }
3777
3778 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3779                                             struct ecore_ptt *p_ptt,
3780                                             u16 coalesce, u8 qid, u16 sb_id)
3781 {
3782         struct ustorm_eth_queue_zone eth_qzone;
3783         u16 fw_qid = 0;
3784         u32 address;
3785         enum _ecore_status_t rc;
3786         u8 timeset, timer_res;
3787
3788         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3789         if (coalesce <= 0x7F) {
3790                 timer_res = 0;
3791         } else if (coalesce <= 0xFF) {
3792                 timer_res = 1;
3793         } else if (coalesce <= 0x1FF) {
3794                 timer_res = 2;
3795         } else {
3796                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3797                 return ECORE_INVAL;
3798         }
3799         timeset = (u8)(coalesce >> timer_res);
3800
3801         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3802         if (rc != ECORE_SUCCESS)
3803                 return rc;
3804
3805         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3806         if (rc != ECORE_SUCCESS)
3807                 goto out;
3808
3809         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3810
3811         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3812                                 sizeof(struct ustorm_eth_queue_zone), timeset);
3813         if (rc != ECORE_SUCCESS)
3814                 goto out;
3815
3816         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3817  out:
3818         return rc;
3819 }
3820
3821 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3822                                             struct ecore_ptt *p_ptt,
3823                                             u16 coalesce, u8 qid, u16 sb_id)
3824 {
3825         struct xstorm_eth_queue_zone eth_qzone;
3826         u16 fw_qid = 0;
3827         u32 address;
3828         enum _ecore_status_t rc;
3829         u8 timeset, timer_res;
3830
3831         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3832         if (coalesce <= 0x7F) {
3833                 timer_res = 0;
3834         } else if (coalesce <= 0xFF) {
3835                 timer_res = 1;
3836         } else if (coalesce <= 0x1FF) {
3837                 timer_res = 2;
3838         } else {
3839                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3840                 return ECORE_INVAL;
3841         }
3842
3843         timeset = (u8)(coalesce >> timer_res);
3844
3845         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3846         if (rc != ECORE_SUCCESS)
3847                 return rc;
3848
3849         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3850         if (rc != ECORE_SUCCESS)
3851                 goto out;
3852
3853         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3854
3855         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3856                                 sizeof(struct xstorm_eth_queue_zone), timeset);
3857         if (rc != ECORE_SUCCESS)
3858                 goto out;
3859
3860         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3861  out:
3862         return rc;
3863 }
3864
3865 /* Calculate final WFQ values for all vports and configure it.
3866  * After this configuration each vport must have
3867  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3868  */
3869 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3870                                                struct ecore_ptt *p_ptt,
3871                                                u32 min_pf_rate)
3872 {
3873         struct init_qm_vport_params *vport_params;
3874         int i;
3875
3876         vport_params = p_hwfn->qm_info.qm_vport_params;
3877
3878         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3879                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3880
3881                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3882                     min_pf_rate;
3883                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3884                                      vport_params[i].first_tx_pq_id,
3885                                      vport_params[i].vport_wfq);
3886         }
3887 }
3888
3889 static void
3890 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3891 {
3892         int i;
3893
3894         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3895                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3896 }
3897
3898 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3899                                              struct ecore_ptt *p_ptt,
3900                                              u32 min_pf_rate)
3901 {
3902         struct init_qm_vport_params *vport_params;
3903         int i;
3904
3905         vport_params = p_hwfn->qm_info.qm_vport_params;
3906
3907         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3908                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3909                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3910                                      vport_params[i].first_tx_pq_id,
3911                                      vport_params[i].vport_wfq);
3912         }
3913 }
3914
3915 /* This function performs several validations for WFQ
3916  * configuration and required min rate for a given vport
3917  * 1. req_rate must be greater than one percent of min_pf_rate.
3918  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3919  *    rates to get less than one percent of min_pf_rate.
3920  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3921  */
3922 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3923                                                  u16 vport_id, u32 req_rate,
3924                                                  u32 min_pf_rate)
3925 {
3926         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3927         int non_requested_count = 0, req_count = 0, i, num_vports;
3928
3929         num_vports = p_hwfn->qm_info.num_vports;
3930
3931 /* Accounting for the vports which are configured for WFQ explicitly */
3932
3933         for (i = 0; i < num_vports; i++) {
3934                 u32 tmp_speed;
3935
3936                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3937                         req_count++;
3938                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3939                         total_req_min_rate += tmp_speed;
3940                 }
3941         }
3942
3943         /* Include current vport data as well */
3944         req_count++;
3945         total_req_min_rate += req_rate;
3946         non_requested_count = num_vports - req_count;
3947
3948         /* validate possible error cases */
3949         if (req_rate > min_pf_rate) {
3950                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3951                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3952                            vport_id, req_rate, min_pf_rate);
3953                 return ECORE_INVAL;
3954         }
3955
3956         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
3957                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3958                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3959                            vport_id, req_rate, min_pf_rate);
3960                 return ECORE_INVAL;
3961         }
3962
3963         /* TBD - for number of vports greater than 100 */
3964         if (num_vports > ECORE_WFQ_UNIT) {
3965                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3966                            "Number of vports is greater than %d\n",
3967                            ECORE_WFQ_UNIT);
3968                 return ECORE_INVAL;
3969         }
3970
3971         if (total_req_min_rate > min_pf_rate) {
3972                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3973                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3974                            total_req_min_rate, min_pf_rate);
3975                 return ECORE_INVAL;
3976         }
3977
3978         /* Data left for non requested vports */
3979         total_left_rate = min_pf_rate - total_req_min_rate;
3980         left_rate_per_vp = total_left_rate / non_requested_count;
3981
3982         /* validate if non requested get < 1% of min bw */
3983         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
3984                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3985                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3986                            left_rate_per_vp, min_pf_rate);
3987                 return ECORE_INVAL;
3988         }
3989
3990         /* now req_rate for given vport passes all scenarios.
3991          * assign final wfq rates to all vports.
3992          */
3993         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3994         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3995
3996         for (i = 0; i < num_vports; i++) {
3997                 if (p_hwfn->qm_info.wfq_data[i].configured)
3998                         continue;
3999
4000                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4001         }
4002
4003         return ECORE_SUCCESS;
4004 }
4005
4006 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4007                                        struct ecore_ptt *p_ptt,
4008                                        u16 vp_id, u32 rate)
4009 {
4010         struct ecore_mcp_link_state *p_link;
4011         int rc = ECORE_SUCCESS;
4012
4013         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4014
4015         if (!p_link->min_pf_rate) {
4016                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4017                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4018                 return rc;
4019         }
4020
4021         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4022
4023         if (rc == ECORE_SUCCESS)
4024                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4025                                                    p_link->min_pf_rate);
4026         else
4027                 DP_NOTICE(p_hwfn, false,
4028                           "Validation failed while configuring min rate\n");
4029
4030         return rc;
4031 }
4032
4033 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4034                                                    struct ecore_ptt *p_ptt,
4035                                                    u32 min_pf_rate)
4036 {
4037         bool use_wfq = false;
4038         int rc = ECORE_SUCCESS;
4039         u16 i;
4040
4041         /* Validate all pre configured vports for wfq */
4042         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4043                 u32 rate;
4044
4045                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4046                         continue;
4047
4048                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4049                 use_wfq = true;
4050
4051                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4052                 if (rc != ECORE_SUCCESS) {
4053                         DP_NOTICE(p_hwfn, false,
4054                                   "WFQ validation failed while configuring min rate\n");
4055                         break;
4056                 }
4057         }
4058
4059         if (rc == ECORE_SUCCESS && use_wfq)
4060                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4061         else
4062                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4063
4064         return rc;
4065 }
4066
4067 /* Main API for ecore clients to configure vport min rate.
4068  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4069  * rate - Speed in Mbps needs to be assigned to a given vport.
4070  */
4071 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4072 {
4073         int i, rc = ECORE_INVAL;
4074
4075         /* TBD - for multiple hardware functions - that is 100 gig */
4076         if (p_dev->num_hwfns > 1) {
4077                 DP_NOTICE(p_dev, false,
4078                           "WFQ configuration is not supported for this device\n");
4079                 return rc;
4080         }
4081
4082         for_each_hwfn(p_dev, i) {
4083                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4084                 struct ecore_ptt *p_ptt;
4085
4086                 p_ptt = ecore_ptt_acquire(p_hwfn);
4087                 if (!p_ptt)
4088                         return ECORE_TIMEOUT;
4089
4090                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4091
4092                 if (rc != ECORE_SUCCESS) {
4093                         ecore_ptt_release(p_hwfn, p_ptt);
4094                         return rc;
4095                 }
4096
4097                 ecore_ptt_release(p_hwfn, p_ptt);
4098         }
4099
4100         return rc;
4101 }
4102
4103 /* API to configure WFQ from mcp link change */
4104 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4105                                            u32 min_pf_rate)
4106 {
4107         int i;
4108
4109         /* TBD - for multiple hardware functions - that is 100 gig */
4110         if (p_dev->num_hwfns > 1) {
4111                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4112                            "WFQ configuration is not supported for this device\n");
4113                 return;
4114         }
4115
4116         for_each_hwfn(p_dev, i) {
4117                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4118
4119                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4120                                                         p_hwfn->p_dpc_ptt,
4121                                                         min_pf_rate);
4122         }
4123 }
4124
4125 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4126                                        struct ecore_ptt *p_ptt,
4127                                        struct ecore_mcp_link_state *p_link,
4128                                        u8 max_bw)
4129 {
4130         int rc = ECORE_SUCCESS;
4131
4132         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4133
4134         if (!p_link->line_speed && (max_bw != 100))
4135                 return rc;
4136
4137         p_link->speed = (p_link->line_speed * max_bw) / 100;
4138         p_hwfn->qm_info.pf_rl = p_link->speed;
4139
4140         /* Since the limiter also affects Tx-switched traffic, we don't want it
4141          * to limit such traffic in case there's no actual limit.
4142          * In that case, set limit to imaginary high boundary.
4143          */
4144         if (max_bw == 100)
4145                 p_hwfn->qm_info.pf_rl = 100000;
4146
4147         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4148                               p_hwfn->qm_info.pf_rl);
4149
4150         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4151                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4152                    p_link->speed);
4153
4154         return rc;
4155 }
4156
4157 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4158 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4159 {
4160         int i, rc = ECORE_INVAL;
4161
4162         if (max_bw < 1 || max_bw > 100) {
4163                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4164                 return rc;
4165         }
4166
4167         for_each_hwfn(p_dev, i) {
4168                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4169                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4170                 struct ecore_mcp_link_state *p_link;
4171                 struct ecore_ptt *p_ptt;
4172
4173                 p_link = &p_lead->mcp_info->link_output;
4174
4175                 p_ptt = ecore_ptt_acquire(p_hwfn);
4176                 if (!p_ptt)
4177                         return ECORE_TIMEOUT;
4178
4179                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4180                                                         p_link, max_bw);
4181
4182                 ecore_ptt_release(p_hwfn, p_ptt);
4183
4184                 if (rc != ECORE_SUCCESS)
4185                         break;
4186         }
4187
4188         return rc;
4189 }
4190
4191 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4192                                        struct ecore_ptt *p_ptt,
4193                                        struct ecore_mcp_link_state *p_link,
4194                                        u8 min_bw)
4195 {
4196         int rc = ECORE_SUCCESS;
4197
4198         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4199         p_hwfn->qm_info.pf_wfq = min_bw;
4200
4201         if (!p_link->line_speed)
4202                 return rc;
4203
4204         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4205
4206         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4207
4208         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4209                    "Configured MIN bandwidth to be %d Mb/sec\n",
4210                    p_link->min_pf_rate);
4211
4212         return rc;
4213 }
4214
4215 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4216 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4217 {
4218         int i, rc = ECORE_INVAL;
4219
4220         if (min_bw < 1 || min_bw > 100) {
4221                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4222                 return rc;
4223         }
4224
4225         for_each_hwfn(p_dev, i) {
4226                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4227                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4228                 struct ecore_mcp_link_state *p_link;
4229                 struct ecore_ptt *p_ptt;
4230
4231                 p_link = &p_lead->mcp_info->link_output;
4232
4233                 p_ptt = ecore_ptt_acquire(p_hwfn);
4234                 if (!p_ptt)
4235                         return ECORE_TIMEOUT;
4236
4237                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4238                                                         p_link, min_bw);
4239                 if (rc != ECORE_SUCCESS) {
4240                         ecore_ptt_release(p_hwfn, p_ptt);
4241                         return rc;
4242                 }
4243
4244                 if (p_link->min_pf_rate) {
4245                         u32 min_rate = p_link->min_pf_rate;
4246
4247                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4248                                                                      p_ptt,
4249                                                                      min_rate);
4250                 }
4251
4252                 ecore_ptt_release(p_hwfn, p_ptt);
4253         }
4254
4255         return rc;
4256 }
4257
4258 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4259 {
4260         struct ecore_mcp_link_state *p_link;
4261
4262         p_link = &p_hwfn->mcp_info->link_output;
4263
4264         if (p_link->min_pf_rate)
4265                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4266                                                  p_link->min_pf_rate);
4267
4268         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4269                     sizeof(*p_hwfn->qm_info.wfq_data) *
4270                     p_hwfn->qm_info.num_vports);
4271 }
4272
4273 int ecore_device_num_engines(struct ecore_dev *p_dev)
4274 {
4275         return ECORE_IS_BB(p_dev) ? 2 : 1;
4276 }
4277
4278 int ecore_device_num_ports(struct ecore_dev *p_dev)
4279 {
4280         /* in CMT always only one port */
4281         if (p_dev->num_hwfns > 1)
4282                 return 1;
4283
4284         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4285 }