1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
9 #include "ecore_gtt_reg_addr.h"
11 #include "ecore_chain.h"
12 #include "ecore_status.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_init_ops.h"
16 #include "ecore_int.h"
17 #include "ecore_cxt.h"
18 #include "ecore_spq.h"
19 #include "ecore_init_fw_funcs.h"
20 #include "ecore_sp_commands.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
24 #include "ecore_mcp.h"
25 #include "ecore_hw_defs.h"
26 #include "mcp_public.h"
27 #include "ecore_iro.h"
29 #include "ecore_dcbx.h"
32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
33 * registers involved are not split and thus configuration is a race where
34 * some of the PFs configuration might be lost.
35 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
36 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
37 * there's more than a single compiled ecore component in system].
39 static osal_spinlock_t qm_lock;
40 static u32 qm_lock_ref_cnt;
43 static bool b_ptt_gtt_init;
46 /******************** Doorbell Recovery *******************/
47 /* The doorbell recovery mechanism consists of a list of entries which represent
48 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
49 * entity needs to register with the mechanism and provide the parameters
50 * describing it's doorbell, including a location where last used doorbell data
51 * can be found. The doorbell execute function will traverse the list and
52 * doorbell all of the registered entries.
54 struct ecore_db_recovery_entry {
55 osal_list_entry_t list_entry;
56 void OSAL_IOMEM *db_addr;
58 enum ecore_db_rec_width db_width;
59 enum ecore_db_rec_space db_space;
63 /* display a single doorbell recovery entry */
64 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
65 struct ecore_db_recovery_entry *db_entry,
68 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
69 action, db_entry, db_entry->db_addr, db_entry->db_data,
70 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
71 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
75 /* doorbell address sanity (address within doorbell bar range) */
76 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
79 /* make sure doorbell address is within the doorbell bar */
80 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
81 (u8 *)p_dev->doorbells + p_dev->db_size) {
83 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
84 db_addr, p_dev->doorbells,
85 (u8 *)p_dev->doorbells + p_dev->db_size);
89 /* make sure doorbell data pointer is not null */
91 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
98 /* find hwfn according to the doorbell address */
99 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
100 void OSAL_IOMEM *db_addr)
102 struct ecore_hwfn *p_hwfn;
104 /* In CMT doorbell bar is split down the middle between engine 0 and
107 if (ECORE_IS_CMT(p_dev))
108 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
109 &p_dev->hwfns[0] : &p_dev->hwfns[1];
111 p_hwfn = ECORE_LEADING_HWFN(p_dev);
116 /* add a new entry to the doorbell recovery mechanism */
117 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
118 void OSAL_IOMEM *db_addr,
120 enum ecore_db_rec_width db_width,
121 enum ecore_db_rec_space db_space)
123 struct ecore_db_recovery_entry *db_entry;
124 struct ecore_hwfn *p_hwfn;
126 /* shortcircuit VFs, for now */
128 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
129 return ECORE_SUCCESS;
132 /* sanitize doorbell address */
133 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
136 /* obtain hwfn from doorbell address */
137 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
140 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
142 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
147 db_entry->db_addr = db_addr;
148 db_entry->db_data = db_data;
149 db_entry->db_width = db_width;
150 db_entry->db_space = db_space;
151 db_entry->hwfn_idx = p_hwfn->my_id;
154 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
156 /* protect the list */
157 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
158 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
159 &p_hwfn->db_recovery_info.list);
160 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
162 return ECORE_SUCCESS;
165 /* remove an entry from the doorbell recovery mechanism */
166 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
167 void OSAL_IOMEM *db_addr,
170 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
171 enum _ecore_status_t rc = ECORE_INVAL;
172 struct ecore_hwfn *p_hwfn;
174 /* shortcircuit VFs, for now */
176 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
177 return ECORE_SUCCESS;
180 /* sanitize doorbell address */
181 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
184 /* obtain hwfn from doorbell address */
185 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
187 /* protect the list */
188 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
189 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
190 &p_hwfn->db_recovery_info.list,
192 struct ecore_db_recovery_entry) {
193 /* search according to db_data addr since db_addr is not unique
196 if (db_entry->db_data == db_data) {
197 ecore_db_recovery_dp_entry(p_hwfn, db_entry,
199 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
200 &p_hwfn->db_recovery_info.list);
206 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
208 if (rc == ECORE_INVAL)
210 DP_NOTICE(p_hwfn, false,
211 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
214 OSAL_FREE(p_dev, db_entry);
219 /* initialize the doorbell recovery mechanism */
220 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
222 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
224 /* make sure db_size was set in p_dev */
225 if (!p_hwfn->p_dev->db_size) {
226 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
230 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
231 #ifdef CONFIG_ECORE_LOCK_ALLOC
232 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
235 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
236 p_hwfn->db_recovery_info.db_recovery_counter = 0;
238 return ECORE_SUCCESS;
241 /* destroy the doorbell recovery mechanism */
242 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
244 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
246 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
247 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
248 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
249 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
250 db_entry = OSAL_LIST_FIRST_ENTRY(
251 &p_hwfn->db_recovery_info.list,
252 struct ecore_db_recovery_entry,
254 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
255 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
256 &p_hwfn->db_recovery_info.list);
257 OSAL_FREE(p_hwfn->p_dev, db_entry);
260 #ifdef CONFIG_ECORE_LOCK_ALLOC
261 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
263 p_hwfn->db_recovery_info.db_recovery_counter = 0;
266 /* print the content of the doorbell recovery mechanism */
267 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
269 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
271 DP_NOTICE(p_hwfn, false,
272 "Dispalying doorbell recovery database. Counter was %d\n",
273 p_hwfn->db_recovery_info.db_recovery_counter);
275 /* protect the list */
276 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
277 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
278 &p_hwfn->db_recovery_info.list,
280 struct ecore_db_recovery_entry) {
281 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
284 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
287 /* ring the doorbell of a single doorbell recovery entry */
288 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
289 struct ecore_db_recovery_entry *db_entry,
290 enum ecore_db_rec_exec db_exec)
292 /* Print according to width */
293 if (db_entry->db_width == DB_REC_WIDTH_32B)
294 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
295 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
296 db_entry->db_addr, *(u32 *)db_entry->db_data);
298 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
299 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
301 *(unsigned long *)(db_entry->db_data));
304 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
308 /* Flush the write combined buffer. Since there are multiple doorbelling
309 * entities using the same address, if we don't flush, a transaction
312 OSAL_WMB(p_hwfn->p_dev);
314 /* Ring the doorbell */
315 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
316 if (db_entry->db_width == DB_REC_WIDTH_32B)
317 DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
318 *(u32 *)(db_entry->db_data));
320 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
321 *(u64 *)(db_entry->db_data));
324 /* Flush the write combined buffer. Next doorbell may come from a
325 * different entity to the same address...
327 OSAL_WMB(p_hwfn->p_dev);
330 /* traverse the doorbell recovery entry list and ring all the doorbells */
331 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
332 enum ecore_db_rec_exec db_exec)
334 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
336 if (db_exec != DB_REC_ONCE) {
337 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
338 p_hwfn->db_recovery_info.db_recovery_counter);
340 /* track amount of times recovery was executed */
341 p_hwfn->db_recovery_info.db_recovery_counter++;
344 /* protect the list */
345 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
346 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
347 &p_hwfn->db_recovery_info.list,
349 struct ecore_db_recovery_entry) {
350 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
351 if (db_exec == DB_REC_ONCE)
355 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
357 /******************** Doorbell Recovery end ****************/
359 /********************************** NIG LLH ***********************************/
361 enum ecore_llh_filter_type {
362 ECORE_LLH_FILTER_TYPE_MAC,
363 ECORE_LLH_FILTER_TYPE_PROTOCOL,
366 struct ecore_llh_mac_filter {
370 struct ecore_llh_protocol_filter {
371 enum ecore_llh_prot_filter_type_t type;
372 u16 source_port_or_eth_type;
376 union ecore_llh_filter {
377 struct ecore_llh_mac_filter mac;
378 struct ecore_llh_protocol_filter protocol;
381 struct ecore_llh_filter_info {
384 enum ecore_llh_filter_type type;
385 union ecore_llh_filter filter;
388 struct ecore_llh_info {
389 /* Number of LLH filters banks */
392 #define MAX_NUM_PPFID 8
393 u8 ppfid_array[MAX_NUM_PPFID];
395 /* Array of filters arrays:
396 * "num_ppfid" elements of filters banks, where each is an array of
397 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
399 struct ecore_llh_filter_info **pp_filters;
402 static void ecore_llh_free(struct ecore_dev *p_dev)
404 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
407 if (p_llh_info != OSAL_NULL) {
408 if (p_llh_info->pp_filters != OSAL_NULL) {
409 for (i = 0; i < p_llh_info->num_ppfid; i++)
410 OSAL_FREE(p_dev, p_llh_info->pp_filters[i]);
413 OSAL_FREE(p_dev, p_llh_info->pp_filters);
416 OSAL_FREE(p_dev, p_llh_info);
417 p_dev->p_llh_info = OSAL_NULL;
420 static enum _ecore_status_t ecore_llh_alloc(struct ecore_dev *p_dev)
422 struct ecore_llh_info *p_llh_info;
426 p_llh_info = OSAL_ZALLOC(p_dev, GFP_KERNEL, sizeof(*p_llh_info));
429 p_dev->p_llh_info = p_llh_info;
431 for (i = 0; i < MAX_NUM_PPFID; i++) {
432 if (!(p_dev->ppfid_bitmap & (0x1 << i)))
435 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
436 DP_VERBOSE(p_dev, ECORE_MSG_SP, "ppfid_array[%d] = %hhd\n",
437 p_llh_info->num_ppfid, i);
438 p_llh_info->num_ppfid++;
441 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
442 p_llh_info->pp_filters = OSAL_ZALLOC(p_dev, GFP_KERNEL, size);
443 if (!p_llh_info->pp_filters)
446 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
447 sizeof(**p_llh_info->pp_filters);
448 for (i = 0; i < p_llh_info->num_ppfid; i++) {
449 p_llh_info->pp_filters[i] = OSAL_ZALLOC(p_dev, GFP_KERNEL,
451 if (!p_llh_info->pp_filters[i])
455 return ECORE_SUCCESS;
458 static enum _ecore_status_t ecore_llh_shadow_sanity(struct ecore_dev *p_dev,
459 u8 ppfid, u8 filter_idx,
462 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
464 if (ppfid >= p_llh_info->num_ppfid) {
465 DP_NOTICE(p_dev, false,
466 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
467 action, ppfid, p_llh_info->num_ppfid);
471 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
472 DP_NOTICE(p_dev, false,
473 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
474 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
478 return ECORE_SUCCESS;
481 #define ECORE_LLH_INVALID_FILTER_IDX 0xff
483 static enum _ecore_status_t
484 ecore_llh_shadow_search_filter(struct ecore_dev *p_dev, u8 ppfid,
485 union ecore_llh_filter *p_filter,
488 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
489 struct ecore_llh_filter_info *p_filters;
490 enum _ecore_status_t rc;
493 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "search");
494 if (rc != ECORE_SUCCESS)
497 *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
499 p_filters = p_llh_info->pp_filters[ppfid];
500 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
501 if (!OSAL_MEMCMP(p_filter, &p_filters[i].filter,
502 sizeof(*p_filter))) {
508 return ECORE_SUCCESS;
511 static enum _ecore_status_t
512 ecore_llh_shadow_get_free_idx(struct ecore_dev *p_dev, u8 ppfid,
515 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
516 struct ecore_llh_filter_info *p_filters;
517 enum _ecore_status_t rc;
520 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "get_free_idx");
521 if (rc != ECORE_SUCCESS)
524 *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
526 p_filters = p_llh_info->pp_filters[ppfid];
527 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
528 if (!p_filters[i].b_enabled) {
534 return ECORE_SUCCESS;
537 static enum _ecore_status_t
538 __ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid, u8 filter_idx,
539 enum ecore_llh_filter_type type,
540 union ecore_llh_filter *p_filter, u32 *p_ref_cnt)
542 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
543 struct ecore_llh_filter_info *p_filters;
544 enum _ecore_status_t rc;
546 rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "add");
547 if (rc != ECORE_SUCCESS)
550 p_filters = p_llh_info->pp_filters[ppfid];
551 if (!p_filters[filter_idx].ref_cnt) {
552 p_filters[filter_idx].b_enabled = true;
553 p_filters[filter_idx].type = type;
554 OSAL_MEMCPY(&p_filters[filter_idx].filter, p_filter,
555 sizeof(p_filters[filter_idx].filter));
558 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
560 return ECORE_SUCCESS;
563 static enum _ecore_status_t
564 ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid,
565 enum ecore_llh_filter_type type,
566 union ecore_llh_filter *p_filter,
567 u8 *p_filter_idx, u32 *p_ref_cnt)
569 enum _ecore_status_t rc;
571 /* Check if the same filter already exist */
572 rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
574 if (rc != ECORE_SUCCESS)
577 /* Find a new entry in case of a new filter */
578 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
579 rc = ecore_llh_shadow_get_free_idx(p_dev, ppfid, p_filter_idx);
580 if (rc != ECORE_SUCCESS)
584 /* No free entry was found */
585 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
586 DP_NOTICE(p_dev, false,
587 "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
589 return ECORE_NORESOURCES;
592 return __ecore_llh_shadow_add_filter(p_dev, ppfid, *p_filter_idx, type,
593 p_filter, p_ref_cnt);
596 static enum _ecore_status_t
597 __ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
598 u8 filter_idx, u32 *p_ref_cnt)
600 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
601 struct ecore_llh_filter_info *p_filters;
602 enum _ecore_status_t rc;
604 rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "remove");
605 if (rc != ECORE_SUCCESS)
608 p_filters = p_llh_info->pp_filters[ppfid];
609 if (!p_filters[filter_idx].ref_cnt) {
610 DP_NOTICE(p_dev, false,
611 "LLH shadow: trying to remove a filter with ref_cnt=0\n");
615 *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
616 if (!p_filters[filter_idx].ref_cnt)
617 OSAL_MEM_ZERO(&p_filters[filter_idx],
618 sizeof(p_filters[filter_idx]));
620 return ECORE_SUCCESS;
623 static enum _ecore_status_t
624 ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
625 union ecore_llh_filter *p_filter,
626 u8 *p_filter_idx, u32 *p_ref_cnt)
628 enum _ecore_status_t rc;
630 rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
632 if (rc != ECORE_SUCCESS)
635 /* No matching filter was found */
636 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
637 DP_NOTICE(p_dev, false,
638 "Failed to find a filter in the LLH shadow\n");
642 return __ecore_llh_shadow_remove_filter(p_dev, ppfid, *p_filter_idx,
646 static enum _ecore_status_t
647 ecore_llh_shadow_remove_all_filters(struct ecore_dev *p_dev, u8 ppfid)
649 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
650 struct ecore_llh_filter_info *p_filters;
651 enum _ecore_status_t rc;
653 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "remove_all");
654 if (rc != ECORE_SUCCESS)
657 p_filters = p_llh_info->pp_filters[ppfid];
658 OSAL_MEM_ZERO(p_filters,
659 NIG_REG_LLH_FUNC_FILTER_EN_SIZE * sizeof(*p_filters));
661 return ECORE_SUCCESS;
664 static enum _ecore_status_t ecore_abs_ppfid(struct ecore_dev *p_dev,
665 u8 rel_ppfid, u8 *p_abs_ppfid)
667 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
668 u8 ppfids = p_llh_info->num_ppfid - 1;
670 if (rel_ppfid >= p_llh_info->num_ppfid) {
671 DP_NOTICE(p_dev, false,
672 "rel_ppfid %d is not valid, available indices are 0..%hhd\n",
677 *p_abs_ppfid = p_llh_info->ppfid_array[rel_ppfid];
679 return ECORE_SUCCESS;
682 static enum _ecore_status_t
683 __ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
685 struct ecore_dev *p_dev = p_hwfn->p_dev;
688 enum _ecore_status_t rc;
690 rc = ecore_mcp_get_engine_config(p_hwfn, p_ptt);
691 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
692 DP_NOTICE(p_hwfn, false,
693 "Failed to get the engine affinity configuration\n");
697 /* RoCE PF is bound to a single engine */
698 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
699 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
700 rc = ecore_llh_set_roce_affinity(p_dev, eng);
701 if (rc != ECORE_SUCCESS) {
702 DP_NOTICE(p_dev, false,
703 "Failed to set the RoCE engine affinity\n");
707 DP_VERBOSE(p_dev, ECORE_MSG_SP,
708 "LLH: Set the engine affinity of RoCE packets as %d\n",
712 /* Storage PF is bound to a single engine while L2 PF uses both */
713 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
714 ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
715 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
716 else /* L2_PERSONALITY */
717 eng = ECORE_BOTH_ENG;
719 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
720 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
721 if (rc != ECORE_SUCCESS) {
722 DP_NOTICE(p_dev, false,
723 "Failed to set the engine affinity of ppfid %d\n",
729 DP_VERBOSE(p_dev, ECORE_MSG_SP,
730 "LLH: Set the engine affinity of non-RoCE packets as %d\n",
733 return ECORE_SUCCESS;
736 static enum _ecore_status_t
737 ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
738 bool avoid_eng_affin)
740 struct ecore_dev *p_dev = p_hwfn->p_dev;
741 enum _ecore_status_t rc;
743 /* Backwards compatible mode:
744 * - RoCE packets - Use engine 0.
745 * - Non-RoCE packets - Use connection based classification for L2 PFs,
746 * and engine 0 otherwise.
748 if (avoid_eng_affin) {
752 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
754 rc = ecore_llh_set_roce_affinity(p_dev, eng);
755 if (rc != ECORE_SUCCESS) {
756 DP_NOTICE(p_dev, false,
757 "Failed to set the RoCE engine affinity\n");
761 DP_VERBOSE(p_dev, ECORE_MSG_SP,
762 "LLH [backwards compatible mode]: Set the engine affinity of RoCE packets as %d\n",
766 eng = (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
767 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) ? ECORE_ENG0
769 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
770 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
771 if (rc != ECORE_SUCCESS) {
772 DP_NOTICE(p_dev, false,
773 "Failed to set the engine affinity of ppfid %d\n",
779 DP_VERBOSE(p_dev, ECORE_MSG_SP,
780 "LLH [backwards compatible mode]: Set the engine affinity of non-RoCE packets as %d\n",
783 return ECORE_SUCCESS;
786 return __ecore_llh_set_engine_affin(p_hwfn, p_ptt);
789 static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn,
790 struct ecore_ptt *p_ptt,
791 bool avoid_eng_affin)
793 struct ecore_dev *p_dev = p_hwfn->p_dev;
795 enum _ecore_status_t rc;
797 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
800 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
801 if (rc != ECORE_SUCCESS)
804 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
805 ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
808 if (OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
809 !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {
810 rc = ecore_llh_add_mac_filter(p_dev, 0,
811 p_hwfn->hw_info.hw_mac_addr);
812 if (rc != ECORE_SUCCESS)
813 DP_NOTICE(p_dev, false,
814 "Failed to add an LLH filter with the primary MAC\n");
817 if (ECORE_IS_CMT(p_dev)) {
818 rc = ecore_llh_set_engine_affin(p_hwfn, p_ptt, avoid_eng_affin);
819 if (rc != ECORE_SUCCESS)
823 return ECORE_SUCCESS;
826 u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev)
828 return p_dev->p_llh_info->num_ppfid;
831 enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev)
833 return p_dev->l2_affin_hint ? ECORE_ENG1 : ECORE_ENG0;
836 /* TBD - should be removed when these definitions are available in reg_addr.h */
837 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3
838 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0
839 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3
840 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2
842 enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev,
843 u8 ppfid, enum ecore_eng eng)
845 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
846 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
847 u32 addr, val, eng_sel;
848 enum _ecore_status_t rc = ECORE_SUCCESS;
851 if (p_ptt == OSAL_NULL)
854 if (!ECORE_IS_CMT(p_dev))
857 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
858 if (rc != ECORE_SUCCESS)
872 DP_NOTICE(p_dev, false,
873 "Invalid affinity value for ppfid [%d]\n", eng);
878 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
879 val = ecore_rd(p_hwfn, p_ptt, addr);
880 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
881 ecore_wr(p_hwfn, p_ptt, addr, val);
883 /* The iWARP affinity is set as the affinity of ppfid 0 */
884 if (!ppfid && ECORE_IS_IWARP_PERSONALITY(p_hwfn))
885 p_dev->iwarp_affin = (eng == ECORE_ENG1) ? 1 : 0;
887 ecore_ptt_release(p_hwfn, p_ptt);
892 enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,
895 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
896 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
897 u32 addr, val, eng_sel;
898 enum _ecore_status_t rc = ECORE_SUCCESS;
901 if (p_ptt == OSAL_NULL)
904 if (!ECORE_IS_CMT(p_dev))
916 ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
917 0xf /* QP bit 15 */);
920 DP_NOTICE(p_dev, false,
921 "Invalid affinity value for RoCE [%d]\n", eng);
926 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
927 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
928 if (rc != ECORE_SUCCESS)
931 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
932 val = ecore_rd(p_hwfn, p_ptt, addr);
933 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
934 ecore_wr(p_hwfn, p_ptt, addr, val);
937 ecore_ptt_release(p_hwfn, p_ptt);
942 struct ecore_llh_filter_details {
950 static enum _ecore_status_t
951 ecore_llh_access_filter(struct ecore_hwfn *p_hwfn,
952 struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx,
953 struct ecore_llh_filter_details *p_details,
956 u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
957 struct dmae_params params;
958 enum _ecore_status_t rc;
961 /* The NIG/LLH registers that are accessed in this function have only 16
962 * rows which are exposed to a PF. I.e. only the 16 filters of its
964 * Accessing filters of other ppfids requires pretending to other PFs,
965 * and thus the usage of the ecore_ppfid_rd/wr() functions.
968 /* Filter enable - should be done first when removing a filter */
969 if (b_write_access && !p_details->enable) {
970 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
971 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
976 addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
977 OSAL_MEMSET(¶ms, 0, sizeof(params));
979 if (b_write_access) {
980 SET_FIELD(params.flags, DMAE_PARAMS_DST_PF_VALID, 0x1);
981 params.dst_pf_id = pfid;
982 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
983 (u64)(osal_uintptr_t)&p_details->value,
984 addr, 2 /* size_in_dwords */, ¶ms);
986 SET_FIELD(params.flags, DMAE_PARAMS_SRC_PF_VALID, 0x1);
987 SET_FIELD(params.flags, DMAE_PARAMS_COMPLETION_DST, 0x1);
988 params.src_pf_id = pfid;
989 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, addr,
990 (u64)(osal_uintptr_t)&p_details->value,
991 2 /* size_in_dwords */, ¶ms);
994 if (rc != ECORE_SUCCESS)
998 addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
1000 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, p_details->mode);
1002 p_details->mode = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1005 /* Filter protocol type */
1006 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
1008 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1009 p_details->protocol_type);
1011 p_details->protocol_type = ecore_ppfid_rd(p_hwfn, p_ptt,
1014 /* Filter header select */
1015 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
1017 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1018 p_details->hdr_sel);
1020 p_details->hdr_sel = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1023 /* Filter enable - should be done last when adding a filter */
1024 if (!b_write_access || p_details->enable) {
1025 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
1027 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1030 p_details->enable = ecore_ppfid_rd(p_hwfn, p_ptt,
1034 return ECORE_SUCCESS;
1037 static enum _ecore_status_t
1038 ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1039 u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type,
1042 struct ecore_llh_filter_details filter_details;
1044 filter_details.enable = 1;
1045 filter_details.value = ((u64)high << 32) | low;
1046 filter_details.hdr_sel =
1047 OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
1048 1 : /* inner/encapsulated header */
1049 0; /* outer/tunnel header */
1050 filter_details.protocol_type = filter_prot_type;
1051 filter_details.mode = filter_prot_type ?
1052 1 : /* protocol-based classification */
1053 0; /* MAC-address based classification */
1055 return ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1057 true /* write access */);
1060 static enum _ecore_status_t
1061 ecore_llh_remove_filter(struct ecore_hwfn *p_hwfn,
1062 struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
1064 struct ecore_llh_filter_details filter_details;
1066 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1068 return ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1070 true /* write access */);
1073 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1074 u8 mac_addr[ETH_ALEN])
1076 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1077 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1078 union ecore_llh_filter filter;
1079 u8 filter_idx, abs_ppfid;
1080 u32 high, low, ref_cnt;
1081 enum _ecore_status_t rc = ECORE_SUCCESS;
1083 if (p_ptt == OSAL_NULL)
1086 if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1089 OSAL_MEM_ZERO(&filter, sizeof(filter));
1090 OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1091 rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1092 ECORE_LLH_FILTER_TYPE_MAC,
1093 &filter, &filter_idx, &ref_cnt);
1094 if (rc != ECORE_SUCCESS)
1097 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1098 if (rc != ECORE_SUCCESS)
1101 /* Configure the LLH only in case of a new the filter */
1103 high = mac_addr[1] | (mac_addr[0] << 8);
1104 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1105 (mac_addr[2] << 24);
1106 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1108 if (rc != ECORE_SUCCESS)
1112 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1113 "LLH: Added MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1114 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1115 mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1121 DP_NOTICE(p_dev, false,
1122 "LLH: Failed to add MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd\n",
1123 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1124 mac_addr[4], mac_addr[5], ppfid);
1126 ecore_ptt_release(p_hwfn, p_ptt);
1131 static enum _ecore_status_t
1132 ecore_llh_protocol_filter_stringify(struct ecore_dev *p_dev,
1133 enum ecore_llh_prot_filter_type_t type,
1134 u16 source_port_or_eth_type, u16 dest_port,
1135 char *str, osal_size_t str_len)
1138 case ECORE_LLH_FILTER_ETHERTYPE:
1139 OSAL_SNPRINTF(str, str_len, "Ethertype 0x%04x",
1140 source_port_or_eth_type);
1142 case ECORE_LLH_FILTER_TCP_SRC_PORT:
1143 OSAL_SNPRINTF(str, str_len, "TCP src port 0x%04x",
1144 source_port_or_eth_type);
1146 case ECORE_LLH_FILTER_UDP_SRC_PORT:
1147 OSAL_SNPRINTF(str, str_len, "UDP src port 0x%04x",
1148 source_port_or_eth_type);
1150 case ECORE_LLH_FILTER_TCP_DEST_PORT:
1151 OSAL_SNPRINTF(str, str_len, "TCP dst port 0x%04x", dest_port);
1153 case ECORE_LLH_FILTER_UDP_DEST_PORT:
1154 OSAL_SNPRINTF(str, str_len, "UDP dst port 0x%04x", dest_port);
1156 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1157 OSAL_SNPRINTF(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1158 source_port_or_eth_type, dest_port);
1160 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1161 OSAL_SNPRINTF(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1162 source_port_or_eth_type, dest_port);
1165 DP_NOTICE(p_dev, true,
1166 "Non valid LLH protocol filter type %d\n", type);
1170 return ECORE_SUCCESS;
1173 static enum _ecore_status_t
1174 ecore_llh_protocol_filter_to_hilo(struct ecore_dev *p_dev,
1175 enum ecore_llh_prot_filter_type_t type,
1176 u16 source_port_or_eth_type, u16 dest_port,
1177 u32 *p_high, u32 *p_low)
1183 case ECORE_LLH_FILTER_ETHERTYPE:
1184 *p_high = source_port_or_eth_type;
1186 case ECORE_LLH_FILTER_TCP_SRC_PORT:
1187 case ECORE_LLH_FILTER_UDP_SRC_PORT:
1188 *p_low = source_port_or_eth_type << 16;
1190 case ECORE_LLH_FILTER_TCP_DEST_PORT:
1191 case ECORE_LLH_FILTER_UDP_DEST_PORT:
1194 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1195 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1196 *p_low = (source_port_or_eth_type << 16) | dest_port;
1199 DP_NOTICE(p_dev, true,
1200 "Non valid LLH protocol filter type %d\n", type);
1204 return ECORE_SUCCESS;
1207 enum _ecore_status_t
1208 ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1209 enum ecore_llh_prot_filter_type_t type,
1210 u16 source_port_or_eth_type, u16 dest_port)
1212 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1213 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1214 u8 filter_idx, abs_ppfid, type_bitmap;
1216 union ecore_llh_filter filter;
1217 u32 high, low, ref_cnt;
1218 enum _ecore_status_t rc = ECORE_SUCCESS;
1220 if (p_ptt == OSAL_NULL)
1223 if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1226 rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1227 source_port_or_eth_type,
1228 dest_port, str, sizeof(str));
1229 if (rc != ECORE_SUCCESS)
1232 OSAL_MEM_ZERO(&filter, sizeof(filter));
1233 filter.protocol.type = type;
1234 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1235 filter.protocol.dest_port = dest_port;
1236 rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1237 ECORE_LLH_FILTER_TYPE_PROTOCOL,
1238 &filter, &filter_idx, &ref_cnt);
1239 if (rc != ECORE_SUCCESS)
1242 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1243 if (rc != ECORE_SUCCESS)
1246 /* Configure the LLH only in case of a new the filter */
1248 rc = ecore_llh_protocol_filter_to_hilo(p_dev, type,
1249 source_port_or_eth_type,
1250 dest_port, &high, &low);
1251 if (rc != ECORE_SUCCESS)
1254 type_bitmap = 0x1 << type;
1255 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1256 type_bitmap, high, low);
1257 if (rc != ECORE_SUCCESS)
1261 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1262 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1263 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1268 DP_NOTICE(p_hwfn, false,
1269 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1272 ecore_ptt_release(p_hwfn, p_ptt);
1277 void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1278 u8 mac_addr[ETH_ALEN])
1280 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1281 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1282 union ecore_llh_filter filter;
1283 u8 filter_idx, abs_ppfid;
1284 enum _ecore_status_t rc = ECORE_SUCCESS;
1287 if (p_ptt == OSAL_NULL)
1290 if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1293 OSAL_MEM_ZERO(&filter, sizeof(filter));
1294 OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1295 rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1297 if (rc != ECORE_SUCCESS)
1300 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1301 if (rc != ECORE_SUCCESS)
1304 /* Remove from the LLH in case the filter is not in use */
1306 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1308 if (rc != ECORE_SUCCESS)
1312 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1313 "LLH: Removed MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1314 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1315 mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1321 DP_NOTICE(p_dev, false,
1322 "LLH: Failed to remove MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd\n",
1323 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1324 mac_addr[4], mac_addr[5], ppfid);
1326 ecore_ptt_release(p_hwfn, p_ptt);
1329 void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1330 enum ecore_llh_prot_filter_type_t type,
1331 u16 source_port_or_eth_type,
1334 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1335 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1336 u8 filter_idx, abs_ppfid;
1338 union ecore_llh_filter filter;
1339 enum _ecore_status_t rc = ECORE_SUCCESS;
1342 if (p_ptt == OSAL_NULL)
1345 if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1348 rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1349 source_port_or_eth_type,
1350 dest_port, str, sizeof(str));
1351 if (rc != ECORE_SUCCESS)
1354 OSAL_MEM_ZERO(&filter, sizeof(filter));
1355 filter.protocol.type = type;
1356 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1357 filter.protocol.dest_port = dest_port;
1358 rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1360 if (rc != ECORE_SUCCESS)
1363 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1364 if (rc != ECORE_SUCCESS)
1367 /* Remove from the LLH in case the filter is not in use */
1369 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1371 if (rc != ECORE_SUCCESS)
1375 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1376 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1377 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1382 DP_NOTICE(p_dev, false,
1383 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1386 ecore_ptt_release(p_hwfn, p_ptt);
1389 void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid)
1391 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1392 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1393 u8 filter_idx, abs_ppfid;
1394 enum _ecore_status_t rc = ECORE_SUCCESS;
1396 if (p_ptt == OSAL_NULL)
1399 if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1400 !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1403 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1404 if (rc != ECORE_SUCCESS)
1407 rc = ecore_llh_shadow_remove_all_filters(p_dev, ppfid);
1408 if (rc != ECORE_SUCCESS)
1411 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1413 rc = ecore_llh_remove_filter(p_hwfn, p_ptt,
1414 abs_ppfid, filter_idx);
1415 if (rc != ECORE_SUCCESS)
1419 ecore_ptt_release(p_hwfn, p_ptt);
1422 void ecore_llh_clear_all_filters(struct ecore_dev *p_dev)
1426 if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1427 !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1430 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)
1431 ecore_llh_clear_ppfid_filters(p_dev, ppfid);
1434 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1435 struct ecore_ptt *p_ptt, u32 addr,
1438 struct ecore_dev *p_dev = p_hwfn->p_dev;
1439 u8 ppfid, abs_ppfid;
1440 enum _ecore_status_t rc;
1442 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1443 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1444 if (rc != ECORE_SUCCESS)
1447 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, val);
1450 return ECORE_SUCCESS;
1453 enum _ecore_status_t
1454 ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid)
1456 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1457 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1458 struct ecore_llh_filter_details filter_details;
1459 u8 abs_ppfid, filter_idx;
1461 enum _ecore_status_t rc;
1466 rc = ecore_abs_ppfid(p_hwfn->p_dev, ppfid, &abs_ppfid);
1467 if (rc != ECORE_SUCCESS)
1470 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
1471 DP_NOTICE(p_hwfn, false,
1472 "[rel_pf_id %hhd, ppfid={rel %hhd, abs %hhd}, engine_sel 0x%x]\n",
1473 p_hwfn->rel_pf_id, ppfid, abs_ppfid,
1474 ecore_rd(p_hwfn, p_ptt, addr));
1476 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1478 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1479 rc = ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid,
1480 filter_idx, &filter_details,
1481 false /* read access */);
1482 if (rc != ECORE_SUCCESS)
1485 DP_NOTICE(p_hwfn, false,
1486 "filter %2hhd: enable %d, value 0x%016lx, mode %d, protocol_type 0x%x, hdr_sel 0x%x\n",
1487 filter_idx, filter_details.enable,
1488 (unsigned long)filter_details.value,
1489 filter_details.mode,
1490 filter_details.protocol_type, filter_details.hdr_sel);
1495 ecore_ptt_release(p_hwfn, p_ptt);
1500 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev)
1503 enum _ecore_status_t rc;
1505 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1506 rc = ecore_llh_dump_ppfid(p_dev, ppfid);
1507 if (rc != ECORE_SUCCESS)
1511 return ECORE_SUCCESS;
1514 /******************************* NIG LLH - End ********************************/
1517 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
1518 * load the driver. The number was
1523 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
1525 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
1526 struct ecore_ptt *p_ptt,
1529 u32 bar_reg = (bar_id == BAR_ID_0 ?
1530 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1533 if (IS_VF(p_hwfn->p_dev))
1534 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
1536 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
1538 return 1 << (val + 15);
1540 /* The above registers were updated in the past only in CMT mode. Since
1541 * they were found to be useful MFW started updating them from 8.7.7.0.
1542 * In older MFW versions they are set to 0 which means disabled.
1544 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
1546 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1547 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1550 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1557 void ecore_init_dp(struct ecore_dev *p_dev,
1558 u32 dp_module, u8 dp_level, void *dp_ctx)
1562 p_dev->dp_level = dp_level;
1563 p_dev->dp_module = dp_module;
1564 p_dev->dp_ctx = dp_ctx;
1565 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1566 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1568 p_hwfn->dp_level = dp_level;
1569 p_hwfn->dp_module = dp_module;
1570 p_hwfn->dp_ctx = dp_ctx;
1574 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
1578 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1579 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1581 p_hwfn->p_dev = p_dev;
1583 p_hwfn->b_active = false;
1585 #ifdef CONFIG_ECORE_LOCK_ALLOC
1586 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
1589 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
1592 /* hwfn 0 is always active */
1593 p_dev->hwfns[0].b_active = true;
1595 /* set the default cache alignment to 128 (may be overridden later) */
1596 p_dev->cache_shift = 7;
1597 return ECORE_SUCCESS;
1598 #ifdef CONFIG_ECORE_LOCK_ALLOC
1601 struct ecore_hwfn *p_hwfn = OSAL_NULL;
1603 p_hwfn = &p_dev->hwfns[i];
1604 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
1610 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
1612 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1614 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
1615 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
1616 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
1617 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
1620 static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)
1622 OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);
1623 p_hwfn->dbg_user_info = OSAL_NULL;
1626 void ecore_resc_free(struct ecore_dev *p_dev)
1631 for_each_hwfn(p_dev, i)
1632 ecore_l2_free(&p_dev->hwfns[i]);
1636 OSAL_FREE(p_dev, p_dev->fw_data);
1638 OSAL_FREE(p_dev, p_dev->reset_stats);
1640 ecore_llh_free(p_dev);
1642 for_each_hwfn(p_dev, i) {
1643 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1645 ecore_cxt_mngr_free(p_hwfn);
1646 ecore_qm_info_free(p_hwfn);
1647 ecore_spq_free(p_hwfn);
1648 ecore_eq_free(p_hwfn);
1649 ecore_consq_free(p_hwfn);
1650 ecore_int_free(p_hwfn);
1651 ecore_iov_free(p_hwfn);
1652 ecore_l2_free(p_hwfn);
1653 ecore_dmae_info_free(p_hwfn);
1654 ecore_dcbx_info_free(p_hwfn);
1655 ecore_dbg_user_data_free(p_hwfn);
1656 ecore_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
1657 /* @@@TBD Flush work-queue ? */
1659 /* destroy doorbell recovery mechanism */
1660 ecore_db_recovery_teardown(p_hwfn);
1664 /******************** QM initialization *******************/
1666 /* bitmaps for indicating active traffic classes.
1667 * Special case for Arrowhead 4 port
1669 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
1670 #define ACTIVE_TCS_BMAP 0x9f
1671 /* 0..3 actually used, OOO and high priority stuff all use 3 */
1672 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1674 /* determines the physical queue flags for a given PF. */
1675 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
1680 flags = PQ_FLAGS_LB;
1683 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
1684 flags |= PQ_FLAGS_VFS;
1685 if (IS_ECORE_PACING(p_hwfn))
1686 flags |= PQ_FLAGS_RLS;
1688 /* protocol flags */
1689 switch (p_hwfn->hw_info.personality) {
1691 if (!IS_ECORE_PACING(p_hwfn))
1692 flags |= PQ_FLAGS_MCOS;
1694 case ECORE_PCI_FCOE:
1695 flags |= PQ_FLAGS_OFLD;
1697 case ECORE_PCI_ISCSI:
1698 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1700 case ECORE_PCI_ETH_ROCE:
1701 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1702 if (!IS_ECORE_PACING(p_hwfn))
1703 flags |= PQ_FLAGS_MCOS;
1705 case ECORE_PCI_ETH_IWARP:
1706 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1707 if (!IS_ECORE_PACING(p_hwfn))
1708 flags |= PQ_FLAGS_MCOS;
1711 DP_ERR(p_hwfn, "unknown personality %d\n",
1712 p_hwfn->hw_info.personality);
1718 /* Getters for resource amounts necessary for qm initialization */
1719 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
1721 return p_hwfn->hw_info.num_hw_tc;
1724 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
1726 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
1727 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
1730 #define NUM_DEFAULT_RLS 1
1732 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
1734 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
1736 /* num RLs can't exceed resource amount of rls or vports or the
1739 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
1740 RESC_NUM(p_hwfn, ECORE_VPORT));
1742 /* make sure after we reserve the default and VF rls we'll have
1745 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
1746 DP_NOTICE(p_hwfn, false,
1747 "no rate limiters left for PF rate limiting"
1748 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
1752 /* subtract rls necessary for VFs and one default one for the PF */
1753 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1758 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
1760 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1762 /* all pqs share the same vport (hence the 1 below), except for vfs
1765 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1766 ecore_init_qm_get_num_pf_rls(p_hwfn) +
1767 (!!(PQ_FLAGS_VFS & pq_flags)) *
1768 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
1771 /* calc amount of PQs according to the requested flags */
1772 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
1774 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1776 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1777 ecore_init_qm_get_num_pf_rls(p_hwfn) +
1778 (!!(PQ_FLAGS_MCOS & pq_flags)) *
1779 ecore_init_qm_get_num_tcs(p_hwfn) +
1780 (!!(PQ_FLAGS_LB & pq_flags)) +
1781 (!!(PQ_FLAGS_OOO & pq_flags)) +
1782 (!!(PQ_FLAGS_ACK & pq_flags)) +
1783 (!!(PQ_FLAGS_OFLD & pq_flags)) +
1784 (!!(PQ_FLAGS_VFS & pq_flags)) *
1785 ecore_init_qm_get_num_vfs(p_hwfn);
1788 /* initialize the top level QM params */
1789 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
1791 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1794 /* pq and vport bases for this PF */
1795 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
1796 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
1798 /* rate limiting and weighted fair queueing are always enabled */
1799 qm_info->vport_rl_en = 1;
1800 qm_info->vport_wfq_en = 1;
1802 /* TC config is different for AH 4 port */
1803 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1805 /* in AH 4 port we have fewer TCs per port */
1806 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1809 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
1812 if (!qm_info->ooo_tc)
1813 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1817 /* initialize qm vport params */
1818 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
1820 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1823 /* all vports participate in weighted fair queueing */
1824 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
1825 qm_info->qm_vport_params[i].wfq = 1;
1828 /* initialize qm port params */
1829 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
1831 /* Initialize qm port parameters */
1832 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
1833 struct ecore_dev *p_dev = p_hwfn->p_dev;
1835 /* indicate how ooo and high pri traffic is dealt with */
1836 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1837 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
1839 for (i = 0; i < num_ports; i++) {
1840 struct init_qm_port_params *p_qm_port =
1841 &p_hwfn->qm_info.qm_port_params[i];
1842 u16 pbf_max_cmd_lines;
1844 p_qm_port->active = 1;
1845 p_qm_port->active_phys_tcs = active_phys_tcs;
1846 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(p_dev);
1847 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
1848 p_qm_port->num_btb_blocks =
1849 NUM_OF_BTB_BLOCKS(p_dev) / num_ports;
1853 /* Reset the params which must be reset for qm init. QM init may be called as
1854 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1855 * params may be affected by the init but would simply recalculate to the same
1856 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1857 * affected as these amounts stay the same.
1859 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
1861 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1863 qm_info->num_pqs = 0;
1864 qm_info->num_vports = 0;
1865 qm_info->num_pf_rls = 0;
1866 qm_info->num_vf_pqs = 0;
1867 qm_info->first_vf_pq = 0;
1868 qm_info->first_mcos_pq = 0;
1869 qm_info->first_rl_pq = 0;
1872 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
1874 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1876 qm_info->num_vports++;
1878 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1880 "vport overflow! qm_info->num_vports %d,"
1881 " qm_init_get_num_vports() %d\n",
1882 qm_info->num_vports,
1883 ecore_init_qm_get_num_vports(p_hwfn));
1886 /* initialize a single pq and manage qm_info resources accounting.
1887 * The pq_init_flags param determines whether the PQ is rate limited
1889 * and whether a new vport is allocated to the pq or not (i.e. vport will be
1893 /* flags for pq init */
1894 #define PQ_INIT_SHARE_VPORT (1 << 0)
1895 #define PQ_INIT_PF_RL (1 << 1)
1896 #define PQ_INIT_VF_RL (1 << 2)
1898 /* defines for pq init */
1899 #define PQ_INIT_DEFAULT_WRR_GROUP 1
1900 #define PQ_INIT_DEFAULT_TC 0
1901 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
1903 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
1904 struct ecore_qm_info *qm_info,
1905 u8 tc, u32 pq_init_flags)
1907 u16 pq_idx = qm_info->num_pqs, max_pq =
1908 ecore_init_qm_get_num_pqs(p_hwfn);
1910 if (pq_idx > max_pq)
1912 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1914 /* init pq params */
1915 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1916 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1917 qm_info->num_vports;
1918 qm_info->qm_pq_params[pq_idx].tc_id = tc;
1919 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1920 qm_info->qm_pq_params[pq_idx].rl_valid =
1921 (pq_init_flags & PQ_INIT_PF_RL ||
1922 pq_init_flags & PQ_INIT_VF_RL);
1924 /* The "rl_id" is set as the "vport_id" */
1925 qm_info->qm_pq_params[pq_idx].rl_id =
1926 qm_info->qm_pq_params[pq_idx].vport_id;
1928 /* qm params accounting */
1930 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1931 qm_info->num_vports++;
1933 if (pq_init_flags & PQ_INIT_PF_RL)
1934 qm_info->num_pf_rls++;
1936 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1938 "vport overflow! qm_info->num_vports %d,"
1939 " qm_init_get_num_vports() %d\n",
1940 qm_info->num_vports,
1941 ecore_init_qm_get_num_vports(p_hwfn));
1943 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
1944 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
1945 " qm_init_get_num_pf_rls() %d\n",
1946 qm_info->num_pf_rls,
1947 ecore_init_qm_get_num_pf_rls(p_hwfn));
1950 /* get pq index according to PQ_FLAGS */
1951 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
1954 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1956 /* Can't have multiple flags set here */
1957 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
1958 sizeof(pq_flags)) > 1)
1963 return &qm_info->first_rl_pq;
1965 return &qm_info->first_mcos_pq;
1967 return &qm_info->pure_lb_pq;
1969 return &qm_info->ooo_pq;
1971 return &qm_info->pure_ack_pq;
1973 return &qm_info->offload_pq;
1975 return &qm_info->first_vf_pq;
1981 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
1985 /* save pq index in qm info */
1986 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
1987 u32 pq_flags, u16 pq_val)
1989 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1991 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
1994 /* get tx pq index, with the PQ TX base already set (ready for context init) */
1995 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
1997 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1999 return *base_pq_idx + CM_TX_PQ_BASE;
2002 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
2004 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
2007 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
2009 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
2012 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
2014 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
2017 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
2019 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
2022 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
2024 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
2026 /* for rate limiters, it is okay to use the modulo behavior - no
2029 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + (rl % max_rl);
2032 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
2034 u16 start_pq, pq, qm_pq_idx;
2036 pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
2037 start_pq = p_hwfn->qm_info.start_pq;
2038 qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;
2040 if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
2042 "qm_pq_idx %d must be smaller than %d\n",
2043 qm_pq_idx, p_hwfn->qm_info.num_pqs);
2046 return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
2049 /* Functions for creating specific types of pqs */
2050 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
2052 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2054 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
2057 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
2058 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
2061 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
2063 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2065 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
2068 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
2069 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
2072 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
2074 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2076 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
2079 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
2080 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2083 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
2085 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2087 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
2090 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
2091 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2094 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
2096 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2099 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
2102 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
2103 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
2104 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
2107 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
2109 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2110 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
2112 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
2115 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
2117 qm_info->num_vf_pqs = num_vfs;
2118 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
2119 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
2123 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
2125 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
2126 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2128 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
2131 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
2132 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
2133 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
2137 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
2139 /* rate limited pqs, must come first (FW assumption) */
2140 ecore_init_qm_rl_pqs(p_hwfn);
2142 /* pqs for multi cos */
2143 ecore_init_qm_mcos_pqs(p_hwfn);
2145 /* pure loopback pq */
2146 ecore_init_qm_lb_pq(p_hwfn);
2148 /* out of order pq */
2149 ecore_init_qm_ooo_pq(p_hwfn);
2152 ecore_init_qm_pure_ack_pq(p_hwfn);
2154 /* pq for offloaded protocol */
2155 ecore_init_qm_offload_pq(p_hwfn);
2157 /* done sharing vports */
2158 ecore_init_qm_advance_vport(p_hwfn);
2161 ecore_init_qm_vf_pqs(p_hwfn);
2164 /* compare values of getters against resources amounts */
2165 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
2167 if (ecore_init_qm_get_num_vports(p_hwfn) >
2168 RESC_NUM(p_hwfn, ECORE_VPORT)) {
2169 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
2173 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
2174 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
2178 return ECORE_SUCCESS;
2182 * Function for verbose printing of the qm initialization results
2184 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
2186 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2187 struct init_qm_vport_params *vport;
2188 struct init_qm_port_params *port;
2189 struct init_qm_pq_params *pq;
2192 /* top level params */
2193 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2194 "qm init top level params: start_pq %d, start_vport %d,"
2195 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
2196 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
2197 qm_info->offload_pq, qm_info->pure_ack_pq);
2198 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2199 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
2200 " num_vports %d, max_phys_tcs_per_port %d\n",
2201 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
2202 qm_info->num_vf_pqs, qm_info->num_vports,
2203 qm_info->max_phys_tcs_per_port);
2204 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2205 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
2206 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2207 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
2208 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
2209 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
2212 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
2213 port = &qm_info->qm_port_params[i];
2214 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2215 "port idx %d, active %d, active_phys_tcs %d,"
2216 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
2218 i, port->active, port->active_phys_tcs,
2219 port->num_pbf_cmd_lines, port->num_btb_blocks,
2224 for (i = 0; i < qm_info->num_vports; i++) {
2225 vport = &qm_info->qm_vport_params[i];
2226 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "vport idx %d, wfq %d, first_tx_pq_id [ ",
2227 qm_info->start_vport + i, vport->wfq);
2228 for (tc = 0; tc < NUM_OF_TCS; tc++)
2229 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
2230 vport->first_tx_pq_id[tc]);
2231 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
2235 for (i = 0; i < qm_info->num_pqs; i++) {
2236 pq = &qm_info->qm_pq_params[i];
2237 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2238 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d, rl_id %d\n",
2239 qm_info->start_pq + i, pq->port_id, pq->vport_id,
2240 pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id);
2244 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
2246 /* reset params required for init run */
2247 ecore_init_qm_reset_params(p_hwfn);
2249 /* init QM top level params */
2250 ecore_init_qm_params(p_hwfn);
2252 /* init QM port params */
2253 ecore_init_qm_port_params(p_hwfn);
2255 /* init QM vport params */
2256 ecore_init_qm_vport_params(p_hwfn);
2258 /* init QM physical queue params */
2259 ecore_init_qm_pq_params(p_hwfn);
2261 /* display all that init */
2262 ecore_dp_init_qm_params(p_hwfn);
2265 /* This function reconfigures the QM pf on the fly.
2266 * For this purpose we:
2267 * 1. reconfigure the QM database
2268 * 2. set new values to runtime array
2269 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2270 * 4. activate init tool in QM_PF stage
2271 * 5. send an sdm_qm_cmd through rbc interface to release the QM
2273 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
2274 struct ecore_ptt *p_ptt)
2276 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2278 enum _ecore_status_t rc = ECORE_SUCCESS;
2280 /* multiple flows can issue qm reconf. Need to lock */
2281 OSAL_SPIN_LOCK(&qm_lock);
2283 /* initialize ecore's qm data structure */
2284 ecore_init_qm_info(p_hwfn);
2286 /* stop PF's qm queues */
2287 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2288 qm_info->start_pq, qm_info->num_pqs);
2294 /* clear the QM_PF runtime phase leftovers from previous init */
2295 ecore_init_clear_rt_data(p_hwfn);
2297 /* prepare QM portion of runtime array */
2298 ecore_qm_init_pf(p_hwfn, p_ptt, false);
2300 /* activate init tool on runtime array */
2301 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2302 p_hwfn->hw_info.hw_mode);
2304 /* start PF's qm queues */
2305 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2306 qm_info->start_pq, qm_info->num_pqs);
2311 OSAL_SPIN_UNLOCK(&qm_lock);
2316 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
2318 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2319 enum _ecore_status_t rc;
2321 rc = ecore_init_qm_sanity(p_hwfn);
2322 if (rc != ECORE_SUCCESS)
2325 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2326 sizeof(struct init_qm_pq_params) *
2327 ecore_init_qm_get_num_pqs(p_hwfn));
2328 if (!qm_info->qm_pq_params)
2331 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2332 sizeof(struct init_qm_vport_params) *
2333 ecore_init_qm_get_num_vports(p_hwfn));
2334 if (!qm_info->qm_vport_params)
2337 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2338 sizeof(struct init_qm_port_params) *
2339 p_hwfn->p_dev->num_ports_in_engine);
2340 if (!qm_info->qm_port_params)
2343 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2344 sizeof(struct ecore_wfq_data) *
2345 ecore_init_qm_get_num_vports(p_hwfn));
2346 if (!qm_info->wfq_data)
2349 return ECORE_SUCCESS;
2352 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
2353 ecore_qm_info_free(p_hwfn);
2356 /******************** End QM initialization ***************/
2358 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
2360 enum _ecore_status_t rc = ECORE_SUCCESS;
2361 enum dbg_status debug_status = DBG_STATUS_OK;
2365 for_each_hwfn(p_dev, i) {
2366 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
2367 if (rc != ECORE_SUCCESS)
2373 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2374 sizeof(*p_dev->fw_data));
2375 if (!p_dev->fw_data)
2378 for_each_hwfn(p_dev, i) {
2379 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2380 u32 n_eqes, num_cons;
2382 /* initialize the doorbell recovery mechanism */
2383 rc = ecore_db_recovery_setup(p_hwfn);
2387 /* First allocate the context manager structure */
2388 rc = ecore_cxt_mngr_alloc(p_hwfn);
2392 /* Set the HW cid/tid numbers (in the context manager)
2393 * Must be done prior to any further computations.
2395 rc = ecore_cxt_set_pf_params(p_hwfn);
2399 rc = ecore_alloc_qm_data(p_hwfn);
2404 ecore_init_qm_info(p_hwfn);
2406 /* Compute the ILT client partition */
2407 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
2411 /* CID map / ILT shadow table / T2
2412 * The talbes sizes are determined by the computations above
2414 rc = ecore_cxt_tables_alloc(p_hwfn);
2418 /* SPQ, must follow ILT because initializes SPQ context */
2419 rc = ecore_spq_alloc(p_hwfn);
2423 /* SP status block allocation */
2424 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
2427 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2431 rc = ecore_iov_alloc(p_hwfn);
2436 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
2437 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
2438 /* Calculate the EQ size
2439 * ---------------------
2440 * Each ICID may generate up to one event at a time i.e.
2441 * the event must be handled/cleared before a new one
2442 * can be generated. We calculate the sum of events per
2443 * protocol and create an EQ deep enough to handle the
2445 * - Core - according to SPQ.
2446 * - RoCE - per QP there are a couple of ICIDs, one
2447 * responder and one requester, each can
2448 * generate an EQE => n_eqes_qp = 2 * n_qp.
2449 * Each CQ can generate an EQE. There are 2 CQs
2450 * per QP => n_eqes_cq = 2 * n_qp.
2451 * Hence the RoCE total is 4 * n_qp or
2453 * - ENet - There can be up to two events per VF. One
2454 * for VF-PF channel and another for VF FLR
2455 * initial cleanup. The number of VFs is
2456 * bounded by MAX_NUM_VFS_BB, and is much
2457 * smaller than RoCE's so we avoid exact
2460 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
2462 ecore_cxt_get_proto_cid_count(
2468 num_cons = ecore_cxt_get_proto_cid_count(
2473 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
2474 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
2476 ecore_cxt_get_proto_cid_count(p_hwfn,
2479 n_eqes += 2 * num_cons;
2482 if (n_eqes > 0xFFFF) {
2483 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
2484 "The maximum of a u16 chain is 0x%x\n",
2489 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
2493 rc = ecore_consq_alloc(p_hwfn);
2497 rc = ecore_l2_alloc(p_hwfn);
2498 if (rc != ECORE_SUCCESS)
2501 /* DMA info initialization */
2502 rc = ecore_dmae_info_alloc(p_hwfn);
2504 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
2508 /* DCBX initialization */
2509 rc = ecore_dcbx_info_alloc(p_hwfn);
2511 DP_NOTICE(p_hwfn, false,
2512 "Failed to allocate memory for dcbx structure\n");
2516 debug_status = OSAL_DBG_ALLOC_USER_DATA(p_hwfn,
2517 &p_hwfn->dbg_user_info);
2519 DP_NOTICE(p_hwfn, false,
2520 "Failed to allocate dbg user info structure\n");
2521 rc = (enum _ecore_status_t)debug_status;
2525 debug_status = OSAL_DBG_ALLOC_USER_DATA(p_hwfn,
2526 &p_hwfn->dbg_user_info);
2528 DP_NOTICE(p_hwfn, false,
2529 "Failed to allocate dbg user info structure\n");
2530 rc = (enum _ecore_status_t)debug_status;
2535 rc = ecore_llh_alloc(p_dev);
2536 if (rc != ECORE_SUCCESS) {
2537 DP_NOTICE(p_dev, true,
2538 "Failed to allocate memory for the llh_info structure\n");
2542 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2543 sizeof(*p_dev->reset_stats));
2544 if (!p_dev->reset_stats) {
2545 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
2549 return ECORE_SUCCESS;
2554 ecore_resc_free(p_dev);
2558 void ecore_resc_setup(struct ecore_dev *p_dev)
2563 for_each_hwfn(p_dev, i)
2564 ecore_l2_setup(&p_dev->hwfns[i]);
2568 for_each_hwfn(p_dev, i) {
2569 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2571 ecore_cxt_mngr_setup(p_hwfn);
2572 ecore_spq_setup(p_hwfn);
2573 ecore_eq_setup(p_hwfn);
2574 ecore_consq_setup(p_hwfn);
2576 /* Read shadow of current MFW mailbox */
2577 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2578 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2579 p_hwfn->mcp_info->mfw_mb_cur,
2580 p_hwfn->mcp_info->mfw_mb_length);
2582 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2584 ecore_l2_setup(p_hwfn);
2585 ecore_iov_setup(p_hwfn);
2589 #define FINAL_CLEANUP_POLL_CNT (100)
2590 #define FINAL_CLEANUP_POLL_TIME (10)
2591 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
2592 struct ecore_ptt *p_ptt,
2595 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2596 enum _ecore_status_t rc = ECORE_TIMEOUT;
2599 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
2600 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2601 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
2602 return ECORE_SUCCESS;
2606 addr = GTT_BAR0_MAP_REG_USDM_RAM +
2607 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2612 command |= X_FINAL_CLEANUP_AGG_INT <<
2613 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2614 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2615 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2616 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2618 /* Make sure notification is not set before initiating final cleanup */
2620 if (REG_RD(p_hwfn, addr)) {
2621 DP_NOTICE(p_hwfn, false,
2622 "Unexpected; Found final cleanup notification");
2623 DP_NOTICE(p_hwfn, false,
2624 " before initiating final cleanup\n");
2625 REG_WR(p_hwfn, addr, 0);
2628 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2629 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2632 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2634 /* Poll until completion */
2635 while (!REG_RD(p_hwfn, addr) && count--)
2636 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
2638 if (REG_RD(p_hwfn, addr))
2641 DP_NOTICE(p_hwfn, true,
2642 "Failed to receive FW final cleanup notification\n");
2644 /* Cleanup afterwards */
2645 REG_WR(p_hwfn, addr, 0);
2650 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
2654 if (ECORE_IS_BB(p_hwfn->p_dev)) {
2655 hw_mode |= 1 << MODE_BB;
2656 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
2657 hw_mode |= 1 << MODE_K2;
2659 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
2660 p_hwfn->p_dev->type);
2664 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
2665 switch (p_hwfn->p_dev->num_ports_in_engine) {
2667 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2670 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2673 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2676 DP_NOTICE(p_hwfn, true,
2677 "num_ports_in_engine = %d not supported\n",
2678 p_hwfn->p_dev->num_ports_in_engine);
2682 if (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
2683 hw_mode |= 1 << MODE_MF_SD;
2685 hw_mode |= 1 << MODE_MF_SI;
2688 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2689 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2690 hw_mode |= 1 << MODE_FPGA;
2692 if (p_hwfn->p_dev->b_is_emul_full)
2693 hw_mode |= 1 << MODE_EMUL_FULL;
2695 hw_mode |= 1 << MODE_EMUL_REDUCED;
2699 hw_mode |= 1 << MODE_ASIC;
2701 if (ECORE_IS_CMT(p_hwfn->p_dev))
2702 hw_mode |= 1 << MODE_100G;
2704 p_hwfn->hw_info.hw_mode = hw_mode;
2706 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
2707 "Configuring function for hw_mode: 0x%08x\n",
2708 p_hwfn->hw_info.hw_mode);
2710 return ECORE_SUCCESS;
2714 /* MFW-replacement initializations for emulation */
2715 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_dev *p_dev,
2716 struct ecore_ptt *p_ptt)
2718 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2723 if (!CHIP_REV_IS_EMUL(p_dev)) {
2724 DP_NOTICE(p_dev, false,
2725 "ecore_hw_init_chip() shouldn't be called in a non-emulation environment\n");
2729 pl_hv = ECORE_IS_BB(p_dev) ? 0x1 : 0x401;
2730 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
2732 if (ECORE_IS_AH(p_dev))
2733 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2, 0x3ffffff);
2735 /* Initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
2736 if (ECORE_IS_BB(p_dev))
2737 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
2739 if (ECORE_IS_AH(p_dev)) {
2740 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
2741 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
2742 p_dev->num_ports_in_engine >> 1);
2744 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
2745 p_dev->num_ports_in_engine == 4 ? 0 : 3);
2748 /* Signal the PSWRQ block to start initializing internal memories */
2749 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
2750 for (i = 0; i < 100; i++) {
2752 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
2756 DP_NOTICE(p_hwfn, true,
2757 "RBC done failed to complete in PSWRQ2\n");
2758 return ECORE_TIMEOUT;
2761 /* Indicate PSWRQ to initialize steering tag table with zeros */
2762 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RESET_STT, 1);
2763 for (i = 0; i < 100; i++) {
2765 if (!ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_RESET_STT))
2769 DP_NOTICE(p_hwfn, true,
2770 "Steering tag table initialization failed to complete in PSWRQ2\n");
2771 return ECORE_TIMEOUT;
2774 /* Clear a possible PSWRQ2 STT parity which might have been generated by
2775 * a previous MSI-X read.
2777 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_PRTY_STS_WR_H_0, 0x8);
2779 /* Configure PSWRQ2_REG_WR_MBS0 according to the MaxPayloadSize field in
2780 * the PCI configuration space. The value is common for all PFs, so it
2781 * is okay to do it according to the first loading PF.
2783 pos = OSAL_PCI_FIND_CAPABILITY(p_dev, PCI_CAP_ID_EXP);
2785 DP_NOTICE(p_dev, true,
2786 "Failed to find the PCI Express Capability structure in the PCI config space\n");
2790 OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2791 wr_mbs = (ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
2792 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0, wr_mbs);
2794 /* Configure the PGLUE_B to discard mode */
2795 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_DISCARD_NBLOCK, 0x3f);
2797 return ECORE_SUCCESS;
2801 /* Init run time data for all PFs and their VFs on an engine.
2802 * TBD - for VFs - Once we have parent PF info for each VF in
2803 * shmem available as CAU requires knowledge of parent PF for each VF.
2805 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
2807 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2811 for_each_hwfn(p_dev, i) {
2812 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2813 struct ecore_igu_info *p_igu_info;
2814 struct ecore_igu_block *p_block;
2815 struct cau_sb_entry sb_entry;
2817 p_igu_info = p_hwfn->hw_info.p_igu_info;
2820 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
2822 p_block = &p_igu_info->entry[igu_sb_id];
2824 if (!p_block->is_pf)
2827 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
2828 p_block->function_id, 0, 0);
2829 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2835 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
2836 struct ecore_ptt *p_ptt)
2838 u32 val, wr_mbs, cache_line_size;
2840 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2853 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2858 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
2859 switch (cache_line_size) {
2874 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2878 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
2880 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2881 OSAL_CACHE_LINE_SIZE, wr_mbs);
2883 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2885 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2886 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2890 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
2891 struct ecore_ptt *p_ptt,
2894 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2895 struct ecore_dev *p_dev = p_hwfn->p_dev;
2896 u8 vf_id, max_num_vfs;
2899 enum _ecore_status_t rc = ECORE_SUCCESS;
2901 ecore_init_cau_rt_data(p_dev);
2903 /* Program GTT windows */
2904 ecore_gtt_init(p_hwfn);
2907 if (CHIP_REV_IS_EMUL(p_dev) && IS_LEAD_HWFN(p_hwfn)) {
2908 rc = ecore_hw_init_chip(p_dev, p_ptt);
2909 if (rc != ECORE_SUCCESS)
2914 if (p_hwfn->mcp_info) {
2915 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2916 qm_info->pf_rl_en = 1;
2917 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2918 qm_info->pf_wfq_en = 1;
2921 ecore_qm_common_rt_init(p_hwfn,
2922 p_dev->num_ports_in_engine,
2923 qm_info->max_phys_tcs_per_port,
2924 qm_info->pf_rl_en, qm_info->pf_wfq_en,
2925 qm_info->vport_rl_en, qm_info->vport_wfq_en,
2926 qm_info->qm_port_params,
2927 OSAL_NULL /* global RLs are not configured */);
2929 ecore_cxt_hw_init_common(p_hwfn);
2931 ecore_init_cache_line_size(p_hwfn, p_ptt);
2933 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
2935 if (rc != ECORE_SUCCESS)
2938 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
2939 * need to decide with which value, maybe runtime
2941 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2942 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2944 if (ECORE_IS_BB(p_dev)) {
2945 /* Workaround clears ROCE search for all functions to prevent
2946 * involving non initialized function in processing ROCE packet.
2948 num_pfs = (u16)NUM_OF_ENG_PFS(p_dev);
2949 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2950 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
2951 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2952 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2954 /* pretend to original PF */
2955 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2958 /* Workaround for avoiding CCFC execution error when getting packets
2959 * with CRC errors, and allowing instead the invoking of the FW error
2961 * This is not done inside the init tool since it currently can't
2962 * perform a pretending to VFs.
2964 max_num_vfs = (u8)NUM_OF_VFS(p_dev);
2965 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2966 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
2967 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
2968 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2969 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2970 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2971 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2973 /* pretend to original PF */
2974 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2980 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
2981 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
2983 #define PMEG_IF_BYTE_COUNT 8
2985 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
2986 struct ecore_ptt *p_ptt,
2987 u32 addr, u64 data, u8 reg_type, u8 port)
2989 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2990 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
2991 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
2992 (8 << PMEG_IF_BYTE_COUNT),
2993 (reg_type << 25) | (addr << 8) | port,
2994 (u32)((data >> 32) & 0xffffffff),
2995 (u32)(data & 0xffffffff));
2997 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
2998 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
2999 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
3000 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
3001 (reg_type << 25) | (addr << 8) | port);
3002 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
3003 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
3004 (data >> 32) & 0xffffffff);
3007 #define XLPORT_MODE_REG (0x20a)
3008 #define XLPORT_MAC_CONTROL (0x210)
3009 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
3010 #define XLPORT_ENABLE_REG (0x20b)
3012 #define XLMAC_CTRL (0x600)
3013 #define XLMAC_MODE (0x601)
3014 #define XLMAC_RX_MAX_SIZE (0x608)
3015 #define XLMAC_TX_CTRL (0x604)
3016 #define XLMAC_PAUSE_CTRL (0x60d)
3017 #define XLMAC_PFC_CTRL (0x60e)
3019 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
3020 struct ecore_ptt *p_ptt)
3022 u8 loopback = 0, port = p_hwfn->port_id * 2;
3024 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
3025 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
3027 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
3028 /* XLMAC: SOFT RESET */
3029 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
3030 /* XLMAC: Port Speed >= 10Gbps */
3031 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
3032 /* XLMAC: Max Size */
3033 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
3034 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
3035 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
3037 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
3038 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
3039 0x30ffffc000ULL, 0, port);
3040 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
3041 port); /* XLMAC: TX_EN, RX_EN */
3042 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
3043 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
3044 0x1003 | (loopback << 2), 0, port);
3045 /* Enabled Parallel PFC interface */
3046 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
3048 /* XLPORT port enable */
3049 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
3052 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
3053 struct ecore_ptt *p_ptt)
3055 u32 mac_base, mac_config_val = 0xa853;
3056 u8 port = p_hwfn->port_id;
3058 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
3059 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_SHIFT) |
3061 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_SHIFT) |
3062 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_SHIFT));
3064 mac_base = NWM_REG_MAC0_K2 + (port << 2) * NWM_REG_MAC0_SIZE;
3066 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2,
3067 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_SHIFT);
3069 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2,
3070 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_SHIFT);
3072 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2,
3073 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_SHIFT);
3075 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2,
3076 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_SHIFT);
3078 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2,
3080 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_SHIFT) |
3082 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_SHIFT));
3084 /* Strip the CRC field from the frame */
3085 mac_config_val &= ~ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2;
3086 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2,
3090 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
3091 struct ecore_ptt *p_ptt)
3093 u8 port = ECORE_IS_BB(p_hwfn->p_dev) ? p_hwfn->port_id * 2
3096 DP_INFO(p_hwfn->p_dev, "Emulation: Configuring Link [port %02x]\n",
3099 if (ECORE_IS_BB(p_hwfn->p_dev))
3100 ecore_emul_link_init_bb(p_hwfn, p_ptt);
3102 ecore_emul_link_init_ah(p_hwfn, p_ptt);
3107 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
3108 struct ecore_ptt *p_ptt, u8 port)
3110 int port_offset = port ? 0x800 : 0;
3111 u32 xmac_rxctrl = 0;
3114 /* FIXME: move to common start */
3115 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3116 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
3118 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3119 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
3121 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
3123 /* Set the number of ports on the Warp Core to 10G */
3124 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
3126 /* Soft reset of XMAC */
3127 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3128 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3130 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3131 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3133 /* FIXME: move to common end */
3134 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3135 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
3137 /* Set Max packet size: initialize XMAC block register for port 0 */
3138 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
3140 /* CRC append for Tx packets: init XMAC block register for port 1 */
3141 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
3143 /* Enable TX and RX: initialize XMAC block register for port 1 */
3144 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
3145 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
3146 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
3147 XMAC_REG_RX_CTRL_BB + port_offset);
3148 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
3149 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
3153 static u32 ecore_hw_norm_region_conn(struct ecore_hwfn *p_hwfn)
3155 u32 norm_region_conn;
3157 /* The order of CIDs allocation is according to the order of
3158 * 'enum protocol_type'. Therefore, the number of CIDs for the normal
3159 * region is calculated based on the CORE CIDs, in case of non-ETH
3160 * personality, and otherwise - based on the ETH CIDs.
3163 ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
3164 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
3166 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
3169 return norm_region_conn;
3172 static enum _ecore_status_t
3173 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
3174 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
3176 u32 dpi_bit_shift, dpi_count, dpi_page_size;
3180 /* Calculate DPI size
3181 * ------------------
3182 * The PWM region contains Doorbell Pages. The first is reserverd for
3183 * the kernel for, e.g, L2. The others are free to be used by non-
3184 * trusted applications, typically from user space. Each page, called a
3185 * doorbell page is sectioned into windows that allow doorbells to be
3186 * issued in parallel by the kernel/application. The size of such a
3187 * window (a.k.a. WID) is 1kB.
3189 * 1kB WID x N WIDS = DPI page size
3190 * DPI page size x N DPIs = PWM region size
3192 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
3193 * in order to ensure that two applications won't share the same page.
3194 * It also must contain at least one WID per CPU to allow parallelism.
3195 * It also must be a power of 2, since it is stored as a bit shift.
3197 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
3198 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
3199 * containing 4 WIDs.
3201 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
3202 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
3203 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
3204 ~(OSAL_PAGE_SIZE - 1);
3205 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
3206 dpi_count = pwm_region_size / dpi_page_size;
3208 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
3209 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
3212 p_hwfn->dpi_size = dpi_page_size;
3213 p_hwfn->dpi_count = dpi_count;
3215 /* Update registers */
3216 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
3218 if (dpi_count < min_dpis)
3219 return ECORE_NORESOURCES;
3221 return ECORE_SUCCESS;
3224 enum ECORE_ROCE_EDPM_MODE {
3225 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
3226 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
3227 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
3230 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn)
3232 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
3238 static enum _ecore_status_t
3239 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
3240 struct ecore_ptt *p_ptt)
3242 u32 norm_region_conn, min_addr_reg1;
3243 u32 pwm_regsize, norm_regsize;
3244 u32 db_bar_size, n_cpus;
3247 enum _ecore_status_t rc = ECORE_SUCCESS;
3250 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
3251 if (ECORE_IS_CMT(p_hwfn->p_dev))
3254 /* Calculate doorbell regions
3255 * -----------------------------------
3256 * The doorbell BAR is made of two regions. The first is called normal
3257 * region and the second is called PWM region. In the normal region
3258 * each ICID has its own set of addresses so that writing to that
3259 * specific address identifies the ICID. In the Process Window Mode
3260 * region the ICID is given in the data written to the doorbell. The
3261 * above per PF register denotes the offset in the doorbell BAR in which
3262 * the PWM region begins.
3263 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
3264 * non-PWM connection. The calculation below computes the total non-PWM
3265 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
3266 * in units of 4,096 bytes.
3268 norm_region_conn = ecore_hw_norm_region_conn(p_hwfn);
3269 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * norm_region_conn,
3271 min_addr_reg1 = norm_regsize / 4096;
3272 pwm_regsize = db_bar_size - norm_regsize;
3274 /* Check that the normal and PWM sizes are valid */
3275 if (db_bar_size < norm_regsize) {
3276 DP_ERR(p_hwfn->p_dev,
3277 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
3278 db_bar_size, norm_regsize);
3279 return ECORE_NORESOURCES;
3281 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
3282 DP_ERR(p_hwfn->p_dev,
3283 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
3284 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
3286 return ECORE_NORESOURCES;
3289 /* Calculate number of DPIs */
3290 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
3291 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
3292 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
3293 /* Either EDPM is mandatory, or we are attempting to allocate a
3296 n_cpus = OSAL_NUM_CPUS();
3297 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3300 cond = ((rc != ECORE_SUCCESS) &&
3301 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
3302 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
3303 if (cond || p_hwfn->dcbx_no_edpm) {
3304 /* Either EDPM is disabled from user configuration, or it is
3305 * disabled via DCBx, or it is not mandatory and we failed to
3306 * allocated a WID per CPU.
3309 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3311 /* If we entered this flow due to DCBX then the DPM register is
3312 * already configured.
3317 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
3318 norm_regsize, pwm_regsize);
3320 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
3321 p_hwfn->dpi_size, p_hwfn->dpi_count,
3322 (!ecore_edpm_enabled(p_hwfn)) ?
3323 "disabled" : "enabled");
3325 /* Check return codes from above calls */
3326 if (rc != ECORE_SUCCESS) {
3328 "Failed to allocate enough DPIs\n");
3329 return ECORE_NORESOURCES;
3333 p_hwfn->dpi_start_offset = norm_regsize;
3335 /* Update registers */
3336 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
3337 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
3338 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
3339 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
3341 return ECORE_SUCCESS;
3344 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
3345 struct ecore_ptt *p_ptt,
3348 struct ecore_dev *p_dev = p_hwfn->p_dev;
3349 enum _ecore_status_t rc = ECORE_SUCCESS;
3351 /* In CMT the gate should be cleared by the 2nd hwfn */
3352 if (!ECORE_IS_CMT(p_dev) || !IS_LEAD_HWFN(p_hwfn))
3353 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
3355 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
3357 if (rc != ECORE_SUCCESS)
3360 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
3363 if (CHIP_REV_IS_FPGA(p_dev) && ECORE_IS_BB(p_dev))
3364 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
3366 if (CHIP_REV_IS_EMUL(p_dev)) {
3367 if (ECORE_IS_CMT(p_dev)) {
3368 /* Activate OPTE in CMT */
3371 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
3373 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
3374 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
3375 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
3376 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
3377 ecore_wr(p_hwfn, p_ptt,
3378 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
3379 ecore_wr(p_hwfn, p_ptt,
3380 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
3381 ecore_wr(p_hwfn, p_ptt,
3382 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
3386 /* Set the TAGMAC default function on the port if needed.
3387 * The ppfid should be set in the vector, except in BB which has
3388 * a bug in the LLH where the ppfid is actually engine based.
3390 if (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {
3391 u8 pf_id = p_hwfn->rel_pf_id;
3393 if (!ECORE_IS_BB(p_dev))
3394 pf_id /= p_dev->num_ports_in_engine;
3395 ecore_wr(p_hwfn, p_ptt,
3396 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
3399 ecore_emul_link_init(p_hwfn, p_ptt);
3403 return ECORE_SUCCESS;
3406 static enum _ecore_status_t
3407 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3408 int hw_mode, struct ecore_hw_init_params *p_params)
3410 u8 rel_pf_id = p_hwfn->rel_pf_id;
3412 enum _ecore_status_t rc = ECORE_SUCCESS;
3416 if (p_hwfn->mcp_info) {
3417 struct ecore_mcp_function_info *p_info;
3419 p_info = &p_hwfn->mcp_info->func_info;
3420 if (p_info->bandwidth_min)
3421 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
3423 /* Update rate limit once we'll actually have a link */
3424 p_hwfn->qm_info.pf_rl = 100000;
3426 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
3428 ecore_int_igu_init_rt(p_hwfn);
3430 /* Set VLAN in NIG if needed */
3431 if (hw_mode & (1 << MODE_MF_SD)) {
3432 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
3433 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
3434 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
3435 p_hwfn->hw_info.ovlan);
3437 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3438 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
3439 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
3443 /* Enable classification by MAC if needed */
3444 if (hw_mode & (1 << MODE_MF_SI)) {
3445 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3446 "Configuring TAGMAC_CLS_TYPE\n");
3447 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
3451 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
3452 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
3453 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
3454 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
3455 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
3456 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
3458 /* perform debug configuration when chip is out of reset */
3459 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
3461 /* Sanity check before the PF init sequence that uses DMAE */
3462 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
3466 /* PF Init sequence */
3467 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
3471 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
3472 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
3476 ecore_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem);
3478 /* Pure runtime initializations - directly to the HW */
3479 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
3481 /* PCI relaxed ordering causes a decrease in the performance on some
3482 * systems. Till a root cause is found, disable this attribute in the
3486 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
3488 * DP_NOTICE(p_hwfn, true,
3489 * "Failed to find the PCIe Cap\n");
3492 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
3493 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
3494 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
3497 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
3498 if (rc != ECORE_SUCCESS)
3501 /* Use the leading hwfn since in CMT only NIG #0 is operational */
3502 if (IS_LEAD_HWFN(p_hwfn)) {
3503 rc = ecore_llh_hw_init_pf(p_hwfn, p_ptt,
3504 p_params->avoid_eng_affin);
3505 if (rc != ECORE_SUCCESS)
3509 if (p_params->b_hw_start) {
3510 /* enable interrupts */
3511 rc = ecore_int_igu_enable(p_hwfn, p_ptt, p_params->int_mode);
3512 if (rc != ECORE_SUCCESS)
3515 /* send function start command */
3516 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_params->p_tunn,
3517 p_params->allow_npar_tx_switch);
3519 DP_NOTICE(p_hwfn, true,
3520 "Function start ramrod failed\n");
3523 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3524 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3525 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3527 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
3528 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
3530 ecore_wr(p_hwfn, p_ptt,
3531 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
3534 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3535 "PRS_REG_SEARCH registers after start PFn\n");
3536 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
3537 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3538 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
3539 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
3540 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3541 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
3542 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
3543 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3544 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
3545 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
3546 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3547 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
3548 prs_reg = ecore_rd(p_hwfn, p_ptt,
3549 PRS_REG_SEARCH_TCP_FIRST_FRAG);
3550 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3551 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
3553 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3554 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3555 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3557 return ECORE_SUCCESS;
3560 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
3561 struct ecore_ptt *p_ptt,
3564 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
3566 /* Configure the PF's internal FID_enable for master transactions */
3567 ecore_wr(p_hwfn, p_ptt,
3568 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
3570 /* Wait until value is set - try for 1 second every 50us */
3571 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
3572 val = ecore_rd(p_hwfn, p_ptt,
3573 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
3580 if (val != set_val) {
3581 DP_NOTICE(p_hwfn, true,
3582 "PFID_ENABLE_MASTER wasn't changed after a second\n");
3583 return ECORE_UNKNOWN_ERROR;
3586 return ECORE_SUCCESS;
3589 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
3590 struct ecore_ptt *p_main_ptt)
3592 /* Read shadow of current MFW mailbox */
3593 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
3594 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
3595 p_hwfn->mcp_info->mfw_mb_cur,
3596 p_hwfn->mcp_info->mfw_mb_length);
3599 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
3600 struct ecore_ptt *p_ptt)
3602 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
3603 1 << p_hwfn->abs_pf_id);
3606 static enum _ecore_status_t
3607 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
3608 struct ecore_load_req_params *p_load_req,
3609 struct ecore_drv_load_params *p_drv_load)
3611 /* Make sure that if ecore-client didn't provide inputs, all the
3612 * expected defaults are indeed zero.
3614 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
3615 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
3616 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
3618 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
3620 if (p_drv_load == OSAL_NULL)
3623 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
3624 ECORE_DRV_ROLE_KDUMP :
3626 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
3627 p_load_req->override_force_load = p_drv_load->override_force_load;
3629 /* Old MFW versions don't support timeout values other than default and
3630 * none, so these values are replaced according to the fall-back action.
3633 if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
3634 p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
3635 (p_hwfn->mcp_info->capabilities &
3636 FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
3637 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
3641 switch (p_drv_load->mfw_timeout_fallback) {
3642 case ECORE_TO_FALLBACK_TO_NONE:
3643 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
3645 case ECORE_TO_FALLBACK_TO_DEFAULT:
3646 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
3648 case ECORE_TO_FALLBACK_FAIL_LOAD:
3649 DP_NOTICE(p_hwfn, false,
3650 "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
3651 p_drv_load->mfw_timeout_val,
3652 ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
3653 ECORE_LOAD_REQ_LOCK_TO_NONE);
3654 return ECORE_ABORTED;
3658 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
3659 p_drv_load->mfw_timeout_val,
3660 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
3662 p_load_req->timeout_val);
3664 return ECORE_SUCCESS;
3667 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
3668 struct ecore_hw_init_params *p_params)
3670 if (p_params->p_tunn) {
3671 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
3672 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
3675 p_hwfn->b_int_enabled = 1;
3677 return ECORE_SUCCESS;
3680 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
3681 struct ecore_hw_init_params *p_params)
3683 struct ecore_load_req_params load_req_params;
3684 u32 load_code, resp, param, drv_mb_param;
3685 bool b_default_mtu = true;
3686 struct ecore_hwfn *p_hwfn;
3687 const u32 *fw_overlays;
3688 u32 fw_overlays_len;
3689 enum _ecore_status_t rc = ECORE_SUCCESS;
3693 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
3694 DP_NOTICE(p_dev, false,
3695 "MSI mode is not supported for CMT devices\n");
3700 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
3701 if (rc != ECORE_SUCCESS)
3705 for_each_hwfn(p_dev, i) {
3706 p_hwfn = &p_dev->hwfns[i];
3708 /* If management didn't provide a default, set one of our own */
3709 if (!p_hwfn->hw_info.mtu) {
3710 p_hwfn->hw_info.mtu = 1500;
3711 b_default_mtu = false;
3715 ecore_vf_start(p_hwfn, p_params);
3719 rc = ecore_calc_hw_mode(p_hwfn);
3720 if (rc != ECORE_SUCCESS)
3723 if (IS_PF(p_dev) && (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING,
3725 OSAL_GET_BIT(ECORE_MF_8021AD_TAGGING,
3726 &p_dev->mf_bits))) {
3727 if (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING,
3729 ether_type = ETHER_TYPE_VLAN;
3731 ether_type = ETHER_TYPE_QINQ;
3732 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3734 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3736 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3738 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3742 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
3744 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
3745 p_params->p_drv_load_params);
3746 if (rc != ECORE_SUCCESS)
3749 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3751 if (rc != ECORE_SUCCESS) {
3752 DP_NOTICE(p_hwfn, false,
3753 "Failed sending a LOAD_REQ command\n");
3757 load_code = load_req_params.load_code;
3758 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3759 "Load request was sent. Load code: 0x%x\n",
3762 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3765 * When coming back from hiberbate state, the registers from
3766 * which shadow is read initially are not initialized. It turns
3767 * out that these registers get initialized during the call to
3768 * ecore_mcp_load_req request. So we need to reread them here
3769 * to get the proper shadow register value.
3770 * Note: This is a workaround for the missing MFW
3771 * initialization. It may be removed once the implementation
3774 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3776 /* Only relevant for recovery:
3777 * Clear the indication after the LOAD_REQ command is responded
3780 p_dev->recov_in_prog = false;
3782 p_hwfn->first_on_engine = (load_code ==
3783 FW_MSG_CODE_DRV_LOAD_ENGINE);
3785 if (!qm_lock_ref_cnt) {
3786 #ifdef CONFIG_ECORE_LOCK_ALLOC
3787 rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
3789 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
3793 OSAL_SPIN_LOCK_INIT(&qm_lock);
3797 /* Clean up chip from previous driver if such remains exist.
3798 * This is not needed when the PF is the first one on the
3799 * engine, since afterwards we are going to init the FW.
3801 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3802 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3803 p_hwfn->rel_pf_id, false);
3804 if (rc != ECORE_SUCCESS) {
3805 ecore_hw_err_notify(p_hwfn,
3806 ECORE_HW_ERR_RAMROD_FAIL);
3811 /* Log and clear previous pglue_b errors if such exist */
3812 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
3814 /* Enable the PF's internal FID_enable in the PXP */
3815 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3817 if (rc != ECORE_SUCCESS)
3820 /* Clear the pglue_b was_error indication.
3821 * It must be done after the BME and the internal FID_enable for
3822 * the PF are set, since VDMs may cause the indication to be set
3825 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3827 fw_overlays = p_dev->fw_data->fw_overlays;
3828 fw_overlays_len = p_dev->fw_data->fw_overlays_len;
3829 p_hwfn->fw_overlay_mem =
3830 ecore_fw_overlay_mem_alloc(p_hwfn, fw_overlays,
3832 if (!p_hwfn->fw_overlay_mem) {
3833 DP_NOTICE(p_hwfn, false,
3834 "Failed to allocate fw overlay memory\n");
3838 switch (load_code) {
3839 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3840 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3841 p_hwfn->hw_info.hw_mode);
3842 if (rc != ECORE_SUCCESS)
3845 case FW_MSG_CODE_DRV_LOAD_PORT:
3846 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3847 p_hwfn->hw_info.hw_mode);
3848 if (rc != ECORE_SUCCESS)
3851 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3852 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3853 p_hwfn->hw_info.hw_mode,
3857 DP_NOTICE(p_hwfn, false,
3858 "Unexpected load code [0x%08x]", load_code);
3863 if (rc != ECORE_SUCCESS) {
3864 DP_NOTICE(p_hwfn, false,
3865 "init phase failed for loadcode 0x%x (rc %d)\n",
3870 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3871 if (rc != ECORE_SUCCESS) {
3872 DP_NOTICE(p_hwfn, false,
3873 "Sending load done failed, rc = %d\n", rc);
3874 if (rc == ECORE_NOMEM) {
3875 DP_NOTICE(p_hwfn, false,
3876 "Sending load done was failed due to memory allocation failure\n");
3882 /* send DCBX attention request command */
3883 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
3884 "sending phony dcbx set command to trigger DCBx attention handling\n");
3885 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3886 DRV_MSG_CODE_SET_DCBX,
3887 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
3889 if (rc != ECORE_SUCCESS) {
3890 DP_NOTICE(p_hwfn, false,
3891 "Failed to send DCBX attention request\n");
3895 p_hwfn->hw_init_done = true;
3899 /* Get pre-negotiated values for stag, bandwidth etc. */
3900 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3901 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3902 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3903 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3904 DRV_MSG_CODE_GET_OEM_UPDATES,
3905 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3907 if (rc != ECORE_SUCCESS)
3908 DP_NOTICE(p_hwfn, false,
3909 "Failed to send GET_OEM_UPDATES attention request\n");
3913 /* Get pre-negotiated values for stag, bandwidth etc. */
3914 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3915 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3916 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3917 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3918 DRV_MSG_CODE_GET_OEM_UPDATES,
3919 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3921 if (rc != ECORE_SUCCESS)
3922 DP_NOTICE(p_hwfn, false,
3923 "Failed to send GET_OEM_UPDATES attention request\n");
3927 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3928 drv_mb_param = STORM_FW_VERSION;
3929 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3930 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3931 drv_mb_param, &resp, ¶m);
3932 if (rc != ECORE_SUCCESS)
3933 DP_INFO(p_hwfn, "Failed to update firmware version\n");
3935 if (!b_default_mtu) {
3936 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3937 p_hwfn->hw_info.mtu);
3938 if (rc != ECORE_SUCCESS)
3939 DP_INFO(p_hwfn, "Failed to update default mtu\n");
3942 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
3944 ECORE_OV_DRIVER_STATE_DISABLED);
3945 if (rc != ECORE_SUCCESS)
3946 DP_INFO(p_hwfn, "Failed to update driver state\n");
3948 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3949 ECORE_OV_ESWITCH_NONE);
3950 if (rc != ECORE_SUCCESS)
3951 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3958 #ifdef CONFIG_ECORE_LOCK_ALLOC
3959 if (!qm_lock_ref_cnt)
3960 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
3963 /* The MFW load lock should be released regardless of success or failure
3964 * of initialization.
3965 * TODO: replace this with an attempt to send cancel_load.
3967 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3971 #define ECORE_HW_STOP_RETRY_LIMIT (10)
3972 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
3973 struct ecore_hwfn *p_hwfn,
3974 struct ecore_ptt *p_ptt)
3979 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3980 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3981 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
3983 if ((!ecore_rd(p_hwfn, p_ptt,
3984 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3985 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3988 /* Dependent on number of connection/tasks, possibly
3989 * 1ms sleep is required between polls
3994 if (i < ECORE_HW_STOP_RETRY_LIMIT)
3997 DP_NOTICE(p_hwfn, false,
3998 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3999 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
4000 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
4003 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
4007 for_each_hwfn(p_dev, j) {
4008 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4009 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
4011 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
4015 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
4016 struct ecore_ptt *p_ptt,
4017 u32 addr, u32 expected_val)
4019 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
4021 if (val != expected_val) {
4022 DP_NOTICE(p_hwfn, true,
4023 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
4024 addr, val, expected_val);
4025 return ECORE_UNKNOWN_ERROR;
4028 return ECORE_SUCCESS;
4031 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
4033 struct ecore_hwfn *p_hwfn;
4034 struct ecore_ptt *p_ptt;
4035 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
4038 for_each_hwfn(p_dev, j) {
4039 p_hwfn = &p_dev->hwfns[j];
4040 p_ptt = p_hwfn->p_main_ptt;
4042 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
4045 ecore_vf_pf_int_cleanup(p_hwfn);
4046 rc = ecore_vf_pf_reset(p_hwfn);
4047 if (rc != ECORE_SUCCESS) {
4048 DP_NOTICE(p_hwfn, true,
4049 "ecore_vf_pf_reset failed. rc = %d.\n",
4051 rc2 = ECORE_UNKNOWN_ERROR;
4056 /* mark the hw as uninitialized... */
4057 p_hwfn->hw_init_done = false;
4059 /* Send unload command to MCP */
4060 if (!p_dev->recov_in_prog) {
4061 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
4062 if (rc != ECORE_SUCCESS) {
4063 DP_NOTICE(p_hwfn, false,
4064 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
4066 rc2 = ECORE_UNKNOWN_ERROR;
4070 OSAL_DPC_SYNC(p_hwfn);
4072 /* After this point no MFW attentions are expected, e.g. prevent
4073 * race between pf stop and dcbx pf update.
4076 rc = ecore_sp_pf_stop(p_hwfn);
4077 if (rc != ECORE_SUCCESS) {
4078 DP_NOTICE(p_hwfn, false,
4079 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
4081 rc2 = ECORE_UNKNOWN_ERROR;
4084 OSAL_DPC_SYNC(p_hwfn);
4086 /* After this point we don't expect the FW to send us async
4090 /* perform debug action after PF stop was sent */
4091 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
4093 /* close NIG to BRB gate */
4094 ecore_wr(p_hwfn, p_ptt,
4095 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4098 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4099 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4100 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4101 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4102 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4104 /* @@@TBD - clean transmission queues (5.b) */
4105 /* @@@TBD - clean BTB (5.c) */
4107 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
4109 /* @@@TBD - verify DMAE requests are done (8) */
4111 /* Disable Attention Generation */
4112 ecore_int_igu_disable_int(p_hwfn, p_ptt);
4113 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
4114 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
4115 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
4116 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
4117 if (rc != ECORE_SUCCESS) {
4118 DP_NOTICE(p_hwfn, true,
4119 "Failed to return IGU CAM to default\n");
4120 rc2 = ECORE_UNKNOWN_ERROR;
4123 /* Need to wait 1ms to guarantee SBs are cleared */
4126 if (IS_LEAD_HWFN(p_hwfn) &&
4127 OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
4128 !ECORE_IS_FCOE_PERSONALITY(p_hwfn))
4129 ecore_llh_remove_mac_filter(p_dev, 0,
4130 p_hwfn->hw_info.hw_mac_addr);
4132 if (!p_dev->recov_in_prog) {
4133 ecore_verify_reg_val(p_hwfn, p_ptt,
4134 QM_REG_USG_CNT_PF_TX, 0);
4135 ecore_verify_reg_val(p_hwfn, p_ptt,
4136 QM_REG_USG_CNT_PF_OTHER, 0);
4137 /* @@@TBD - assert on incorrect xCFC values (10.b) */
4140 /* Disable PF in HW blocks */
4141 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
4142 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
4145 #ifdef CONFIG_ECORE_LOCK_ALLOC
4146 if (!qm_lock_ref_cnt)
4147 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
4150 if (!p_dev->recov_in_prog) {
4151 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4152 if (rc == ECORE_NOMEM) {
4153 DP_NOTICE(p_hwfn, false,
4154 "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
4155 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4157 if (rc != ECORE_SUCCESS) {
4158 DP_NOTICE(p_hwfn, false,
4159 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
4161 rc2 = ECORE_UNKNOWN_ERROR;
4166 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
4167 p_hwfn = ECORE_LEADING_HWFN(p_dev);
4168 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
4170 /* Clear the PF's internal FID_enable in the PXP.
4171 * In CMT this should only be done for first hw-function, and
4172 * only after all transactions have stopped for all active
4175 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
4177 if (rc != ECORE_SUCCESS) {
4178 DP_NOTICE(p_hwfn, true,
4179 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
4181 rc2 = ECORE_UNKNOWN_ERROR;
4188 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
4192 for_each_hwfn(p_dev, j) {
4193 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4194 struct ecore_ptt *p_ptt;
4197 ecore_vf_pf_int_cleanup(p_hwfn);
4200 p_ptt = ecore_ptt_acquire(p_hwfn);
4204 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4205 "Shutting down the fastpath\n");
4207 ecore_wr(p_hwfn, p_ptt,
4208 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4210 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4211 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4212 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4213 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4214 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4216 /* @@@TBD - clean transmission queues (5.b) */
4217 /* @@@TBD - clean BTB (5.c) */
4219 /* @@@TBD - verify DMAE requests are done (8) */
4221 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
4222 /* Need to wait 1ms to guarantee SBs are cleared */
4224 ecore_ptt_release(p_hwfn, p_ptt);
4227 return ECORE_SUCCESS;
4230 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
4232 struct ecore_ptt *p_ptt;
4234 if (IS_VF(p_hwfn->p_dev))
4235 return ECORE_SUCCESS;
4237 p_ptt = ecore_ptt_acquire(p_hwfn);
4241 /* If roce info is allocated it means roce is initialized and should
4242 * be enabled in searcher.
4244 if (p_hwfn->p_rdma_info) {
4245 if (p_hwfn->b_rdma_enabled_in_prs)
4246 ecore_wr(p_hwfn, p_ptt,
4247 p_hwfn->rdma_prs_search_reg, 0x1);
4248 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
4251 /* Re-open incoming traffic */
4252 ecore_wr(p_hwfn, p_ptt,
4253 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
4254 ecore_ptt_release(p_hwfn, p_ptt);
4256 return ECORE_SUCCESS;
4259 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
4260 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
4262 ecore_ptt_pool_free(p_hwfn);
4263 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
4266 /* Setup bar access */
4267 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
4269 /* clear indirect access */
4270 if (ECORE_IS_AH(p_hwfn->p_dev)) {
4271 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4272 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
4273 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4274 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
4275 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4276 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
4277 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4278 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
4280 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4281 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
4282 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4283 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
4284 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4285 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
4286 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4287 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
4290 /* Clean previous pglue_b errors if such exist */
4291 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
4293 /* enable internal target-read */
4294 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4295 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
4298 static void get_function_id(struct ecore_hwfn *p_hwfn)
4301 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
4302 PXP_PF_ME_OPAQUE_ADDR);
4304 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
4306 /* Bits 16-19 from the ME registers are the pf_num */
4307 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
4308 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4309 PXP_CONCRETE_FID_PFID);
4310 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4311 PXP_CONCRETE_FID_PORT);
4313 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4314 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
4315 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
4318 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
4320 u32 *feat_num = p_hwfn->hw_info.feat_num;
4321 struct ecore_sb_cnt_info sb_cnt;
4324 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
4325 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
4327 /* L2 Queues require each: 1 status block. 1 L2 queue */
4328 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
4329 /* Start by allocating VF queues, then PF's */
4330 feat_num[ECORE_VF_L2_QUE] =
4332 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
4334 feat_num[ECORE_PF_L2_QUE] =
4336 sb_cnt.cnt - non_l2_sbs,
4337 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
4338 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
4341 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
4342 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) {
4343 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ?
4344 &feat_num[ECORE_FCOE_CQ] :
4345 &feat_num[ECORE_ISCSI_CQ];
4346 u32 limit = sb_cnt.cnt;
4348 /* The number of queues should not exceed the number of FP SBs.
4349 * In storage target, the queues are divided into pairs of a CQ
4350 * and a CmdQ, and each pair uses a single SB. The limit in
4351 * this case should allow a max ratio of 2:1 instead of 1:1.
4353 if (p_hwfn->p_dev->b_is_target)
4355 *p_storage_feat = OSAL_MIN_T(u32, limit,
4356 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
4359 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init
4360 * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2".
4362 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat,
4363 (NUM_OF_GLOBAL_QUEUES / 2));
4366 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4367 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
4368 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
4369 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
4370 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
4371 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
4372 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
4376 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
4379 case ECORE_L2_QUEUE:
4393 case ECORE_RDMA_CNQ_RAM:
4394 return "RDMA_CNQ_RAM";
4397 case ECORE_LL2_QUEUE:
4399 case ECORE_CMDQS_CQS:
4401 case ECORE_RDMA_STATS_QUEUE:
4402 return "RDMA_STATS_QUEUE";
4408 return "UNKNOWN_RESOURCE";
4412 static enum _ecore_status_t
4413 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4414 struct ecore_ptt *p_ptt,
4415 enum ecore_resources res_id,
4419 enum _ecore_status_t rc;
4421 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
4422 resc_max_val, p_mcp_resp);
4423 if (rc != ECORE_SUCCESS) {
4424 DP_NOTICE(p_hwfn, false,
4425 "MFW response failure for a max value setting of resource %d [%s]\n",
4426 res_id, ecore_hw_get_resc_name(res_id));
4430 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
4432 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
4433 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
4435 return ECORE_SUCCESS;
4438 #define RDMA_NUM_STATISTIC_COUNTERS_K2 MAX_NUM_VPORTS_K2
4439 #define RDMA_NUM_STATISTIC_COUNTERS_BB MAX_NUM_VPORTS_BB
4441 static u32 ecore_hsi_def_val[][MAX_CHIP_IDS] = {
4442 {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2},
4443 {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2},
4444 {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2},
4445 {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2, },
4446 {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2},
4447 {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2},
4448 {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2},
4449 {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2},
4450 {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2},
4451 {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2},
4452 {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS},
4453 {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES},
4454 {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2},
4457 u32 ecore_get_hsi_def_val(struct ecore_dev *p_dev, enum ecore_hsi_def_type type)
4459 enum chip_ids chip_id = ECORE_IS_BB(p_dev) ? CHIP_BB : CHIP_K2;
4461 if (type >= ECORE_NUM_HSI_DEFS) {
4462 DP_ERR(p_dev, "Unexpected HSI definition type [%d]\n", type);
4466 return ecore_hsi_def_val[type][chip_id];
4469 static enum _ecore_status_t
4470 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4471 struct ecore_ptt *p_ptt)
4473 u32 resc_max_val, mcp_resp;
4475 enum _ecore_status_t rc;
4477 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4480 case ECORE_LL2_QUEUE:
4481 case ECORE_RDMA_CNQ_RAM:
4482 case ECORE_RDMA_STATS_QUEUE:
4490 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
4491 resc_max_val, &mcp_resp);
4492 if (rc != ECORE_SUCCESS)
4495 /* There's no point to continue to the next resource if the
4496 * command is not supported by the MFW.
4497 * We do continue if the command is supported but the resource
4498 * is unknown to the MFW. Such a resource will be later
4499 * configured with the default allocation values.
4501 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
4502 return ECORE_NOTIMPL;
4505 return ECORE_SUCCESS;
4509 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
4510 enum ecore_resources res_id,
4511 u32 *p_resc_num, u32 *p_resc_start)
4513 u8 num_funcs = p_hwfn->num_funcs_on_engine;
4514 struct ecore_dev *p_dev = p_hwfn->p_dev;
4517 case ECORE_L2_QUEUE:
4518 *p_resc_num = NUM_OF_L2_QUEUES(p_dev) / num_funcs;
4521 *p_resc_num = NUM_OF_VPORTS(p_dev) / num_funcs;
4524 *p_resc_num = NUM_OF_RSS_ENGINES(p_dev) / num_funcs;
4527 *p_resc_num = NUM_OF_QM_TX_QUEUES(p_dev) / num_funcs;
4528 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
4531 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(p_dev) / num_funcs;
4535 /* Each VFC resource can accommodate both a MAC and a VLAN */
4536 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
4539 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(p_dev) / num_funcs;
4541 case ECORE_LL2_QUEUE:
4542 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;
4544 case ECORE_RDMA_CNQ_RAM:
4545 case ECORE_CMDQS_CQS:
4546 /* CNQ/CMDQS are the same resource */
4548 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
4550 case ECORE_RDMA_STATS_QUEUE:
4551 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(p_dev) / num_funcs;
4568 /* Since we want its value to reflect whether MFW supports
4569 * the new scheme, have a default of 0.
4574 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
4578 return ECORE_SUCCESS;
4581 static enum _ecore_status_t
4582 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
4583 bool drv_resc_alloc)
4585 u32 dflt_resc_num = 0, dflt_resc_start = 0;
4586 u32 mcp_resp, *p_resc_num, *p_resc_start;
4587 enum _ecore_status_t rc;
4589 p_resc_num = &RESC_NUM(p_hwfn, res_id);
4590 p_resc_start = &RESC_START(p_hwfn, res_id);
4592 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
4594 if (rc != ECORE_SUCCESS) {
4596 "Failed to get default amount for resource %d [%s]\n",
4597 res_id, ecore_hw_get_resc_name(res_id));
4602 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
4603 *p_resc_num = dflt_resc_num;
4604 *p_resc_start = dflt_resc_start;
4609 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
4610 &mcp_resp, p_resc_num, p_resc_start);
4611 if (rc != ECORE_SUCCESS) {
4612 DP_NOTICE(p_hwfn, true,
4613 "MFW response failure for an allocation request for"
4614 " resource %d [%s]\n",
4615 res_id, ecore_hw_get_resc_name(res_id));
4619 /* Default driver values are applied in the following cases:
4620 * - The resource allocation MB command is not supported by the MFW
4621 * - There is an internal error in the MFW while processing the request
4622 * - The resource ID is unknown to the MFW
4624 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
4626 "Failed to receive allocation info for resource %d [%s]."
4627 " mcp_resp = 0x%x. Applying default values"
4629 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
4630 dflt_resc_num, dflt_resc_start);
4632 *p_resc_num = dflt_resc_num;
4633 *p_resc_start = dflt_resc_start;
4637 if ((*p_resc_num != dflt_resc_num ||
4638 *p_resc_start != dflt_resc_start) &&
4639 res_id != ECORE_SB) {
4641 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
4642 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
4643 *p_resc_start, dflt_resc_num, dflt_resc_start,
4644 drv_resc_alloc ? " - Applying default values" : "");
4645 if (drv_resc_alloc) {
4646 *p_resc_num = dflt_resc_num;
4647 *p_resc_start = dflt_resc_start;
4651 return ECORE_SUCCESS;
4654 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
4655 bool drv_resc_alloc)
4657 enum _ecore_status_t rc;
4660 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4661 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
4662 if (rc != ECORE_SUCCESS)
4666 return ECORE_SUCCESS;
4669 #define ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS 0xaa
4670 #define ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS 0x55
4671 #define ECORE_NONUSED_PPFID_MASK_AH_4P 0xf0
4673 static enum _ecore_status_t ecore_hw_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,
4674 struct ecore_ptt *p_ptt)
4676 u8 native_ppfid_idx = ECORE_PPFID_BY_PFID(p_hwfn), new_bitmap;
4677 struct ecore_dev *p_dev = p_hwfn->p_dev;
4678 enum _ecore_status_t rc;
4680 rc = ecore_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
4681 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL)
4683 else if (rc == ECORE_NOTIMPL)
4684 p_dev->ppfid_bitmap = 0x1 << native_ppfid_idx;
4686 /* 4-ports mode has limitations that should be enforced:
4687 * - BB: the MFW can access only PPFIDs which their corresponding PFIDs
4688 * belong to this certain port.
4689 * - AH: only 4 PPFIDs per port are available.
4691 if (ecore_device_num_ports(p_dev) == 4) {
4694 if (ECORE_IS_BB(p_dev))
4695 mask = MFW_PORT(p_hwfn) > 1 ?
4696 ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS :
4697 ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS;
4699 mask = ECORE_NONUSED_PPFID_MASK_AH_4P;
4701 if (p_dev->ppfid_bitmap & mask) {
4702 new_bitmap = p_dev->ppfid_bitmap & ~mask;
4704 "Fix the PPFID bitmap for 4-ports mode: 0x%hhx -> 0x%hhx\n",
4705 p_dev->ppfid_bitmap, new_bitmap);
4706 p_dev->ppfid_bitmap = new_bitmap;
4710 /* The native PPFID is expected to be part of the allocated bitmap */
4711 if (!(p_dev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
4712 new_bitmap = 0x1 << native_ppfid_idx;
4714 "Fix the PPFID bitmap to inculde the native PPFID: %hhd -> 0x%hhx\n",
4715 p_dev->ppfid_bitmap, new_bitmap);
4716 p_dev->ppfid_bitmap = new_bitmap;
4719 return ECORE_SUCCESS;
4722 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
4723 struct ecore_ptt *p_ptt,
4724 bool drv_resc_alloc)
4726 struct ecore_resc_unlock_params resc_unlock_params;
4727 struct ecore_resc_lock_params resc_lock_params;
4728 struct ecore_dev *p_dev = p_hwfn->p_dev;
4731 enum _ecore_status_t rc;
4733 u32 *resc_start = p_hwfn->hw_info.resc_start;
4734 u32 *resc_num = p_hwfn->hw_info.resc_num;
4735 /* For AH, an equal share of the ILT lines between the maximal number of
4736 * PFs is not enough for RoCE. This would be solved by the future
4737 * resource allocation scheme, but isn't currently present for
4738 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
4739 * to work - the BB number of ILT lines divided by its max PFs number.
4741 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
4744 /* Setting the max values of the soft resources and the following
4745 * resources allocation queries should be atomic. Since several PFs can
4746 * run in parallel - a resource lock is needed.
4747 * If either the resource lock or resource set value commands are not
4748 * supported - skip the max values setting, release the lock if
4749 * needed, and proceed to the queries. Other failures, including a
4750 * failure to acquire the lock, will cause this function to fail.
4751 * Old drivers that don't acquire the lock can run in parallel, and
4752 * their allocation values won't be affected by the updated max values.
4754 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
4755 ECORE_RESC_LOCK_RESC_ALLOC, false);
4757 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
4758 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4760 } else if (rc == ECORE_NOTIMPL) {
4762 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
4763 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
4764 DP_NOTICE(p_hwfn, false,
4765 "Failed to acquire the resource lock for the resource allocation commands\n");
4767 goto unlock_and_exit;
4769 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
4770 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4771 DP_NOTICE(p_hwfn, false,
4772 "Failed to set the max values of the soft resources\n");
4773 goto unlock_and_exit;
4774 } else if (rc == ECORE_NOTIMPL) {
4776 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
4777 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4778 &resc_unlock_params);
4779 if (rc != ECORE_SUCCESS)
4781 "Failed to release the resource lock for the resource allocation commands\n");
4785 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
4786 if (rc != ECORE_SUCCESS)
4787 goto unlock_and_exit;
4789 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
4790 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4791 &resc_unlock_params);
4792 if (rc != ECORE_SUCCESS)
4794 "Failed to release the resource lock for the resource allocation commands\n");
4798 if (IS_LEAD_HWFN(p_hwfn)) {
4799 rc = ecore_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
4800 if (rc != ECORE_SUCCESS)
4805 if (CHIP_REV_IS_EMUL(p_dev)) {
4806 /* Reduced build contains less PQs */
4807 if (!(p_dev->b_is_emul_full)) {
4808 resc_num[ECORE_PQ] = 32;
4809 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
4810 p_hwfn->enabled_func_idx;
4813 /* For AH emulation, since we have a possible maximal number of
4814 * 16 enabled PFs, in case there are not enough ILT lines -
4815 * allocate only first PF as RoCE and have all the other as
4816 * ETH-only with less ILT lines.
4817 * In case we increase the number of ILT lines for PF0, we need
4818 * also to correct the start value for PF1-15.
4820 if (ECORE_IS_AH(p_dev) && p_dev->b_is_emul_full) {
4821 if (!p_hwfn->rel_pf_id) {
4822 resc_num[ECORE_ILT] =
4823 OSAL_MAX_T(u32, resc_num[ECORE_ILT],
4824 roce_min_ilt_lines);
4825 } else if (resc_num[ECORE_ILT] < roce_min_ilt_lines) {
4826 resc_start[ECORE_ILT] += roce_min_ilt_lines -
4827 resc_num[ECORE_ILT];
4833 /* Sanity for ILT */
4834 max_ilt_lines = NUM_OF_PXP_ILT_RECORDS(p_dev);
4835 if (RESC_END(p_hwfn, ECORE_ILT) > max_ilt_lines) {
4836 DP_NOTICE(p_hwfn, true,
4837 "Can't assign ILT pages [%08x,...,%08x]\n",
4838 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
4844 /* This will also learn the number of SBs from MFW */
4845 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
4848 ecore_hw_set_feat(p_hwfn);
4850 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4851 "The numbers for each resource are:\n");
4852 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
4853 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
4854 ecore_hw_get_resc_name(res_id),
4855 RESC_NUM(p_hwfn, res_id),
4856 RESC_START(p_hwfn, res_id));
4858 return ECORE_SUCCESS;
4861 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
4862 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4863 &resc_unlock_params);
4868 static enum _ecore_status_t
4869 ecore_emul_hw_get_nvm_info(struct ecore_hwfn *p_hwfn)
4871 if (IS_LEAD_HWFN(p_hwfn)) {
4872 struct ecore_dev *p_dev = p_hwfn->p_dev;
4874 /* The MF mode on emulation is either default or NPAR 1.0 */
4875 p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
4876 1 << ECORE_MF_LLH_PROTO_CLSS |
4877 1 << ECORE_MF_LL2_NON_UNICAST;
4878 if (p_hwfn->num_funcs_on_port > 1)
4879 p_dev->mf_bits |= 1 << ECORE_MF_INTER_PF_SWITCH |
4880 1 << ECORE_MF_DISABLE_ARFS;
4882 p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
4885 return ECORE_SUCCESS;
4889 static enum _ecore_status_t
4890 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
4891 struct ecore_ptt *p_ptt,
4892 struct ecore_hw_prepare_params *p_params)
4894 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
4895 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
4896 struct ecore_mcp_link_capabilities *p_caps;
4897 struct ecore_mcp_link_params *link;
4898 enum _ecore_status_t rc;
4901 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
4902 return ecore_emul_hw_get_nvm_info(p_hwfn);
4905 /* Read global nvm_cfg address */
4906 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
4908 /* Verify MCP has initialized it */
4909 if (!nvm_cfg_addr) {
4910 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
4911 if (p_params->b_relaxed_probe)
4912 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
4916 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
4918 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
4920 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4921 OFFSETOF(struct nvm_cfg1, glob) +
4922 OFFSETOF(struct nvm_cfg1_glob, core_cfg);
4924 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
4926 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
4927 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
4928 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
4929 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
4931 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4932 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
4934 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4935 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
4937 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4938 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
4940 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4941 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
4943 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4944 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
4946 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4947 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
4949 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4950 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
4952 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4953 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
4955 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4956 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
4958 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4959 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
4962 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
4967 /* Read DCBX configuration */
4968 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4969 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4970 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
4972 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
4973 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
4974 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
4975 switch (dcbx_mode) {
4976 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
4977 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
4979 case NVM_CFG1_PORT_DCBX_MODE_CEE:
4980 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
4982 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
4983 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
4986 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
4989 /* Read default link configuration */
4990 link = &p_hwfn->mcp_info->link_input;
4991 p_caps = &p_hwfn->mcp_info->link_capabilities;
4992 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4993 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4994 link_temp = ecore_rd(p_hwfn, p_ptt,
4996 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
4997 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4998 link->speed.advertised_speeds = link_temp;
4999 p_caps->speed_capabilities = link->speed.advertised_speeds;
5001 link_temp = ecore_rd(p_hwfn, p_ptt,
5003 OFFSETOF(struct nvm_cfg1_port, link_settings));
5004 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
5005 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
5006 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
5007 link->speed.autoneg = true;
5009 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
5010 link->speed.forced_speed = 1000;
5012 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
5013 link->speed.forced_speed = 10000;
5015 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
5016 link->speed.forced_speed = 25000;
5018 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
5019 link->speed.forced_speed = 40000;
5021 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
5022 link->speed.forced_speed = 50000;
5024 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
5025 link->speed.forced_speed = 100000;
5028 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
5031 p_caps->default_speed = link->speed.forced_speed;
5032 p_caps->default_speed_autoneg = link->speed.autoneg;
5034 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
5035 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
5036 link->pause.autoneg = !!(link_temp &
5037 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
5038 link->pause.forced_rx = !!(link_temp &
5039 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
5040 link->pause.forced_tx = !!(link_temp &
5041 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
5042 link->loopback_mode = 0;
5044 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
5045 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
5046 OFFSETOF(struct nvm_cfg1_port, ext_phy));
5047 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
5048 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
5049 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
5050 link->eee.enable = true;
5051 switch (link_temp) {
5052 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
5053 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
5054 link->eee.enable = false;
5056 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
5057 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
5059 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
5060 p_caps->eee_lpi_timer =
5061 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
5063 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
5064 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
5068 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
5069 link->eee.tx_lpi_enable = link->eee.enable;
5070 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
5072 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
5075 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5076 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
5077 link->speed.forced_speed, link->speed.advertised_speeds,
5078 link->speed.autoneg, link->pause.autoneg,
5079 p_caps->default_eee, p_caps->eee_lpi_timer);
5081 /* Read Multi-function information from shmem */
5082 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5083 OFFSETOF(struct nvm_cfg1, glob) +
5084 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
5086 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
5088 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
5089 NVM_CFG1_GLOB_MF_MODE_OFFSET;
5092 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
5093 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
5095 case NVM_CFG1_GLOB_MF_MODE_UFP:
5096 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
5097 1 << ECORE_MF_UFP_SPECIFIC |
5098 1 << ECORE_MF_8021Q_TAGGING;
5100 case NVM_CFG1_GLOB_MF_MODE_BD:
5101 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
5102 1 << ECORE_MF_LLH_PROTO_CLSS |
5103 1 << ECORE_MF_8021AD_TAGGING |
5104 1 << ECORE_MF_FIP_SPECIAL;
5106 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
5107 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
5108 1 << ECORE_MF_LLH_PROTO_CLSS |
5109 1 << ECORE_MF_LL2_NON_UNICAST |
5110 1 << ECORE_MF_INTER_PF_SWITCH |
5111 1 << ECORE_MF_DISABLE_ARFS;
5113 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
5114 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
5115 1 << ECORE_MF_LLH_PROTO_CLSS |
5116 1 << ECORE_MF_LL2_NON_UNICAST;
5117 if (ECORE_IS_BB(p_hwfn->p_dev))
5118 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
5121 DP_INFO(p_hwfn, "Multi function mode is 0x%x\n",
5122 p_hwfn->p_dev->mf_bits);
5124 if (ECORE_IS_CMT(p_hwfn->p_dev))
5125 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
5127 /* It's funny since we have another switch, but it's easier
5128 * to throw this away in linux this way. Long term, it might be
5129 * better to have have getters for needed ECORE_MF_* fields,
5130 * convert client code and eliminate this.
5133 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
5134 case NVM_CFG1_GLOB_MF_MODE_BD:
5135 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
5137 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
5138 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
5140 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
5141 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
5143 case NVM_CFG1_GLOB_MF_MODE_UFP:
5144 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
5148 /* Read Multi-function information from shmem */
5149 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5150 OFFSETOF(struct nvm_cfg1, glob) +
5151 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
5153 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
5154 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
5155 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
5156 &p_hwfn->hw_info.device_capabilities);
5157 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
5158 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
5159 &p_hwfn->hw_info.device_capabilities);
5160 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
5161 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
5162 &p_hwfn->hw_info.device_capabilities);
5163 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
5164 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
5165 &p_hwfn->hw_info.device_capabilities);
5166 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
5167 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
5168 &p_hwfn->hw_info.device_capabilities);
5170 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
5171 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5173 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5179 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
5180 struct ecore_ptt *p_ptt)
5182 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
5183 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
5184 struct ecore_dev *p_dev = p_hwfn->p_dev;
5186 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
5188 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
5189 * in the other bits are selected.
5190 * Bits 1-15 are for functions 1-15, respectively, and their value is
5191 * '0' only for enabled functions (function 0 always exists and
5193 * In case of CMT in BB, only the "even" functions are enabled, and thus
5194 * the number of functions for both hwfns is learnt from the same bits.
5196 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
5197 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
5198 MISCS_REG_FUNCTION_HIDE_BB_K2);
5200 reg_function_hide = 0;
5203 if (reg_function_hide & 0x1) {
5204 if (ECORE_IS_BB(p_dev)) {
5205 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
5217 /* Get the number of the enabled functions on the engine */
5218 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
5225 /* Get the PF index within the enabled functions */
5226 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
5227 tmp = reg_function_hide & eng_mask & low_pfs_mask;
5235 p_hwfn->num_funcs_on_engine = num_funcs;
5236 p_hwfn->enabled_func_idx = enabled_func_idx;
5239 if (CHIP_REV_IS_FPGA(p_dev)) {
5240 DP_NOTICE(p_hwfn, false,
5241 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
5242 p_hwfn->num_funcs_on_engine = 4;
5246 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
5247 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
5248 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
5249 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
5253 static void ecore_emul_hw_info_port_num(struct ecore_hwfn *p_hwfn,
5254 struct ecore_ptt *p_ptt)
5256 struct ecore_dev *p_dev = p_hwfn->p_dev;
5259 /* MISCS_REG_ECO_RESERVED[15:12]: num of ports in an engine */
5260 eco_reserved = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5261 switch ((eco_reserved & 0xf000) >> 12) {
5263 p_dev->num_ports_in_engine = 1;
5266 p_dev->num_ports_in_engine = 2;
5269 p_dev->num_ports_in_engine = 4;
5272 DP_NOTICE(p_hwfn, false,
5273 "Emulation: Unknown port mode [ECO_RESERVED 0x%08x]\n",
5275 p_dev->num_ports_in_engine = 1; /* Default to something */
5279 p_dev->num_ports = p_dev->num_ports_in_engine *
5280 ecore_device_num_engines(p_dev);
5284 /* Determine the number of ports of the device and per engine */
5285 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
5286 struct ecore_ptt *p_ptt)
5288 u32 addr, global_offsize, global_addr, port_mode;
5289 struct ecore_dev *p_dev = p_hwfn->p_dev;
5292 if (CHIP_REV_IS_TEDIBEAR(p_dev)) {
5293 p_dev->num_ports_in_engine = 1;
5294 p_dev->num_ports = 2;
5298 if (CHIP_REV_IS_EMUL(p_dev)) {
5299 ecore_emul_hw_info_port_num(p_hwfn, p_ptt);
5304 /* In CMT there is always only one port */
5305 if (ECORE_IS_CMT(p_dev)) {
5306 p_dev->num_ports_in_engine = 1;
5307 p_dev->num_ports = 1;
5311 /* Determine the number of ports per engine */
5312 port_mode = ecore_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
5313 switch (port_mode) {
5315 p_dev->num_ports_in_engine = 1;
5318 p_dev->num_ports_in_engine = 2;
5321 p_dev->num_ports_in_engine = 4;
5324 DP_NOTICE(p_hwfn, false, "Unknown port mode 0x%08x\n",
5326 p_dev->num_ports_in_engine = 1; /* Default to something */
5330 /* Get the total number of ports of the device */
5331 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
5333 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
5334 global_addr = SECTION_ADDR(global_offsize, 0);
5335 addr = global_addr + OFFSETOF(struct public_global, max_ports);
5336 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
5339 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
5340 struct ecore_ptt *p_ptt)
5342 struct ecore_mcp_link_capabilities *p_caps;
5345 p_caps = &p_hwfn->mcp_info->link_capabilities;
5346 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
5349 p_caps->eee_speed_caps = 0;
5350 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
5351 OFFSETOF(struct public_port, eee_status));
5352 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
5353 EEE_SUPPORTED_SPEED_OFFSET;
5354 if (eee_status & EEE_1G_SUPPORTED)
5355 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
5356 if (eee_status & EEE_10G_ADV)
5357 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
5360 static enum _ecore_status_t
5361 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
5362 enum ecore_pci_personality personality,
5363 struct ecore_hw_prepare_params *p_params)
5365 bool drv_resc_alloc = p_params->drv_resc_alloc;
5366 enum _ecore_status_t rc;
5368 if (IS_ECORE_PACING(p_hwfn)) {
5369 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV,
5370 "Skipping IOV as packet pacing is requested\n");
5373 /* Since all information is common, only first hwfns should do this */
5374 if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) {
5375 rc = ecore_iov_hw_info(p_hwfn);
5376 if (rc != ECORE_SUCCESS) {
5377 if (p_params->b_relaxed_probe)
5378 p_params->p_relaxed_res =
5379 ECORE_HW_PREPARE_BAD_IOV;
5385 if (IS_LEAD_HWFN(p_hwfn))
5386 ecore_hw_info_port_num(p_hwfn, p_ptt);
5388 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
5390 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
5391 if (rc != ECORE_SUCCESS)
5394 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
5395 if (rc != ECORE_SUCCESS) {
5396 if (p_params->b_relaxed_probe)
5397 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
5403 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
5405 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
5406 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
5409 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
5411 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
5412 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
5416 if (ecore_mcp_is_init(p_hwfn)) {
5417 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
5418 p_hwfn->hw_info.ovlan =
5419 p_hwfn->mcp_info->func_info.ovlan;
5421 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
5423 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
5425 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
5428 if (personality != ECORE_PCI_DEFAULT) {
5429 p_hwfn->hw_info.personality = personality;
5430 } else if (ecore_mcp_is_init(p_hwfn)) {
5431 enum ecore_pci_personality protocol;
5433 protocol = p_hwfn->mcp_info->func_info.protocol;
5434 p_hwfn->hw_info.personality = protocol;
5437 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
5439 * Allow only PF0 to be RoCE to overcome a lack of ILT lines.
5441 if (ECORE_IS_AH(p_hwfn->p_dev) && p_hwfn->rel_pf_id)
5442 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
5444 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
5448 /* although in BB some constellations may support more than 4 tcs,
5449 * that can result in performance penalty in some cases. 4
5450 * represents a good tradeoff between performance and flexibility.
5452 if (IS_ECORE_PACING(p_hwfn))
5453 p_hwfn->hw_info.num_hw_tc = 1;
5455 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
5457 /* start out with a single active tc. This can be increased either
5458 * by dcbx negotiation or by upper layer driver
5460 p_hwfn->hw_info.num_active_tc = 1;
5462 ecore_get_num_funcs(p_hwfn, p_ptt);
5464 if (ecore_mcp_is_init(p_hwfn))
5465 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
5467 /* In case of forcing the driver's default resource allocation, calling
5468 * ecore_hw_get_resc() should come after initializing the personality
5469 * and after getting the number of functions, since the calculation of
5470 * the resources/features depends on them.
5471 * This order is not harmful if not forcing.
5473 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
5474 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5476 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5482 #define ECORE_MAX_DEVICE_NAME_LEN (8)
5484 void ecore_get_dev_name(struct ecore_dev *p_dev, u8 *name, u8 max_chars)
5488 n = OSAL_MIN_T(u8, max_chars, ECORE_MAX_DEVICE_NAME_LEN);
5489 OSAL_SNPRINTF((char *)name, n, "%s %c%d",
5490 ECORE_IS_BB(p_dev) ? "BB" : "AH",
5491 'A' + p_dev->chip_rev, (int)p_dev->chip_metal);
5494 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
5495 struct ecore_ptt *p_ptt)
5497 struct ecore_dev *p_dev = p_hwfn->p_dev;
5501 /* Read Vendor Id / Device Id */
5502 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
5504 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
5507 /* Determine type */
5508 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
5509 switch (device_id_mask) {
5510 case ECORE_DEV_ID_MASK_BB:
5511 p_dev->type = ECORE_DEV_TYPE_BB;
5513 case ECORE_DEV_ID_MASK_AH:
5514 p_dev->type = ECORE_DEV_TYPE_AH;
5517 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
5519 return ECORE_ABORTED;
5522 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
5523 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
5524 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
5525 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
5527 /* Learn number of HW-functions */
5528 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
5530 if (tmp & (1 << p_hwfn->rel_pf_id)) {
5531 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
5532 p_dev->num_hwfns = 2;
5534 p_dev->num_hwfns = 1;
5538 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_BB(p_dev)) {
5539 /* For some reason we have problems with this register
5540 * in BB B0 emulation; Simply assume no CMT
5542 DP_NOTICE(p_dev->hwfns, false,
5543 "device on emul - assume no CMT\n");
5544 p_dev->num_hwfns = 1;
5548 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
5549 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
5550 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
5551 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
5553 DP_INFO(p_dev->hwfns,
5554 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
5555 ECORE_IS_BB(p_dev) ? "BB" : "AH",
5556 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
5557 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
5560 if (ECORE_IS_BB_A0(p_dev)) {
5561 DP_NOTICE(p_dev->hwfns, false,
5562 "The chip type/rev (BB A0) is not supported!\n");
5563 return ECORE_ABORTED;
5566 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
5567 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
5569 if (CHIP_REV_IS_EMUL(p_dev)) {
5570 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5572 /* MISCS_REG_ECO_RESERVED[29]: full/reduced emulation build */
5573 p_dev->b_is_emul_full = !!(tmp & (1 << 29));
5575 /* MISCS_REG_ECO_RESERVED[28]: emulation build w/ or w/o MAC */
5576 p_dev->b_is_emul_mac = !!(tmp & (1 << 28));
5578 DP_NOTICE(p_hwfn, false,
5579 "Emulation: Running on a %s build %s MAC\n",
5580 p_dev->b_is_emul_full ? "full" : "reduced",
5581 p_dev->b_is_emul_mac ? "with" : "without");
5585 return ECORE_SUCCESS;
5588 #ifndef LINUX_REMOVE
5589 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
5596 for_each_hwfn(p_dev, j) {
5597 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
5599 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
5600 "Mark hw/fw uninitialized\n");
5602 p_hwfn->hw_init_done = false;
5604 ecore_ptt_invalidate(p_hwfn);
5609 static enum _ecore_status_t
5610 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
5611 void OSAL_IOMEM *p_doorbells, u64 db_phys_addr,
5612 struct ecore_hw_prepare_params *p_params)
5614 struct ecore_mdump_retain_data mdump_retain;
5615 struct ecore_dev *p_dev = p_hwfn->p_dev;
5616 struct ecore_mdump_info mdump_info;
5617 enum _ecore_status_t rc = ECORE_SUCCESS;
5619 /* Split PCI bars evenly between hwfns */
5620 p_hwfn->regview = p_regview;
5621 p_hwfn->doorbells = p_doorbells;
5622 p_hwfn->db_phys_addr = db_phys_addr;
5625 return ecore_vf_hw_prepare(p_hwfn, p_params);
5627 /* Validate that chip access is feasible */
5628 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
5630 "Reading the ME register returns all Fs; Preventing further chip access\n");
5631 if (p_params->b_relaxed_probe)
5632 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
5636 get_function_id(p_hwfn);
5638 /* Allocate PTT pool */
5639 rc = ecore_ptt_pool_alloc(p_hwfn);
5641 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
5642 if (p_params->b_relaxed_probe)
5643 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5647 /* Allocate the main PTT */
5648 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
5650 /* First hwfn learns basic information, e.g., number of hwfns */
5651 if (IS_LEAD_HWFN(p_hwfn)) {
5652 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
5653 if (rc != ECORE_SUCCESS) {
5654 if (p_params->b_relaxed_probe)
5655 p_params->p_relaxed_res =
5656 ECORE_HW_PREPARE_FAILED_DEV;
5662 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) && !b_ptt_gtt_init) {
5663 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
5666 /* Initialize PTT/GTT (done by MFW on ASIC) */
5667 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_START_INIT_PTT_GTT, 1);
5669 ecore_ptt_invalidate(p_hwfn);
5670 val = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_INIT_DONE_PTT_GTT);
5673 "PTT and GTT init in PGLUE_B didn't complete\n");
5677 /* Clear a possible PGLUE_B parity from a previous GRC access */
5678 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_PRTY_STS_WR_H_0, 0x380);
5680 b_ptt_gtt_init = true;
5684 /* Store the precompiled init data ptrs */
5685 if (IS_LEAD_HWFN(p_hwfn))
5686 ecore_init_iro_array(p_hwfn->p_dev);
5688 ecore_hw_hwfn_prepare(p_hwfn);
5690 /* Initialize MCP structure */
5691 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
5693 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
5694 if (p_params->b_relaxed_probe)
5695 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5699 /* Read the device configuration information from the HW and SHMEM */
5700 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
5701 p_params->personality, p_params);
5703 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
5707 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
5708 * called, since among others it sets the ports number in an engine.
5710 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
5711 !p_dev->recov_in_prog) {
5712 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
5713 if (rc != ECORE_SUCCESS)
5714 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
5716 /* Workaround for MFW issue where PF FLR does not cleanup
5719 if (!(p_hwfn->mcp_info->capabilities &
5720 FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
5721 ecore_pf_flr_igu_cleanup(p_hwfn);
5724 /* Check if mdump logs/data are present and update the epoch value */
5725 if (IS_LEAD_HWFN(p_hwfn)) {
5726 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
5728 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
5729 DP_NOTICE(p_hwfn, false,
5730 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
5732 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
5734 if (rc == ECORE_SUCCESS && mdump_retain.valid)
5735 DP_NOTICE(p_hwfn, false,
5736 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
5737 mdump_retain.epoch, mdump_retain.pf,
5738 mdump_retain.status);
5740 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
5744 /* Allocate the init RT array and initialize the init-ops engine */
5745 rc = ecore_init_alloc(p_hwfn);
5747 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
5748 if (p_params->b_relaxed_probe)
5749 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5753 if (CHIP_REV_IS_FPGA(p_dev)) {
5754 if (ECORE_IS_AH(p_dev)) {
5755 DP_NOTICE(p_hwfn, false,
5756 "FPGA: workaround; Prevent DMAE parities\n");
5757 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
5758 PCIE_REG_PRTY_MASK_K2, 7);
5761 DP_NOTICE(p_hwfn, false,
5762 "FPGA: workaround: Set VF bar0 size\n");
5763 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
5764 PGLUE_B_REG_VF_BAR0_SIZE_K2, 4);
5770 if (IS_LEAD_HWFN(p_hwfn))
5771 ecore_iov_free_hw_info(p_dev);
5772 ecore_mcp_free(p_hwfn);
5774 ecore_hw_hwfn_free(p_hwfn);
5779 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
5780 struct ecore_hw_prepare_params *p_params)
5782 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5783 enum _ecore_status_t rc;
5785 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
5786 p_dev->allow_mdump = p_params->allow_mdump;
5787 p_hwfn->b_en_pacing = p_params->b_en_pacing;
5788 p_dev->b_is_target = p_params->b_is_target;
5790 if (p_params->b_relaxed_probe)
5791 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
5793 /* Initialize the first hwfn - will learn number of hwfns */
5794 rc = ecore_hw_prepare_single(p_hwfn, p_dev->regview,
5795 p_dev->doorbells, p_dev->db_phys_addr,
5797 if (rc != ECORE_SUCCESS)
5800 p_params->personality = p_hwfn->hw_info.personality;
5802 /* Initialize 2nd hwfn if necessary */
5803 if (ECORE_IS_CMT(p_dev)) {
5804 void OSAL_IOMEM *p_regview, *p_doorbell;
5805 u8 OSAL_IOMEM *addr;
5809 /* adjust bar offset for second engine */
5810 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
5812 addr = (u8 OSAL_IOMEM *)p_dev->regview + offset;
5813 p_regview = (void OSAL_IOMEM *)addr;
5815 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
5817 addr = (u8 OSAL_IOMEM *)p_dev->doorbells + offset;
5818 p_doorbell = (void OSAL_IOMEM *)addr;
5819 db_phys_addr = p_dev->db_phys_addr + offset;
5821 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;
5822 /* prepare second hw function */
5823 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
5824 p_doorbell, db_phys_addr,
5827 /* in case of error, need to free the previously
5828 * initiliazed hwfn 0.
5830 if (rc != ECORE_SUCCESS) {
5831 if (p_params->b_relaxed_probe)
5832 p_params->p_relaxed_res =
5833 ECORE_HW_PREPARE_FAILED_ENG2;
5836 ecore_init_free(p_hwfn);
5837 ecore_mcp_free(p_hwfn);
5838 ecore_hw_hwfn_free(p_hwfn);
5840 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
5849 void ecore_hw_remove(struct ecore_dev *p_dev)
5851 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5855 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
5856 ECORE_OV_DRIVER_STATE_NOT_LOADED);
5858 for_each_hwfn(p_dev, i) {
5859 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5862 ecore_vf_pf_release(p_hwfn);
5866 ecore_init_free(p_hwfn);
5867 ecore_hw_hwfn_free(p_hwfn);
5868 ecore_mcp_free(p_hwfn);
5870 #ifdef CONFIG_ECORE_LOCK_ALLOC
5871 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
5875 ecore_iov_free_hw_info(p_dev);
5878 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
5879 struct ecore_chain *p_chain)
5881 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
5882 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
5883 struct ecore_chain_next *p_next;
5889 size = p_chain->elem_size * p_chain->usable_per_page;
5891 for (i = 0; i < p_chain->page_cnt; i++) {
5895 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
5896 p_virt_next = p_next->next_virt;
5897 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
5899 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
5900 ECORE_CHAIN_PAGE_SIZE);
5902 p_virt = p_virt_next;
5903 p_phys = p_phys_next;
5907 static void ecore_chain_free_single(struct ecore_dev *p_dev,
5908 struct ecore_chain *p_chain)
5910 if (!p_chain->p_virt_addr)
5913 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
5914 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
5917 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
5918 struct ecore_chain *p_chain)
5920 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
5921 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
5922 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
5924 if (!pp_virt_addr_tbl)
5930 for (i = 0; i < page_cnt; i++) {
5931 if (!pp_virt_addr_tbl[i])
5934 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
5935 *(dma_addr_t *)p_pbl_virt,
5936 ECORE_CHAIN_PAGE_SIZE);
5938 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
5941 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
5943 if (!p_chain->b_external_pbl)
5944 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
5945 p_chain->pbl_sp.p_phys_table, pbl_size);
5947 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
5950 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5952 switch (p_chain->mode) {
5953 case ECORE_CHAIN_MODE_NEXT_PTR:
5954 ecore_chain_free_next_ptr(p_dev, p_chain);
5956 case ECORE_CHAIN_MODE_SINGLE:
5957 ecore_chain_free_single(p_dev, p_chain);
5959 case ECORE_CHAIN_MODE_PBL:
5960 ecore_chain_free_pbl(p_dev, p_chain);
5965 static enum _ecore_status_t
5966 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
5967 enum ecore_chain_cnt_type cnt_type,
5968 osal_size_t elem_size, u32 page_cnt)
5970 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
5972 /* The actual chain size can be larger than the maximal possible value
5973 * after rounding up the requested elements number to pages, and after
5974 * taking into acount the unusuable elements (next-ptr elements).
5975 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
5976 * size/capacity fields are of a u32 type.
5978 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
5979 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
5980 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
5981 chain_size > ECORE_U32_MAX)) {
5982 DP_NOTICE(p_dev, true,
5983 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
5984 (unsigned long)chain_size);
5988 return ECORE_SUCCESS;
5991 static enum _ecore_status_t
5992 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5994 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
5995 dma_addr_t p_phys = 0;
5998 for (i = 0; i < p_chain->page_cnt; i++) {
5999 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
6000 ECORE_CHAIN_PAGE_SIZE);
6002 DP_NOTICE(p_dev, false,
6003 "Failed to allocate chain memory\n");
6008 ecore_chain_init_mem(p_chain, p_virt, p_phys);
6009 ecore_chain_reset(p_chain);
6011 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
6015 p_virt_prev = p_virt;
6017 /* Last page's next element should point to the beginning of the
6020 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
6021 p_chain->p_virt_addr,
6022 p_chain->p_phys_addr);
6024 return ECORE_SUCCESS;
6027 static enum _ecore_status_t
6028 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
6030 dma_addr_t p_phys = 0;
6031 void *p_virt = OSAL_NULL;
6033 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
6035 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
6039 ecore_chain_init_mem(p_chain, p_virt, p_phys);
6040 ecore_chain_reset(p_chain);
6042 return ECORE_SUCCESS;
6045 static enum _ecore_status_t
6046 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
6047 struct ecore_chain *p_chain,
6048 struct ecore_chain_ext_pbl *ext_pbl)
6050 u32 page_cnt = p_chain->page_cnt, size, i;
6051 dma_addr_t p_phys = 0, p_pbl_phys = 0;
6052 void **pp_virt_addr_tbl = OSAL_NULL;
6053 u8 *p_pbl_virt = OSAL_NULL;
6054 void *p_virt = OSAL_NULL;
6056 size = page_cnt * sizeof(*pp_virt_addr_tbl);
6057 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
6058 if (!pp_virt_addr_tbl) {
6059 DP_NOTICE(p_dev, false,
6060 "Failed to allocate memory for the chain virtual addresses table\n");
6064 /* The allocation of the PBL table is done with its full size, since it
6065 * is expected to be successive.
6066 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
6067 * failure, since pp_virt_addr_tbl was previously allocated, and it
6068 * should be saved to allow its freeing during the error flow.
6070 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
6072 if (ext_pbl == OSAL_NULL) {
6073 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
6075 p_pbl_virt = ext_pbl->p_pbl_virt;
6076 p_pbl_phys = ext_pbl->p_pbl_phys;
6077 p_chain->b_external_pbl = true;
6080 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
6083 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
6087 for (i = 0; i < page_cnt; i++) {
6088 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
6089 ECORE_CHAIN_PAGE_SIZE);
6091 DP_NOTICE(p_dev, false,
6092 "Failed to allocate chain memory\n");
6097 ecore_chain_init_mem(p_chain, p_virt, p_phys);
6098 ecore_chain_reset(p_chain);
6101 /* Fill the PBL table with the physical address of the page */
6102 *(dma_addr_t *)p_pbl_virt = p_phys;
6103 /* Keep the virtual address of the page */
6104 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
6106 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
6109 return ECORE_SUCCESS;
6112 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
6113 enum ecore_chain_use_mode intended_use,
6114 enum ecore_chain_mode mode,
6115 enum ecore_chain_cnt_type cnt_type,
6116 u32 num_elems, osal_size_t elem_size,
6117 struct ecore_chain *p_chain,
6118 struct ecore_chain_ext_pbl *ext_pbl)
6121 enum _ecore_status_t rc = ECORE_SUCCESS;
6123 if (mode == ECORE_CHAIN_MODE_SINGLE)
6126 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
6128 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
6131 DP_NOTICE(p_dev, false,
6132 "Cannot allocate a chain with the given arguments:\n"
6133 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
6134 intended_use, mode, cnt_type, num_elems, elem_size);
6138 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
6139 mode, cnt_type, p_dev->dp_ctx);
6142 case ECORE_CHAIN_MODE_NEXT_PTR:
6143 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
6145 case ECORE_CHAIN_MODE_SINGLE:
6146 rc = ecore_chain_alloc_single(p_dev, p_chain);
6148 case ECORE_CHAIN_MODE_PBL:
6149 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
6155 return ECORE_SUCCESS;
6158 ecore_chain_free(p_dev, p_chain);
6162 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
6163 u16 src_id, u16 *dst_id)
6165 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
6168 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
6169 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
6170 DP_NOTICE(p_hwfn, true,
6171 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
6177 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
6179 return ECORE_SUCCESS;
6182 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
6183 u8 src_id, u8 *dst_id)
6185 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
6188 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
6189 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
6190 DP_NOTICE(p_hwfn, true,
6191 "vport id [%d] is not valid, available indices [%d - %d]\n",
6197 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
6199 return ECORE_SUCCESS;
6202 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
6203 u8 src_id, u8 *dst_id)
6205 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
6208 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
6209 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
6210 DP_NOTICE(p_hwfn, true,
6211 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
6217 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
6219 return ECORE_SUCCESS;
6222 enum _ecore_status_t
6223 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
6224 struct ecore_ptt *p_ptt)
6226 if (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
6227 ecore_wr(p_hwfn, p_ptt,
6228 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
6229 1 << p_hwfn->abs_pf_id / 2);
6230 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
6231 return ECORE_SUCCESS;
6234 DP_NOTICE(p_hwfn, false,
6235 "This function can't be set as default\n");
6239 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
6240 struct ecore_ptt *p_ptt,
6241 u32 hw_addr, void *p_eth_qzone,
6242 osal_size_t eth_qzone_size,
6245 struct coalescing_timeset *p_coal_timeset;
6247 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
6248 DP_NOTICE(p_hwfn, true,
6249 "Coalescing configuration not enabled\n");
6253 p_coal_timeset = p_eth_qzone;
6254 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
6255 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
6256 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
6257 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
6259 return ECORE_SUCCESS;
6262 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
6263 u16 rx_coal, u16 tx_coal,
6266 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
6267 enum _ecore_status_t rc = ECORE_SUCCESS;
6268 struct ecore_ptt *p_ptt;
6270 /* TODO - Configuring a single queue's coalescing but
6271 * claiming all queues are abiding same configuration
6272 * for PF and VF both.
6275 if (IS_VF(p_hwfn->p_dev))
6276 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
6279 p_ptt = ecore_ptt_acquire(p_hwfn);
6284 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
6287 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
6291 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
6294 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
6297 ecore_ptt_release(p_hwfn, p_ptt);
6302 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
6303 struct ecore_ptt *p_ptt,
6305 struct ecore_queue_cid *p_cid)
6307 struct ustorm_eth_queue_zone eth_qzone;
6308 u8 timeset, timer_res;
6310 enum _ecore_status_t rc;
6312 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6313 if (coalesce <= 0x7F) {
6315 } else if (coalesce <= 0xFF) {
6317 } else if (coalesce <= 0x1FF) {
6320 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6323 timeset = (u8)(coalesce >> timer_res);
6325 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6326 p_cid->sb_igu_id, false);
6327 if (rc != ECORE_SUCCESS)
6330 address = BAR0_MAP_REG_USDM_RAM +
6331 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6333 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
6334 sizeof(struct ustorm_eth_queue_zone), timeset);
6335 if (rc != ECORE_SUCCESS)
6342 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
6343 struct ecore_ptt *p_ptt,
6345 struct ecore_queue_cid *p_cid)
6347 struct xstorm_eth_queue_zone eth_qzone;
6348 u8 timeset, timer_res;
6350 enum _ecore_status_t rc;
6352 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6353 if (coalesce <= 0x7F) {
6355 } else if (coalesce <= 0xFF) {
6357 } else if (coalesce <= 0x1FF) {
6360 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6364 timeset = (u8)(coalesce >> timer_res);
6366 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6367 p_cid->sb_igu_id, true);
6368 if (rc != ECORE_SUCCESS)
6371 address = BAR0_MAP_REG_XSDM_RAM +
6372 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6374 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
6375 sizeof(struct xstorm_eth_queue_zone), timeset);
6380 /* Calculate final WFQ values for all vports and configure it.
6381 * After this configuration each vport must have
6382 * approx min rate = wfq * min_pf_rate / ECORE_WFQ_UNIT
6384 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6385 struct ecore_ptt *p_ptt,
6388 struct init_qm_vport_params *vport_params;
6391 vport_params = p_hwfn->qm_info.qm_vport_params;
6393 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6394 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6396 vport_params[i].wfq = (wfq_speed * ECORE_WFQ_UNIT) /
6398 ecore_init_vport_wfq(p_hwfn, p_ptt,
6399 vport_params[i].first_tx_pq_id,
6400 vport_params[i].wfq);
6404 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
6408 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
6409 p_hwfn->qm_info.qm_vport_params[i].wfq = 1;
6412 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6413 struct ecore_ptt *p_ptt)
6415 struct init_qm_vport_params *vport_params;
6418 vport_params = p_hwfn->qm_info.qm_vport_params;
6420 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6421 ecore_init_wfq_default_param(p_hwfn);
6422 ecore_init_vport_wfq(p_hwfn, p_ptt,
6423 vport_params[i].first_tx_pq_id,
6424 vport_params[i].wfq);
6428 /* This function performs several validations for WFQ
6429 * configuration and required min rate for a given vport
6430 * 1. req_rate must be greater than one percent of min_pf_rate.
6431 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
6432 * rates to get less than one percent of min_pf_rate.
6433 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
6435 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
6436 u16 vport_id, u32 req_rate,
6439 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
6440 int non_requested_count = 0, req_count = 0, i, num_vports;
6442 num_vports = p_hwfn->qm_info.num_vports;
6444 /* Accounting for the vports which are configured for WFQ explicitly */
6446 for (i = 0; i < num_vports; i++) {
6449 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
6451 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6452 total_req_min_rate += tmp_speed;
6456 /* Include current vport data as well */
6458 total_req_min_rate += req_rate;
6459 non_requested_count = num_vports - req_count;
6461 /* validate possible error cases */
6462 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
6463 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6464 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6465 vport_id, req_rate, min_pf_rate);
6469 /* TBD - for number of vports greater than 100 */
6470 if (num_vports > ECORE_WFQ_UNIT) {
6471 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6472 "Number of vports is greater than %d\n",
6477 if (total_req_min_rate > min_pf_rate) {
6478 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6479 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
6480 total_req_min_rate, min_pf_rate);
6484 /* Data left for non requested vports */
6485 total_left_rate = min_pf_rate - total_req_min_rate;
6486 left_rate_per_vp = total_left_rate / non_requested_count;
6488 /* validate if non requested get < 1% of min bw */
6489 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
6490 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6491 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6492 left_rate_per_vp, min_pf_rate);
6496 /* now req_rate for given vport passes all scenarios.
6497 * assign final wfq rates to all vports.
6499 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
6500 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
6502 for (i = 0; i < num_vports; i++) {
6503 if (p_hwfn->qm_info.wfq_data[i].configured)
6506 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
6509 return ECORE_SUCCESS;
6512 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
6513 struct ecore_ptt *p_ptt,
6514 u16 vp_id, u32 rate)
6516 struct ecore_mcp_link_state *p_link;
6517 int rc = ECORE_SUCCESS;
6519 p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output;
6521 if (!p_link->min_pf_rate) {
6522 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
6523 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
6527 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
6529 if (rc == ECORE_SUCCESS)
6530 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
6531 p_link->min_pf_rate);
6533 DP_NOTICE(p_hwfn, false,
6534 "Validation failed while configuring min rate\n");
6539 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
6540 struct ecore_ptt *p_ptt,
6543 bool use_wfq = false;
6544 int rc = ECORE_SUCCESS;
6547 /* Validate all pre configured vports for wfq */
6548 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6551 if (!p_hwfn->qm_info.wfq_data[i].configured)
6554 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
6557 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
6558 if (rc != ECORE_SUCCESS) {
6559 DP_NOTICE(p_hwfn, false,
6560 "WFQ validation failed while configuring min rate\n");
6565 if (rc == ECORE_SUCCESS && use_wfq)
6566 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
6568 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6573 /* Main API for ecore clients to configure vport min rate.
6574 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
6575 * rate - Speed in Mbps needs to be assigned to a given vport.
6577 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
6579 int i, rc = ECORE_INVAL;
6581 /* TBD - for multiple hardware functions - that is 100 gig */
6582 if (ECORE_IS_CMT(p_dev)) {
6583 DP_NOTICE(p_dev, false,
6584 "WFQ configuration is not supported for this device\n");
6588 for_each_hwfn(p_dev, i) {
6589 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6590 struct ecore_ptt *p_ptt;
6592 p_ptt = ecore_ptt_acquire(p_hwfn);
6594 return ECORE_TIMEOUT;
6596 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
6598 if (rc != ECORE_SUCCESS) {
6599 ecore_ptt_release(p_hwfn, p_ptt);
6603 ecore_ptt_release(p_hwfn, p_ptt);
6609 /* API to configure WFQ from mcp link change */
6610 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
6611 struct ecore_ptt *p_ptt,
6616 /* TBD - for multiple hardware functions - that is 100 gig */
6617 if (ECORE_IS_CMT(p_dev)) {
6618 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
6619 "WFQ configuration is not supported for this device\n");
6623 for_each_hwfn(p_dev, i) {
6624 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6626 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
6631 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
6632 struct ecore_ptt *p_ptt,
6633 struct ecore_mcp_link_state *p_link,
6636 int rc = ECORE_SUCCESS;
6638 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
6640 if (!p_link->line_speed && (max_bw != 100))
6643 p_link->speed = (p_link->line_speed * max_bw) / 100;
6644 p_hwfn->qm_info.pf_rl = p_link->speed;
6646 /* Since the limiter also affects Tx-switched traffic, we don't want it
6647 * to limit such traffic in case there's no actual limit.
6648 * In that case, set limit to imaginary high boundary.
6651 p_hwfn->qm_info.pf_rl = 100000;
6653 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
6654 p_hwfn->qm_info.pf_rl);
6656 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6657 "Configured MAX bandwidth to be %08x Mb/sec\n",
6663 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
6664 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
6666 int i, rc = ECORE_INVAL;
6668 if (max_bw < 1 || max_bw > 100) {
6669 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
6673 for_each_hwfn(p_dev, i) {
6674 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6675 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6676 struct ecore_mcp_link_state *p_link;
6677 struct ecore_ptt *p_ptt;
6679 p_link = &p_lead->mcp_info->link_output;
6681 p_ptt = ecore_ptt_acquire(p_hwfn);
6683 return ECORE_TIMEOUT;
6685 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
6688 ecore_ptt_release(p_hwfn, p_ptt);
6690 if (rc != ECORE_SUCCESS)
6697 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
6698 struct ecore_ptt *p_ptt,
6699 struct ecore_mcp_link_state *p_link,
6702 int rc = ECORE_SUCCESS;
6704 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
6705 p_hwfn->qm_info.pf_wfq = min_bw;
6707 if (!p_link->line_speed)
6710 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
6712 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
6714 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6715 "Configured MIN bandwidth to be %d Mb/sec\n",
6716 p_link->min_pf_rate);
6721 /* Main API to configure PF min bandwidth where bw range is [1-100] */
6722 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
6724 int i, rc = ECORE_INVAL;
6726 if (min_bw < 1 || min_bw > 100) {
6727 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
6731 for_each_hwfn(p_dev, i) {
6732 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6733 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6734 struct ecore_mcp_link_state *p_link;
6735 struct ecore_ptt *p_ptt;
6737 p_link = &p_lead->mcp_info->link_output;
6739 p_ptt = ecore_ptt_acquire(p_hwfn);
6741 return ECORE_TIMEOUT;
6743 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
6745 if (rc != ECORE_SUCCESS) {
6746 ecore_ptt_release(p_hwfn, p_ptt);
6750 if (p_link->min_pf_rate) {
6751 u32 min_rate = p_link->min_pf_rate;
6753 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
6758 ecore_ptt_release(p_hwfn, p_ptt);
6764 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
6766 struct ecore_mcp_link_state *p_link;
6768 p_link = &p_hwfn->mcp_info->link_output;
6770 if (p_link->min_pf_rate)
6771 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6773 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
6774 sizeof(*p_hwfn->qm_info.wfq_data) *
6775 p_hwfn->qm_info.num_vports);
6778 int ecore_device_num_engines(struct ecore_dev *p_dev)
6780 return ECORE_IS_BB(p_dev) ? 2 : 1;
6783 int ecore_device_num_ports(struct ecore_dev *p_dev)
6785 return p_dev->num_ports;
6788 void ecore_set_fw_mac_addr(__le16 *fw_msb,
6793 ((u8 *)fw_msb)[0] = mac[1];
6794 ((u8 *)fw_msb)[1] = mac[0];
6795 ((u8 *)fw_mid)[0] = mac[3];
6796 ((u8 *)fw_mid)[1] = mac[2];
6797 ((u8 *)fw_lsb)[0] = mac[5];
6798 ((u8 *)fw_lsb)[1] = mac[4];
6801 void ecore_set_platform_str(struct ecore_hwfn *p_hwfn,
6802 char *buf_str, u32 buf_size)
6806 OSAL_SNPRINTF(buf_str, buf_size, "Ecore %d.%d.%d.%d. ",
6807 ECORE_MAJOR_VERSION, ECORE_MINOR_VERSION,
6808 ECORE_REVISION_VERSION, ECORE_ENGINEERING_VERSION);
6810 len = OSAL_STRLEN(buf_str);
6811 OSAL_SET_PLATFORM_STR(p_hwfn, &buf_str[len], buf_size - len);
6814 bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
6816 return !!OSAL_GET_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);