2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
36 * registers involved are not split and thus configuration is a race where
37 * some of the PFs configuration might be lost.
38 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
39 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
40 * there's more than a single compiled ecore component in system].
42 static osal_spinlock_t qm_lock;
43 static bool qm_lock_init;
46 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
47 * load the driver. The number was
52 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
55 BAR_ID_0, /* used for GRC */
56 BAR_ID_1 /* Used for doorbells */
59 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
61 u32 bar_reg = (bar_id == BAR_ID_0 ?
62 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
65 if (IS_VF(p_hwfn->p_dev)) {
66 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
67 * read from actual register, but we're currently not using
68 * it for actual doorbelling.
73 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
75 return 1 << (val + 15);
77 /* The above registers were updated in the past only in CMT mode. Since
78 * they were found to be useful MFW started updating them from 8.7.7.0.
79 * In older MFW versions they are set to 0 which means disabled.
81 if (p_hwfn->p_dev->num_hwfns > 1) {
82 DP_NOTICE(p_hwfn, false,
83 "BAR size not configured. Assuming BAR size of 256kB"
84 " for GRC and 512kB for DB\n");
85 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
87 DP_NOTICE(p_hwfn, false,
88 "BAR size not configured. Assuming BAR size of 512kB"
89 " for GRC and 512kB for DB\n");
96 void ecore_init_dp(struct ecore_dev *p_dev,
97 u32 dp_module, u8 dp_level, void *dp_ctx)
101 p_dev->dp_level = dp_level;
102 p_dev->dp_module = dp_module;
103 p_dev->dp_ctx = dp_ctx;
104 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
105 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
107 p_hwfn->dp_level = dp_level;
108 p_hwfn->dp_module = dp_module;
109 p_hwfn->dp_ctx = dp_ctx;
113 void ecore_init_struct(struct ecore_dev *p_dev)
117 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
118 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
120 p_hwfn->p_dev = p_dev;
122 p_hwfn->b_active = false;
124 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
125 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
128 /* hwfn 0 is always active */
129 p_dev->hwfns[0].b_active = true;
131 /* set the default cache alignment to 128 (may be overridden later) */
132 p_dev->cache_shift = 7;
135 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
137 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
139 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
141 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
142 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
145 void ecore_resc_free(struct ecore_dev *p_dev)
150 for_each_hwfn(p_dev, i)
151 ecore_l2_free(&p_dev->hwfns[i]);
155 OSAL_FREE(p_dev, p_dev->fw_data);
157 OSAL_FREE(p_dev, p_dev->reset_stats);
159 for_each_hwfn(p_dev, i) {
160 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
162 ecore_cxt_mngr_free(p_hwfn);
163 ecore_qm_info_free(p_hwfn);
164 ecore_spq_free(p_hwfn);
165 ecore_eq_free(p_hwfn);
166 ecore_consq_free(p_hwfn);
167 ecore_int_free(p_hwfn);
168 ecore_iov_free(p_hwfn);
169 ecore_l2_free(p_hwfn);
170 ecore_dmae_info_free(p_hwfn);
171 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
172 /* @@@TBD Flush work-queue ? */
176 /******************** QM initialization *******************/
178 /* bitmaps for indicating active traffic classes.
179 * Special case for Arrowhead 4 port
181 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
182 #define ACTIVE_TCS_BMAP 0x9f
183 /* 0..3 actually used, OOO and high priority stuff all use 3 */
184 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
186 /* determines the physical queue flags for a given PF. */
187 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
195 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
196 flags |= PQ_FLAGS_VFS;
199 switch (p_hwfn->hw_info.personality) {
201 flags |= PQ_FLAGS_MCOS;
204 flags |= PQ_FLAGS_OFLD;
206 case ECORE_PCI_ISCSI:
207 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
209 case ECORE_PCI_ETH_ROCE:
210 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
212 case ECORE_PCI_ETH_IWARP:
213 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
217 DP_ERR(p_hwfn, "unknown personality %d\n",
218 p_hwfn->hw_info.personality);
224 /* Getters for resource amounts necessary for qm initialization */
225 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
227 return p_hwfn->hw_info.num_hw_tc;
230 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
232 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
233 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
236 #define NUM_DEFAULT_RLS 1
238 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
240 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
243 /* num RLs can't exceed resource amount of rls or vports or the
246 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
247 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
249 /* make sure after we reserve the default and VF rls we'll have
252 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
253 DP_NOTICE(p_hwfn, false,
254 "no rate limiters left for PF rate limiting"
255 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
259 /* subtract rls necessary for VFs and one default one for the PF */
260 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
265 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
267 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
269 /* all pqs share the same vport (hence the 1 below), except for vfs
272 return (!!(PQ_FLAGS_RLS & pq_flags)) *
273 ecore_init_qm_get_num_pf_rls(p_hwfn) +
274 (!!(PQ_FLAGS_VFS & pq_flags)) *
275 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
278 /* calc amount of PQs according to the requested flags */
279 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
281 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
283 return (!!(PQ_FLAGS_RLS & pq_flags)) *
284 ecore_init_qm_get_num_pf_rls(p_hwfn) +
285 (!!(PQ_FLAGS_MCOS & pq_flags)) *
286 ecore_init_qm_get_num_tcs(p_hwfn) +
287 (!!(PQ_FLAGS_LB & pq_flags)) +
288 (!!(PQ_FLAGS_OOO & pq_flags)) +
289 (!!(PQ_FLAGS_ACK & pq_flags)) +
290 (!!(PQ_FLAGS_OFLD & pq_flags)) +
291 (!!(PQ_FLAGS_VFS & pq_flags)) *
292 ecore_init_qm_get_num_vfs(p_hwfn);
295 /* initialize the top level QM params */
296 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
298 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
301 /* pq and vport bases for this PF */
302 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
303 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
305 /* rate limiting and weighted fair queueing are always enabled */
306 qm_info->vport_rl_en = 1;
307 qm_info->vport_wfq_en = 1;
309 /* TC config is different for AH 4 port */
310 four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
312 /* in AH 4 port we have fewer TCs per port */
313 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
316 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
319 if (!qm_info->ooo_tc)
320 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
324 /* initialize qm vport params */
325 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
327 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
330 /* all vports participate in weighted fair queueing */
331 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
332 qm_info->qm_vport_params[i].vport_wfq = 1;
335 /* initialize qm port params */
336 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
338 /* Initialize qm port parameters */
339 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
341 /* indicate how ooo and high pri traffic is dealt with */
342 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
343 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
345 for (i = 0; i < num_ports; i++) {
346 struct init_qm_port_params *p_qm_port =
347 &p_hwfn->qm_info.qm_port_params[i];
349 p_qm_port->active = 1;
350 p_qm_port->active_phys_tcs = active_phys_tcs;
351 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
352 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
356 /* Reset the params which must be reset for qm init. QM init may be called as
357 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
358 * params may be affected by the init but would simply recalculate to the same
359 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
360 * affected as these amounts stay the same.
362 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
364 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
366 qm_info->num_pqs = 0;
367 qm_info->num_vports = 0;
368 qm_info->num_pf_rls = 0;
369 qm_info->num_vf_pqs = 0;
370 qm_info->first_vf_pq = 0;
371 qm_info->first_mcos_pq = 0;
372 qm_info->first_rl_pq = 0;
375 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
377 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
379 qm_info->num_vports++;
381 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
383 "vport overflow! qm_info->num_vports %d,"
384 " qm_init_get_num_vports() %d\n",
386 ecore_init_qm_get_num_vports(p_hwfn));
389 /* initialize a single pq and manage qm_info resources accounting.
390 * The pq_init_flags param determines whether the PQ is rate limited
392 * and whether a new vport is allocated to the pq or not (i.e. vport will be
396 /* flags for pq init */
397 #define PQ_INIT_SHARE_VPORT (1 << 0)
398 #define PQ_INIT_PF_RL (1 << 1)
399 #define PQ_INIT_VF_RL (1 << 2)
401 /* defines for pq init */
402 #define PQ_INIT_DEFAULT_WRR_GROUP 1
403 #define PQ_INIT_DEFAULT_TC 0
404 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
406 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
407 struct ecore_qm_info *qm_info,
408 u8 tc, u32 pq_init_flags)
410 u16 pq_idx = qm_info->num_pqs, max_pq =
411 ecore_init_qm_get_num_pqs(p_hwfn);
415 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
418 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
420 qm_info->qm_pq_params[pq_idx].tc_id = tc;
421 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
422 qm_info->qm_pq_params[pq_idx].rl_valid =
423 (pq_init_flags & PQ_INIT_PF_RL ||
424 pq_init_flags & PQ_INIT_VF_RL);
426 /* qm params accounting */
428 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
429 qm_info->num_vports++;
431 if (pq_init_flags & PQ_INIT_PF_RL)
432 qm_info->num_pf_rls++;
434 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
436 "vport overflow! qm_info->num_vports %d,"
437 " qm_init_get_num_vports() %d\n",
439 ecore_init_qm_get_num_vports(p_hwfn));
441 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
442 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
443 " qm_init_get_num_pf_rls() %d\n",
445 ecore_init_qm_get_num_pf_rls(p_hwfn));
448 /* get pq index according to PQ_FLAGS */
449 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
452 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
454 /* Can't have multiple flags set here */
455 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
456 sizeof(pq_flags)) > 1)
461 return &qm_info->first_rl_pq;
463 return &qm_info->first_mcos_pq;
465 return &qm_info->pure_lb_pq;
467 return &qm_info->ooo_pq;
469 return &qm_info->pure_ack_pq;
471 return &qm_info->offload_pq;
473 return &qm_info->first_vf_pq;
479 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
483 /* save pq index in qm info */
484 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
485 u32 pq_flags, u16 pq_val)
487 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
489 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
492 /* get tx pq index, with the PQ TX base already set (ready for context init) */
493 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
495 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
497 return *base_pq_idx + CM_TX_PQ_BASE;
500 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
502 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
505 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
507 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
510 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
512 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
515 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
517 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
520 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
522 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
525 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
527 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
530 /* Functions for creating specific types of pqs */
531 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
533 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
535 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
538 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
539 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
542 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
544 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
546 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
549 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
550 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
553 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
555 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
557 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
560 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
561 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
564 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
566 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
568 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
571 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
572 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
575 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
577 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
580 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
583 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
584 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
585 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
588 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
590 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
591 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
593 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
596 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
598 qm_info->num_vf_pqs = num_vfs;
599 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
600 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
604 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
606 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
607 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
609 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
612 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
613 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
614 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
618 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
620 /* rate limited pqs, must come first (FW assumption) */
621 ecore_init_qm_rl_pqs(p_hwfn);
623 /* pqs for multi cos */
624 ecore_init_qm_mcos_pqs(p_hwfn);
626 /* pure loopback pq */
627 ecore_init_qm_lb_pq(p_hwfn);
629 /* out of order pq */
630 ecore_init_qm_ooo_pq(p_hwfn);
633 ecore_init_qm_pure_ack_pq(p_hwfn);
635 /* pq for offloaded protocol */
636 ecore_init_qm_offload_pq(p_hwfn);
638 /* done sharing vports */
639 ecore_init_qm_advance_vport(p_hwfn);
642 ecore_init_qm_vf_pqs(p_hwfn);
645 /* compare values of getters against resources amounts */
646 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
648 if (ecore_init_qm_get_num_vports(p_hwfn) >
649 RESC_NUM(p_hwfn, ECORE_VPORT)) {
650 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
654 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
655 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
659 return ECORE_SUCCESS;
663 * Function for verbose printing of the qm initialization results
665 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
667 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
668 struct init_qm_vport_params *vport;
669 struct init_qm_port_params *port;
670 struct init_qm_pq_params *pq;
673 /* top level params */
674 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
675 "qm init top level params: start_pq %d, start_vport %d,"
676 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
677 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
678 qm_info->offload_pq, qm_info->pure_ack_pq);
679 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
680 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
681 " num_vports %d, max_phys_tcs_per_port %d\n",
682 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
683 qm_info->num_vf_pqs, qm_info->num_vports,
684 qm_info->max_phys_tcs_per_port);
685 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
686 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
687 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
688 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
689 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
690 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
693 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
694 port = &qm_info->qm_port_params[i];
695 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
696 "port idx %d, active %d, active_phys_tcs %d,"
697 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
699 i, port->active, port->active_phys_tcs,
700 port->num_pbf_cmd_lines, port->num_btb_blocks,
705 for (i = 0; i < qm_info->num_vports; i++) {
706 vport = &qm_info->qm_vport_params[i];
707 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
708 "vport idx %d, vport_rl %d, wfq %d,"
709 " first_tx_pq_id [ ",
710 qm_info->start_vport + i, vport->vport_rl,
712 for (tc = 0; tc < NUM_OF_TCS; tc++)
713 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
714 vport->first_tx_pq_id[tc]);
715 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
719 for (i = 0; i < qm_info->num_pqs; i++) {
720 pq = &qm_info->qm_pq_params[i];
721 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
722 "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
724 qm_info->start_pq + i, pq->vport_id, pq->tc_id,
725 pq->wrr_group, pq->rl_valid);
729 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
731 /* reset params required for init run */
732 ecore_init_qm_reset_params(p_hwfn);
734 /* init QM top level params */
735 ecore_init_qm_params(p_hwfn);
737 /* init QM port params */
738 ecore_init_qm_port_params(p_hwfn);
740 /* init QM vport params */
741 ecore_init_qm_vport_params(p_hwfn);
743 /* init QM physical queue params */
744 ecore_init_qm_pq_params(p_hwfn);
746 /* display all that init */
747 ecore_dp_init_qm_params(p_hwfn);
750 /* This function reconfigures the QM pf on the fly.
751 * For this purpose we:
752 * 1. reconfigure the QM database
753 * 2. set new values to runtime array
754 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
755 * 4. activate init tool in QM_PF stage
756 * 5. send an sdm_qm_cmd through rbc interface to release the QM
758 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
759 struct ecore_ptt *p_ptt)
761 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
763 enum _ecore_status_t rc;
765 /* initialize ecore's qm data structure */
766 ecore_init_qm_info(p_hwfn);
768 /* stop PF's qm queues */
769 OSAL_SPIN_LOCK(&qm_lock);
770 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
771 qm_info->start_pq, qm_info->num_pqs);
772 OSAL_SPIN_UNLOCK(&qm_lock);
776 /* clear the QM_PF runtime phase leftovers from previous init */
777 ecore_init_clear_rt_data(p_hwfn);
779 /* prepare QM portion of runtime array */
780 ecore_qm_init_pf(p_hwfn);
782 /* activate init tool on runtime array */
783 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
784 p_hwfn->hw_info.hw_mode);
785 if (rc != ECORE_SUCCESS)
788 /* start PF's qm queues */
789 OSAL_SPIN_LOCK(&qm_lock);
790 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
791 qm_info->start_pq, qm_info->num_pqs);
792 OSAL_SPIN_UNLOCK(&qm_lock);
796 return ECORE_SUCCESS;
799 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
801 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
802 enum _ecore_status_t rc;
804 rc = ecore_init_qm_sanity(p_hwfn);
805 if (rc != ECORE_SUCCESS)
808 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
809 sizeof(struct init_qm_pq_params) *
810 ecore_init_qm_get_num_pqs(p_hwfn));
811 if (!qm_info->qm_pq_params)
814 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
815 sizeof(struct init_qm_vport_params) *
816 ecore_init_qm_get_num_vports(p_hwfn));
817 if (!qm_info->qm_vport_params)
820 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
821 sizeof(struct init_qm_port_params) *
822 p_hwfn->p_dev->num_ports_in_engines);
823 if (!qm_info->qm_port_params)
826 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
827 sizeof(struct ecore_wfq_data) *
828 ecore_init_qm_get_num_vports(p_hwfn));
829 if (!qm_info->wfq_data)
832 return ECORE_SUCCESS;
835 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
836 ecore_qm_info_free(p_hwfn);
839 /******************** End QM initialization ***************/
841 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
843 enum _ecore_status_t rc = ECORE_SUCCESS;
847 for_each_hwfn(p_dev, i) {
848 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
849 if (rc != ECORE_SUCCESS)
855 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
856 sizeof(*p_dev->fw_data));
860 for_each_hwfn(p_dev, i) {
861 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
862 u32 n_eqes, num_cons;
864 /* First allocate the context manager structure */
865 rc = ecore_cxt_mngr_alloc(p_hwfn);
869 /* Set the HW cid/tid numbers (in the contest manager)
870 * Must be done prior to any further computations.
872 rc = ecore_cxt_set_pf_params(p_hwfn);
876 rc = ecore_alloc_qm_data(p_hwfn);
881 ecore_init_qm_info(p_hwfn);
883 /* Compute the ILT client partition */
884 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
888 /* CID map / ILT shadow table / T2
889 * The talbes sizes are determined by the computations above
891 rc = ecore_cxt_tables_alloc(p_hwfn);
895 /* SPQ, must follow ILT because initializes SPQ context */
896 rc = ecore_spq_alloc(p_hwfn);
900 /* SP status block allocation */
901 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
904 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
908 rc = ecore_iov_alloc(p_hwfn);
913 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
914 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
915 /* Calculate the EQ size
916 * ---------------------
917 * Each ICID may generate up to one event at a time i.e.
918 * the event must be handled/cleared before a new one
919 * can be generated. We calculate the sum of events per
920 * protocol and create an EQ deep enough to handle the
922 * - Core - according to SPQ.
923 * - RoCE - per QP there are a couple of ICIDs, one
924 * responder and one requester, each can
925 * generate an EQE => n_eqes_qp = 2 * n_qp.
926 * Each CQ can generate an EQE. There are 2 CQs
927 * per QP => n_eqes_cq = 2 * n_qp.
928 * Hence the RoCE total is 4 * n_qp or
930 * - ENet - There can be up to two events per VF. One
931 * for VF-PF channel and another for VF FLR
932 * initial cleanup. The number of VFs is
933 * bounded by MAX_NUM_VFS_BB, and is much
934 * smaller than RoCE's so we avoid exact
937 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
939 ecore_cxt_get_proto_cid_count(
945 num_cons = ecore_cxt_get_proto_cid_count(
950 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
951 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
953 ecore_cxt_get_proto_cid_count(p_hwfn,
956 n_eqes += 2 * num_cons;
959 if (n_eqes > 0xFFFF) {
960 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
961 "The maximum of a u16 chain is 0x%x\n",
966 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
970 rc = ecore_consq_alloc(p_hwfn);
974 rc = ecore_l2_alloc(p_hwfn);
975 if (rc != ECORE_SUCCESS)
978 /* DMA info initialization */
979 rc = ecore_dmae_info_alloc(p_hwfn);
981 DP_NOTICE(p_hwfn, true,
982 "Failed to allocate memory for dmae_info"
987 /* DCBX initialization */
988 rc = ecore_dcbx_info_alloc(p_hwfn);
990 DP_NOTICE(p_hwfn, true,
991 "Failed to allocate memory for dcbx structure\n");
996 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
997 sizeof(*p_dev->reset_stats));
998 if (!p_dev->reset_stats) {
999 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1003 return ECORE_SUCCESS;
1008 ecore_resc_free(p_dev);
1012 void ecore_resc_setup(struct ecore_dev *p_dev)
1017 for_each_hwfn(p_dev, i)
1018 ecore_l2_setup(&p_dev->hwfns[i]);
1022 for_each_hwfn(p_dev, i) {
1023 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1025 ecore_cxt_mngr_setup(p_hwfn);
1026 ecore_spq_setup(p_hwfn);
1027 ecore_eq_setup(p_hwfn);
1028 ecore_consq_setup(p_hwfn);
1030 /* Read shadow of current MFW mailbox */
1031 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1032 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1033 p_hwfn->mcp_info->mfw_mb_cur,
1034 p_hwfn->mcp_info->mfw_mb_length);
1036 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1038 ecore_l2_setup(p_hwfn);
1039 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1043 #define FINAL_CLEANUP_POLL_CNT (100)
1044 #define FINAL_CLEANUP_POLL_TIME (10)
1045 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1046 struct ecore_ptt *p_ptt,
1049 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1050 enum _ecore_status_t rc = ECORE_TIMEOUT;
1053 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1054 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1055 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1056 return ECORE_SUCCESS;
1060 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1061 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1066 command |= X_FINAL_CLEANUP_AGG_INT <<
1067 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1068 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1069 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1070 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1072 /* Make sure notification is not set before initiating final cleanup */
1074 if (REG_RD(p_hwfn, addr)) {
1075 DP_NOTICE(p_hwfn, false,
1076 "Unexpected; Found final cleanup notification");
1077 DP_NOTICE(p_hwfn, false,
1078 " before initiating final cleanup\n");
1079 REG_WR(p_hwfn, addr, 0);
1082 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1083 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1086 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1088 /* Poll until completion */
1089 while (!REG_RD(p_hwfn, addr) && count--)
1090 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1092 if (REG_RD(p_hwfn, addr))
1095 DP_NOTICE(p_hwfn, true,
1096 "Failed to receive FW final cleanup notification\n");
1098 /* Cleanup afterwards */
1099 REG_WR(p_hwfn, addr, 0);
1104 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1108 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1109 hw_mode |= 1 << MODE_BB;
1110 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1111 hw_mode |= 1 << MODE_K2;
1113 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1114 p_hwfn->p_dev->type);
1118 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1119 switch (p_hwfn->p_dev->num_ports_in_engines) {
1121 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1124 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1127 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1130 DP_NOTICE(p_hwfn, true,
1131 "num_ports_in_engine = %d not supported\n",
1132 p_hwfn->p_dev->num_ports_in_engines);
1136 switch (p_hwfn->p_dev->mf_mode) {
1137 case ECORE_MF_DEFAULT:
1139 hw_mode |= 1 << MODE_MF_SI;
1141 case ECORE_MF_OVLAN:
1142 hw_mode |= 1 << MODE_MF_SD;
1145 DP_NOTICE(p_hwfn, true,
1146 "Unsupported MF mode, init as DEFAULT\n");
1147 hw_mode |= 1 << MODE_MF_SI;
1151 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1152 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1153 hw_mode |= 1 << MODE_FPGA;
1155 if (p_hwfn->p_dev->b_is_emul_full)
1156 hw_mode |= 1 << MODE_EMUL_FULL;
1158 hw_mode |= 1 << MODE_EMUL_REDUCED;
1162 hw_mode |= 1 << MODE_ASIC;
1164 if (p_hwfn->p_dev->num_hwfns > 1)
1165 hw_mode |= 1 << MODE_100G;
1167 p_hwfn->hw_info.hw_mode = hw_mode;
1169 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1170 "Configuring function for hw_mode: 0x%08x\n",
1171 p_hwfn->hw_info.hw_mode);
1173 return ECORE_SUCCESS;
1177 /* MFW-replacement initializations for non-ASIC */
1178 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1179 struct ecore_ptt *p_ptt)
1181 struct ecore_dev *p_dev = p_hwfn->p_dev;
1185 if (CHIP_REV_IS_EMUL(p_dev)) {
1186 if (ECORE_IS_AH(p_dev))
1190 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1192 if (CHIP_REV_IS_EMUL(p_dev) &&
1193 (ECORE_IS_AH(p_dev)))
1194 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1197 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1198 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1199 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1200 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1202 if (CHIP_REV_IS_EMUL(p_dev)) {
1203 if (ECORE_IS_AH(p_dev)) {
1204 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1205 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1206 (p_dev->num_ports_in_engines >> 1));
1208 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1209 p_dev->num_ports_in_engines == 4 ? 0 : 3);
1214 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1215 for (i = 0; i < 100; i++) {
1217 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1221 DP_NOTICE(p_hwfn, true,
1222 "RBC done failed to complete in PSWRQ2\n");
1224 return ECORE_SUCCESS;
1228 /* Init run time data for all PFs and their VFs on an engine.
1229 * TBD - for VFs - Once we have parent PF info for each VF in
1230 * shmem available as CAU requires knowledge of parent PF for each VF.
1232 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1234 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1237 for_each_hwfn(p_dev, i) {
1238 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1239 struct ecore_igu_info *p_igu_info;
1240 struct ecore_igu_block *p_block;
1241 struct cau_sb_entry sb_entry;
1243 p_igu_info = p_hwfn->hw_info.p_igu_info;
1246 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1248 p_block = &p_igu_info->entry[igu_sb_id];
1250 if (!p_block->is_pf)
1253 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1254 p_block->function_id, 0, 0);
1255 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1261 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1262 struct ecore_ptt *p_ptt,
1265 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1266 struct ecore_dev *p_dev = p_hwfn->p_dev;
1267 u8 vf_id, max_num_vfs;
1270 enum _ecore_status_t rc = ECORE_SUCCESS;
1272 ecore_init_cau_rt_data(p_dev);
1274 /* Program GTT windows */
1275 ecore_gtt_init(p_hwfn);
1278 if (CHIP_REV_IS_EMUL(p_dev)) {
1279 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1280 if (rc != ECORE_SUCCESS)
1285 if (p_hwfn->mcp_info) {
1286 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1287 qm_info->pf_rl_en = 1;
1288 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1289 qm_info->pf_wfq_en = 1;
1292 ecore_qm_common_rt_init(p_hwfn,
1293 p_dev->num_ports_in_engines,
1294 qm_info->max_phys_tcs_per_port,
1295 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1296 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1297 qm_info->qm_port_params);
1299 ecore_cxt_hw_init_common(p_hwfn);
1301 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1302 if (rc != ECORE_SUCCESS)
1305 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1306 * need to decide with which value, maybe runtime
1308 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1309 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1311 if (ECORE_IS_BB(p_dev)) {
1312 /* Workaround clears ROCE search for all functions to prevent
1313 * involving non initialized function in processing ROCE packet.
1315 num_pfs = NUM_OF_ENG_PFS(p_dev);
1316 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1317 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1318 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1319 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1321 /* pretend to original PF */
1322 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1325 /* Workaround for avoiding CCFC execution error when getting packets
1326 * with CRC errors, and allowing instead the invoking of the FW error
1328 * This is not done inside the init tool since it currently can't
1329 * perform a pretending to VFs.
1331 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1332 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1333 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1334 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1335 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1336 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1337 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1338 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1340 /* pretend to original PF */
1341 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1347 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1348 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1350 #define PMEG_IF_BYTE_COUNT 8
1352 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1353 struct ecore_ptt *p_ptt,
1354 u32 addr, u64 data, u8 reg_type, u8 port)
1356 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1357 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1358 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1359 (8 << PMEG_IF_BYTE_COUNT),
1360 (reg_type << 25) | (addr << 8) | port,
1361 (u32)((data >> 32) & 0xffffffff),
1362 (u32)(data & 0xffffffff));
1364 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1365 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1366 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1367 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1368 (reg_type << 25) | (addr << 8) | port);
1369 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1370 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1371 (data >> 32) & 0xffffffff);
1374 #define XLPORT_MODE_REG (0x20a)
1375 #define XLPORT_MAC_CONTROL (0x210)
1376 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1377 #define XLPORT_ENABLE_REG (0x20b)
1379 #define XLMAC_CTRL (0x600)
1380 #define XLMAC_MODE (0x601)
1381 #define XLMAC_RX_MAX_SIZE (0x608)
1382 #define XLMAC_TX_CTRL (0x604)
1383 #define XLMAC_PAUSE_CTRL (0x60d)
1384 #define XLMAC_PFC_CTRL (0x60e)
1386 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1387 struct ecore_ptt *p_ptt)
1389 u8 loopback = 0, port = p_hwfn->port_id * 2;
1391 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1393 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1394 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1396 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1397 /* XLMAC: SOFT RESET */
1398 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1399 /* XLMAC: Port Speed >= 10Gbps */
1400 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1401 /* XLMAC: Max Size */
1402 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1403 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1404 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1406 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1407 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1408 0x30ffffc000ULL, 0, port);
1409 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1410 port); /* XLMAC: TX_EN, RX_EN */
1411 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1412 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1413 0x1003 | (loopback << 2), 0, port);
1414 /* Enabled Parallel PFC interface */
1415 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1417 /* XLPORT port enable */
1418 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1421 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1422 struct ecore_ptt *p_ptt)
1424 u8 port = p_hwfn->port_id;
1425 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1427 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1429 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1430 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1432 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1433 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1435 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1436 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1438 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1439 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1441 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1442 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1444 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1445 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1447 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1449 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1451 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1453 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1457 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1458 struct ecore_ptt *p_ptt)
1460 if (ECORE_IS_AH(p_hwfn->p_dev))
1461 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1463 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1466 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1467 struct ecore_ptt *p_ptt, u8 port)
1469 int port_offset = port ? 0x800 : 0;
1470 u32 xmac_rxctrl = 0;
1473 /* FIXME: move to common start */
1474 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1475 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1477 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1478 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1480 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1482 /* Set the number of ports on the Warp Core to 10G */
1483 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1485 /* Soft reset of XMAC */
1486 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1487 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1489 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1490 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1492 /* FIXME: move to common end */
1493 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1494 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1496 /* Set Max packet size: initialize XMAC block register for port 0 */
1497 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1499 /* CRC append for Tx packets: init XMAC block register for port 1 */
1500 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1502 /* Enable TX and RX: initialize XMAC block register for port 1 */
1503 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1504 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1505 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1506 XMAC_REG_RX_CTRL_BB + port_offset);
1507 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1508 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1512 static enum _ecore_status_t
1513 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1514 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1516 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1517 u32 dpi_bit_shift, dpi_count;
1520 /* Calculate DPI size
1521 * ------------------
1522 * The PWM region contains Doorbell Pages. The first is reserverd for
1523 * the kernel for, e.g, L2. The others are free to be used by non-
1524 * trusted applications, typically from user space. Each page, called a
1525 * doorbell page is sectioned into windows that allow doorbells to be
1526 * issued in parallel by the kernel/application. The size of such a
1527 * window (a.k.a. WID) is 1kB.
1529 * 1kB WID x N WIDS = DPI page size
1530 * DPI page size x N DPIs = PWM region size
1532 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1533 * in order to ensure that two applications won't share the same page.
1534 * It also must contain at least one WID per CPU to allow parallelism.
1535 * It also must be a power of 2, since it is stored as a bit shift.
1537 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1538 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1539 * containing 4 WIDs.
1541 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1542 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1543 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1544 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1545 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1547 dpi_count = pwm_region_size / dpi_page_size;
1549 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1550 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1553 p_hwfn->dpi_size = dpi_page_size;
1554 p_hwfn->dpi_count = dpi_count;
1556 /* Update registers */
1557 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1559 if (dpi_count < min_dpis)
1560 return ECORE_NORESOURCES;
1562 return ECORE_SUCCESS;
1565 enum ECORE_ROCE_EDPM_MODE {
1566 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1567 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1568 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1571 static enum _ecore_status_t
1572 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1573 struct ecore_ptt *p_ptt)
1575 u32 pwm_regsize, norm_regsize;
1576 u32 non_pwm_conn, min_addr_reg1;
1577 u32 db_bar_size, n_cpus;
1580 enum _ecore_status_t rc = ECORE_SUCCESS;
1583 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1584 if (p_hwfn->p_dev->num_hwfns > 1)
1587 /* Calculate doorbell regions
1588 * -----------------------------------
1589 * The doorbell BAR is made of two regions. The first is called normal
1590 * region and the second is called PWM region. In the normal region
1591 * each ICID has its own set of addresses so that writing to that
1592 * specific address identifies the ICID. In the Process Window Mode
1593 * region the ICID is given in the data written to the doorbell. The
1594 * above per PF register denotes the offset in the doorbell BAR in which
1595 * the PWM region begins.
1596 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1597 * non-PWM connection. The calculation below computes the total non-PWM
1598 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1599 * in units of 4,096 bytes.
1601 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1602 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1604 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1605 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1606 min_addr_reg1 = norm_regsize / 4096;
1607 pwm_regsize = db_bar_size - norm_regsize;
1609 /* Check that the normal and PWM sizes are valid */
1610 if (db_bar_size < norm_regsize) {
1611 DP_ERR(p_hwfn->p_dev,
1612 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1613 db_bar_size, norm_regsize);
1614 return ECORE_NORESOURCES;
1616 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1617 DP_ERR(p_hwfn->p_dev,
1618 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1619 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1621 return ECORE_NORESOURCES;
1624 /* Calculate number of DPIs */
1625 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1626 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1627 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1628 /* Either EDPM is mandatory, or we are attempting to allocate a
1631 n_cpus = OSAL_NUM_ACTIVE_CPU();
1632 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1635 cond = ((rc != ECORE_SUCCESS) &&
1636 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1637 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1638 if (cond || p_hwfn->dcbx_no_edpm) {
1639 /* Either EDPM is disabled from user configuration, or it is
1640 * disabled via DCBx, or it is not mandatory and we failed to
1641 * allocated a WID per CPU.
1644 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1646 /* If we entered this flow due to DCBX then the DPM register is
1647 * already configured.
1652 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1653 norm_regsize, pwm_regsize);
1655 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1656 p_hwfn->dpi_size, p_hwfn->dpi_count,
1657 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1658 "disabled" : "enabled");
1660 /* Check return codes from above calls */
1661 if (rc != ECORE_SUCCESS) {
1663 "Failed to allocate enough DPIs\n");
1664 return ECORE_NORESOURCES;
1668 p_hwfn->dpi_start_offset = norm_regsize;
1670 /* Update registers */
1671 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1672 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1673 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1674 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1676 return ECORE_SUCCESS;
1679 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1680 struct ecore_ptt *p_ptt,
1683 enum _ecore_status_t rc = ECORE_SUCCESS;
1685 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1687 if (rc != ECORE_SUCCESS)
1690 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1691 return ECORE_SUCCESS;
1693 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1694 if (ECORE_IS_AH(p_hwfn->p_dev))
1695 return ECORE_SUCCESS;
1696 else if (ECORE_IS_BB(p_hwfn->p_dev))
1697 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1698 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1699 if (p_hwfn->p_dev->num_hwfns > 1) {
1700 /* Activate OPTE in CMT */
1703 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1705 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1706 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1707 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1708 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1709 ecore_wr(p_hwfn, p_ptt,
1710 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1711 ecore_wr(p_hwfn, p_ptt,
1712 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1713 ecore_wr(p_hwfn, p_ptt,
1714 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1718 ecore_emul_link_init(p_hwfn, p_ptt);
1720 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1727 static enum _ecore_status_t
1728 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1729 struct ecore_ptt *p_ptt,
1730 struct ecore_tunnel_info *p_tunn,
1733 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1735 u8 rel_pf_id = p_hwfn->rel_pf_id;
1737 enum _ecore_status_t rc = ECORE_SUCCESS;
1741 if (p_hwfn->mcp_info) {
1742 struct ecore_mcp_function_info *p_info;
1744 p_info = &p_hwfn->mcp_info->func_info;
1745 if (p_info->bandwidth_min)
1746 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1748 /* Update rate limit once we'll actually have a link */
1749 p_hwfn->qm_info.pf_rl = 100000;
1751 ecore_cxt_hw_init_pf(p_hwfn);
1753 ecore_int_igu_init_rt(p_hwfn);
1755 /* Set VLAN in NIG if needed */
1756 if (hw_mode & (1 << MODE_MF_SD)) {
1757 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1758 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1759 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1760 p_hwfn->hw_info.ovlan);
1763 /* Enable classification by MAC if needed */
1764 if (hw_mode & (1 << MODE_MF_SI)) {
1765 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1766 "Configuring TAGMAC_CLS_TYPE\n");
1767 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1771 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1772 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1773 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1774 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1775 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1776 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1778 /* perform debug configuration when chip is out of reset */
1779 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1781 /* PF Init sequence */
1782 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1786 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1787 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1791 /* Pure runtime initializations - directly to the HW */
1792 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1794 /* PCI relaxed ordering causes a decrease in the performance on some
1795 * systems. Till a root cause is found, disable this attribute in the
1799 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1801 * DP_NOTICE(p_hwfn, true,
1802 * "Failed to find the PCIe Cap\n");
1805 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1806 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1807 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1810 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1814 /* enable interrupts */
1815 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1816 if (rc != ECORE_SUCCESS)
1819 /* send function start command */
1820 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1821 allow_npar_tx_switch);
1823 DP_NOTICE(p_hwfn, true,
1824 "Function start ramrod failed\n");
1826 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1827 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1828 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1830 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1831 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1833 ecore_wr(p_hwfn, p_ptt,
1834 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1837 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1838 "PRS_REG_SEARCH registers after start PFn\n");
1839 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1840 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1841 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1842 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1843 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1844 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1845 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1846 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1847 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1848 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1849 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1850 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1851 prs_reg = ecore_rd(p_hwfn, p_ptt,
1852 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1853 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1854 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1856 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1857 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1858 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1864 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
1865 struct ecore_ptt *p_ptt,
1868 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
1870 /* Configure the PF's internal FID_enable for master transactions */
1871 ecore_wr(p_hwfn, p_ptt,
1872 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1874 /* Wait until value is set - try for 1 second every 50us */
1875 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1876 val = ecore_rd(p_hwfn, p_ptt,
1877 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1884 if (val != set_val) {
1885 DP_NOTICE(p_hwfn, true,
1886 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1887 return ECORE_UNKNOWN_ERROR;
1890 return ECORE_SUCCESS;
1893 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1894 struct ecore_ptt *p_main_ptt)
1896 /* Read shadow of current MFW mailbox */
1897 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1898 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1899 p_hwfn->mcp_info->mfw_mb_cur,
1900 p_hwfn->mcp_info->mfw_mb_length);
1903 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1904 struct ecore_hw_init_params *p_params)
1906 if (p_params->p_tunn) {
1907 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1908 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1911 p_hwfn->b_int_enabled = 1;
1913 return ECORE_SUCCESS;
1916 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
1917 struct ecore_ptt *p_ptt)
1919 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
1920 1 << p_hwfn->abs_pf_id);
1923 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1924 struct ecore_hw_init_params *p_params)
1926 struct ecore_load_req_params load_req_params;
1927 u32 load_code, resp, param, drv_mb_param;
1928 bool b_default_mtu = true;
1929 struct ecore_hwfn *p_hwfn;
1930 enum _ecore_status_t rc = ECORE_SUCCESS;
1933 if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1934 (p_dev->num_hwfns > 1)) {
1935 DP_NOTICE(p_dev, false,
1936 "MSI mode is not supported for CMT devices\n");
1941 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1942 if (rc != ECORE_SUCCESS)
1946 for_each_hwfn(p_dev, i) {
1947 p_hwfn = &p_dev->hwfns[i];
1949 /* If management didn't provide a default, set one of our own */
1950 if (!p_hwfn->hw_info.mtu) {
1951 p_hwfn->hw_info.mtu = 1500;
1952 b_default_mtu = false;
1956 ecore_vf_start(p_hwfn, p_params);
1960 rc = ecore_calc_hw_mode(p_hwfn);
1961 if (rc != ECORE_SUCCESS)
1964 OSAL_MEM_ZERO(&load_req_params, sizeof(load_req_params));
1965 load_req_params.drv_role = p_params->is_crash_kernel ?
1966 ECORE_DRV_ROLE_KDUMP :
1968 load_req_params.timeout_val = p_params->mfw_timeout_val;
1969 load_req_params.avoid_eng_reset = p_params->avoid_eng_reset;
1970 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1972 if (rc != ECORE_SUCCESS) {
1973 DP_NOTICE(p_hwfn, true,
1974 "Failed sending a LOAD_REQ command\n");
1978 load_code = load_req_params.load_code;
1979 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1980 "Load request was sent. Load code: 0x%x\n",
1984 * When coming back from hiberbate state, the registers from
1985 * which shadow is read initially are not initialized. It turns
1986 * out that these registers get initialized during the call to
1987 * ecore_mcp_load_req request. So we need to reread them here
1988 * to get the proper shadow register value.
1989 * Note: This is a workaround for the missing MFW
1990 * initialization. It may be removed once the implementation
1993 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1995 /* Only relevant for recovery:
1996 * Clear the indication after the LOAD_REQ command is responded
1999 p_dev->recov_in_prog = false;
2001 p_hwfn->first_on_engine = (load_code ==
2002 FW_MSG_CODE_DRV_LOAD_ENGINE);
2004 if (!qm_lock_init) {
2005 OSAL_SPIN_LOCK_INIT(&qm_lock);
2006 qm_lock_init = true;
2009 /* Clean up chip from previous driver if such remains exist.
2010 * This is not needed when the PF is the first one on the
2011 * engine, since afterwards we are going to init the FW.
2013 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2014 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2015 p_hwfn->rel_pf_id, false);
2016 if (rc != ECORE_SUCCESS) {
2017 ecore_hw_err_notify(p_hwfn,
2018 ECORE_HW_ERR_RAMROD_FAIL);
2023 /* Log and clean previous pglue_b errors if such exist */
2024 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2025 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2027 /* Enable the PF's internal FID_enable in the PXP */
2028 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2030 if (rc != ECORE_SUCCESS)
2033 switch (load_code) {
2034 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2035 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2036 p_hwfn->hw_info.hw_mode);
2037 if (rc != ECORE_SUCCESS)
2040 case FW_MSG_CODE_DRV_LOAD_PORT:
2041 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2042 p_hwfn->hw_info.hw_mode);
2043 if (rc != ECORE_SUCCESS)
2046 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2047 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2049 p_hwfn->hw_info.hw_mode,
2050 p_params->b_hw_start,
2052 p_params->allow_npar_tx_switch);
2055 DP_NOTICE(p_hwfn, false,
2056 "Unexpected load code [0x%08x]", load_code);
2061 if (rc != ECORE_SUCCESS) {
2062 DP_NOTICE(p_hwfn, true,
2063 "init phase failed for loadcode 0x%x (rc %d)\n",
2068 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2069 if (rc != ECORE_SUCCESS)
2072 /* send DCBX attention request command */
2073 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2074 "sending phony dcbx set command to trigger DCBx attention handling\n");
2075 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2076 DRV_MSG_CODE_SET_DCBX,
2077 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, &resp,
2079 if (rc != ECORE_SUCCESS) {
2080 DP_NOTICE(p_hwfn, true,
2081 "Failed to send DCBX attention request\n");
2085 p_hwfn->hw_init_done = true;
2089 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2090 drv_mb_param = STORM_FW_VERSION;
2091 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2092 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2093 drv_mb_param, &resp, ¶m);
2094 if (rc != ECORE_SUCCESS)
2095 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2098 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2099 p_hwfn->hw_info.mtu);
2100 if (rc != ECORE_SUCCESS)
2101 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2103 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2105 ECORE_OV_DRIVER_STATE_DISABLED);
2106 if (rc != ECORE_SUCCESS)
2107 DP_INFO(p_hwfn, "Failed to update driver state\n");
2113 /* The MFW load lock should be released regardless of success or failure
2114 * of initialization.
2115 * TODO: replace this with an attempt to send cancel_load.
2117 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2121 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2122 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2123 struct ecore_hwfn *p_hwfn,
2124 struct ecore_ptt *p_ptt)
2129 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2130 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2131 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2133 if ((!ecore_rd(p_hwfn, p_ptt,
2134 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2135 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2138 /* Dependent on number of connection/tasks, possibly
2139 * 1ms sleep is required between polls
2144 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2147 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2148 " [Connection %02x Tasks %02x]\n",
2149 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2150 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2153 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2157 for_each_hwfn(p_dev, j) {
2158 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2159 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2161 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2165 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2166 struct ecore_ptt *p_ptt,
2167 u32 addr, u32 expected_val)
2169 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2171 if (val != expected_val) {
2172 DP_NOTICE(p_hwfn, true,
2173 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2174 addr, val, expected_val);
2175 return ECORE_UNKNOWN_ERROR;
2178 return ECORE_SUCCESS;
2181 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2183 struct ecore_hwfn *p_hwfn;
2184 struct ecore_ptt *p_ptt;
2185 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2188 for_each_hwfn(p_dev, j) {
2189 p_hwfn = &p_dev->hwfns[j];
2190 p_ptt = p_hwfn->p_main_ptt;
2192 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2195 ecore_vf_pf_int_cleanup(p_hwfn);
2196 rc = ecore_vf_pf_reset(p_hwfn);
2197 if (rc != ECORE_SUCCESS) {
2198 DP_NOTICE(p_hwfn, true,
2199 "ecore_vf_pf_reset failed. rc = %d.\n",
2201 rc2 = ECORE_UNKNOWN_ERROR;
2206 /* mark the hw as uninitialized... */
2207 p_hwfn->hw_init_done = false;
2209 /* Send unload command to MCP */
2210 if (!p_dev->recov_in_prog) {
2211 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2212 if (rc != ECORE_SUCCESS) {
2213 DP_NOTICE(p_hwfn, true,
2214 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2216 rc2 = ECORE_UNKNOWN_ERROR;
2220 OSAL_DPC_SYNC(p_hwfn);
2222 /* After this point no MFW attentions are expected, e.g. prevent
2223 * race between pf stop and dcbx pf update.
2226 rc = ecore_sp_pf_stop(p_hwfn);
2227 if (rc != ECORE_SUCCESS) {
2228 DP_NOTICE(p_hwfn, true,
2229 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2231 rc2 = ECORE_UNKNOWN_ERROR;
2234 /* perform debug action after PF stop was sent */
2235 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2237 /* close NIG to BRB gate */
2238 ecore_wr(p_hwfn, p_ptt,
2239 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2242 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2243 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2244 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2245 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2246 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2248 /* @@@TBD - clean transmission queues (5.b) */
2249 /* @@@TBD - clean BTB (5.c) */
2251 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2253 /* @@@TBD - verify DMAE requests are done (8) */
2255 /* Disable Attention Generation */
2256 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2257 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2258 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2259 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2260 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2261 if (rc != ECORE_SUCCESS) {
2262 DP_NOTICE(p_hwfn, true,
2263 "Failed to return IGU CAM to default\n");
2264 rc2 = ECORE_UNKNOWN_ERROR;
2267 /* Need to wait 1ms to guarantee SBs are cleared */
2270 if (!p_dev->recov_in_prog) {
2271 ecore_verify_reg_val(p_hwfn, p_ptt,
2272 QM_REG_USG_CNT_PF_TX, 0);
2273 ecore_verify_reg_val(p_hwfn, p_ptt,
2274 QM_REG_USG_CNT_PF_OTHER, 0);
2275 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2278 /* Disable PF in HW blocks */
2279 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2280 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2282 if (!p_dev->recov_in_prog) {
2283 ecore_mcp_unload_done(p_hwfn, p_ptt);
2284 if (rc != ECORE_SUCCESS) {
2285 DP_NOTICE(p_hwfn, true,
2286 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2288 rc2 = ECORE_UNKNOWN_ERROR;
2293 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2294 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2295 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2297 /* Clear the PF's internal FID_enable in the PXP.
2298 * In CMT this should only be done for first hw-function, and
2299 * only after all transactions have stopped for all active
2302 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2304 if (rc != ECORE_SUCCESS) {
2305 DP_NOTICE(p_hwfn, true,
2306 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2308 rc2 = ECORE_UNKNOWN_ERROR;
2315 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2319 for_each_hwfn(p_dev, j) {
2320 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2321 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2324 ecore_vf_pf_int_cleanup(p_hwfn);
2328 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2329 "Shutting down the fastpath\n");
2331 ecore_wr(p_hwfn, p_ptt,
2332 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2334 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2335 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2336 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2337 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2338 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2340 /* @@@TBD - clean transmission queues (5.b) */
2341 /* @@@TBD - clean BTB (5.c) */
2343 /* @@@TBD - verify DMAE requests are done (8) */
2345 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2346 /* Need to wait 1ms to guarantee SBs are cleared */
2351 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2353 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2355 if (IS_VF(p_hwfn->p_dev))
2358 /* If roce info is allocated it means roce is initialized and should
2359 * be enabled in searcher.
2361 if (p_hwfn->p_rdma_info) {
2362 if (p_hwfn->b_rdma_enabled_in_prs)
2363 ecore_wr(p_hwfn, p_ptt,
2364 p_hwfn->rdma_prs_search_reg, 0x1);
2365 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2368 /* Re-open incoming traffic */
2369 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2370 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2373 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2374 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2376 ecore_ptt_pool_free(p_hwfn);
2377 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2380 /* Setup bar access */
2381 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2383 /* clear indirect access */
2384 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2385 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2386 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2387 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2388 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2389 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2390 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2391 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2392 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2394 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2395 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2396 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2397 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2398 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2399 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2400 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2401 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2404 /* Clean previous pglue_b errors if such exist */
2405 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2407 /* enable internal target-read */
2408 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2409 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2412 static void get_function_id(struct ecore_hwfn *p_hwfn)
2415 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2416 PXP_PF_ME_OPAQUE_ADDR);
2418 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2420 /* Bits 16-19 from the ME registers are the pf_num */
2421 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2422 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2423 PXP_CONCRETE_FID_PFID);
2424 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2425 PXP_CONCRETE_FID_PORT);
2427 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2428 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2429 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2432 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2434 u32 *feat_num = p_hwfn->hw_info.feat_num;
2435 struct ecore_sb_cnt_info sb_cnt;
2438 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2439 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2441 /* L2 Queues require each: 1 status block. 1 L2 queue */
2442 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2443 /* Start by allocating VF queues, then PF's */
2444 feat_num[ECORE_VF_L2_QUE] =
2446 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2448 feat_num[ECORE_PF_L2_QUE] =
2450 sb_cnt.cnt - non_l2_sbs,
2451 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2452 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2455 feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2458 feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2462 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2463 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2464 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2465 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2466 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2467 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2468 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2472 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2475 case ECORE_L2_QUEUE:
2489 case ECORE_RDMA_CNQ_RAM:
2490 return "RDMA_CNQ_RAM";
2493 case ECORE_LL2_QUEUE:
2495 case ECORE_CMDQS_CQS:
2497 case ECORE_RDMA_STATS_QUEUE:
2498 return "RDMA_STATS_QUEUE";
2504 return "UNKNOWN_RESOURCE";
2508 static enum _ecore_status_t
2509 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2510 enum ecore_resources res_id, u32 resc_max_val,
2513 enum _ecore_status_t rc;
2515 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_hwfn->p_main_ptt, res_id,
2516 resc_max_val, p_mcp_resp);
2517 if (rc != ECORE_SUCCESS) {
2518 DP_NOTICE(p_hwfn, true,
2519 "MFW response failure for a max value setting of resource %d [%s]\n",
2520 res_id, ecore_hw_get_resc_name(res_id));
2524 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2526 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2527 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2529 return ECORE_SUCCESS;
2532 static enum _ecore_status_t
2533 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn)
2535 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2536 u32 resc_max_val, mcp_resp;
2538 enum _ecore_status_t rc;
2540 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2543 case ECORE_LL2_QUEUE:
2544 case ECORE_RDMA_CNQ_RAM:
2545 case ECORE_RDMA_STATS_QUEUE:
2553 rc = __ecore_hw_set_soft_resc_size(p_hwfn, res_id,
2554 resc_max_val, &mcp_resp);
2555 if (rc != ECORE_SUCCESS)
2558 /* There's no point to continue to the next resource if the
2559 * command is not supported by the MFW.
2560 * We do continue if the command is supported but the resource
2561 * is unknown to the MFW. Such a resource will be later
2562 * configured with the default allocation values.
2564 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2565 return ECORE_NOTIMPL;
2568 return ECORE_SUCCESS;
2572 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2573 enum ecore_resources res_id,
2574 u32 *p_resc_num, u32 *p_resc_start)
2576 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2577 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2580 case ECORE_L2_QUEUE:
2581 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2582 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2585 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2586 MAX_NUM_VPORTS_BB) / num_funcs;
2589 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2590 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2593 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2594 MAX_QM_TX_QUEUES_BB) / num_funcs;
2597 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2601 /* Each VFC resource can accommodate both a MAC and a VLAN */
2602 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2605 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2606 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2608 case ECORE_LL2_QUEUE:
2609 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2611 case ECORE_RDMA_CNQ_RAM:
2612 case ECORE_CMDQS_CQS:
2613 /* CNQ/CMDQS are the same resource */
2615 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2617 case ECORE_RDMA_STATS_QUEUE:
2619 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2620 MAX_NUM_VPORTS_BB) / num_funcs;
2637 /* Since we want its value to reflect whether MFW supports
2638 * the new scheme, have a default of 0.
2643 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2647 return ECORE_SUCCESS;
2650 static enum _ecore_status_t
2651 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
2652 bool drv_resc_alloc)
2654 u32 dflt_resc_num = 0, dflt_resc_start = 0;
2655 u32 mcp_resp, *p_resc_num, *p_resc_start;
2656 enum _ecore_status_t rc;
2658 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2659 p_resc_start = &RESC_START(p_hwfn, res_id);
2661 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2663 if (rc != ECORE_SUCCESS) {
2665 "Failed to get default amount for resource %d [%s]\n",
2666 res_id, ecore_hw_get_resc_name(res_id));
2671 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2672 *p_resc_num = dflt_resc_num;
2673 *p_resc_start = dflt_resc_start;
2678 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2679 &mcp_resp, p_resc_num, p_resc_start);
2680 if (rc != ECORE_SUCCESS) {
2681 DP_NOTICE(p_hwfn, true,
2682 "MFW response failure for an allocation request for"
2683 " resource %d [%s]\n",
2684 res_id, ecore_hw_get_resc_name(res_id));
2688 /* Default driver values are applied in the following cases:
2689 * - The resource allocation MB command is not supported by the MFW
2690 * - There is an internal error in the MFW while processing the request
2691 * - The resource ID is unknown to the MFW
2693 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2695 "Failed to receive allocation info for resource %d [%s]."
2696 " mcp_resp = 0x%x. Applying default values"
2698 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2699 dflt_resc_num, dflt_resc_start);
2701 *p_resc_num = dflt_resc_num;
2702 *p_resc_start = dflt_resc_start;
2706 if ((*p_resc_num != dflt_resc_num ||
2707 *p_resc_start != dflt_resc_start) &&
2708 res_id != ECORE_SB) {
2710 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
2711 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2712 *p_resc_start, dflt_resc_num, dflt_resc_start,
2713 drv_resc_alloc ? " - Applying default values" : "");
2714 if (drv_resc_alloc) {
2715 *p_resc_num = dflt_resc_num;
2716 *p_resc_start = dflt_resc_start;
2720 return ECORE_SUCCESS;
2723 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2724 bool drv_resc_alloc)
2726 enum _ecore_status_t rc;
2729 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2730 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2731 if (rc != ECORE_SUCCESS)
2735 return ECORE_SUCCESS;
2738 #define ECORE_RESC_ALLOC_LOCK_RETRY_CNT 10
2739 #define ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US 10000 /* 10 msec */
2741 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2742 bool drv_resc_alloc)
2744 struct ecore_resc_unlock_params resc_unlock_params;
2745 struct ecore_resc_lock_params resc_lock_params;
2746 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2748 enum _ecore_status_t rc;
2750 u32 *resc_start = p_hwfn->hw_info.resc_start;
2751 u32 *resc_num = p_hwfn->hw_info.resc_num;
2752 /* For AH, an equal share of the ILT lines between the maximal number of
2753 * PFs is not enough for RoCE. This would be solved by the future
2754 * resource allocation scheme, but isn't currently present for
2755 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2756 * to work - the BB number of ILT lines divided by its max PFs number.
2758 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2761 /* Setting the max values of the soft resources and the following
2762 * resources allocation queries should be atomic. Since several PFs can
2763 * run in parallel - a resource lock is needed.
2764 * If either the resource lock or resource set value commands are not
2765 * supported - skip the the max values setting, release the lock if
2766 * needed, and proceed to the queries. Other failures, including a
2767 * failure to acquire the lock, will cause this function to fail.
2768 * Old drivers that don't acquire the lock can run in parallel, and
2769 * their allocation values won't be affected by the updated max values.
2771 OSAL_MEM_ZERO(&resc_lock_params, sizeof(resc_lock_params));
2772 resc_lock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2773 resc_lock_params.retry_num = ECORE_RESC_ALLOC_LOCK_RETRY_CNT;
2774 resc_lock_params.retry_interval = ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2775 resc_lock_params.sleep_b4_retry = true;
2776 OSAL_MEM_ZERO(&resc_unlock_params, sizeof(resc_unlock_params));
2777 resc_unlock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2779 rc = ecore_mcp_resc_lock(p_hwfn, p_hwfn->p_main_ptt, &resc_lock_params);
2780 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2782 } else if (rc == ECORE_NOTIMPL) {
2784 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2785 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
2786 DP_NOTICE(p_hwfn, false,
2787 "Failed to acquire the resource lock for the resource allocation commands\n");
2789 goto unlock_and_exit;
2791 rc = ecore_hw_set_soft_resc_size(p_hwfn);
2792 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2793 DP_NOTICE(p_hwfn, false,
2794 "Failed to set the max values of the soft resources\n");
2795 goto unlock_and_exit;
2796 } else if (rc == ECORE_NOTIMPL) {
2798 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2799 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2800 &resc_unlock_params);
2801 if (rc != ECORE_SUCCESS)
2803 "Failed to release the resource lock for the resource allocation commands\n");
2807 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
2808 if (rc != ECORE_SUCCESS)
2809 goto unlock_and_exit;
2811 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2812 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2813 &resc_unlock_params);
2814 if (rc != ECORE_SUCCESS)
2816 "Failed to release the resource lock for the resource allocation commands\n");
2820 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2821 /* Reduced build contains less PQs */
2822 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2823 resc_num[ECORE_PQ] = 32;
2824 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2825 p_hwfn->enabled_func_idx;
2828 /* For AH emulation, since we have a possible maximal number of
2829 * 16 enabled PFs, in case there are not enough ILT lines -
2830 * allocate only first PF as RoCE and have all the other ETH
2831 * only with less ILT lines.
2833 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2834 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2835 resc_num[ECORE_ILT],
2836 roce_min_ilt_lines);
2839 /* Correct the common ILT calculation if PF0 has more */
2840 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2841 p_hwfn->p_dev->b_is_emul_full &&
2842 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2843 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2844 resc_num[ECORE_ILT];
2847 /* Sanity for ILT */
2848 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2849 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2850 DP_NOTICE(p_hwfn, true,
2851 "Can't assign ILT pages [%08x,...,%08x]\n",
2852 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2858 /* This will also learn the number of SBs from MFW */
2859 if (ecore_int_igu_reset_cam(p_hwfn, p_hwfn->p_main_ptt))
2862 ecore_hw_set_feat(p_hwfn);
2864 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2865 "The numbers for each resource are:\n");
2866 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2867 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2868 ecore_hw_get_resc_name(res_id),
2869 RESC_NUM(p_hwfn, res_id),
2870 RESC_START(p_hwfn, res_id));
2872 return ECORE_SUCCESS;
2875 ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt, &resc_unlock_params);
2879 static enum _ecore_status_t
2880 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2881 struct ecore_ptt *p_ptt,
2882 struct ecore_hw_prepare_params *p_params)
2884 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2885 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2886 struct ecore_mcp_link_params *link;
2887 enum _ecore_status_t rc;
2889 /* Read global nvm_cfg address */
2890 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2892 /* Verify MCP has initialized it */
2893 if (!nvm_cfg_addr) {
2894 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2895 if (p_params->b_relaxed_probe)
2896 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2900 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2902 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2904 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2905 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2908 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2910 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2911 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2912 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2913 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2915 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2916 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2918 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2919 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2921 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2922 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2924 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2925 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2927 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2928 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2930 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2931 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2933 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2934 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2936 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2937 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2939 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2940 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2942 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2943 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2946 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2951 /* Read DCBX configuration */
2952 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2953 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2954 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2956 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2957 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2958 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2959 switch (dcbx_mode) {
2960 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2961 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2963 case NVM_CFG1_PORT_DCBX_MODE_CEE:
2964 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2966 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2967 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2970 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2973 /* Read default link configuration */
2974 link = &p_hwfn->mcp_info->link_input;
2975 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2976 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2977 link_temp = ecore_rd(p_hwfn, p_ptt,
2979 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2980 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2981 link->speed.advertised_speeds = link_temp;
2983 link_temp = link->speed.advertised_speeds;
2984 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2986 link_temp = ecore_rd(p_hwfn, p_ptt,
2988 OFFSETOF(struct nvm_cfg1_port, link_settings));
2989 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2990 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2991 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2992 link->speed.autoneg = true;
2994 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2995 link->speed.forced_speed = 1000;
2997 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2998 link->speed.forced_speed = 10000;
3000 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3001 link->speed.forced_speed = 25000;
3003 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3004 link->speed.forced_speed = 40000;
3006 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3007 link->speed.forced_speed = 50000;
3009 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3010 link->speed.forced_speed = 100000;
3013 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3016 p_hwfn->mcp_info->link_capabilities.default_speed =
3017 link->speed.forced_speed;
3018 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
3019 link->speed.autoneg;
3021 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3022 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3023 link->pause.autoneg = !!(link_temp &
3024 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3025 link->pause.forced_rx = !!(link_temp &
3026 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3027 link->pause.forced_tx = !!(link_temp &
3028 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3029 link->loopback_mode = 0;
3031 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3032 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
3033 link->speed.forced_speed, link->speed.advertised_speeds,
3034 link->speed.autoneg, link->pause.autoneg);
3036 /* Read Multi-function information from shmem */
3037 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3038 OFFSETOF(struct nvm_cfg1, glob) +
3039 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3041 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3043 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3044 NVM_CFG1_GLOB_MF_MODE_OFFSET;
3047 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3048 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3050 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3051 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3053 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3054 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3057 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3058 p_hwfn->p_dev->mf_mode);
3060 /* Read Multi-function information from shmem */
3061 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3062 OFFSETOF(struct nvm_cfg1, glob) +
3063 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3065 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3066 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3067 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3068 &p_hwfn->hw_info.device_capabilities);
3069 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3070 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3071 &p_hwfn->hw_info.device_capabilities);
3072 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3073 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3074 &p_hwfn->hw_info.device_capabilities);
3075 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3076 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3077 &p_hwfn->hw_info.device_capabilities);
3078 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3079 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3080 &p_hwfn->hw_info.device_capabilities);
3082 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3083 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3085 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3091 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3092 struct ecore_ptt *p_ptt)
3094 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3095 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3096 struct ecore_dev *p_dev = p_hwfn->p_dev;
3098 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3100 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3101 * in the other bits are selected.
3102 * Bits 1-15 are for functions 1-15, respectively, and their value is
3103 * '0' only for enabled functions (function 0 always exists and
3105 * In case of CMT in BB, only the "even" functions are enabled, and thus
3106 * the number of functions for both hwfns is learnt from the same bits.
3108 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3109 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3110 MISCS_REG_FUNCTION_HIDE_BB_K2);
3112 reg_function_hide = 0;
3115 if (reg_function_hide & 0x1) {
3116 if (ECORE_IS_BB(p_dev)) {
3117 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3129 /* Get the number of the enabled functions on the engine */
3130 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3137 /* Get the PF index within the enabled functions */
3138 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3139 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3147 p_hwfn->num_funcs_on_engine = num_funcs;
3148 p_hwfn->enabled_func_idx = enabled_func_idx;
3151 if (CHIP_REV_IS_FPGA(p_dev)) {
3152 DP_NOTICE(p_hwfn, false,
3153 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3154 p_hwfn->num_funcs_on_engine = 4;
3158 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3159 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3160 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3161 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3164 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3165 struct ecore_ptt *p_ptt)
3170 /* Read the port mode */
3171 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3173 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3174 (p_hwfn->p_dev->num_hwfns > 1))
3175 /* In CMT on emulation, assume 1 port */
3179 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3181 if (port_mode < 3) {
3182 p_hwfn->p_dev->num_ports_in_engines = 1;
3183 } else if (port_mode <= 5) {
3184 p_hwfn->p_dev->num_ports_in_engines = 2;
3186 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3187 p_hwfn->p_dev->num_ports_in_engines);
3189 /* Default num_ports_in_engines to something */
3190 p_hwfn->p_dev->num_ports_in_engines = 1;
3194 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3195 struct ecore_ptt *p_ptt)
3200 p_hwfn->p_dev->num_ports_in_engines = 0;
3203 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3204 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3205 switch ((port & 0xf000) >> 12) {
3207 p_hwfn->p_dev->num_ports_in_engines = 1;
3210 p_hwfn->p_dev->num_ports_in_engines = 2;
3213 p_hwfn->p_dev->num_ports_in_engines = 4;
3216 DP_NOTICE(p_hwfn, false,
3217 "Unknown port mode in ECO_RESERVED %08x\n",
3222 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3223 port = ecore_rd(p_hwfn, p_ptt,
3224 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3227 p_hwfn->p_dev->num_ports_in_engines++;
3231 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3232 struct ecore_ptt *p_ptt)
3234 if (ECORE_IS_BB(p_hwfn->p_dev))
3235 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3237 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3240 static enum _ecore_status_t
3241 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3242 enum ecore_pci_personality personality,
3243 struct ecore_hw_prepare_params *p_params)
3245 bool drv_resc_alloc = p_params->drv_resc_alloc;
3246 enum _ecore_status_t rc;
3248 /* Since all information is common, only first hwfns should do this */
3249 if (IS_LEAD_HWFN(p_hwfn)) {
3250 rc = ecore_iov_hw_info(p_hwfn);
3251 if (rc != ECORE_SUCCESS) {
3252 if (p_params->b_relaxed_probe)
3253 p_params->p_relaxed_res =
3254 ECORE_HW_PREPARE_BAD_IOV;
3260 /* TODO In get_hw_info, amoungst others:
3261 * Get MCP FW revision and determine according to it the supported
3262 * featrues (e.g. DCB)
3264 * ecore_get_pcie_width_speed, WOL capability.
3265 * Number of global CQ-s (for storage
3267 ecore_hw_info_port_num(p_hwfn, p_ptt);
3270 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3272 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3273 if (rc != ECORE_SUCCESS)
3279 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3280 if (rc != ECORE_SUCCESS) {
3281 if (p_params->b_relaxed_probe)
3282 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3288 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3290 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3291 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3294 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3296 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3297 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3301 if (ecore_mcp_is_init(p_hwfn)) {
3302 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3303 p_hwfn->hw_info.ovlan =
3304 p_hwfn->mcp_info->func_info.ovlan;
3306 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3309 if (personality != ECORE_PCI_DEFAULT) {
3310 p_hwfn->hw_info.personality = personality;
3311 } else if (ecore_mcp_is_init(p_hwfn)) {
3312 enum ecore_pci_personality protocol;
3314 protocol = p_hwfn->mcp_info->func_info.protocol;
3315 p_hwfn->hw_info.personality = protocol;
3319 /* To overcome ILT lack for emulation, until at least until we'll have
3320 * a definite answer from system about it, allow only PF0 to be RoCE.
3322 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3323 if (!p_hwfn->rel_pf_id)
3324 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3326 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3330 /* although in BB some constellations may support more than 4 tcs,
3331 * that can result in performance penalty in some cases. 4
3332 * represents a good tradeoff between performance and flexibility.
3334 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3336 /* start out with a single active tc. This can be increased either
3337 * by dcbx negotiation or by upper layer driver
3339 p_hwfn->hw_info.num_active_tc = 1;
3341 ecore_get_num_funcs(p_hwfn, p_ptt);
3343 if (ecore_mcp_is_init(p_hwfn))
3344 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3346 /* In case of forcing the driver's default resource allocation, calling
3347 * ecore_hw_get_resc() should come after initializing the personality
3348 * and after getting the number of functions, since the calculation of
3349 * the resources/features depends on them.
3350 * This order is not harmful if not forcing.
3352 rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3353 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3355 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3361 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3363 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3367 /* Read Vendor Id / Device Id */
3368 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3370 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3373 /* Determine type */
3374 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3375 switch (device_id_mask) {
3376 case ECORE_DEV_ID_MASK_BB:
3377 p_dev->type = ECORE_DEV_TYPE_BB;
3379 case ECORE_DEV_ID_MASK_AH:
3380 p_dev->type = ECORE_DEV_TYPE_AH;
3383 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3385 return ECORE_ABORTED;
3388 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3389 MISCS_REG_CHIP_NUM);
3390 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3391 MISCS_REG_CHIP_REV);
3393 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3395 /* Learn number of HW-functions */
3396 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3397 MISCS_REG_CMT_ENABLED_FOR_PAIR);
3399 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3400 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3401 p_dev->num_hwfns = 2;
3403 p_dev->num_hwfns = 1;
3407 if (CHIP_REV_IS_EMUL(p_dev)) {
3408 /* For some reason we have problems with this register
3409 * in B0 emulation; Simply assume no CMT
3411 DP_NOTICE(p_dev->hwfns, false,
3412 "device on emul - assume no CMT\n");
3413 p_dev->num_hwfns = 1;
3417 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3418 MISCS_REG_CHIP_TEST_REG) >> 4;
3419 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3420 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3421 MISCS_REG_CHIP_METAL);
3422 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3423 DP_INFO(p_dev->hwfns,
3424 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3425 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3426 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3427 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3430 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3431 DP_NOTICE(p_dev->hwfns, false,
3432 "The chip type/rev (BB A0) is not supported!\n");
3433 return ECORE_ABORTED;
3436 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3437 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3438 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3440 if (CHIP_REV_IS_EMUL(p_dev)) {
3441 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3442 MISCS_REG_ECO_RESERVED);
3443 if (tmp & (1 << 29)) {
3444 DP_NOTICE(p_hwfn, false,
3445 "Emulation: Running on a FULL build\n");
3446 p_dev->b_is_emul_full = true;
3448 DP_NOTICE(p_hwfn, false,
3449 "Emulation: Running on a REDUCED build\n");
3454 return ECORE_SUCCESS;
3457 #ifndef LINUX_REMOVE
3458 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3465 for_each_hwfn(p_dev, j) {
3466 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3468 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3469 "Mark hw/fw uninitialized\n");
3471 p_hwfn->hw_init_done = false;
3472 p_hwfn->first_on_engine = false;
3474 ecore_ptt_invalidate(p_hwfn);
3479 static enum _ecore_status_t
3480 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3481 void OSAL_IOMEM * p_regview,
3482 void OSAL_IOMEM * p_doorbells,
3483 struct ecore_hw_prepare_params *p_params)
3485 struct ecore_dev *p_dev = p_hwfn->p_dev;
3486 struct ecore_mdump_info mdump_info;
3487 enum _ecore_status_t rc = ECORE_SUCCESS;
3489 /* Split PCI bars evenly between hwfns */
3490 p_hwfn->regview = p_regview;
3491 p_hwfn->doorbells = p_doorbells;
3494 return ecore_vf_hw_prepare(p_hwfn);
3496 /* Validate that chip access is feasible */
3497 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3499 "Reading the ME register returns all Fs; Preventing further chip access\n");
3500 if (p_params->b_relaxed_probe)
3501 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3505 get_function_id(p_hwfn);
3507 /* Allocate PTT pool */
3508 rc = ecore_ptt_pool_alloc(p_hwfn);
3510 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3511 if (p_params->b_relaxed_probe)
3512 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3516 /* Allocate the main PTT */
3517 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3519 /* First hwfn learns basic information, e.g., number of hwfns */
3520 if (!p_hwfn->my_id) {
3521 rc = ecore_get_dev_info(p_dev);
3522 if (rc != ECORE_SUCCESS) {
3523 if (p_params->b_relaxed_probe)
3524 p_params->p_relaxed_res =
3525 ECORE_HW_PREPARE_FAILED_DEV;
3530 ecore_hw_hwfn_prepare(p_hwfn);
3532 /* Initialize MCP structure */
3533 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3535 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3536 if (p_params->b_relaxed_probe)
3537 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3541 /* Read the device configuration information from the HW and SHMEM */
3542 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3543 p_params->personality, p_params);
3545 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3549 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3550 * called, since among others it sets the ports number in an engine.
3552 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3553 !p_dev->recov_in_prog) {
3554 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3555 if (rc != ECORE_SUCCESS)
3556 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3559 /* Check if mdump logs are present and update the epoch value */
3560 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3561 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3563 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3564 DP_NOTICE(p_hwfn, false,
3565 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3568 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3572 /* Allocate the init RT array and initialize the init-ops engine */
3573 rc = ecore_init_alloc(p_hwfn);
3575 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3576 if (p_params->b_relaxed_probe)
3577 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3581 if (CHIP_REV_IS_FPGA(p_dev)) {
3582 DP_NOTICE(p_hwfn, false,
3583 "FPGA: workaround; Prevent DMAE parities\n");
3584 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3587 DP_NOTICE(p_hwfn, false,
3588 "FPGA: workaround: Set VF bar0 size\n");
3589 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3590 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3596 if (IS_LEAD_HWFN(p_hwfn))
3597 ecore_iov_free_hw_info(p_dev);
3598 ecore_mcp_free(p_hwfn);
3600 ecore_hw_hwfn_free(p_hwfn);
3605 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3606 struct ecore_hw_prepare_params *p_params)
3608 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3609 enum _ecore_status_t rc;
3611 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3612 p_dev->allow_mdump = p_params->allow_mdump;
3614 if (p_params->b_relaxed_probe)
3615 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3617 /* Store the precompiled init data ptrs */
3619 ecore_init_iro_array(p_dev);
3621 /* Initialize the first hwfn - will learn number of hwfns */
3622 rc = ecore_hw_prepare_single(p_hwfn,
3624 p_dev->doorbells, p_params);
3625 if (rc != ECORE_SUCCESS)
3628 p_params->personality = p_hwfn->hw_info.personality;
3630 /* initilalize 2nd hwfn if necessary */
3631 if (p_dev->num_hwfns > 1) {
3632 void OSAL_IOMEM *p_regview, *p_doorbell;
3633 u8 OSAL_IOMEM *addr;
3635 /* adjust bar offset for second engine */
3636 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3637 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3638 p_regview = (void OSAL_IOMEM *)addr;
3640 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3641 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3642 p_doorbell = (void OSAL_IOMEM *)addr;
3644 /* prepare second hw function */
3645 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3646 p_doorbell, p_params);
3648 /* in case of error, need to free the previously
3649 * initiliazed hwfn 0.
3651 if (rc != ECORE_SUCCESS) {
3652 if (p_params->b_relaxed_probe)
3653 p_params->p_relaxed_res =
3654 ECORE_HW_PREPARE_FAILED_ENG2;
3657 ecore_init_free(p_hwfn);
3658 ecore_mcp_free(p_hwfn);
3659 ecore_hw_hwfn_free(p_hwfn);
3661 DP_NOTICE(p_dev, true,
3662 "What do we need to free when VF hwfn1 init fails\n");
3671 void ecore_hw_remove(struct ecore_dev *p_dev)
3673 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3677 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3678 ECORE_OV_DRIVER_STATE_NOT_LOADED);
3680 for_each_hwfn(p_dev, i) {
3681 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3684 ecore_vf_pf_release(p_hwfn);
3688 ecore_init_free(p_hwfn);
3689 ecore_hw_hwfn_free(p_hwfn);
3690 ecore_mcp_free(p_hwfn);
3692 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3695 ecore_iov_free_hw_info(p_dev);
3698 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3699 struct ecore_chain *p_chain)
3701 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3702 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3703 struct ecore_chain_next *p_next;
3709 size = p_chain->elem_size * p_chain->usable_per_page;
3711 for (i = 0; i < p_chain->page_cnt; i++) {
3715 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3716 p_virt_next = p_next->next_virt;
3717 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3719 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3720 ECORE_CHAIN_PAGE_SIZE);
3722 p_virt = p_virt_next;
3723 p_phys = p_phys_next;
3727 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3728 struct ecore_chain *p_chain)
3730 if (!p_chain->p_virt_addr)
3733 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3734 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3737 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3738 struct ecore_chain *p_chain)
3740 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3741 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3742 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3744 if (!pp_virt_addr_tbl)
3750 for (i = 0; i < page_cnt; i++) {
3751 if (!pp_virt_addr_tbl[i])
3754 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3755 *(dma_addr_t *)p_pbl_virt,
3756 ECORE_CHAIN_PAGE_SIZE);
3758 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3761 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3763 if (!p_chain->b_external_pbl)
3764 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3765 p_chain->pbl_sp.p_phys_table, pbl_size);
3767 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3770 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3772 switch (p_chain->mode) {
3773 case ECORE_CHAIN_MODE_NEXT_PTR:
3774 ecore_chain_free_next_ptr(p_dev, p_chain);
3776 case ECORE_CHAIN_MODE_SINGLE:
3777 ecore_chain_free_single(p_dev, p_chain);
3779 case ECORE_CHAIN_MODE_PBL:
3780 ecore_chain_free_pbl(p_dev, p_chain);
3785 static enum _ecore_status_t
3786 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3787 enum ecore_chain_cnt_type cnt_type,
3788 osal_size_t elem_size, u32 page_cnt)
3790 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3792 /* The actual chain size can be larger than the maximal possible value
3793 * after rounding up the requested elements number to pages, and after
3794 * taking into acount the unusuable elements (next-ptr elements).
3795 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3796 * size/capacity fields are of a u32 type.
3798 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3799 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3800 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3801 chain_size > ECORE_U32_MAX)) {
3802 DP_NOTICE(p_dev, true,
3803 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3804 (unsigned long)chain_size);
3808 return ECORE_SUCCESS;
3811 static enum _ecore_status_t
3812 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3814 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3815 dma_addr_t p_phys = 0;
3818 for (i = 0; i < p_chain->page_cnt; i++) {
3819 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3820 ECORE_CHAIN_PAGE_SIZE);
3822 DP_NOTICE(p_dev, true,
3823 "Failed to allocate chain memory\n");
3828 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3829 ecore_chain_reset(p_chain);
3831 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3835 p_virt_prev = p_virt;
3837 /* Last page's next element should point to the beginning of the
3840 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3841 p_chain->p_virt_addr,
3842 p_chain->p_phys_addr);
3844 return ECORE_SUCCESS;
3847 static enum _ecore_status_t
3848 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3850 dma_addr_t p_phys = 0;
3851 void *p_virt = OSAL_NULL;
3853 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3855 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3859 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3860 ecore_chain_reset(p_chain);
3862 return ECORE_SUCCESS;
3865 static enum _ecore_status_t
3866 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3867 struct ecore_chain *p_chain,
3868 struct ecore_chain_ext_pbl *ext_pbl)
3870 void *p_virt = OSAL_NULL;
3871 u8 *p_pbl_virt = OSAL_NULL;
3872 void **pp_virt_addr_tbl = OSAL_NULL;
3873 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3874 u32 page_cnt = p_chain->page_cnt, size, i;
3876 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3877 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
3878 if (!pp_virt_addr_tbl) {
3879 DP_NOTICE(p_dev, true,
3880 "Failed to allocate memory for the chain virtual addresses table\n");
3884 /* The allocation of the PBL table is done with its full size, since it
3885 * is expected to be successive.
3886 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3887 * failure, since pp_virt_addr_tbl was previously allocated, and it
3888 * should be saved to allow its freeing during the error flow.
3890 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3892 if (ext_pbl == OSAL_NULL) {
3893 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3895 p_pbl_virt = ext_pbl->p_pbl_virt;
3896 p_pbl_phys = ext_pbl->p_pbl_phys;
3897 p_chain->b_external_pbl = true;
3900 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3903 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3907 for (i = 0; i < page_cnt; i++) {
3908 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3909 ECORE_CHAIN_PAGE_SIZE);
3911 DP_NOTICE(p_dev, true,
3912 "Failed to allocate chain memory\n");
3917 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3918 ecore_chain_reset(p_chain);
3921 /* Fill the PBL table with the physical address of the page */
3922 *(dma_addr_t *)p_pbl_virt = p_phys;
3923 /* Keep the virtual address of the page */
3924 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3926 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3929 return ECORE_SUCCESS;
3932 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3933 enum ecore_chain_use_mode intended_use,
3934 enum ecore_chain_mode mode,
3935 enum ecore_chain_cnt_type cnt_type,
3936 u32 num_elems, osal_size_t elem_size,
3937 struct ecore_chain *p_chain,
3938 struct ecore_chain_ext_pbl *ext_pbl)
3941 enum _ecore_status_t rc = ECORE_SUCCESS;
3943 if (mode == ECORE_CHAIN_MODE_SINGLE)
3946 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3948 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3951 DP_NOTICE(p_dev, true,
3952 "Cannot allocate a chain with the given arguments:\n"
3953 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3954 intended_use, mode, cnt_type, num_elems, elem_size);
3958 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3959 mode, cnt_type, p_dev->dp_ctx);
3962 case ECORE_CHAIN_MODE_NEXT_PTR:
3963 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3965 case ECORE_CHAIN_MODE_SINGLE:
3966 rc = ecore_chain_alloc_single(p_dev, p_chain);
3968 case ECORE_CHAIN_MODE_PBL:
3969 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3975 return ECORE_SUCCESS;
3978 ecore_chain_free(p_dev, p_chain);
3982 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3983 u16 src_id, u16 *dst_id)
3985 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3988 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3989 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3990 DP_NOTICE(p_hwfn, true,
3991 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3997 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3999 return ECORE_SUCCESS;
4002 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4003 u8 src_id, u8 *dst_id)
4005 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4008 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4009 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4010 DP_NOTICE(p_hwfn, true,
4011 "vport id [%d] is not valid, available indices [%d - %d]\n",
4017 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4019 return ECORE_SUCCESS;
4022 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4023 u8 src_id, u8 *dst_id)
4025 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4028 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4029 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4030 DP_NOTICE(p_hwfn, true,
4031 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4037 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4039 return ECORE_SUCCESS;
4042 static enum _ecore_status_t
4043 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4044 struct ecore_ptt *p_ptt, u32 high, u32 low,
4050 /* Find a free entry and utilize it */
4051 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4052 en = ecore_rd(p_hwfn, p_ptt,
4053 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4057 ecore_wr(p_hwfn, p_ptt,
4058 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4059 2 * i * sizeof(u32), low);
4060 ecore_wr(p_hwfn, p_ptt,
4061 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4062 (2 * i + 1) * sizeof(u32), high);
4063 ecore_wr(p_hwfn, p_ptt,
4064 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4065 i * sizeof(u32), 0);
4066 ecore_wr(p_hwfn, p_ptt,
4067 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4068 i * sizeof(u32), 0);
4069 ecore_wr(p_hwfn, p_ptt,
4070 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4071 i * sizeof(u32), 1);
4075 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4076 return ECORE_NORESOURCES;
4080 return ECORE_SUCCESS;
4083 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4084 struct ecore_ptt *p_ptt, u8 *p_filter)
4086 u32 high, low, entry_num;
4087 enum _ecore_status_t rc;
4089 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4090 return ECORE_SUCCESS;
4092 high = p_filter[1] | (p_filter[0] << 8);
4093 low = p_filter[5] | (p_filter[4] << 8) |
4094 (p_filter[3] << 16) | (p_filter[2] << 24);
4096 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4097 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4099 if (rc != ECORE_SUCCESS) {
4100 DP_NOTICE(p_hwfn, false,
4101 "Failed to find an empty LLH filter to utilize\n");
4105 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4106 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4107 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4108 p_filter[4], p_filter[5], entry_num);
4110 return ECORE_SUCCESS;
4113 static enum _ecore_status_t
4114 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4115 struct ecore_ptt *p_ptt, u32 high, u32 low,
4120 /* Find the entry and clean it */
4121 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4122 if (ecore_rd(p_hwfn, p_ptt,
4123 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4124 2 * i * sizeof(u32)) != low)
4126 if (ecore_rd(p_hwfn, p_ptt,
4127 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4128 (2 * i + 1) * sizeof(u32)) != high)
4131 ecore_wr(p_hwfn, p_ptt,
4132 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4133 ecore_wr(p_hwfn, p_ptt,
4134 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4135 2 * i * sizeof(u32), 0);
4136 ecore_wr(p_hwfn, p_ptt,
4137 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4138 (2 * i + 1) * sizeof(u32), 0);
4142 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4147 return ECORE_SUCCESS;
4150 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4151 struct ecore_ptt *p_ptt, u8 *p_filter)
4153 u32 high, low, entry_num;
4154 enum _ecore_status_t rc;
4156 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4159 high = p_filter[1] | (p_filter[0] << 8);
4160 low = p_filter[5] | (p_filter[4] << 8) |
4161 (p_filter[3] << 16) | (p_filter[2] << 24);
4163 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4164 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4166 if (rc != ECORE_SUCCESS) {
4167 DP_NOTICE(p_hwfn, false,
4168 "Tried to remove a non-configured filter\n");
4173 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4174 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4175 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4176 p_filter[4], p_filter[5], entry_num);
4179 static enum _ecore_status_t
4180 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4181 struct ecore_ptt *p_ptt,
4182 enum ecore_llh_port_filter_type_t type,
4183 u32 high, u32 low, u32 *p_entry_num)
4188 /* Find a free entry and utilize it */
4189 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4190 en = ecore_rd(p_hwfn, p_ptt,
4191 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4195 ecore_wr(p_hwfn, p_ptt,
4196 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4197 2 * i * sizeof(u32), low);
4198 ecore_wr(p_hwfn, p_ptt,
4199 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4200 (2 * i + 1) * sizeof(u32), high);
4201 ecore_wr(p_hwfn, p_ptt,
4202 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4203 i * sizeof(u32), 1);
4204 ecore_wr(p_hwfn, p_ptt,
4205 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4206 i * sizeof(u32), 1 << type);
4207 ecore_wr(p_hwfn, p_ptt,
4208 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4212 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4213 return ECORE_NORESOURCES;
4217 return ECORE_SUCCESS;
4220 enum _ecore_status_t
4221 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4222 struct ecore_ptt *p_ptt,
4223 u16 source_port_or_eth_type,
4225 enum ecore_llh_port_filter_type_t type)
4227 u32 high, low, entry_num;
4228 enum _ecore_status_t rc;
4230 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4231 return ECORE_SUCCESS;
4237 case ECORE_LLH_FILTER_ETHERTYPE:
4238 high = source_port_or_eth_type;
4240 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4241 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4242 low = source_port_or_eth_type << 16;
4244 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4245 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4248 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4249 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4250 low = (source_port_or_eth_type << 16) | dest_port;
4253 DP_NOTICE(p_hwfn, true,
4254 "Non valid LLH protocol filter type %d\n", type);
4258 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4259 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4260 high, low, &entry_num);
4261 if (rc != ECORE_SUCCESS) {
4262 DP_NOTICE(p_hwfn, false,
4263 "Failed to find an empty LLH filter to utilize\n");
4267 case ECORE_LLH_FILTER_ETHERTYPE:
4268 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4269 "ETH type %x is added at %d\n",
4270 source_port_or_eth_type, entry_num);
4272 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4273 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4274 "TCP src port %x is added at %d\n",
4275 source_port_or_eth_type, entry_num);
4277 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4278 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4279 "UDP src port %x is added at %d\n",
4280 source_port_or_eth_type, entry_num);
4282 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4283 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4284 "TCP dst port %x is added at %d\n", dest_port,
4287 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4288 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4289 "UDP dst port %x is added at %d\n", dest_port,
4292 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4293 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4294 "TCP src/dst ports %x/%x are added at %d\n",
4295 source_port_or_eth_type, dest_port, entry_num);
4297 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4298 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4299 "UDP src/dst ports %x/%x are added at %d\n",
4300 source_port_or_eth_type, dest_port, entry_num);
4304 return ECORE_SUCCESS;
4307 static enum _ecore_status_t
4308 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4309 struct ecore_ptt *p_ptt,
4310 enum ecore_llh_port_filter_type_t type,
4311 u32 high, u32 low, u32 *p_entry_num)
4315 /* Find the entry and clean it */
4316 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4317 if (!ecore_rd(p_hwfn, p_ptt,
4318 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4321 if (!ecore_rd(p_hwfn, p_ptt,
4322 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4325 if (!(ecore_rd(p_hwfn, p_ptt,
4326 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4327 i * sizeof(u32)) & (1 << type)))
4329 if (ecore_rd(p_hwfn, p_ptt,
4330 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4331 2 * i * sizeof(u32)) != low)
4333 if (ecore_rd(p_hwfn, p_ptt,
4334 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4335 (2 * i + 1) * sizeof(u32)) != high)
4338 ecore_wr(p_hwfn, p_ptt,
4339 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4340 ecore_wr(p_hwfn, p_ptt,
4341 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4342 i * sizeof(u32), 0);
4343 ecore_wr(p_hwfn, p_ptt,
4344 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4345 i * sizeof(u32), 0);
4346 ecore_wr(p_hwfn, p_ptt,
4347 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4348 2 * i * sizeof(u32), 0);
4349 ecore_wr(p_hwfn, p_ptt,
4350 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4351 (2 * i + 1) * sizeof(u32), 0);
4355 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4360 return ECORE_SUCCESS;
4364 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4365 struct ecore_ptt *p_ptt,
4366 u16 source_port_or_eth_type,
4368 enum ecore_llh_port_filter_type_t type)
4370 u32 high, low, entry_num;
4371 enum _ecore_status_t rc;
4373 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4380 case ECORE_LLH_FILTER_ETHERTYPE:
4381 high = source_port_or_eth_type;
4383 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4384 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4385 low = source_port_or_eth_type << 16;
4387 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4388 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4391 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4392 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4393 low = (source_port_or_eth_type << 16) | dest_port;
4396 DP_NOTICE(p_hwfn, true,
4397 "Non valid LLH protocol filter type %d\n", type);
4401 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4402 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4405 if (rc != ECORE_SUCCESS) {
4406 DP_NOTICE(p_hwfn, false,
4407 "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4408 type, source_port_or_eth_type, dest_port);
4412 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4413 "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4414 type, source_port_or_eth_type, dest_port, entry_num);
4417 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4418 struct ecore_ptt *p_ptt)
4422 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4425 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4426 ecore_wr(p_hwfn, p_ptt,
4427 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4428 i * sizeof(u32), 0);
4429 ecore_wr(p_hwfn, p_ptt,
4430 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4431 2 * i * sizeof(u32), 0);
4432 ecore_wr(p_hwfn, p_ptt,
4433 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4434 (2 * i + 1) * sizeof(u32), 0);
4438 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4439 struct ecore_ptt *p_ptt)
4441 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4444 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4445 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
4448 enum _ecore_status_t
4449 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4450 struct ecore_ptt *p_ptt)
4452 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4453 ecore_wr(p_hwfn, p_ptt,
4454 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4455 1 << p_hwfn->abs_pf_id / 2);
4456 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4457 return ECORE_SUCCESS;
4460 DP_NOTICE(p_hwfn, false,
4461 "This function can't be set as default\n");
4465 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4466 struct ecore_ptt *p_ptt,
4467 u32 hw_addr, void *p_eth_qzone,
4468 osal_size_t eth_qzone_size,
4471 struct coalescing_timeset *p_coal_timeset;
4473 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4474 DP_NOTICE(p_hwfn, true,
4475 "Coalescing configuration not enabled\n");
4479 p_coal_timeset = p_eth_qzone;
4480 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4481 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4482 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4483 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4485 return ECORE_SUCCESS;
4488 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4489 u16 rx_coal, u16 tx_coal,
4492 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
4493 enum _ecore_status_t rc = ECORE_SUCCESS;
4494 struct ecore_ptt *p_ptt;
4496 /* TODO - Configuring a single queue's coalescing but
4497 * claiming all queues are abiding same configuration
4498 * for PF and VF both.
4501 if (IS_VF(p_hwfn->p_dev))
4502 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
4505 p_ptt = ecore_ptt_acquire(p_hwfn);
4510 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4513 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
4517 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4520 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
4523 ecore_ptt_release(p_hwfn, p_ptt);
4528 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4529 struct ecore_ptt *p_ptt,
4531 struct ecore_queue_cid *p_cid)
4533 struct ustorm_eth_queue_zone eth_qzone;
4534 u8 timeset, timer_res;
4536 enum _ecore_status_t rc;
4538 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4539 if (coalesce <= 0x7F) {
4541 } else if (coalesce <= 0xFF) {
4543 } else if (coalesce <= 0x1FF) {
4546 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4549 timeset = (u8)(coalesce >> timer_res);
4551 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4552 p_cid->sb_igu_id, false);
4553 if (rc != ECORE_SUCCESS)
4556 address = BAR0_MAP_REG_USDM_RAM +
4557 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4559 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4560 sizeof(struct ustorm_eth_queue_zone), timeset);
4561 if (rc != ECORE_SUCCESS)
4568 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4569 struct ecore_ptt *p_ptt,
4571 struct ecore_queue_cid *p_cid)
4573 struct xstorm_eth_queue_zone eth_qzone;
4574 u8 timeset, timer_res;
4576 enum _ecore_status_t rc;
4578 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4579 if (coalesce <= 0x7F) {
4581 } else if (coalesce <= 0xFF) {
4583 } else if (coalesce <= 0x1FF) {
4586 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4590 timeset = (u8)(coalesce >> timer_res);
4592 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4593 p_cid->sb_igu_id, true);
4594 if (rc != ECORE_SUCCESS)
4597 address = BAR0_MAP_REG_XSDM_RAM +
4598 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4600 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4601 sizeof(struct xstorm_eth_queue_zone), timeset);
4606 /* Calculate final WFQ values for all vports and configure it.
4607 * After this configuration each vport must have
4608 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4610 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4611 struct ecore_ptt *p_ptt,
4614 struct init_qm_vport_params *vport_params;
4617 vport_params = p_hwfn->qm_info.qm_vport_params;
4619 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4620 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4622 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4624 ecore_init_vport_wfq(p_hwfn, p_ptt,
4625 vport_params[i].first_tx_pq_id,
4626 vport_params[i].vport_wfq);
4631 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4635 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4636 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4639 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4640 struct ecore_ptt *p_ptt,
4643 struct init_qm_vport_params *vport_params;
4646 vport_params = p_hwfn->qm_info.qm_vport_params;
4648 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4649 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4650 ecore_init_vport_wfq(p_hwfn, p_ptt,
4651 vport_params[i].first_tx_pq_id,
4652 vport_params[i].vport_wfq);
4656 /* This function performs several validations for WFQ
4657 * configuration and required min rate for a given vport
4658 * 1. req_rate must be greater than one percent of min_pf_rate.
4659 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4660 * rates to get less than one percent of min_pf_rate.
4661 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4663 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4664 u16 vport_id, u32 req_rate,
4667 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4668 int non_requested_count = 0, req_count = 0, i, num_vports;
4670 num_vports = p_hwfn->qm_info.num_vports;
4672 /* Accounting for the vports which are configured for WFQ explicitly */
4674 for (i = 0; i < num_vports; i++) {
4677 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4679 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4680 total_req_min_rate += tmp_speed;
4684 /* Include current vport data as well */
4686 total_req_min_rate += req_rate;
4687 non_requested_count = num_vports - req_count;
4689 /* validate possible error cases */
4690 if (req_rate > min_pf_rate) {
4691 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4692 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4693 vport_id, req_rate, min_pf_rate);
4697 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4698 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4699 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4700 vport_id, req_rate, min_pf_rate);
4704 /* TBD - for number of vports greater than 100 */
4705 if (num_vports > ECORE_WFQ_UNIT) {
4706 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4707 "Number of vports is greater than %d\n",
4712 if (total_req_min_rate > min_pf_rate) {
4713 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4714 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4715 total_req_min_rate, min_pf_rate);
4719 /* Data left for non requested vports */
4720 total_left_rate = min_pf_rate - total_req_min_rate;
4721 left_rate_per_vp = total_left_rate / non_requested_count;
4723 /* validate if non requested get < 1% of min bw */
4724 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4725 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4726 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4727 left_rate_per_vp, min_pf_rate);
4731 /* now req_rate for given vport passes all scenarios.
4732 * assign final wfq rates to all vports.
4734 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4735 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4737 for (i = 0; i < num_vports; i++) {
4738 if (p_hwfn->qm_info.wfq_data[i].configured)
4741 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4744 return ECORE_SUCCESS;
4747 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4748 struct ecore_ptt *p_ptt,
4749 u16 vp_id, u32 rate)
4751 struct ecore_mcp_link_state *p_link;
4752 int rc = ECORE_SUCCESS;
4754 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4756 if (!p_link->min_pf_rate) {
4757 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4758 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4762 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4764 if (rc == ECORE_SUCCESS)
4765 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4766 p_link->min_pf_rate);
4768 DP_NOTICE(p_hwfn, false,
4769 "Validation failed while configuring min rate\n");
4774 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4775 struct ecore_ptt *p_ptt,
4778 bool use_wfq = false;
4779 int rc = ECORE_SUCCESS;
4782 /* Validate all pre configured vports for wfq */
4783 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4786 if (!p_hwfn->qm_info.wfq_data[i].configured)
4789 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4792 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4793 if (rc != ECORE_SUCCESS) {
4794 DP_NOTICE(p_hwfn, false,
4795 "WFQ validation failed while configuring min rate\n");
4800 if (rc == ECORE_SUCCESS && use_wfq)
4801 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4803 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4808 /* Main API for ecore clients to configure vport min rate.
4809 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4810 * rate - Speed in Mbps needs to be assigned to a given vport.
4812 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4814 int i, rc = ECORE_INVAL;
4816 /* TBD - for multiple hardware functions - that is 100 gig */
4817 if (p_dev->num_hwfns > 1) {
4818 DP_NOTICE(p_dev, false,
4819 "WFQ configuration is not supported for this device\n");
4823 for_each_hwfn(p_dev, i) {
4824 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4825 struct ecore_ptt *p_ptt;
4827 p_ptt = ecore_ptt_acquire(p_hwfn);
4829 return ECORE_TIMEOUT;
4831 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4833 if (rc != ECORE_SUCCESS) {
4834 ecore_ptt_release(p_hwfn, p_ptt);
4838 ecore_ptt_release(p_hwfn, p_ptt);
4844 /* API to configure WFQ from mcp link change */
4845 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4850 /* TBD - for multiple hardware functions - that is 100 gig */
4851 if (p_dev->num_hwfns > 1) {
4852 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4853 "WFQ configuration is not supported for this device\n");
4857 for_each_hwfn(p_dev, i) {
4858 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4860 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4866 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4867 struct ecore_ptt *p_ptt,
4868 struct ecore_mcp_link_state *p_link,
4871 int rc = ECORE_SUCCESS;
4873 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4875 if (!p_link->line_speed && (max_bw != 100))
4878 p_link->speed = (p_link->line_speed * max_bw) / 100;
4879 p_hwfn->qm_info.pf_rl = p_link->speed;
4881 /* Since the limiter also affects Tx-switched traffic, we don't want it
4882 * to limit such traffic in case there's no actual limit.
4883 * In that case, set limit to imaginary high boundary.
4886 p_hwfn->qm_info.pf_rl = 100000;
4888 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4889 p_hwfn->qm_info.pf_rl);
4891 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4892 "Configured MAX bandwidth to be %08x Mb/sec\n",
4898 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4899 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4901 int i, rc = ECORE_INVAL;
4903 if (max_bw < 1 || max_bw > 100) {
4904 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4908 for_each_hwfn(p_dev, i) {
4909 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4910 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4911 struct ecore_mcp_link_state *p_link;
4912 struct ecore_ptt *p_ptt;
4914 p_link = &p_lead->mcp_info->link_output;
4916 p_ptt = ecore_ptt_acquire(p_hwfn);
4918 return ECORE_TIMEOUT;
4920 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4923 ecore_ptt_release(p_hwfn, p_ptt);
4925 if (rc != ECORE_SUCCESS)
4932 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4933 struct ecore_ptt *p_ptt,
4934 struct ecore_mcp_link_state *p_link,
4937 int rc = ECORE_SUCCESS;
4939 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4940 p_hwfn->qm_info.pf_wfq = min_bw;
4942 if (!p_link->line_speed)
4945 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4947 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4949 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4950 "Configured MIN bandwidth to be %d Mb/sec\n",
4951 p_link->min_pf_rate);
4956 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4957 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4959 int i, rc = ECORE_INVAL;
4961 if (min_bw < 1 || min_bw > 100) {
4962 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4966 for_each_hwfn(p_dev, i) {
4967 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4968 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4969 struct ecore_mcp_link_state *p_link;
4970 struct ecore_ptt *p_ptt;
4972 p_link = &p_lead->mcp_info->link_output;
4974 p_ptt = ecore_ptt_acquire(p_hwfn);
4976 return ECORE_TIMEOUT;
4978 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4980 if (rc != ECORE_SUCCESS) {
4981 ecore_ptt_release(p_hwfn, p_ptt);
4985 if (p_link->min_pf_rate) {
4986 u32 min_rate = p_link->min_pf_rate;
4988 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4993 ecore_ptt_release(p_hwfn, p_ptt);
4999 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5001 struct ecore_mcp_link_state *p_link;
5003 p_link = &p_hwfn->mcp_info->link_output;
5005 if (p_link->min_pf_rate)
5006 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5007 p_link->min_pf_rate);
5009 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5010 sizeof(*p_hwfn->qm_info.wfq_data) *
5011 p_hwfn->qm_info.num_vports);
5014 int ecore_device_num_engines(struct ecore_dev *p_dev)
5016 return ECORE_IS_BB(p_dev) ? 2 : 1;
5019 int ecore_device_num_ports(struct ecore_dev *p_dev)
5021 /* in CMT always only one port */
5022 if (p_dev->num_hwfns > 1)
5025 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
5028 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5033 ((u8 *)fw_msb)[0] = mac[1];
5034 ((u8 *)fw_msb)[1] = mac[0];
5035 ((u8 *)fw_mid)[0] = mac[3];
5036 ((u8 *)fw_mid)[1] = mac[2];
5037 ((u8 *)fw_lsb)[0] = mac[5];
5038 ((u8 *)fw_lsb)[1] = mac[4];