1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
9 #include "ecore_gtt_reg_addr.h"
11 #include "ecore_chain.h"
12 #include "ecore_status.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_init_ops.h"
16 #include "ecore_int.h"
17 #include "ecore_cxt.h"
18 #include "ecore_spq.h"
19 #include "ecore_init_fw_funcs.h"
20 #include "ecore_sp_commands.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
24 #include "ecore_mcp.h"
25 #include "ecore_hw_defs.h"
26 #include "mcp_public.h"
27 #include "ecore_iro.h"
29 #include "ecore_dcbx.h"
32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
33 * registers involved are not split and thus configuration is a race where
34 * some of the PFs configuration might be lost.
35 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
36 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
37 * there's more than a single compiled ecore component in system].
39 static osal_spinlock_t qm_lock;
40 static u32 qm_lock_ref_cnt;
42 /******************** Doorbell Recovery *******************/
43 /* The doorbell recovery mechanism consists of a list of entries which represent
44 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
45 * entity needs to register with the mechanism and provide the parameters
46 * describing it's doorbell, including a location where last used doorbell data
47 * can be found. The doorbell execute function will traverse the list and
48 * doorbell all of the registered entries.
50 struct ecore_db_recovery_entry {
51 osal_list_entry_t list_entry;
52 void OSAL_IOMEM *db_addr;
54 enum ecore_db_rec_width db_width;
55 enum ecore_db_rec_space db_space;
59 /* display a single doorbell recovery entry */
60 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
61 struct ecore_db_recovery_entry *db_entry,
64 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
65 action, db_entry, db_entry->db_addr, db_entry->db_data,
66 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
67 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
71 /* doorbell address sanity (address within doorbell bar range) */
72 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
75 /* make sure doorbell address is within the doorbell bar */
76 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
77 (u8 *)p_dev->doorbells + p_dev->db_size) {
79 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
80 db_addr, p_dev->doorbells,
81 (u8 *)p_dev->doorbells + p_dev->db_size);
85 /* make sure doorbell data pointer is not null */
87 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
94 /* find hwfn according to the doorbell address */
95 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
96 void OSAL_IOMEM *db_addr)
98 struct ecore_hwfn *p_hwfn;
100 /* In CMT doorbell bar is split down the middle between engine 0 and
103 if (ECORE_IS_CMT(p_dev))
104 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
105 &p_dev->hwfns[0] : &p_dev->hwfns[1];
107 p_hwfn = ECORE_LEADING_HWFN(p_dev);
112 /* add a new entry to the doorbell recovery mechanism */
113 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
114 void OSAL_IOMEM *db_addr,
116 enum ecore_db_rec_width db_width,
117 enum ecore_db_rec_space db_space)
119 struct ecore_db_recovery_entry *db_entry;
120 struct ecore_hwfn *p_hwfn;
122 /* shortcircuit VFs, for now */
124 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
125 return ECORE_SUCCESS;
128 /* sanitize doorbell address */
129 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
132 /* obtain hwfn from doorbell address */
133 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
136 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
138 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
143 db_entry->db_addr = db_addr;
144 db_entry->db_data = db_data;
145 db_entry->db_width = db_width;
146 db_entry->db_space = db_space;
147 db_entry->hwfn_idx = p_hwfn->my_id;
150 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
152 /* protect the list */
153 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
154 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
155 &p_hwfn->db_recovery_info.list);
156 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
158 return ECORE_SUCCESS;
161 /* remove an entry from the doorbell recovery mechanism */
162 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
163 void OSAL_IOMEM *db_addr,
166 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
167 enum _ecore_status_t rc = ECORE_INVAL;
168 struct ecore_hwfn *p_hwfn;
170 /* shortcircuit VFs, for now */
172 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
173 return ECORE_SUCCESS;
176 /* sanitize doorbell address */
177 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
180 /* obtain hwfn from doorbell address */
181 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
183 /* protect the list */
184 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
185 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
186 &p_hwfn->db_recovery_info.list,
188 struct ecore_db_recovery_entry) {
189 /* search according to db_data addr since db_addr is not unique
192 if (db_entry->db_data == db_data) {
193 ecore_db_recovery_dp_entry(p_hwfn, db_entry,
195 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
196 &p_hwfn->db_recovery_info.list);
202 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
204 if (rc == ECORE_INVAL)
206 DP_NOTICE(p_hwfn, false,
207 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
210 OSAL_FREE(p_dev, db_entry);
215 /* initialize the doorbell recovery mechanism */
216 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
218 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
220 /* make sure db_size was set in p_dev */
221 if (!p_hwfn->p_dev->db_size) {
222 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
226 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
227 #ifdef CONFIG_ECORE_LOCK_ALLOC
228 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
231 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
232 p_hwfn->db_recovery_info.db_recovery_counter = 0;
234 return ECORE_SUCCESS;
237 /* destroy the doorbell recovery mechanism */
238 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
240 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
242 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
243 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
244 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
245 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
246 db_entry = OSAL_LIST_FIRST_ENTRY(
247 &p_hwfn->db_recovery_info.list,
248 struct ecore_db_recovery_entry,
250 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
251 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
252 &p_hwfn->db_recovery_info.list);
253 OSAL_FREE(p_hwfn->p_dev, db_entry);
256 #ifdef CONFIG_ECORE_LOCK_ALLOC
257 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
259 p_hwfn->db_recovery_info.db_recovery_counter = 0;
262 /* print the content of the doorbell recovery mechanism */
263 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
265 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
267 DP_NOTICE(p_hwfn, false,
268 "Dispalying doorbell recovery database. Counter was %d\n",
269 p_hwfn->db_recovery_info.db_recovery_counter);
271 /* protect the list */
272 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
273 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
274 &p_hwfn->db_recovery_info.list,
276 struct ecore_db_recovery_entry) {
277 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
280 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
283 /* ring the doorbell of a single doorbell recovery entry */
284 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
285 struct ecore_db_recovery_entry *db_entry,
286 enum ecore_db_rec_exec db_exec)
288 /* Print according to width */
289 if (db_entry->db_width == DB_REC_WIDTH_32B)
290 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
291 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
292 db_entry->db_addr, *(u32 *)db_entry->db_data);
294 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
295 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
297 *(unsigned long *)(db_entry->db_data));
300 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
304 /* Flush the write combined buffer. Since there are multiple doorbelling
305 * entities using the same address, if we don't flush, a transaction
308 OSAL_WMB(p_hwfn->p_dev);
310 /* Ring the doorbell */
311 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
312 if (db_entry->db_width == DB_REC_WIDTH_32B)
313 DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
314 *(u32 *)(db_entry->db_data));
316 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
317 *(u64 *)(db_entry->db_data));
320 /* Flush the write combined buffer. Next doorbell may come from a
321 * different entity to the same address...
323 OSAL_WMB(p_hwfn->p_dev);
326 /* traverse the doorbell recovery entry list and ring all the doorbells */
327 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
328 enum ecore_db_rec_exec db_exec)
330 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
332 if (db_exec != DB_REC_ONCE) {
333 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
334 p_hwfn->db_recovery_info.db_recovery_counter);
336 /* track amount of times recovery was executed */
337 p_hwfn->db_recovery_info.db_recovery_counter++;
340 /* protect the list */
341 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
342 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
343 &p_hwfn->db_recovery_info.list,
345 struct ecore_db_recovery_entry) {
346 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
347 if (db_exec == DB_REC_ONCE)
351 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
353 /******************** Doorbell Recovery end ****************/
356 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
357 * load the driver. The number was
362 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
364 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
365 struct ecore_ptt *p_ptt,
368 u32 bar_reg = (bar_id == BAR_ID_0 ?
369 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
372 if (IS_VF(p_hwfn->p_dev))
373 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
375 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
377 return 1 << (val + 15);
379 /* The above registers were updated in the past only in CMT mode. Since
380 * they were found to be useful MFW started updating them from 8.7.7.0.
381 * In older MFW versions they are set to 0 which means disabled.
383 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
385 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
386 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
389 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
396 void ecore_init_dp(struct ecore_dev *p_dev,
397 u32 dp_module, u8 dp_level, void *dp_ctx)
401 p_dev->dp_level = dp_level;
402 p_dev->dp_module = dp_module;
403 p_dev->dp_ctx = dp_ctx;
404 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
405 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
407 p_hwfn->dp_level = dp_level;
408 p_hwfn->dp_module = dp_module;
409 p_hwfn->dp_ctx = dp_ctx;
413 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
417 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
418 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
420 p_hwfn->p_dev = p_dev;
422 p_hwfn->b_active = false;
424 #ifdef CONFIG_ECORE_LOCK_ALLOC
425 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
428 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
431 /* hwfn 0 is always active */
432 p_dev->hwfns[0].b_active = true;
434 /* set the default cache alignment to 128 (may be overridden later) */
435 p_dev->cache_shift = 7;
436 return ECORE_SUCCESS;
437 #ifdef CONFIG_ECORE_LOCK_ALLOC
440 struct ecore_hwfn *p_hwfn = OSAL_NULL;
442 p_hwfn = &p_dev->hwfns[i];
443 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
449 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
451 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
453 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
454 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
455 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
456 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
459 static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)
461 OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);
462 p_hwfn->dbg_user_info = OSAL_NULL;
465 void ecore_resc_free(struct ecore_dev *p_dev)
470 for_each_hwfn(p_dev, i)
471 ecore_l2_free(&p_dev->hwfns[i]);
475 OSAL_FREE(p_dev, p_dev->fw_data);
477 OSAL_FREE(p_dev, p_dev->reset_stats);
479 for_each_hwfn(p_dev, i) {
480 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
482 ecore_cxt_mngr_free(p_hwfn);
483 ecore_qm_info_free(p_hwfn);
484 ecore_spq_free(p_hwfn);
485 ecore_eq_free(p_hwfn);
486 ecore_consq_free(p_hwfn);
487 ecore_int_free(p_hwfn);
488 ecore_iov_free(p_hwfn);
489 ecore_l2_free(p_hwfn);
490 ecore_dmae_info_free(p_hwfn);
491 ecore_dcbx_info_free(p_hwfn);
492 ecore_dbg_user_data_free(p_hwfn);
493 /* @@@TBD Flush work-queue ? */
495 /* destroy doorbell recovery mechanism */
496 ecore_db_recovery_teardown(p_hwfn);
500 /******************** QM initialization *******************/
502 /* bitmaps for indicating active traffic classes.
503 * Special case for Arrowhead 4 port
505 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
506 #define ACTIVE_TCS_BMAP 0x9f
507 /* 0..3 actually used, OOO and high priority stuff all use 3 */
508 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
510 /* determines the physical queue flags for a given PF. */
511 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
519 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
520 flags |= PQ_FLAGS_VFS;
521 if (IS_ECORE_PACING(p_hwfn))
522 flags |= PQ_FLAGS_RLS;
525 switch (p_hwfn->hw_info.personality) {
527 if (!IS_ECORE_PACING(p_hwfn))
528 flags |= PQ_FLAGS_MCOS;
531 flags |= PQ_FLAGS_OFLD;
533 case ECORE_PCI_ISCSI:
534 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
536 case ECORE_PCI_ETH_ROCE:
537 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
538 if (!IS_ECORE_PACING(p_hwfn))
539 flags |= PQ_FLAGS_MCOS;
541 case ECORE_PCI_ETH_IWARP:
542 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
543 if (!IS_ECORE_PACING(p_hwfn))
544 flags |= PQ_FLAGS_MCOS;
547 DP_ERR(p_hwfn, "unknown personality %d\n",
548 p_hwfn->hw_info.personality);
554 /* Getters for resource amounts necessary for qm initialization */
555 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
557 return p_hwfn->hw_info.num_hw_tc;
560 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
562 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
563 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
566 #define NUM_DEFAULT_RLS 1
568 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
570 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
573 /* num RLs can't exceed resource amount of rls or vports or the
576 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
577 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
579 /* make sure after we reserve the default and VF rls we'll have
582 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
583 DP_NOTICE(p_hwfn, false,
584 "no rate limiters left for PF rate limiting"
585 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
589 /* subtract rls necessary for VFs and one default one for the PF */
590 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
595 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
597 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
599 /* all pqs share the same vport (hence the 1 below), except for vfs
602 return (!!(PQ_FLAGS_RLS & pq_flags)) *
603 ecore_init_qm_get_num_pf_rls(p_hwfn) +
604 (!!(PQ_FLAGS_VFS & pq_flags)) *
605 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
608 /* calc amount of PQs according to the requested flags */
609 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
611 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
613 return (!!(PQ_FLAGS_RLS & pq_flags)) *
614 ecore_init_qm_get_num_pf_rls(p_hwfn) +
615 (!!(PQ_FLAGS_MCOS & pq_flags)) *
616 ecore_init_qm_get_num_tcs(p_hwfn) +
617 (!!(PQ_FLAGS_LB & pq_flags)) +
618 (!!(PQ_FLAGS_OOO & pq_flags)) +
619 (!!(PQ_FLAGS_ACK & pq_flags)) +
620 (!!(PQ_FLAGS_OFLD & pq_flags)) +
621 (!!(PQ_FLAGS_VFS & pq_flags)) *
622 ecore_init_qm_get_num_vfs(p_hwfn);
625 /* initialize the top level QM params */
626 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
628 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
631 /* pq and vport bases for this PF */
632 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
633 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
635 /* rate limiting and weighted fair queueing are always enabled */
636 qm_info->vport_rl_en = 1;
637 qm_info->vport_wfq_en = 1;
639 /* TC config is different for AH 4 port */
640 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
642 /* in AH 4 port we have fewer TCs per port */
643 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
646 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
649 if (!qm_info->ooo_tc)
650 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
654 /* initialize qm vport params */
655 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
657 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
660 /* all vports participate in weighted fair queueing */
661 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
662 qm_info->qm_vport_params[i].vport_wfq = 1;
665 /* initialize qm port params */
666 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
668 /* Initialize qm port parameters */
669 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
671 /* indicate how ooo and high pri traffic is dealt with */
672 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
673 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
675 for (i = 0; i < num_ports; i++) {
676 struct init_qm_port_params *p_qm_port =
677 &p_hwfn->qm_info.qm_port_params[i];
679 p_qm_port->active = 1;
680 p_qm_port->active_phys_tcs = active_phys_tcs;
681 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
682 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
686 /* Reset the params which must be reset for qm init. QM init may be called as
687 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
688 * params may be affected by the init but would simply recalculate to the same
689 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
690 * affected as these amounts stay the same.
692 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
694 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
696 qm_info->num_pqs = 0;
697 qm_info->num_vports = 0;
698 qm_info->num_pf_rls = 0;
699 qm_info->num_vf_pqs = 0;
700 qm_info->first_vf_pq = 0;
701 qm_info->first_mcos_pq = 0;
702 qm_info->first_rl_pq = 0;
705 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
707 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
709 qm_info->num_vports++;
711 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
713 "vport overflow! qm_info->num_vports %d,"
714 " qm_init_get_num_vports() %d\n",
716 ecore_init_qm_get_num_vports(p_hwfn));
719 /* initialize a single pq and manage qm_info resources accounting.
720 * The pq_init_flags param determines whether the PQ is rate limited
722 * and whether a new vport is allocated to the pq or not (i.e. vport will be
726 /* flags for pq init */
727 #define PQ_INIT_SHARE_VPORT (1 << 0)
728 #define PQ_INIT_PF_RL (1 << 1)
729 #define PQ_INIT_VF_RL (1 << 2)
731 /* defines for pq init */
732 #define PQ_INIT_DEFAULT_WRR_GROUP 1
733 #define PQ_INIT_DEFAULT_TC 0
734 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
736 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
737 struct ecore_qm_info *qm_info,
738 u8 tc, u32 pq_init_flags)
740 u16 pq_idx = qm_info->num_pqs, max_pq =
741 ecore_init_qm_get_num_pqs(p_hwfn);
745 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
748 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
749 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
751 qm_info->qm_pq_params[pq_idx].tc_id = tc;
752 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
753 qm_info->qm_pq_params[pq_idx].rl_valid =
754 (pq_init_flags & PQ_INIT_PF_RL ||
755 pq_init_flags & PQ_INIT_VF_RL);
757 /* qm params accounting */
759 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
760 qm_info->num_vports++;
762 if (pq_init_flags & PQ_INIT_PF_RL)
763 qm_info->num_pf_rls++;
765 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
767 "vport overflow! qm_info->num_vports %d,"
768 " qm_init_get_num_vports() %d\n",
770 ecore_init_qm_get_num_vports(p_hwfn));
772 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
773 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
774 " qm_init_get_num_pf_rls() %d\n",
776 ecore_init_qm_get_num_pf_rls(p_hwfn));
779 /* get pq index according to PQ_FLAGS */
780 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
783 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
785 /* Can't have multiple flags set here */
786 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
787 sizeof(pq_flags)) > 1)
792 return &qm_info->first_rl_pq;
794 return &qm_info->first_mcos_pq;
796 return &qm_info->pure_lb_pq;
798 return &qm_info->ooo_pq;
800 return &qm_info->pure_ack_pq;
802 return &qm_info->offload_pq;
804 return &qm_info->first_vf_pq;
810 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
814 /* save pq index in qm info */
815 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
816 u32 pq_flags, u16 pq_val)
818 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
820 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
823 /* get tx pq index, with the PQ TX base already set (ready for context init) */
824 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
826 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
828 return *base_pq_idx + CM_TX_PQ_BASE;
831 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
833 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
836 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
838 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
841 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
843 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
846 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
848 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
851 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
853 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
856 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
858 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
861 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
863 u16 start_pq, pq, qm_pq_idx;
865 pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
866 start_pq = p_hwfn->qm_info.start_pq;
867 qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;
869 if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
871 "qm_pq_idx %d must be smaller than %d\n",
872 qm_pq_idx, p_hwfn->qm_info.num_pqs);
875 return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
878 /* Functions for creating specific types of pqs */
879 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
881 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
883 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
886 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
887 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
890 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
892 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
894 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
897 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
898 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
901 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
903 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
905 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
908 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
909 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
912 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
914 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
916 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
919 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
920 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
923 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
925 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
928 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
931 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
932 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
933 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
936 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
938 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
939 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
941 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
944 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
946 qm_info->num_vf_pqs = num_vfs;
947 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
948 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
952 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
954 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
955 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
957 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
960 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
961 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
962 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
966 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
968 /* rate limited pqs, must come first (FW assumption) */
969 ecore_init_qm_rl_pqs(p_hwfn);
971 /* pqs for multi cos */
972 ecore_init_qm_mcos_pqs(p_hwfn);
974 /* pure loopback pq */
975 ecore_init_qm_lb_pq(p_hwfn);
977 /* out of order pq */
978 ecore_init_qm_ooo_pq(p_hwfn);
981 ecore_init_qm_pure_ack_pq(p_hwfn);
983 /* pq for offloaded protocol */
984 ecore_init_qm_offload_pq(p_hwfn);
986 /* done sharing vports */
987 ecore_init_qm_advance_vport(p_hwfn);
990 ecore_init_qm_vf_pqs(p_hwfn);
993 /* compare values of getters against resources amounts */
994 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
996 if (ecore_init_qm_get_num_vports(p_hwfn) >
997 RESC_NUM(p_hwfn, ECORE_VPORT)) {
998 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1002 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
1003 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1007 return ECORE_SUCCESS;
1011 * Function for verbose printing of the qm initialization results
1013 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
1015 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1016 struct init_qm_vport_params *vport;
1017 struct init_qm_port_params *port;
1018 struct init_qm_pq_params *pq;
1021 /* top level params */
1022 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1023 "qm init top level params: start_pq %d, start_vport %d,"
1024 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
1025 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
1026 qm_info->offload_pq, qm_info->pure_ack_pq);
1027 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1028 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
1029 " num_vports %d, max_phys_tcs_per_port %d\n",
1030 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
1031 qm_info->num_vf_pqs, qm_info->num_vports,
1032 qm_info->max_phys_tcs_per_port);
1033 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1034 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
1035 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1036 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
1037 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
1038 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1041 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1042 port = &qm_info->qm_port_params[i];
1043 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1044 "port idx %d, active %d, active_phys_tcs %d,"
1045 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1047 i, port->active, port->active_phys_tcs,
1048 port->num_pbf_cmd_lines, port->num_btb_blocks,
1053 for (i = 0; i < qm_info->num_vports; i++) {
1054 vport = &qm_info->qm_vport_params[i];
1055 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1056 "vport idx %d, vport_rl %d, wfq %d,"
1057 " first_tx_pq_id [ ",
1058 qm_info->start_vport + i, vport->vport_rl,
1060 for (tc = 0; tc < NUM_OF_TCS; tc++)
1061 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1062 vport->first_tx_pq_id[tc]);
1063 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1067 for (i = 0; i < qm_info->num_pqs; i++) {
1068 pq = &qm_info->qm_pq_params[i];
1069 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1070 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1071 qm_info->start_pq + i, pq->port_id, pq->vport_id,
1072 pq->tc_id, pq->wrr_group, pq->rl_valid);
1076 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1078 /* reset params required for init run */
1079 ecore_init_qm_reset_params(p_hwfn);
1081 /* init QM top level params */
1082 ecore_init_qm_params(p_hwfn);
1084 /* init QM port params */
1085 ecore_init_qm_port_params(p_hwfn);
1087 /* init QM vport params */
1088 ecore_init_qm_vport_params(p_hwfn);
1090 /* init QM physical queue params */
1091 ecore_init_qm_pq_params(p_hwfn);
1093 /* display all that init */
1094 ecore_dp_init_qm_params(p_hwfn);
1097 /* This function reconfigures the QM pf on the fly.
1098 * For this purpose we:
1099 * 1. reconfigure the QM database
1100 * 2. set new values to runtime array
1101 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1102 * 4. activate init tool in QM_PF stage
1103 * 5. send an sdm_qm_cmd through rbc interface to release the QM
1105 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1106 struct ecore_ptt *p_ptt)
1108 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1110 enum _ecore_status_t rc;
1112 /* initialize ecore's qm data structure */
1113 ecore_init_qm_info(p_hwfn);
1115 /* stop PF's qm queues */
1116 OSAL_SPIN_LOCK(&qm_lock);
1117 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1118 qm_info->start_pq, qm_info->num_pqs);
1119 OSAL_SPIN_UNLOCK(&qm_lock);
1123 /* clear the QM_PF runtime phase leftovers from previous init */
1124 ecore_init_clear_rt_data(p_hwfn);
1126 /* prepare QM portion of runtime array */
1127 ecore_qm_init_pf(p_hwfn, p_ptt, false);
1129 /* activate init tool on runtime array */
1130 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1131 p_hwfn->hw_info.hw_mode);
1132 if (rc != ECORE_SUCCESS)
1135 /* start PF's qm queues */
1136 OSAL_SPIN_LOCK(&qm_lock);
1137 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1138 qm_info->start_pq, qm_info->num_pqs);
1139 OSAL_SPIN_UNLOCK(&qm_lock);
1143 return ECORE_SUCCESS;
1146 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1148 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1149 enum _ecore_status_t rc;
1151 rc = ecore_init_qm_sanity(p_hwfn);
1152 if (rc != ECORE_SUCCESS)
1155 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1156 sizeof(struct init_qm_pq_params) *
1157 ecore_init_qm_get_num_pqs(p_hwfn));
1158 if (!qm_info->qm_pq_params)
1161 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1162 sizeof(struct init_qm_vport_params) *
1163 ecore_init_qm_get_num_vports(p_hwfn));
1164 if (!qm_info->qm_vport_params)
1167 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1168 sizeof(struct init_qm_port_params) *
1169 p_hwfn->p_dev->num_ports_in_engine);
1170 if (!qm_info->qm_port_params)
1173 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1174 sizeof(struct ecore_wfq_data) *
1175 ecore_init_qm_get_num_vports(p_hwfn));
1176 if (!qm_info->wfq_data)
1179 return ECORE_SUCCESS;
1182 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1183 ecore_qm_info_free(p_hwfn);
1186 /******************** End QM initialization ***************/
1188 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1190 enum _ecore_status_t rc = ECORE_SUCCESS;
1194 for_each_hwfn(p_dev, i) {
1195 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1196 if (rc != ECORE_SUCCESS)
1202 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1203 sizeof(*p_dev->fw_data));
1204 if (!p_dev->fw_data)
1207 for_each_hwfn(p_dev, i) {
1208 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1209 u32 n_eqes, num_cons;
1211 /* initialize the doorbell recovery mechanism */
1212 rc = ecore_db_recovery_setup(p_hwfn);
1216 /* First allocate the context manager structure */
1217 rc = ecore_cxt_mngr_alloc(p_hwfn);
1221 /* Set the HW cid/tid numbers (in the context manager)
1222 * Must be done prior to any further computations.
1224 rc = ecore_cxt_set_pf_params(p_hwfn);
1228 rc = ecore_alloc_qm_data(p_hwfn);
1233 ecore_init_qm_info(p_hwfn);
1235 /* Compute the ILT client partition */
1236 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1240 /* CID map / ILT shadow table / T2
1241 * The talbes sizes are determined by the computations above
1243 rc = ecore_cxt_tables_alloc(p_hwfn);
1247 /* SPQ, must follow ILT because initializes SPQ context */
1248 rc = ecore_spq_alloc(p_hwfn);
1252 /* SP status block allocation */
1253 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1256 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1260 rc = ecore_iov_alloc(p_hwfn);
1265 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1266 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1267 /* Calculate the EQ size
1268 * ---------------------
1269 * Each ICID may generate up to one event at a time i.e.
1270 * the event must be handled/cleared before a new one
1271 * can be generated. We calculate the sum of events per
1272 * protocol and create an EQ deep enough to handle the
1274 * - Core - according to SPQ.
1275 * - RoCE - per QP there are a couple of ICIDs, one
1276 * responder and one requester, each can
1277 * generate an EQE => n_eqes_qp = 2 * n_qp.
1278 * Each CQ can generate an EQE. There are 2 CQs
1279 * per QP => n_eqes_cq = 2 * n_qp.
1280 * Hence the RoCE total is 4 * n_qp or
1282 * - ENet - There can be up to two events per VF. One
1283 * for VF-PF channel and another for VF FLR
1284 * initial cleanup. The number of VFs is
1285 * bounded by MAX_NUM_VFS_BB, and is much
1286 * smaller than RoCE's so we avoid exact
1289 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1291 ecore_cxt_get_proto_cid_count(
1297 num_cons = ecore_cxt_get_proto_cid_count(
1302 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1303 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1305 ecore_cxt_get_proto_cid_count(p_hwfn,
1308 n_eqes += 2 * num_cons;
1311 if (n_eqes > 0xFFFF) {
1312 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1313 "The maximum of a u16 chain is 0x%x\n",
1318 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1322 rc = ecore_consq_alloc(p_hwfn);
1326 rc = ecore_l2_alloc(p_hwfn);
1327 if (rc != ECORE_SUCCESS)
1330 /* DMA info initialization */
1331 rc = ecore_dmae_info_alloc(p_hwfn);
1333 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
1337 /* DCBX initialization */
1338 rc = ecore_dcbx_info_alloc(p_hwfn);
1340 DP_NOTICE(p_hwfn, false,
1341 "Failed to allocate memory for dcbx structure\n");
1345 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
1347 DP_NOTICE(p_hwfn, false,
1348 "Failed to allocate dbg user info structure\n");
1353 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1354 sizeof(*p_dev->reset_stats));
1355 if (!p_dev->reset_stats) {
1356 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
1360 return ECORE_SUCCESS;
1365 ecore_resc_free(p_dev);
1369 void ecore_resc_setup(struct ecore_dev *p_dev)
1374 for_each_hwfn(p_dev, i)
1375 ecore_l2_setup(&p_dev->hwfns[i]);
1379 for_each_hwfn(p_dev, i) {
1380 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1382 ecore_cxt_mngr_setup(p_hwfn);
1383 ecore_spq_setup(p_hwfn);
1384 ecore_eq_setup(p_hwfn);
1385 ecore_consq_setup(p_hwfn);
1387 /* Read shadow of current MFW mailbox */
1388 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1389 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1390 p_hwfn->mcp_info->mfw_mb_cur,
1391 p_hwfn->mcp_info->mfw_mb_length);
1393 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1395 ecore_l2_setup(p_hwfn);
1396 ecore_iov_setup(p_hwfn);
1400 #define FINAL_CLEANUP_POLL_CNT (100)
1401 #define FINAL_CLEANUP_POLL_TIME (10)
1402 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1403 struct ecore_ptt *p_ptt,
1406 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1407 enum _ecore_status_t rc = ECORE_TIMEOUT;
1410 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1411 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1412 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1413 return ECORE_SUCCESS;
1417 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1418 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1423 command |= X_FINAL_CLEANUP_AGG_INT <<
1424 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1425 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1426 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1427 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1429 /* Make sure notification is not set before initiating final cleanup */
1431 if (REG_RD(p_hwfn, addr)) {
1432 DP_NOTICE(p_hwfn, false,
1433 "Unexpected; Found final cleanup notification");
1434 DP_NOTICE(p_hwfn, false,
1435 " before initiating final cleanup\n");
1436 REG_WR(p_hwfn, addr, 0);
1439 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1440 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1443 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1445 /* Poll until completion */
1446 while (!REG_RD(p_hwfn, addr) && count--)
1447 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1449 if (REG_RD(p_hwfn, addr))
1452 DP_NOTICE(p_hwfn, true,
1453 "Failed to receive FW final cleanup notification\n");
1455 /* Cleanup afterwards */
1456 REG_WR(p_hwfn, addr, 0);
1461 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1465 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1466 hw_mode |= 1 << MODE_BB;
1467 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1468 hw_mode |= 1 << MODE_K2;
1470 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1471 p_hwfn->p_dev->type);
1475 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1476 switch (p_hwfn->p_dev->num_ports_in_engine) {
1478 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1481 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1484 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1487 DP_NOTICE(p_hwfn, true,
1488 "num_ports_in_engine = %d not supported\n",
1489 p_hwfn->p_dev->num_ports_in_engine);
1493 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1494 &p_hwfn->p_dev->mf_bits))
1495 hw_mode |= 1 << MODE_MF_SD;
1497 hw_mode |= 1 << MODE_MF_SI;
1500 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1501 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1502 hw_mode |= 1 << MODE_FPGA;
1504 if (p_hwfn->p_dev->b_is_emul_full)
1505 hw_mode |= 1 << MODE_EMUL_FULL;
1507 hw_mode |= 1 << MODE_EMUL_REDUCED;
1511 hw_mode |= 1 << MODE_ASIC;
1513 if (ECORE_IS_CMT(p_hwfn->p_dev))
1514 hw_mode |= 1 << MODE_100G;
1516 p_hwfn->hw_info.hw_mode = hw_mode;
1518 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1519 "Configuring function for hw_mode: 0x%08x\n",
1520 p_hwfn->hw_info.hw_mode);
1522 return ECORE_SUCCESS;
1526 /* MFW-replacement initializations for non-ASIC */
1527 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1528 struct ecore_ptt *p_ptt)
1530 struct ecore_dev *p_dev = p_hwfn->p_dev;
1534 if (CHIP_REV_IS_EMUL(p_dev)) {
1535 if (ECORE_IS_AH(p_dev))
1539 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1541 if (CHIP_REV_IS_EMUL(p_dev) &&
1542 (ECORE_IS_AH(p_dev)))
1543 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1546 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1547 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1548 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1549 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1551 if (CHIP_REV_IS_EMUL(p_dev)) {
1552 if (ECORE_IS_AH(p_dev)) {
1553 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1554 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1555 (p_dev->num_ports_in_engine >> 1));
1557 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1558 p_dev->num_ports_in_engine == 4 ? 0 : 3);
1563 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1564 for (i = 0; i < 100; i++) {
1566 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1570 DP_NOTICE(p_hwfn, true,
1571 "RBC done failed to complete in PSWRQ2\n");
1573 return ECORE_SUCCESS;
1577 /* Init run time data for all PFs and their VFs on an engine.
1578 * TBD - for VFs - Once we have parent PF info for each VF in
1579 * shmem available as CAU requires knowledge of parent PF for each VF.
1581 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1583 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1586 for_each_hwfn(p_dev, i) {
1587 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1588 struct ecore_igu_info *p_igu_info;
1589 struct ecore_igu_block *p_block;
1590 struct cau_sb_entry sb_entry;
1592 p_igu_info = p_hwfn->hw_info.p_igu_info;
1595 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1597 p_block = &p_igu_info->entry[igu_sb_id];
1599 if (!p_block->is_pf)
1602 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1603 p_block->function_id, 0, 0);
1604 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1610 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1611 struct ecore_ptt *p_ptt)
1613 u32 val, wr_mbs, cache_line_size;
1615 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1628 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1633 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1634 switch (cache_line_size) {
1649 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1653 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1655 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1656 OSAL_CACHE_LINE_SIZE, wr_mbs);
1658 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1660 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1661 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1665 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1666 struct ecore_ptt *p_ptt,
1669 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1670 struct ecore_dev *p_dev = p_hwfn->p_dev;
1671 u8 vf_id, max_num_vfs;
1674 enum _ecore_status_t rc = ECORE_SUCCESS;
1676 ecore_init_cau_rt_data(p_dev);
1678 /* Program GTT windows */
1679 ecore_gtt_init(p_hwfn, p_ptt);
1682 if (CHIP_REV_IS_EMUL(p_dev)) {
1683 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1684 if (rc != ECORE_SUCCESS)
1689 if (p_hwfn->mcp_info) {
1690 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1691 qm_info->pf_rl_en = 1;
1692 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1693 qm_info->pf_wfq_en = 1;
1696 ecore_qm_common_rt_init(p_hwfn,
1697 p_dev->num_ports_in_engine,
1698 qm_info->max_phys_tcs_per_port,
1699 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1700 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1701 qm_info->qm_port_params);
1703 ecore_cxt_hw_init_common(p_hwfn);
1705 ecore_init_cache_line_size(p_hwfn, p_ptt);
1707 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
1709 if (rc != ECORE_SUCCESS)
1712 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1713 * need to decide with which value, maybe runtime
1715 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1716 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1718 if (ECORE_IS_BB(p_dev)) {
1719 /* Workaround clears ROCE search for all functions to prevent
1720 * involving non initialized function in processing ROCE packet.
1722 num_pfs = NUM_OF_ENG_PFS(p_dev);
1723 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1724 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1725 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1726 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1728 /* pretend to original PF */
1729 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1732 /* Workaround for avoiding CCFC execution error when getting packets
1733 * with CRC errors, and allowing instead the invoking of the FW error
1735 * This is not done inside the init tool since it currently can't
1736 * perform a pretending to VFs.
1738 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1739 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1740 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1741 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1742 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1743 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1744 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1745 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1747 /* pretend to original PF */
1748 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1754 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1755 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1757 #define PMEG_IF_BYTE_COUNT 8
1759 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1760 struct ecore_ptt *p_ptt,
1761 u32 addr, u64 data, u8 reg_type, u8 port)
1763 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1764 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1765 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1766 (8 << PMEG_IF_BYTE_COUNT),
1767 (reg_type << 25) | (addr << 8) | port,
1768 (u32)((data >> 32) & 0xffffffff),
1769 (u32)(data & 0xffffffff));
1771 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1772 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1773 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1774 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1775 (reg_type << 25) | (addr << 8) | port);
1776 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1777 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1778 (data >> 32) & 0xffffffff);
1781 #define XLPORT_MODE_REG (0x20a)
1782 #define XLPORT_MAC_CONTROL (0x210)
1783 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1784 #define XLPORT_ENABLE_REG (0x20b)
1786 #define XLMAC_CTRL (0x600)
1787 #define XLMAC_MODE (0x601)
1788 #define XLMAC_RX_MAX_SIZE (0x608)
1789 #define XLMAC_TX_CTRL (0x604)
1790 #define XLMAC_PAUSE_CTRL (0x60d)
1791 #define XLMAC_PFC_CTRL (0x60e)
1793 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1794 struct ecore_ptt *p_ptt)
1796 u8 loopback = 0, port = p_hwfn->port_id * 2;
1798 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1800 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1801 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1803 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1804 /* XLMAC: SOFT RESET */
1805 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1806 /* XLMAC: Port Speed >= 10Gbps */
1807 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1808 /* XLMAC: Max Size */
1809 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1810 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1811 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1813 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1814 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1815 0x30ffffc000ULL, 0, port);
1816 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1817 port); /* XLMAC: TX_EN, RX_EN */
1818 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1819 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1820 0x1003 | (loopback << 2), 0, port);
1821 /* Enabled Parallel PFC interface */
1822 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1824 /* XLPORT port enable */
1825 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1828 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1829 struct ecore_ptt *p_ptt)
1831 u8 port = p_hwfn->port_id;
1832 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1834 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1836 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1837 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1839 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1840 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1842 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1843 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1845 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1846 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1848 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1849 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1851 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1852 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1854 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1856 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1858 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1860 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1864 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1865 struct ecore_ptt *p_ptt)
1867 if (ECORE_IS_AH(p_hwfn->p_dev))
1868 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1870 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1873 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1874 struct ecore_ptt *p_ptt, u8 port)
1876 int port_offset = port ? 0x800 : 0;
1877 u32 xmac_rxctrl = 0;
1880 /* FIXME: move to common start */
1881 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1882 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1884 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1885 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1887 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1889 /* Set the number of ports on the Warp Core to 10G */
1890 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1892 /* Soft reset of XMAC */
1893 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1894 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1896 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1897 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1899 /* FIXME: move to common end */
1900 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1901 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1903 /* Set Max packet size: initialize XMAC block register for port 0 */
1904 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1906 /* CRC append for Tx packets: init XMAC block register for port 1 */
1907 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1909 /* Enable TX and RX: initialize XMAC block register for port 1 */
1910 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1911 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1912 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1913 XMAC_REG_RX_CTRL_BB + port_offset);
1914 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1915 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1919 static enum _ecore_status_t
1920 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1921 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1923 u32 dpi_bit_shift, dpi_count, dpi_page_size;
1927 /* Calculate DPI size
1928 * ------------------
1929 * The PWM region contains Doorbell Pages. The first is reserverd for
1930 * the kernel for, e.g, L2. The others are free to be used by non-
1931 * trusted applications, typically from user space. Each page, called a
1932 * doorbell page is sectioned into windows that allow doorbells to be
1933 * issued in parallel by the kernel/application. The size of such a
1934 * window (a.k.a. WID) is 1kB.
1936 * 1kB WID x N WIDS = DPI page size
1937 * DPI page size x N DPIs = PWM region size
1939 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1940 * in order to ensure that two applications won't share the same page.
1941 * It also must contain at least one WID per CPU to allow parallelism.
1942 * It also must be a power of 2, since it is stored as a bit shift.
1944 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1945 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1946 * containing 4 WIDs.
1948 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1949 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1950 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1951 ~(OSAL_PAGE_SIZE - 1);
1952 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1953 dpi_count = pwm_region_size / dpi_page_size;
1955 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1956 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1959 p_hwfn->dpi_size = dpi_page_size;
1960 p_hwfn->dpi_count = dpi_count;
1962 /* Update registers */
1963 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1965 if (dpi_count < min_dpis)
1966 return ECORE_NORESOURCES;
1968 return ECORE_SUCCESS;
1971 enum ECORE_ROCE_EDPM_MODE {
1972 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1973 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1974 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1977 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn)
1979 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
1985 static enum _ecore_status_t
1986 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1987 struct ecore_ptt *p_ptt)
1989 u32 pwm_regsize, norm_regsize;
1990 u32 non_pwm_conn, min_addr_reg1;
1991 u32 db_bar_size, n_cpus;
1994 enum _ecore_status_t rc = ECORE_SUCCESS;
1997 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1998 if (ECORE_IS_CMT(p_hwfn->p_dev))
2001 /* Calculate doorbell regions
2002 * -----------------------------------
2003 * The doorbell BAR is made of two regions. The first is called normal
2004 * region and the second is called PWM region. In the normal region
2005 * each ICID has its own set of addresses so that writing to that
2006 * specific address identifies the ICID. In the Process Window Mode
2007 * region the ICID is given in the data written to the doorbell. The
2008 * above per PF register denotes the offset in the doorbell BAR in which
2009 * the PWM region begins.
2010 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
2011 * non-PWM connection. The calculation below computes the total non-PWM
2012 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
2013 * in units of 4,096 bytes.
2015 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2016 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2018 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
2019 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
2021 min_addr_reg1 = norm_regsize / 4096;
2022 pwm_regsize = db_bar_size - norm_regsize;
2024 /* Check that the normal and PWM sizes are valid */
2025 if (db_bar_size < norm_regsize) {
2026 DP_ERR(p_hwfn->p_dev,
2027 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2028 db_bar_size, norm_regsize);
2029 return ECORE_NORESOURCES;
2031 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
2032 DP_ERR(p_hwfn->p_dev,
2033 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2034 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
2036 return ECORE_NORESOURCES;
2039 /* Calculate number of DPIs */
2040 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2041 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
2042 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
2043 /* Either EDPM is mandatory, or we are attempting to allocate a
2046 n_cpus = OSAL_NUM_CPUS();
2047 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2050 cond = ((rc != ECORE_SUCCESS) &&
2051 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2052 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2053 if (cond || p_hwfn->dcbx_no_edpm) {
2054 /* Either EDPM is disabled from user configuration, or it is
2055 * disabled via DCBx, or it is not mandatory and we failed to
2056 * allocated a WID per CPU.
2059 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2061 /* If we entered this flow due to DCBX then the DPM register is
2062 * already configured.
2067 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2068 norm_regsize, pwm_regsize);
2070 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2071 p_hwfn->dpi_size, p_hwfn->dpi_count,
2072 (!ecore_edpm_enabled(p_hwfn)) ?
2073 "disabled" : "enabled");
2075 /* Check return codes from above calls */
2076 if (rc != ECORE_SUCCESS) {
2078 "Failed to allocate enough DPIs\n");
2079 return ECORE_NORESOURCES;
2083 p_hwfn->dpi_start_offset = norm_regsize;
2085 /* Update registers */
2086 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2087 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2088 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2089 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2091 return ECORE_SUCCESS;
2094 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2095 struct ecore_ptt *p_ptt,
2098 u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2100 enum _ecore_status_t rc = ECORE_SUCCESS;
2103 /* In CMT for non-RoCE packets - use connection based classification */
2104 val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2105 for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2106 ppf_to_eng_sel[i] = val;
2107 STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2110 /* In CMT the gate should be cleared by the 2nd hwfn */
2111 if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2112 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2114 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2116 if (rc != ECORE_SUCCESS)
2119 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2122 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2123 return ECORE_SUCCESS;
2125 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2126 if (ECORE_IS_AH(p_hwfn->p_dev))
2127 return ECORE_SUCCESS;
2128 else if (ECORE_IS_BB(p_hwfn->p_dev))
2129 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2130 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2131 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2132 /* Activate OPTE in CMT */
2135 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2137 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2138 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2139 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2140 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2141 ecore_wr(p_hwfn, p_ptt,
2142 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2143 ecore_wr(p_hwfn, p_ptt,
2144 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2145 ecore_wr(p_hwfn, p_ptt,
2146 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2150 ecore_emul_link_init(p_hwfn, p_ptt);
2152 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2159 static enum _ecore_status_t
2160 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2161 struct ecore_ptt *p_ptt,
2162 struct ecore_tunnel_info *p_tunn,
2165 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2167 u8 rel_pf_id = p_hwfn->rel_pf_id;
2169 enum _ecore_status_t rc = ECORE_SUCCESS;
2173 if (p_hwfn->mcp_info) {
2174 struct ecore_mcp_function_info *p_info;
2176 p_info = &p_hwfn->mcp_info->func_info;
2177 if (p_info->bandwidth_min)
2178 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2180 /* Update rate limit once we'll actually have a link */
2181 p_hwfn->qm_info.pf_rl = 100000;
2183 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2185 ecore_int_igu_init_rt(p_hwfn);
2187 /* Set VLAN in NIG if needed */
2188 if (hw_mode & (1 << MODE_MF_SD)) {
2189 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2190 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2191 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2192 p_hwfn->hw_info.ovlan);
2194 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2195 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2196 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2200 /* Enable classification by MAC if needed */
2201 if (hw_mode & (1 << MODE_MF_SI)) {
2202 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2203 "Configuring TAGMAC_CLS_TYPE\n");
2204 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2208 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
2209 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2210 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2211 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2212 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2213 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2215 /* perform debug configuration when chip is out of reset */
2216 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2218 /* Sanity check before the PF init sequence that uses DMAE */
2219 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2223 /* PF Init sequence */
2224 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2228 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2229 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2233 /* Pure runtime initializations - directly to the HW */
2234 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2236 /* PCI relaxed ordering causes a decrease in the performance on some
2237 * systems. Till a root cause is found, disable this attribute in the
2241 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2243 * DP_NOTICE(p_hwfn, true,
2244 * "Failed to find the PCIe Cap\n");
2247 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2248 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2249 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2252 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2256 /* enable interrupts */
2257 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2258 if (rc != ECORE_SUCCESS)
2261 /* send function start command */
2262 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2263 allow_npar_tx_switch);
2265 DP_NOTICE(p_hwfn, true,
2266 "Function start ramrod failed\n");
2270 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2271 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2272 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2274 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2275 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2277 ecore_wr(p_hwfn, p_ptt,
2278 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2281 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2282 "PRS_REG_SEARCH registers after start PFn\n");
2283 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2284 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2285 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2286 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2287 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2288 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2289 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2290 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2291 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2292 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2293 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2294 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2295 prs_reg = ecore_rd(p_hwfn, p_ptt,
2296 PRS_REG_SEARCH_TCP_FIRST_FRAG);
2297 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2298 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2300 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2301 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2302 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2304 return ECORE_SUCCESS;
2307 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2308 struct ecore_ptt *p_ptt,
2311 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2313 /* Configure the PF's internal FID_enable for master transactions */
2314 ecore_wr(p_hwfn, p_ptt,
2315 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2317 /* Wait until value is set - try for 1 second every 50us */
2318 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2319 val = ecore_rd(p_hwfn, p_ptt,
2320 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2327 if (val != set_val) {
2328 DP_NOTICE(p_hwfn, true,
2329 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2330 return ECORE_UNKNOWN_ERROR;
2333 return ECORE_SUCCESS;
2336 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2337 struct ecore_ptt *p_main_ptt)
2339 /* Read shadow of current MFW mailbox */
2340 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2341 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2342 p_hwfn->mcp_info->mfw_mb_cur,
2343 p_hwfn->mcp_info->mfw_mb_length);
2346 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2347 struct ecore_ptt *p_ptt)
2349 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2350 1 << p_hwfn->abs_pf_id);
2353 static enum _ecore_status_t
2354 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
2355 struct ecore_load_req_params *p_load_req,
2356 struct ecore_drv_load_params *p_drv_load)
2358 /* Make sure that if ecore-client didn't provide inputs, all the
2359 * expected defaults are indeed zero.
2361 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2362 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2363 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2365 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2367 if (p_drv_load == OSAL_NULL)
2370 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2371 ECORE_DRV_ROLE_KDUMP :
2373 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2374 p_load_req->override_force_load = p_drv_load->override_force_load;
2376 /* Old MFW versions don't support timeout values other than default and
2377 * none, so these values are replaced according to the fall-back action.
2380 if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
2381 p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
2382 (p_hwfn->mcp_info->capabilities &
2383 FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
2384 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2388 switch (p_drv_load->mfw_timeout_fallback) {
2389 case ECORE_TO_FALLBACK_TO_NONE:
2390 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
2392 case ECORE_TO_FALLBACK_TO_DEFAULT:
2393 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
2395 case ECORE_TO_FALLBACK_FAIL_LOAD:
2396 DP_NOTICE(p_hwfn, false,
2397 "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
2398 p_drv_load->mfw_timeout_val,
2399 ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
2400 ECORE_LOAD_REQ_LOCK_TO_NONE);
2401 return ECORE_ABORTED;
2405 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
2406 p_drv_load->mfw_timeout_val,
2407 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
2409 p_load_req->timeout_val);
2411 return ECORE_SUCCESS;
2414 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2415 struct ecore_hw_init_params *p_params)
2417 if (p_params->p_tunn) {
2418 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2419 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2422 p_hwfn->b_int_enabled = 1;
2424 return ECORE_SUCCESS;
2427 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2428 struct ecore_hw_init_params *p_params)
2430 struct ecore_load_req_params load_req_params;
2431 u32 load_code, resp, param, drv_mb_param;
2432 bool b_default_mtu = true;
2433 struct ecore_hwfn *p_hwfn;
2434 enum _ecore_status_t rc = ECORE_SUCCESS;
2438 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2439 DP_NOTICE(p_dev, false,
2440 "MSI mode is not supported for CMT devices\n");
2445 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2446 if (rc != ECORE_SUCCESS)
2450 for_each_hwfn(p_dev, i) {
2451 p_hwfn = &p_dev->hwfns[i];
2453 /* If management didn't provide a default, set one of our own */
2454 if (!p_hwfn->hw_info.mtu) {
2455 p_hwfn->hw_info.mtu = 1500;
2456 b_default_mtu = false;
2460 ecore_vf_start(p_hwfn, p_params);
2464 rc = ecore_calc_hw_mode(p_hwfn);
2465 if (rc != ECORE_SUCCESS)
2468 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
2470 OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
2471 &p_dev->mf_bits))) {
2472 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
2474 ether_type = ETHER_TYPE_VLAN;
2476 ether_type = ETHER_TYPE_QINQ;
2477 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2479 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2481 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2483 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
2487 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
2489 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
2490 p_params->p_drv_load_params);
2491 if (rc != ECORE_SUCCESS)
2494 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2496 if (rc != ECORE_SUCCESS) {
2497 DP_NOTICE(p_hwfn, false,
2498 "Failed sending a LOAD_REQ command\n");
2502 load_code = load_req_params.load_code;
2503 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2504 "Load request was sent. Load code: 0x%x\n",
2507 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2510 * When coming back from hiberbate state, the registers from
2511 * which shadow is read initially are not initialized. It turns
2512 * out that these registers get initialized during the call to
2513 * ecore_mcp_load_req request. So we need to reread them here
2514 * to get the proper shadow register value.
2515 * Note: This is a workaround for the missing MFW
2516 * initialization. It may be removed once the implementation
2519 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2521 /* Only relevant for recovery:
2522 * Clear the indication after the LOAD_REQ command is responded
2525 p_dev->recov_in_prog = false;
2527 p_hwfn->first_on_engine = (load_code ==
2528 FW_MSG_CODE_DRV_LOAD_ENGINE);
2530 if (!qm_lock_ref_cnt) {
2531 #ifdef CONFIG_ECORE_LOCK_ALLOC
2532 rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
2534 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
2538 OSAL_SPIN_LOCK_INIT(&qm_lock);
2542 /* Clean up chip from previous driver if such remains exist.
2543 * This is not needed when the PF is the first one on the
2544 * engine, since afterwards we are going to init the FW.
2546 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2547 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2548 p_hwfn->rel_pf_id, false);
2549 if (rc != ECORE_SUCCESS) {
2550 ecore_hw_err_notify(p_hwfn,
2551 ECORE_HW_ERR_RAMROD_FAIL);
2556 /* Log and clear previous pglue_b errors if such exist */
2557 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
2559 /* Enable the PF's internal FID_enable in the PXP */
2560 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2562 if (rc != ECORE_SUCCESS)
2565 /* Clear the pglue_b was_error indication.
2566 * In E4 it must be done after the BME and the internal
2567 * FID_enable for the PF are set, since VDMs may cause the
2568 * indication to be set again.
2570 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2572 switch (load_code) {
2573 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2574 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2575 p_hwfn->hw_info.hw_mode);
2576 if (rc != ECORE_SUCCESS)
2579 case FW_MSG_CODE_DRV_LOAD_PORT:
2580 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2581 p_hwfn->hw_info.hw_mode);
2582 if (rc != ECORE_SUCCESS)
2585 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2586 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2588 p_hwfn->hw_info.hw_mode,
2589 p_params->b_hw_start,
2591 p_params->allow_npar_tx_switch);
2594 DP_NOTICE(p_hwfn, false,
2595 "Unexpected load code [0x%08x]", load_code);
2600 if (rc != ECORE_SUCCESS) {
2601 DP_NOTICE(p_hwfn, false,
2602 "init phase failed for loadcode 0x%x (rc %d)\n",
2607 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2608 if (rc != ECORE_SUCCESS) {
2609 DP_NOTICE(p_hwfn, false,
2610 "Sending load done failed, rc = %d\n", rc);
2611 if (rc == ECORE_NOMEM) {
2612 DP_NOTICE(p_hwfn, false,
2613 "Sending load done was failed due to memory allocation failure\n");
2619 /* send DCBX attention request command */
2620 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2621 "sending phony dcbx set command to trigger DCBx attention handling\n");
2622 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2623 DRV_MSG_CODE_SET_DCBX,
2624 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2626 if (rc != ECORE_SUCCESS) {
2627 DP_NOTICE(p_hwfn, false,
2628 "Failed to send DCBX attention request\n");
2632 p_hwfn->hw_init_done = true;
2636 /* Get pre-negotiated values for stag, bandwidth etc. */
2637 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2638 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
2639 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
2640 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2641 DRV_MSG_CODE_GET_OEM_UPDATES,
2642 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
2644 if (rc != ECORE_SUCCESS)
2645 DP_NOTICE(p_hwfn, false,
2646 "Failed to send GET_OEM_UPDATES attention request\n");
2650 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2651 drv_mb_param = STORM_FW_VERSION;
2652 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2653 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2654 drv_mb_param, &resp, ¶m);
2655 if (rc != ECORE_SUCCESS)
2656 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2658 if (!b_default_mtu) {
2659 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2660 p_hwfn->hw_info.mtu);
2661 if (rc != ECORE_SUCCESS)
2662 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2665 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2667 ECORE_OV_DRIVER_STATE_DISABLED);
2668 if (rc != ECORE_SUCCESS)
2669 DP_INFO(p_hwfn, "Failed to update driver state\n");
2671 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
2672 ECORE_OV_ESWITCH_NONE);
2673 if (rc != ECORE_SUCCESS)
2674 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
2681 #ifdef CONFIG_ECORE_LOCK_ALLOC
2682 if (!qm_lock_ref_cnt)
2683 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2686 /* The MFW load lock should be released regardless of success or failure
2687 * of initialization.
2688 * TODO: replace this with an attempt to send cancel_load.
2690 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2694 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2695 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2696 struct ecore_hwfn *p_hwfn,
2697 struct ecore_ptt *p_ptt)
2702 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2703 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2704 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2706 if ((!ecore_rd(p_hwfn, p_ptt,
2707 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2708 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2711 /* Dependent on number of connection/tasks, possibly
2712 * 1ms sleep is required between polls
2717 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2720 DP_NOTICE(p_hwfn, false,
2721 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
2722 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2723 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2726 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2730 for_each_hwfn(p_dev, j) {
2731 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2732 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2734 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2738 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2739 struct ecore_ptt *p_ptt,
2740 u32 addr, u32 expected_val)
2742 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2744 if (val != expected_val) {
2745 DP_NOTICE(p_hwfn, true,
2746 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2747 addr, val, expected_val);
2748 return ECORE_UNKNOWN_ERROR;
2751 return ECORE_SUCCESS;
2754 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2756 struct ecore_hwfn *p_hwfn;
2757 struct ecore_ptt *p_ptt;
2758 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2761 for_each_hwfn(p_dev, j) {
2762 p_hwfn = &p_dev->hwfns[j];
2763 p_ptt = p_hwfn->p_main_ptt;
2765 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2768 ecore_vf_pf_int_cleanup(p_hwfn);
2769 rc = ecore_vf_pf_reset(p_hwfn);
2770 if (rc != ECORE_SUCCESS) {
2771 DP_NOTICE(p_hwfn, true,
2772 "ecore_vf_pf_reset failed. rc = %d.\n",
2774 rc2 = ECORE_UNKNOWN_ERROR;
2779 /* mark the hw as uninitialized... */
2780 p_hwfn->hw_init_done = false;
2782 /* Send unload command to MCP */
2783 if (!p_dev->recov_in_prog) {
2784 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2785 if (rc != ECORE_SUCCESS) {
2786 DP_NOTICE(p_hwfn, false,
2787 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2789 rc2 = ECORE_UNKNOWN_ERROR;
2793 OSAL_DPC_SYNC(p_hwfn);
2795 /* After this point no MFW attentions are expected, e.g. prevent
2796 * race between pf stop and dcbx pf update.
2799 rc = ecore_sp_pf_stop(p_hwfn);
2800 if (rc != ECORE_SUCCESS) {
2801 DP_NOTICE(p_hwfn, false,
2802 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2804 rc2 = ECORE_UNKNOWN_ERROR;
2807 OSAL_DPC_SYNC(p_hwfn);
2809 /* After this point we don't expect the FW to send us async
2813 /* perform debug action after PF stop was sent */
2814 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2816 /* close NIG to BRB gate */
2817 ecore_wr(p_hwfn, p_ptt,
2818 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2821 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2822 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2823 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2824 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2825 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2827 /* @@@TBD - clean transmission queues (5.b) */
2828 /* @@@TBD - clean BTB (5.c) */
2830 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2832 /* @@@TBD - verify DMAE requests are done (8) */
2834 /* Disable Attention Generation */
2835 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2836 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2837 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2838 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2839 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2840 if (rc != ECORE_SUCCESS) {
2841 DP_NOTICE(p_hwfn, true,
2842 "Failed to return IGU CAM to default\n");
2843 rc2 = ECORE_UNKNOWN_ERROR;
2846 /* Need to wait 1ms to guarantee SBs are cleared */
2849 if (!p_dev->recov_in_prog) {
2850 ecore_verify_reg_val(p_hwfn, p_ptt,
2851 QM_REG_USG_CNT_PF_TX, 0);
2852 ecore_verify_reg_val(p_hwfn, p_ptt,
2853 QM_REG_USG_CNT_PF_OTHER, 0);
2854 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2857 /* Disable PF in HW blocks */
2858 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2859 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2862 #ifdef CONFIG_ECORE_LOCK_ALLOC
2863 if (!qm_lock_ref_cnt)
2864 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2867 if (!p_dev->recov_in_prog) {
2868 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2869 if (rc == ECORE_NOMEM) {
2870 DP_NOTICE(p_hwfn, false,
2871 "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
2872 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2874 if (rc != ECORE_SUCCESS) {
2875 DP_NOTICE(p_hwfn, false,
2876 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2878 rc2 = ECORE_UNKNOWN_ERROR;
2883 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2884 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2885 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2887 /* Clear the PF's internal FID_enable in the PXP.
2888 * In CMT this should only be done for first hw-function, and
2889 * only after all transactions have stopped for all active
2892 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2894 if (rc != ECORE_SUCCESS) {
2895 DP_NOTICE(p_hwfn, true,
2896 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2898 rc2 = ECORE_UNKNOWN_ERROR;
2905 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2909 for_each_hwfn(p_dev, j) {
2910 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2911 struct ecore_ptt *p_ptt;
2914 ecore_vf_pf_int_cleanup(p_hwfn);
2917 p_ptt = ecore_ptt_acquire(p_hwfn);
2921 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2922 "Shutting down the fastpath\n");
2924 ecore_wr(p_hwfn, p_ptt,
2925 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2927 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2928 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2929 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2930 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2931 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2933 /* @@@TBD - clean transmission queues (5.b) */
2934 /* @@@TBD - clean BTB (5.c) */
2936 /* @@@TBD - verify DMAE requests are done (8) */
2938 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2939 /* Need to wait 1ms to guarantee SBs are cleared */
2941 ecore_ptt_release(p_hwfn, p_ptt);
2944 return ECORE_SUCCESS;
2947 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2949 struct ecore_ptt *p_ptt;
2951 if (IS_VF(p_hwfn->p_dev))
2952 return ECORE_SUCCESS;
2954 p_ptt = ecore_ptt_acquire(p_hwfn);
2958 /* If roce info is allocated it means roce is initialized and should
2959 * be enabled in searcher.
2961 if (p_hwfn->p_rdma_info) {
2962 if (p_hwfn->b_rdma_enabled_in_prs)
2963 ecore_wr(p_hwfn, p_ptt,
2964 p_hwfn->rdma_prs_search_reg, 0x1);
2965 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2968 /* Re-open incoming traffic */
2969 ecore_wr(p_hwfn, p_ptt,
2970 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2971 ecore_ptt_release(p_hwfn, p_ptt);
2973 return ECORE_SUCCESS;
2976 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2977 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2979 ecore_ptt_pool_free(p_hwfn);
2980 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2983 /* Setup bar access */
2984 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2986 /* clear indirect access */
2987 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2988 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2989 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2990 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2991 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2992 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2993 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2994 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2995 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2997 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2998 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2999 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3000 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
3001 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3002 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
3003 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3004 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
3007 /* Clean previous pglue_b errors if such exist */
3008 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3010 /* enable internal target-read */
3011 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3012 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3015 static void get_function_id(struct ecore_hwfn *p_hwfn)
3018 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
3019 PXP_PF_ME_OPAQUE_ADDR);
3021 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3023 /* Bits 16-19 from the ME registers are the pf_num */
3024 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3025 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3026 PXP_CONCRETE_FID_PFID);
3027 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3028 PXP_CONCRETE_FID_PORT);
3030 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3031 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3032 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3035 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
3037 u32 *feat_num = p_hwfn->hw_info.feat_num;
3038 struct ecore_sb_cnt_info sb_cnt;
3041 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
3042 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
3044 /* L2 Queues require each: 1 status block. 1 L2 queue */
3045 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
3046 /* Start by allocating VF queues, then PF's */
3047 feat_num[ECORE_VF_L2_QUE] =
3049 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
3051 feat_num[ECORE_PF_L2_QUE] =
3053 sb_cnt.cnt - non_l2_sbs,
3054 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
3055 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
3058 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
3059 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) {
3060 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ?
3061 &feat_num[ECORE_FCOE_CQ] :
3062 &feat_num[ECORE_ISCSI_CQ];
3063 u32 limit = sb_cnt.cnt;
3065 /* The number of queues should not exceed the number of FP SBs.
3066 * In storage target, the queues are divided into pairs of a CQ
3067 * and a CmdQ, and each pair uses a single SB. The limit in
3068 * this case should allow a max ratio of 2:1 instead of 1:1.
3070 if (p_hwfn->p_dev->b_is_target)
3072 *p_storage_feat = OSAL_MIN_T(u32, limit,
3073 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
3076 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init
3077 * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2".
3079 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat,
3080 (NUM_OF_GLOBAL_QUEUES / 2));
3083 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3084 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
3085 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
3086 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
3087 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
3088 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
3089 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
3093 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
3096 case ECORE_L2_QUEUE:
3110 case ECORE_RDMA_CNQ_RAM:
3111 return "RDMA_CNQ_RAM";
3114 case ECORE_LL2_QUEUE:
3116 case ECORE_CMDQS_CQS:
3118 case ECORE_RDMA_STATS_QUEUE:
3119 return "RDMA_STATS_QUEUE";
3125 return "UNKNOWN_RESOURCE";
3129 static enum _ecore_status_t
3130 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3131 struct ecore_ptt *p_ptt,
3132 enum ecore_resources res_id,
3136 enum _ecore_status_t rc;
3138 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3139 resc_max_val, p_mcp_resp);
3140 if (rc != ECORE_SUCCESS) {
3141 DP_NOTICE(p_hwfn, false,
3142 "MFW response failure for a max value setting of resource %d [%s]\n",
3143 res_id, ecore_hw_get_resc_name(res_id));
3147 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3149 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3150 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
3152 return ECORE_SUCCESS;
3155 static enum _ecore_status_t
3156 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3157 struct ecore_ptt *p_ptt)
3159 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3160 u32 resc_max_val, mcp_resp;
3162 enum _ecore_status_t rc;
3164 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3167 case ECORE_LL2_QUEUE:
3168 case ECORE_RDMA_CNQ_RAM:
3169 case ECORE_RDMA_STATS_QUEUE:
3177 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3178 resc_max_val, &mcp_resp);
3179 if (rc != ECORE_SUCCESS)
3182 /* There's no point to continue to the next resource if the
3183 * command is not supported by the MFW.
3184 * We do continue if the command is supported but the resource
3185 * is unknown to the MFW. Such a resource will be later
3186 * configured with the default allocation values.
3188 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3189 return ECORE_NOTIMPL;
3192 return ECORE_SUCCESS;
3196 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3197 enum ecore_resources res_id,
3198 u32 *p_resc_num, u32 *p_resc_start)
3200 u8 num_funcs = p_hwfn->num_funcs_on_engine;
3201 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3204 case ECORE_L2_QUEUE:
3205 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3206 MAX_NUM_L2_QUEUES_BB) / num_funcs;
3209 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3210 MAX_NUM_VPORTS_BB) / num_funcs;
3213 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3214 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3217 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3218 MAX_QM_TX_QUEUES_BB) / num_funcs;
3221 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3225 /* Each VFC resource can accommodate both a MAC and a VLAN */
3226 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3229 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3230 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3232 case ECORE_LL2_QUEUE:
3233 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3235 case ECORE_RDMA_CNQ_RAM:
3236 case ECORE_CMDQS_CQS:
3237 /* CNQ/CMDQS are the same resource */
3239 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3241 case ECORE_RDMA_STATS_QUEUE:
3243 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3244 MAX_NUM_VPORTS_BB) / num_funcs;
3261 /* Since we want its value to reflect whether MFW supports
3262 * the new scheme, have a default of 0.
3267 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3271 return ECORE_SUCCESS;
3274 static enum _ecore_status_t
3275 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3276 bool drv_resc_alloc)
3278 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3279 u32 mcp_resp, *p_resc_num, *p_resc_start;
3280 enum _ecore_status_t rc;
3282 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3283 p_resc_start = &RESC_START(p_hwfn, res_id);
3285 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3287 if (rc != ECORE_SUCCESS) {
3289 "Failed to get default amount for resource %d [%s]\n",
3290 res_id, ecore_hw_get_resc_name(res_id));
3295 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3296 *p_resc_num = dflt_resc_num;
3297 *p_resc_start = dflt_resc_start;
3302 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3303 &mcp_resp, p_resc_num, p_resc_start);
3304 if (rc != ECORE_SUCCESS) {
3305 DP_NOTICE(p_hwfn, true,
3306 "MFW response failure for an allocation request for"
3307 " resource %d [%s]\n",
3308 res_id, ecore_hw_get_resc_name(res_id));
3312 /* Default driver values are applied in the following cases:
3313 * - The resource allocation MB command is not supported by the MFW
3314 * - There is an internal error in the MFW while processing the request
3315 * - The resource ID is unknown to the MFW
3317 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3319 "Failed to receive allocation info for resource %d [%s]."
3320 " mcp_resp = 0x%x. Applying default values"
3322 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3323 dflt_resc_num, dflt_resc_start);
3325 *p_resc_num = dflt_resc_num;
3326 *p_resc_start = dflt_resc_start;
3330 if ((*p_resc_num != dflt_resc_num ||
3331 *p_resc_start != dflt_resc_start) &&
3332 res_id != ECORE_SB) {
3334 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3335 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3336 *p_resc_start, dflt_resc_num, dflt_resc_start,
3337 drv_resc_alloc ? " - Applying default values" : "");
3338 if (drv_resc_alloc) {
3339 *p_resc_num = dflt_resc_num;
3340 *p_resc_start = dflt_resc_start;
3344 return ECORE_SUCCESS;
3347 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3348 bool drv_resc_alloc)
3350 enum _ecore_status_t rc;
3353 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3354 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3355 if (rc != ECORE_SUCCESS)
3359 return ECORE_SUCCESS;
3362 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3363 struct ecore_ptt *p_ptt,
3364 bool drv_resc_alloc)
3366 struct ecore_resc_unlock_params resc_unlock_params;
3367 struct ecore_resc_lock_params resc_lock_params;
3368 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3370 enum _ecore_status_t rc;
3372 u32 *resc_start = p_hwfn->hw_info.resc_start;
3373 u32 *resc_num = p_hwfn->hw_info.resc_num;
3374 /* For AH, an equal share of the ILT lines between the maximal number of
3375 * PFs is not enough for RoCE. This would be solved by the future
3376 * resource allocation scheme, but isn't currently present for
3377 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3378 * to work - the BB number of ILT lines divided by its max PFs number.
3380 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3383 /* Setting the max values of the soft resources and the following
3384 * resources allocation queries should be atomic. Since several PFs can
3385 * run in parallel - a resource lock is needed.
3386 * If either the resource lock or resource set value commands are not
3387 * supported - skip the max values setting, release the lock if
3388 * needed, and proceed to the queries. Other failures, including a
3389 * failure to acquire the lock, will cause this function to fail.
3390 * Old drivers that don't acquire the lock can run in parallel, and
3391 * their allocation values won't be affected by the updated max values.
3393 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3394 ECORE_RESC_LOCK_RESC_ALLOC, false);
3396 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3397 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3399 } else if (rc == ECORE_NOTIMPL) {
3401 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3402 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3403 DP_NOTICE(p_hwfn, false,
3404 "Failed to acquire the resource lock for the resource allocation commands\n");
3406 goto unlock_and_exit;
3408 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3409 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3410 DP_NOTICE(p_hwfn, false,
3411 "Failed to set the max values of the soft resources\n");
3412 goto unlock_and_exit;
3413 } else if (rc == ECORE_NOTIMPL) {
3415 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3416 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3417 &resc_unlock_params);
3418 if (rc != ECORE_SUCCESS)
3420 "Failed to release the resource lock for the resource allocation commands\n");
3424 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3425 if (rc != ECORE_SUCCESS)
3426 goto unlock_and_exit;
3428 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3429 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3430 &resc_unlock_params);
3431 if (rc != ECORE_SUCCESS)
3433 "Failed to release the resource lock for the resource allocation commands\n");
3437 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3438 /* Reduced build contains less PQs */
3439 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3440 resc_num[ECORE_PQ] = 32;
3441 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3442 p_hwfn->enabled_func_idx;
3445 /* For AH emulation, since we have a possible maximal number of
3446 * 16 enabled PFs, in case there are not enough ILT lines -
3447 * allocate only first PF as RoCE and have all the other ETH
3448 * only with less ILT lines.
3450 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3451 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3452 resc_num[ECORE_ILT],
3453 roce_min_ilt_lines);
3456 /* Correct the common ILT calculation if PF0 has more */
3457 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3458 p_hwfn->p_dev->b_is_emul_full &&
3459 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3460 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3461 resc_num[ECORE_ILT];
3464 /* Sanity for ILT */
3465 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3466 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3467 DP_NOTICE(p_hwfn, true,
3468 "Can't assign ILT pages [%08x,...,%08x]\n",
3469 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3475 /* This will also learn the number of SBs from MFW */
3476 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3479 ecore_hw_set_feat(p_hwfn);
3481 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3482 "The numbers for each resource are:\n");
3483 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3484 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3485 ecore_hw_get_resc_name(res_id),
3486 RESC_NUM(p_hwfn, res_id),
3487 RESC_START(p_hwfn, res_id));
3489 return ECORE_SUCCESS;
3492 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3493 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3494 &resc_unlock_params);
3498 static enum _ecore_status_t
3499 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3500 struct ecore_ptt *p_ptt,
3501 struct ecore_hw_prepare_params *p_params)
3503 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3504 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3505 struct ecore_mcp_link_capabilities *p_caps;
3506 struct ecore_mcp_link_params *link;
3507 enum _ecore_status_t rc;
3509 /* Read global nvm_cfg address */
3510 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3512 /* Verify MCP has initialized it */
3513 if (!nvm_cfg_addr) {
3514 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3515 if (p_params->b_relaxed_probe)
3516 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3520 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
3522 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3524 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3525 OFFSETOF(struct nvm_cfg1, glob) +
3526 OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3528 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3530 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3531 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3532 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3533 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3535 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3536 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3538 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3539 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3541 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3542 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3544 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3545 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3547 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3548 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3550 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3551 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3553 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3554 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3556 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3557 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3559 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3560 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3562 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3563 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3566 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3571 /* Read DCBX configuration */
3572 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3573 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3574 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3576 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3577 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3578 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3579 switch (dcbx_mode) {
3580 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3581 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3583 case NVM_CFG1_PORT_DCBX_MODE_CEE:
3584 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3586 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3587 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3590 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3593 /* Read default link configuration */
3594 link = &p_hwfn->mcp_info->link_input;
3595 p_caps = &p_hwfn->mcp_info->link_capabilities;
3596 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3597 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3598 link_temp = ecore_rd(p_hwfn, p_ptt,
3600 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3601 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3602 link->speed.advertised_speeds = link_temp;
3603 p_caps->speed_capabilities = link->speed.advertised_speeds;
3605 link_temp = ecore_rd(p_hwfn, p_ptt,
3607 OFFSETOF(struct nvm_cfg1_port, link_settings));
3608 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3609 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3610 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3611 link->speed.autoneg = true;
3613 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3614 link->speed.forced_speed = 1000;
3616 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3617 link->speed.forced_speed = 10000;
3619 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3620 link->speed.forced_speed = 25000;
3622 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3623 link->speed.forced_speed = 40000;
3625 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3626 link->speed.forced_speed = 50000;
3628 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3629 link->speed.forced_speed = 100000;
3632 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3635 p_caps->default_speed = link->speed.forced_speed;
3636 p_caps->default_speed_autoneg = link->speed.autoneg;
3638 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3639 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3640 link->pause.autoneg = !!(link_temp &
3641 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3642 link->pause.forced_rx = !!(link_temp &
3643 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3644 link->pause.forced_tx = !!(link_temp &
3645 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3646 link->loopback_mode = 0;
3648 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3649 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3650 OFFSETOF(struct nvm_cfg1_port, ext_phy));
3651 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3652 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3653 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3654 link->eee.enable = true;
3655 switch (link_temp) {
3656 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3657 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3658 link->eee.enable = false;
3660 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3661 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3663 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3664 p_caps->eee_lpi_timer =
3665 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3667 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3668 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3672 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3673 link->eee.tx_lpi_enable = link->eee.enable;
3674 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3676 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3679 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3680 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3681 link->speed.forced_speed, link->speed.advertised_speeds,
3682 link->speed.autoneg, link->pause.autoneg,
3683 p_caps->default_eee, p_caps->eee_lpi_timer);
3685 /* Read Multi-function information from shmem */
3686 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3687 OFFSETOF(struct nvm_cfg1, glob) +
3688 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3690 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3692 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3693 NVM_CFG1_GLOB_MF_MODE_OFFSET;
3696 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3697 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3699 case NVM_CFG1_GLOB_MF_MODE_UFP:
3700 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3701 1 << ECORE_MF_UFP_SPECIFIC |
3702 1 << ECORE_MF_8021Q_TAGGING;
3704 case NVM_CFG1_GLOB_MF_MODE_BD:
3705 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3706 1 << ECORE_MF_LLH_PROTO_CLSS |
3707 1 << ECORE_MF_8021AD_TAGGING;
3709 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3710 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3711 1 << ECORE_MF_LLH_PROTO_CLSS |
3712 1 << ECORE_MF_LL2_NON_UNICAST |
3713 1 << ECORE_MF_INTER_PF_SWITCH |
3714 1 << ECORE_MF_DISABLE_ARFS;
3716 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3717 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3718 1 << ECORE_MF_LLH_PROTO_CLSS |
3719 1 << ECORE_MF_LL2_NON_UNICAST;
3720 if (ECORE_IS_BB(p_hwfn->p_dev))
3721 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3724 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3725 p_hwfn->p_dev->mf_bits);
3727 if (ECORE_IS_CMT(p_hwfn->p_dev))
3728 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3730 /* It's funny since we have another switch, but it's easier
3731 * to throw this away in linux this way. Long term, it might be
3732 * better to have have getters for needed ECORE_MF_* fields,
3733 * convert client code and eliminate this.
3736 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3737 case NVM_CFG1_GLOB_MF_MODE_BD:
3738 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3740 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3741 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3743 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3744 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3746 case NVM_CFG1_GLOB_MF_MODE_UFP:
3747 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3751 /* Read Multi-function information from shmem */
3752 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3753 OFFSETOF(struct nvm_cfg1, glob) +
3754 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3756 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3757 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3758 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3759 &p_hwfn->hw_info.device_capabilities);
3760 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3761 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3762 &p_hwfn->hw_info.device_capabilities);
3763 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3764 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3765 &p_hwfn->hw_info.device_capabilities);
3766 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3767 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3768 &p_hwfn->hw_info.device_capabilities);
3769 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3770 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3771 &p_hwfn->hw_info.device_capabilities);
3773 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3774 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3776 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3782 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3783 struct ecore_ptt *p_ptt)
3785 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3786 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3787 struct ecore_dev *p_dev = p_hwfn->p_dev;
3789 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3791 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3792 * in the other bits are selected.
3793 * Bits 1-15 are for functions 1-15, respectively, and their value is
3794 * '0' only for enabled functions (function 0 always exists and
3796 * In case of CMT in BB, only the "even" functions are enabled, and thus
3797 * the number of functions for both hwfns is learnt from the same bits.
3799 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3800 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3801 MISCS_REG_FUNCTION_HIDE_BB_K2);
3803 reg_function_hide = 0;
3806 if (reg_function_hide & 0x1) {
3807 if (ECORE_IS_BB(p_dev)) {
3808 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3820 /* Get the number of the enabled functions on the engine */
3821 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3828 /* Get the PF index within the enabled functions */
3829 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3830 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3838 p_hwfn->num_funcs_on_engine = num_funcs;
3839 p_hwfn->enabled_func_idx = enabled_func_idx;
3842 if (CHIP_REV_IS_FPGA(p_dev)) {
3843 DP_NOTICE(p_hwfn, false,
3844 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3845 p_hwfn->num_funcs_on_engine = 4;
3849 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3850 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3851 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3852 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3855 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3856 struct ecore_ptt *p_ptt)
3858 struct ecore_dev *p_dev = p_hwfn->p_dev;
3862 /* Read the port mode */
3863 if (CHIP_REV_IS_FPGA(p_dev))
3865 else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3866 /* In CMT on emulation, assume 1 port */
3870 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3872 if (port_mode < 3) {
3873 p_dev->num_ports_in_engine = 1;
3874 } else if (port_mode <= 5) {
3875 p_dev->num_ports_in_engine = 2;
3877 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3878 p_dev->num_ports_in_engine);
3880 /* Default num_ports_in_engine to something */
3881 p_dev->num_ports_in_engine = 1;
3885 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3886 struct ecore_ptt *p_ptt)
3888 struct ecore_dev *p_dev = p_hwfn->p_dev;
3892 p_dev->num_ports_in_engine = 0;
3895 if (CHIP_REV_IS_EMUL(p_dev)) {
3896 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3897 switch ((port & 0xf000) >> 12) {
3899 p_dev->num_ports_in_engine = 1;
3902 p_dev->num_ports_in_engine = 2;
3905 p_dev->num_ports_in_engine = 4;
3908 DP_NOTICE(p_hwfn, false,
3909 "Unknown port mode in ECO_RESERVED %08x\n",
3914 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3915 port = ecore_rd(p_hwfn, p_ptt,
3916 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3919 p_dev->num_ports_in_engine++;
3922 if (!p_dev->num_ports_in_engine) {
3923 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3925 /* Default num_ports_in_engine to something */
3926 p_dev->num_ports_in_engine = 1;
3930 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3931 struct ecore_ptt *p_ptt)
3933 struct ecore_dev *p_dev = p_hwfn->p_dev;
3935 /* Determine the number of ports per engine */
3936 if (ECORE_IS_BB(p_dev))
3937 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3939 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3941 /* Get the total number of ports of the device */
3942 if (ECORE_IS_CMT(p_dev)) {
3943 /* In CMT there is always only one port */
3944 p_dev->num_ports = 1;
3946 } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3947 p_dev->num_ports = p_dev->num_ports_in_engine *
3948 ecore_device_num_engines(p_dev);
3951 u32 addr, global_offsize, global_addr;
3953 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3955 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3956 global_addr = SECTION_ADDR(global_offsize, 0);
3957 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3958 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3962 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3963 struct ecore_ptt *p_ptt)
3965 struct ecore_mcp_link_capabilities *p_caps;
3968 p_caps = &p_hwfn->mcp_info->link_capabilities;
3969 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3972 p_caps->eee_speed_caps = 0;
3973 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3974 OFFSETOF(struct public_port, eee_status));
3975 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3976 EEE_SUPPORTED_SPEED_OFFSET;
3977 if (eee_status & EEE_1G_SUPPORTED)
3978 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3979 if (eee_status & EEE_10G_ADV)
3980 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3983 static enum _ecore_status_t
3984 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3985 enum ecore_pci_personality personality,
3986 struct ecore_hw_prepare_params *p_params)
3988 bool drv_resc_alloc = p_params->drv_resc_alloc;
3989 enum _ecore_status_t rc;
3991 if (IS_ECORE_PACING(p_hwfn)) {
3992 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV,
3993 "Skipping IOV as packet pacing is requested\n");
3996 /* Since all information is common, only first hwfns should do this */
3997 if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) {
3998 rc = ecore_iov_hw_info(p_hwfn);
3999 if (rc != ECORE_SUCCESS) {
4000 if (p_params->b_relaxed_probe)
4001 p_params->p_relaxed_res =
4002 ECORE_HW_PREPARE_BAD_IOV;
4008 if (IS_LEAD_HWFN(p_hwfn))
4009 ecore_hw_info_port_num(p_hwfn, p_ptt);
4011 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
4014 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
4016 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
4017 if (rc != ECORE_SUCCESS)
4023 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
4024 if (rc != ECORE_SUCCESS) {
4025 if (p_params->b_relaxed_probe)
4026 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
4032 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
4034 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
4035 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
4038 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
4040 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
4041 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
4045 if (ecore_mcp_is_init(p_hwfn)) {
4046 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
4047 p_hwfn->hw_info.ovlan =
4048 p_hwfn->mcp_info->func_info.ovlan;
4050 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
4052 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
4054 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
4057 if (personality != ECORE_PCI_DEFAULT) {
4058 p_hwfn->hw_info.personality = personality;
4059 } else if (ecore_mcp_is_init(p_hwfn)) {
4060 enum ecore_pci_personality protocol;
4062 protocol = p_hwfn->mcp_info->func_info.protocol;
4063 p_hwfn->hw_info.personality = protocol;
4067 /* To overcome ILT lack for emulation, until at least until we'll have
4068 * a definite answer from system about it, allow only PF0 to be RoCE.
4070 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
4071 if (!p_hwfn->rel_pf_id)
4072 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
4074 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
4078 /* although in BB some constellations may support more than 4 tcs,
4079 * that can result in performance penalty in some cases. 4
4080 * represents a good tradeoff between performance and flexibility.
4082 if (IS_ECORE_PACING(p_hwfn))
4083 p_hwfn->hw_info.num_hw_tc = 1;
4085 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4087 /* start out with a single active tc. This can be increased either
4088 * by dcbx negotiation or by upper layer driver
4090 p_hwfn->hw_info.num_active_tc = 1;
4092 ecore_get_num_funcs(p_hwfn, p_ptt);
4094 if (ecore_mcp_is_init(p_hwfn))
4095 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4097 /* In case of forcing the driver's default resource allocation, calling
4098 * ecore_hw_get_resc() should come after initializing the personality
4099 * and after getting the number of functions, since the calculation of
4100 * the resources/features depends on them.
4101 * This order is not harmful if not forcing.
4103 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
4104 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
4106 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
4112 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
4113 struct ecore_ptt *p_ptt)
4115 struct ecore_dev *p_dev = p_hwfn->p_dev;
4119 /* Read Vendor Id / Device Id */
4120 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
4122 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
4125 /* Determine type */
4126 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
4127 switch (device_id_mask) {
4128 case ECORE_DEV_ID_MASK_BB:
4129 p_dev->type = ECORE_DEV_TYPE_BB;
4131 case ECORE_DEV_ID_MASK_AH:
4132 p_dev->type = ECORE_DEV_TYPE_AH;
4135 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
4137 return ECORE_ABORTED;
4140 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4141 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
4142 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4143 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
4145 /* Learn number of HW-functions */
4146 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4148 if (tmp & (1 << p_hwfn->rel_pf_id)) {
4149 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
4150 p_dev->num_hwfns = 2;
4152 p_dev->num_hwfns = 1;
4156 if (CHIP_REV_IS_EMUL(p_dev)) {
4157 /* For some reason we have problems with this register
4158 * in B0 emulation; Simply assume no CMT
4160 DP_NOTICE(p_dev->hwfns, false,
4161 "device on emul - assume no CMT\n");
4162 p_dev->num_hwfns = 1;
4166 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
4167 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
4168 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4169 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
4171 DP_INFO(p_dev->hwfns,
4172 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
4173 ECORE_IS_BB(p_dev) ? "BB" : "AH",
4174 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
4175 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
4178 if (ECORE_IS_BB_A0(p_dev)) {
4179 DP_NOTICE(p_dev->hwfns, false,
4180 "The chip type/rev (BB A0) is not supported!\n");
4181 return ECORE_ABORTED;
4184 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
4185 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
4187 if (CHIP_REV_IS_EMUL(p_dev)) {
4188 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
4189 if (tmp & (1 << 29)) {
4190 DP_NOTICE(p_hwfn, false,
4191 "Emulation: Running on a FULL build\n");
4192 p_dev->b_is_emul_full = true;
4194 DP_NOTICE(p_hwfn, false,
4195 "Emulation: Running on a REDUCED build\n");
4200 return ECORE_SUCCESS;
4203 #ifndef LINUX_REMOVE
4204 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
4211 for_each_hwfn(p_dev, j) {
4212 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4214 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4215 "Mark hw/fw uninitialized\n");
4217 p_hwfn->hw_init_done = false;
4219 ecore_ptt_invalidate(p_hwfn);
4224 static enum _ecore_status_t
4225 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4226 void OSAL_IOMEM * p_regview,
4227 void OSAL_IOMEM * p_doorbells,
4228 struct ecore_hw_prepare_params *p_params)
4230 struct ecore_mdump_retain_data mdump_retain;
4231 struct ecore_dev *p_dev = p_hwfn->p_dev;
4232 struct ecore_mdump_info mdump_info;
4233 enum _ecore_status_t rc = ECORE_SUCCESS;
4235 /* Split PCI bars evenly between hwfns */
4236 p_hwfn->regview = p_regview;
4237 p_hwfn->doorbells = p_doorbells;
4240 return ecore_vf_hw_prepare(p_hwfn);
4242 /* Validate that chip access is feasible */
4243 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4245 "Reading the ME register returns all Fs; Preventing further chip access\n");
4246 if (p_params->b_relaxed_probe)
4247 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4251 get_function_id(p_hwfn);
4253 /* Allocate PTT pool */
4254 rc = ecore_ptt_pool_alloc(p_hwfn);
4256 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
4257 if (p_params->b_relaxed_probe)
4258 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4262 /* Allocate the main PTT */
4263 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4265 /* First hwfn learns basic information, e.g., number of hwfns */
4266 if (!p_hwfn->my_id) {
4267 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4268 if (rc != ECORE_SUCCESS) {
4269 if (p_params->b_relaxed_probe)
4270 p_params->p_relaxed_res =
4271 ECORE_HW_PREPARE_FAILED_DEV;
4276 ecore_hw_hwfn_prepare(p_hwfn);
4278 /* Initialize MCP structure */
4279 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4281 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
4282 if (p_params->b_relaxed_probe)
4283 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4287 /* Read the device configuration information from the HW and SHMEM */
4288 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4289 p_params->personality, p_params);
4291 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
4295 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4296 * called, since among others it sets the ports number in an engine.
4298 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4299 !p_dev->recov_in_prog) {
4300 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4301 if (rc != ECORE_SUCCESS)
4302 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4304 /* Workaround for MFW issue where PF FLR does not cleanup
4307 if (!(p_hwfn->mcp_info->capabilities &
4308 FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
4309 ecore_pf_flr_igu_cleanup(p_hwfn);
4312 /* Check if mdump logs/data are present and update the epoch value */
4313 if (IS_LEAD_HWFN(p_hwfn)) {
4315 if (!CHIP_REV_IS_EMUL(p_dev)) {
4317 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4319 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4320 DP_NOTICE(p_hwfn, false,
4321 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4323 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4325 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4326 DP_NOTICE(p_hwfn, false,
4327 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4328 mdump_retain.epoch, mdump_retain.pf,
4329 mdump_retain.status);
4331 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4338 /* Allocate the init RT array and initialize the init-ops engine */
4339 rc = ecore_init_alloc(p_hwfn);
4341 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
4342 if (p_params->b_relaxed_probe)
4343 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4347 if (CHIP_REV_IS_FPGA(p_dev)) {
4348 DP_NOTICE(p_hwfn, false,
4349 "FPGA: workaround; Prevent DMAE parities\n");
4350 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4353 DP_NOTICE(p_hwfn, false,
4354 "FPGA: workaround: Set VF bar0 size\n");
4355 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4356 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4362 if (IS_LEAD_HWFN(p_hwfn))
4363 ecore_iov_free_hw_info(p_dev);
4364 ecore_mcp_free(p_hwfn);
4366 ecore_hw_hwfn_free(p_hwfn);
4371 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4372 struct ecore_hw_prepare_params *p_params)
4374 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4375 enum _ecore_status_t rc;
4377 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4378 p_dev->allow_mdump = p_params->allow_mdump;
4379 p_hwfn->b_en_pacing = p_params->b_en_pacing;
4380 p_dev->b_is_target = p_params->b_is_target;
4382 if (p_params->b_relaxed_probe)
4383 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4385 /* Store the precompiled init data ptrs */
4387 ecore_init_iro_array(p_dev);
4389 /* Initialize the first hwfn - will learn number of hwfns */
4390 rc = ecore_hw_prepare_single(p_hwfn,
4392 p_dev->doorbells, p_params);
4393 if (rc != ECORE_SUCCESS)
4396 p_params->personality = p_hwfn->hw_info.personality;
4398 /* initilalize 2nd hwfn if necessary */
4399 if (ECORE_IS_CMT(p_dev)) {
4400 void OSAL_IOMEM *p_regview, *p_doorbell;
4401 u8 OSAL_IOMEM *addr;
4403 /* adjust bar offset for second engine */
4404 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4405 ecore_hw_bar_size(p_hwfn,
4408 p_regview = (void OSAL_IOMEM *)addr;
4410 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4411 ecore_hw_bar_size(p_hwfn,
4414 p_doorbell = (void OSAL_IOMEM *)addr;
4416 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;
4417 /* prepare second hw function */
4418 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4419 p_doorbell, p_params);
4421 /* in case of error, need to free the previously
4422 * initiliazed hwfn 0.
4424 if (rc != ECORE_SUCCESS) {
4425 if (p_params->b_relaxed_probe)
4426 p_params->p_relaxed_res =
4427 ECORE_HW_PREPARE_FAILED_ENG2;
4430 ecore_init_free(p_hwfn);
4431 ecore_mcp_free(p_hwfn);
4432 ecore_hw_hwfn_free(p_hwfn);
4434 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
4443 void ecore_hw_remove(struct ecore_dev *p_dev)
4445 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4449 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4450 ECORE_OV_DRIVER_STATE_NOT_LOADED);
4452 for_each_hwfn(p_dev, i) {
4453 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4456 ecore_vf_pf_release(p_hwfn);
4460 ecore_init_free(p_hwfn);
4461 ecore_hw_hwfn_free(p_hwfn);
4462 ecore_mcp_free(p_hwfn);
4464 #ifdef CONFIG_ECORE_LOCK_ALLOC
4465 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
4469 ecore_iov_free_hw_info(p_dev);
4472 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4473 struct ecore_chain *p_chain)
4475 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4476 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4477 struct ecore_chain_next *p_next;
4483 size = p_chain->elem_size * p_chain->usable_per_page;
4485 for (i = 0; i < p_chain->page_cnt; i++) {
4489 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4490 p_virt_next = p_next->next_virt;
4491 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4493 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4494 ECORE_CHAIN_PAGE_SIZE);
4496 p_virt = p_virt_next;
4497 p_phys = p_phys_next;
4501 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4502 struct ecore_chain *p_chain)
4504 if (!p_chain->p_virt_addr)
4507 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4508 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4511 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4512 struct ecore_chain *p_chain)
4514 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4515 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4516 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4518 if (!pp_virt_addr_tbl)
4524 for (i = 0; i < page_cnt; i++) {
4525 if (!pp_virt_addr_tbl[i])
4528 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4529 *(dma_addr_t *)p_pbl_virt,
4530 ECORE_CHAIN_PAGE_SIZE);
4532 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4535 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4537 if (!p_chain->b_external_pbl)
4538 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4539 p_chain->pbl_sp.p_phys_table, pbl_size);
4541 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4544 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4546 switch (p_chain->mode) {
4547 case ECORE_CHAIN_MODE_NEXT_PTR:
4548 ecore_chain_free_next_ptr(p_dev, p_chain);
4550 case ECORE_CHAIN_MODE_SINGLE:
4551 ecore_chain_free_single(p_dev, p_chain);
4553 case ECORE_CHAIN_MODE_PBL:
4554 ecore_chain_free_pbl(p_dev, p_chain);
4559 static enum _ecore_status_t
4560 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4561 enum ecore_chain_cnt_type cnt_type,
4562 osal_size_t elem_size, u32 page_cnt)
4564 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4566 /* The actual chain size can be larger than the maximal possible value
4567 * after rounding up the requested elements number to pages, and after
4568 * taking into acount the unusuable elements (next-ptr elements).
4569 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4570 * size/capacity fields are of a u32 type.
4572 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4573 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4574 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4575 chain_size > ECORE_U32_MAX)) {
4576 DP_NOTICE(p_dev, true,
4577 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4578 (unsigned long)chain_size);
4582 return ECORE_SUCCESS;
4585 static enum _ecore_status_t
4586 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4588 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4589 dma_addr_t p_phys = 0;
4592 for (i = 0; i < p_chain->page_cnt; i++) {
4593 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4594 ECORE_CHAIN_PAGE_SIZE);
4596 DP_NOTICE(p_dev, false,
4597 "Failed to allocate chain memory\n");
4602 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4603 ecore_chain_reset(p_chain);
4605 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4609 p_virt_prev = p_virt;
4611 /* Last page's next element should point to the beginning of the
4614 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4615 p_chain->p_virt_addr,
4616 p_chain->p_phys_addr);
4618 return ECORE_SUCCESS;
4621 static enum _ecore_status_t
4622 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4624 dma_addr_t p_phys = 0;
4625 void *p_virt = OSAL_NULL;
4627 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4629 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
4633 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4634 ecore_chain_reset(p_chain);
4636 return ECORE_SUCCESS;
4639 static enum _ecore_status_t
4640 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4641 struct ecore_chain *p_chain,
4642 struct ecore_chain_ext_pbl *ext_pbl)
4644 u32 page_cnt = p_chain->page_cnt, size, i;
4645 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4646 void **pp_virt_addr_tbl = OSAL_NULL;
4647 u8 *p_pbl_virt = OSAL_NULL;
4648 void *p_virt = OSAL_NULL;
4650 size = page_cnt * sizeof(*pp_virt_addr_tbl);
4651 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4652 if (!pp_virt_addr_tbl) {
4653 DP_NOTICE(p_dev, false,
4654 "Failed to allocate memory for the chain virtual addresses table\n");
4658 /* The allocation of the PBL table is done with its full size, since it
4659 * is expected to be successive.
4660 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4661 * failure, since pp_virt_addr_tbl was previously allocated, and it
4662 * should be saved to allow its freeing during the error flow.
4664 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4666 if (ext_pbl == OSAL_NULL) {
4667 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4669 p_pbl_virt = ext_pbl->p_pbl_virt;
4670 p_pbl_phys = ext_pbl->p_pbl_phys;
4671 p_chain->b_external_pbl = true;
4674 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4677 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
4681 for (i = 0; i < page_cnt; i++) {
4682 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4683 ECORE_CHAIN_PAGE_SIZE);
4685 DP_NOTICE(p_dev, false,
4686 "Failed to allocate chain memory\n");
4691 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4692 ecore_chain_reset(p_chain);
4695 /* Fill the PBL table with the physical address of the page */
4696 *(dma_addr_t *)p_pbl_virt = p_phys;
4697 /* Keep the virtual address of the page */
4698 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4700 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4703 return ECORE_SUCCESS;
4706 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4707 enum ecore_chain_use_mode intended_use,
4708 enum ecore_chain_mode mode,
4709 enum ecore_chain_cnt_type cnt_type,
4710 u32 num_elems, osal_size_t elem_size,
4711 struct ecore_chain *p_chain,
4712 struct ecore_chain_ext_pbl *ext_pbl)
4715 enum _ecore_status_t rc = ECORE_SUCCESS;
4717 if (mode == ECORE_CHAIN_MODE_SINGLE)
4720 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4722 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4725 DP_NOTICE(p_dev, false,
4726 "Cannot allocate a chain with the given arguments:\n"
4727 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4728 intended_use, mode, cnt_type, num_elems, elem_size);
4732 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4733 mode, cnt_type, p_dev->dp_ctx);
4736 case ECORE_CHAIN_MODE_NEXT_PTR:
4737 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4739 case ECORE_CHAIN_MODE_SINGLE:
4740 rc = ecore_chain_alloc_single(p_dev, p_chain);
4742 case ECORE_CHAIN_MODE_PBL:
4743 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4749 return ECORE_SUCCESS;
4752 ecore_chain_free(p_dev, p_chain);
4756 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4757 u16 src_id, u16 *dst_id)
4759 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4762 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4763 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4764 DP_NOTICE(p_hwfn, true,
4765 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4771 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4773 return ECORE_SUCCESS;
4776 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4777 u8 src_id, u8 *dst_id)
4779 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4782 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4783 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4784 DP_NOTICE(p_hwfn, true,
4785 "vport id [%d] is not valid, available indices [%d - %d]\n",
4791 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4793 return ECORE_SUCCESS;
4796 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4797 u8 src_id, u8 *dst_id)
4799 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4802 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4803 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4804 DP_NOTICE(p_hwfn, true,
4805 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4811 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4813 return ECORE_SUCCESS;
4816 static enum _ecore_status_t
4817 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4818 struct ecore_ptt *p_ptt, u32 high, u32 low,
4824 /* Find a free entry and utilize it */
4825 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4826 en = ecore_rd(p_hwfn, p_ptt,
4827 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4831 ecore_wr(p_hwfn, p_ptt,
4832 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4833 2 * i * sizeof(u32), low);
4834 ecore_wr(p_hwfn, p_ptt,
4835 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4836 (2 * i + 1) * sizeof(u32), high);
4837 ecore_wr(p_hwfn, p_ptt,
4838 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4839 i * sizeof(u32), 0);
4840 ecore_wr(p_hwfn, p_ptt,
4841 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4842 i * sizeof(u32), 0);
4843 ecore_wr(p_hwfn, p_ptt,
4844 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4845 i * sizeof(u32), 1);
4849 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4850 return ECORE_NORESOURCES;
4854 return ECORE_SUCCESS;
4857 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4858 struct ecore_ptt *p_ptt, u8 *p_filter)
4860 u32 high, low, entry_num;
4861 enum _ecore_status_t rc = ECORE_SUCCESS;
4863 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4864 &p_hwfn->p_dev->mf_bits))
4865 return ECORE_SUCCESS;
4867 high = p_filter[1] | (p_filter[0] << 8);
4868 low = p_filter[5] | (p_filter[4] << 8) |
4869 (p_filter[3] << 16) | (p_filter[2] << 24);
4871 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4872 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4874 if (rc != ECORE_SUCCESS) {
4875 DP_NOTICE(p_hwfn, false,
4876 "Failed to find an empty LLH filter to utilize\n");
4880 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4881 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4882 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4883 p_filter[4], p_filter[5], entry_num);
4888 static enum _ecore_status_t
4889 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4890 struct ecore_ptt *p_ptt, u32 high, u32 low,
4895 /* Find the entry and clean it */
4896 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4897 if (ecore_rd(p_hwfn, p_ptt,
4898 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4899 2 * i * sizeof(u32)) != low)
4901 if (ecore_rd(p_hwfn, p_ptt,
4902 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4903 (2 * i + 1) * sizeof(u32)) != high)
4906 ecore_wr(p_hwfn, p_ptt,
4907 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4908 ecore_wr(p_hwfn, p_ptt,
4909 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4910 2 * i * sizeof(u32), 0);
4911 ecore_wr(p_hwfn, p_ptt,
4912 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4913 (2 * i + 1) * sizeof(u32), 0);
4917 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4922 return ECORE_SUCCESS;
4925 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4926 struct ecore_ptt *p_ptt, u8 *p_filter)
4928 u32 high, low, entry_num;
4929 enum _ecore_status_t rc = ECORE_SUCCESS;
4931 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4932 &p_hwfn->p_dev->mf_bits))
4935 high = p_filter[1] | (p_filter[0] << 8);
4936 low = p_filter[5] | (p_filter[4] << 8) |
4937 (p_filter[3] << 16) | (p_filter[2] << 24);
4939 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4940 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4942 if (rc != ECORE_SUCCESS) {
4943 DP_NOTICE(p_hwfn, false,
4944 "Tried to remove a non-configured filter\n");
4949 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4950 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4951 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4952 p_filter[4], p_filter[5], entry_num);
4955 static enum _ecore_status_t
4956 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4957 struct ecore_ptt *p_ptt,
4958 enum ecore_llh_port_filter_type_t type,
4959 u32 high, u32 low, u32 *p_entry_num)
4964 /* Find a free entry and utilize it */
4965 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4966 en = ecore_rd(p_hwfn, p_ptt,
4967 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4971 ecore_wr(p_hwfn, p_ptt,
4972 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4973 2 * i * sizeof(u32), low);
4974 ecore_wr(p_hwfn, p_ptt,
4975 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4976 (2 * i + 1) * sizeof(u32), high);
4977 ecore_wr(p_hwfn, p_ptt,
4978 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4979 i * sizeof(u32), 1);
4980 ecore_wr(p_hwfn, p_ptt,
4981 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4982 i * sizeof(u32), 1 << type);
4983 ecore_wr(p_hwfn, p_ptt,
4984 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4988 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4989 return ECORE_NORESOURCES;
4993 return ECORE_SUCCESS;
4996 enum _ecore_status_t
4997 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4998 struct ecore_ptt *p_ptt,
4999 u16 source_port_or_eth_type,
5001 enum ecore_llh_port_filter_type_t type)
5003 u32 high, low, entry_num;
5004 enum _ecore_status_t rc = ECORE_SUCCESS;
5006 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5007 &p_hwfn->p_dev->mf_bits))
5014 case ECORE_LLH_FILTER_ETHERTYPE:
5015 high = source_port_or_eth_type;
5017 case ECORE_LLH_FILTER_TCP_SRC_PORT:
5018 case ECORE_LLH_FILTER_UDP_SRC_PORT:
5019 low = source_port_or_eth_type << 16;
5021 case ECORE_LLH_FILTER_TCP_DEST_PORT:
5022 case ECORE_LLH_FILTER_UDP_DEST_PORT:
5025 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5026 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5027 low = (source_port_or_eth_type << 16) | dest_port;
5030 DP_NOTICE(p_hwfn, true,
5031 "Non valid LLH protocol filter type %d\n", type);
5035 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5036 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5037 high, low, &entry_num);
5038 if (rc != ECORE_SUCCESS) {
5039 DP_NOTICE(p_hwfn, false,
5040 "Failed to find an empty LLH filter to utilize\n");
5044 case ECORE_LLH_FILTER_ETHERTYPE:
5045 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5046 "ETH type %x is added at %d\n",
5047 source_port_or_eth_type, entry_num);
5049 case ECORE_LLH_FILTER_TCP_SRC_PORT:
5050 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5051 "TCP src port %x is added at %d\n",
5052 source_port_or_eth_type, entry_num);
5054 case ECORE_LLH_FILTER_UDP_SRC_PORT:
5055 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5056 "UDP src port %x is added at %d\n",
5057 source_port_or_eth_type, entry_num);
5059 case ECORE_LLH_FILTER_TCP_DEST_PORT:
5060 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5061 "TCP dst port %x is added at %d\n", dest_port,
5064 case ECORE_LLH_FILTER_UDP_DEST_PORT:
5065 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5066 "UDP dst port %x is added at %d\n", dest_port,
5069 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5070 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5071 "TCP src/dst ports %x/%x are added at %d\n",
5072 source_port_or_eth_type, dest_port, entry_num);
5074 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5075 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5076 "UDP src/dst ports %x/%x are added at %d\n",
5077 source_port_or_eth_type, dest_port, entry_num);
5084 static enum _ecore_status_t
5085 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
5086 struct ecore_ptt *p_ptt,
5087 enum ecore_llh_port_filter_type_t type,
5088 u32 high, u32 low, u32 *p_entry_num)
5092 /* Find the entry and clean it */
5093 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5094 if (!ecore_rd(p_hwfn, p_ptt,
5095 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
5098 if (!ecore_rd(p_hwfn, p_ptt,
5099 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
5102 if (!(ecore_rd(p_hwfn, p_ptt,
5103 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
5104 i * sizeof(u32)) & (1 << type)))
5106 if (ecore_rd(p_hwfn, p_ptt,
5107 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5108 2 * i * sizeof(u32)) != low)
5110 if (ecore_rd(p_hwfn, p_ptt,
5111 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5112 (2 * i + 1) * sizeof(u32)) != high)
5115 ecore_wr(p_hwfn, p_ptt,
5116 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
5117 ecore_wr(p_hwfn, p_ptt,
5118 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
5119 i * sizeof(u32), 0);
5120 ecore_wr(p_hwfn, p_ptt,
5121 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
5122 i * sizeof(u32), 0);
5123 ecore_wr(p_hwfn, p_ptt,
5124 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5125 2 * i * sizeof(u32), 0);
5126 ecore_wr(p_hwfn, p_ptt,
5127 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5128 (2 * i + 1) * sizeof(u32), 0);
5132 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
5137 return ECORE_SUCCESS;
5141 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
5142 struct ecore_ptt *p_ptt,
5143 u16 source_port_or_eth_type,
5145 enum ecore_llh_port_filter_type_t type)
5147 u32 high, low, entry_num;
5148 enum _ecore_status_t rc = ECORE_SUCCESS;
5150 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5151 &p_hwfn->p_dev->mf_bits))
5158 case ECORE_LLH_FILTER_ETHERTYPE:
5159 high = source_port_or_eth_type;
5161 case ECORE_LLH_FILTER_TCP_SRC_PORT:
5162 case ECORE_LLH_FILTER_UDP_SRC_PORT:
5163 low = source_port_or_eth_type << 16;
5165 case ECORE_LLH_FILTER_TCP_DEST_PORT:
5166 case ECORE_LLH_FILTER_UDP_DEST_PORT:
5169 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5170 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5171 low = (source_port_or_eth_type << 16) | dest_port;
5174 DP_NOTICE(p_hwfn, true,
5175 "Non valid LLH protocol filter type %d\n", type);
5179 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5180 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5183 if (rc != ECORE_SUCCESS) {
5184 DP_NOTICE(p_hwfn, false,
5185 "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
5186 type, source_port_or_eth_type, dest_port);
5190 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5191 "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
5192 type, source_port_or_eth_type, dest_port, entry_num);
5195 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
5196 struct ecore_ptt *p_ptt)
5200 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
5203 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5204 ecore_wr(p_hwfn, p_ptt,
5205 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
5206 i * sizeof(u32), 0);
5207 ecore_wr(p_hwfn, p_ptt,
5208 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5209 2 * i * sizeof(u32), 0);
5210 ecore_wr(p_hwfn, p_ptt,
5211 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5212 (2 * i + 1) * sizeof(u32), 0);
5216 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
5217 struct ecore_ptt *p_ptt)
5219 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5220 &p_hwfn->p_dev->mf_bits) &&
5221 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5222 &p_hwfn->p_dev->mf_bits))
5225 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5226 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5229 enum _ecore_status_t
5230 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5231 struct ecore_ptt *p_ptt)
5233 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5234 ecore_wr(p_hwfn, p_ptt,
5235 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5236 1 << p_hwfn->abs_pf_id / 2);
5237 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5238 return ECORE_SUCCESS;
5241 DP_NOTICE(p_hwfn, false,
5242 "This function can't be set as default\n");
5246 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5247 struct ecore_ptt *p_ptt,
5248 u32 hw_addr, void *p_eth_qzone,
5249 osal_size_t eth_qzone_size,
5252 struct coalescing_timeset *p_coal_timeset;
5254 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5255 DP_NOTICE(p_hwfn, true,
5256 "Coalescing configuration not enabled\n");
5260 p_coal_timeset = p_eth_qzone;
5261 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5262 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5263 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5264 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5266 return ECORE_SUCCESS;
5269 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5270 u16 rx_coal, u16 tx_coal,
5273 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5274 enum _ecore_status_t rc = ECORE_SUCCESS;
5275 struct ecore_ptt *p_ptt;
5277 /* TODO - Configuring a single queue's coalescing but
5278 * claiming all queues are abiding same configuration
5279 * for PF and VF both.
5282 if (IS_VF(p_hwfn->p_dev))
5283 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5286 p_ptt = ecore_ptt_acquire(p_hwfn);
5291 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5294 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5298 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5301 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5304 ecore_ptt_release(p_hwfn, p_ptt);
5309 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5310 struct ecore_ptt *p_ptt,
5312 struct ecore_queue_cid *p_cid)
5314 struct ustorm_eth_queue_zone eth_qzone;
5315 u8 timeset, timer_res;
5317 enum _ecore_status_t rc;
5319 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5320 if (coalesce <= 0x7F) {
5322 } else if (coalesce <= 0xFF) {
5324 } else if (coalesce <= 0x1FF) {
5327 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5330 timeset = (u8)(coalesce >> timer_res);
5332 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5333 p_cid->sb_igu_id, false);
5334 if (rc != ECORE_SUCCESS)
5337 address = BAR0_MAP_REG_USDM_RAM +
5338 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5340 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5341 sizeof(struct ustorm_eth_queue_zone), timeset);
5342 if (rc != ECORE_SUCCESS)
5349 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5350 struct ecore_ptt *p_ptt,
5352 struct ecore_queue_cid *p_cid)
5354 struct xstorm_eth_queue_zone eth_qzone;
5355 u8 timeset, timer_res;
5357 enum _ecore_status_t rc;
5359 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5360 if (coalesce <= 0x7F) {
5362 } else if (coalesce <= 0xFF) {
5364 } else if (coalesce <= 0x1FF) {
5367 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5371 timeset = (u8)(coalesce >> timer_res);
5373 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5374 p_cid->sb_igu_id, true);
5375 if (rc != ECORE_SUCCESS)
5378 address = BAR0_MAP_REG_XSDM_RAM +
5379 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5381 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5382 sizeof(struct xstorm_eth_queue_zone), timeset);
5387 /* Calculate final WFQ values for all vports and configure it.
5388 * After this configuration each vport must have
5389 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5391 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5392 struct ecore_ptt *p_ptt,
5395 struct init_qm_vport_params *vport_params;
5398 vport_params = p_hwfn->qm_info.qm_vport_params;
5400 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5401 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5403 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5405 ecore_init_vport_wfq(p_hwfn, p_ptt,
5406 vport_params[i].first_tx_pq_id,
5407 vport_params[i].vport_wfq);
5411 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5415 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5416 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5419 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5420 struct ecore_ptt *p_ptt)
5422 struct init_qm_vport_params *vport_params;
5425 vport_params = p_hwfn->qm_info.qm_vport_params;
5427 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5428 ecore_init_wfq_default_param(p_hwfn);
5429 ecore_init_vport_wfq(p_hwfn, p_ptt,
5430 vport_params[i].first_tx_pq_id,
5431 vport_params[i].vport_wfq);
5435 /* This function performs several validations for WFQ
5436 * configuration and required min rate for a given vport
5437 * 1. req_rate must be greater than one percent of min_pf_rate.
5438 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5439 * rates to get less than one percent of min_pf_rate.
5440 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5442 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5443 u16 vport_id, u32 req_rate,
5446 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5447 int non_requested_count = 0, req_count = 0, i, num_vports;
5449 num_vports = p_hwfn->qm_info.num_vports;
5451 /* Accounting for the vports which are configured for WFQ explicitly */
5453 for (i = 0; i < num_vports; i++) {
5456 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5458 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5459 total_req_min_rate += tmp_speed;
5463 /* Include current vport data as well */
5465 total_req_min_rate += req_rate;
5466 non_requested_count = num_vports - req_count;
5468 /* validate possible error cases */
5469 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5470 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5471 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5472 vport_id, req_rate, min_pf_rate);
5476 /* TBD - for number of vports greater than 100 */
5477 if (num_vports > ECORE_WFQ_UNIT) {
5478 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5479 "Number of vports is greater than %d\n",
5484 if (total_req_min_rate > min_pf_rate) {
5485 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5486 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5487 total_req_min_rate, min_pf_rate);
5491 /* Data left for non requested vports */
5492 total_left_rate = min_pf_rate - total_req_min_rate;
5493 left_rate_per_vp = total_left_rate / non_requested_count;
5495 /* validate if non requested get < 1% of min bw */
5496 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5497 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5498 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5499 left_rate_per_vp, min_pf_rate);
5503 /* now req_rate for given vport passes all scenarios.
5504 * assign final wfq rates to all vports.
5506 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5507 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5509 for (i = 0; i < num_vports; i++) {
5510 if (p_hwfn->qm_info.wfq_data[i].configured)
5513 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5516 return ECORE_SUCCESS;
5519 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5520 struct ecore_ptt *p_ptt,
5521 u16 vp_id, u32 rate)
5523 struct ecore_mcp_link_state *p_link;
5524 int rc = ECORE_SUCCESS;
5526 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5528 if (!p_link->min_pf_rate) {
5529 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5530 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5534 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5536 if (rc == ECORE_SUCCESS)
5537 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5538 p_link->min_pf_rate);
5540 DP_NOTICE(p_hwfn, false,
5541 "Validation failed while configuring min rate\n");
5546 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5547 struct ecore_ptt *p_ptt,
5550 bool use_wfq = false;
5551 int rc = ECORE_SUCCESS;
5554 /* Validate all pre configured vports for wfq */
5555 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5558 if (!p_hwfn->qm_info.wfq_data[i].configured)
5561 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5564 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5565 if (rc != ECORE_SUCCESS) {
5566 DP_NOTICE(p_hwfn, false,
5567 "WFQ validation failed while configuring min rate\n");
5572 if (rc == ECORE_SUCCESS && use_wfq)
5573 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5575 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5580 /* Main API for ecore clients to configure vport min rate.
5581 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5582 * rate - Speed in Mbps needs to be assigned to a given vport.
5584 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5586 int i, rc = ECORE_INVAL;
5588 /* TBD - for multiple hardware functions - that is 100 gig */
5589 if (ECORE_IS_CMT(p_dev)) {
5590 DP_NOTICE(p_dev, false,
5591 "WFQ configuration is not supported for this device\n");
5595 for_each_hwfn(p_dev, i) {
5596 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5597 struct ecore_ptt *p_ptt;
5599 p_ptt = ecore_ptt_acquire(p_hwfn);
5601 return ECORE_TIMEOUT;
5603 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5605 if (rc != ECORE_SUCCESS) {
5606 ecore_ptt_release(p_hwfn, p_ptt);
5610 ecore_ptt_release(p_hwfn, p_ptt);
5616 /* API to configure WFQ from mcp link change */
5617 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5618 struct ecore_ptt *p_ptt,
5623 /* TBD - for multiple hardware functions - that is 100 gig */
5624 if (ECORE_IS_CMT(p_dev)) {
5625 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5626 "WFQ configuration is not supported for this device\n");
5630 for_each_hwfn(p_dev, i) {
5631 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5633 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5638 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5639 struct ecore_ptt *p_ptt,
5640 struct ecore_mcp_link_state *p_link,
5643 int rc = ECORE_SUCCESS;
5645 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5647 if (!p_link->line_speed && (max_bw != 100))
5650 p_link->speed = (p_link->line_speed * max_bw) / 100;
5651 p_hwfn->qm_info.pf_rl = p_link->speed;
5653 /* Since the limiter also affects Tx-switched traffic, we don't want it
5654 * to limit such traffic in case there's no actual limit.
5655 * In that case, set limit to imaginary high boundary.
5658 p_hwfn->qm_info.pf_rl = 100000;
5660 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5661 p_hwfn->qm_info.pf_rl);
5663 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5664 "Configured MAX bandwidth to be %08x Mb/sec\n",
5670 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5671 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5673 int i, rc = ECORE_INVAL;
5675 if (max_bw < 1 || max_bw > 100) {
5676 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5680 for_each_hwfn(p_dev, i) {
5681 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5682 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5683 struct ecore_mcp_link_state *p_link;
5684 struct ecore_ptt *p_ptt;
5686 p_link = &p_lead->mcp_info->link_output;
5688 p_ptt = ecore_ptt_acquire(p_hwfn);
5690 return ECORE_TIMEOUT;
5692 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5695 ecore_ptt_release(p_hwfn, p_ptt);
5697 if (rc != ECORE_SUCCESS)
5704 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5705 struct ecore_ptt *p_ptt,
5706 struct ecore_mcp_link_state *p_link,
5709 int rc = ECORE_SUCCESS;
5711 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5712 p_hwfn->qm_info.pf_wfq = min_bw;
5714 if (!p_link->line_speed)
5717 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5719 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5721 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5722 "Configured MIN bandwidth to be %d Mb/sec\n",
5723 p_link->min_pf_rate);
5728 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5729 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5731 int i, rc = ECORE_INVAL;
5733 if (min_bw < 1 || min_bw > 100) {
5734 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5738 for_each_hwfn(p_dev, i) {
5739 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5740 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5741 struct ecore_mcp_link_state *p_link;
5742 struct ecore_ptt *p_ptt;
5744 p_link = &p_lead->mcp_info->link_output;
5746 p_ptt = ecore_ptt_acquire(p_hwfn);
5748 return ECORE_TIMEOUT;
5750 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5752 if (rc != ECORE_SUCCESS) {
5753 ecore_ptt_release(p_hwfn, p_ptt);
5757 if (p_link->min_pf_rate) {
5758 u32 min_rate = p_link->min_pf_rate;
5760 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5765 ecore_ptt_release(p_hwfn, p_ptt);
5771 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5773 struct ecore_mcp_link_state *p_link;
5775 p_link = &p_hwfn->mcp_info->link_output;
5777 if (p_link->min_pf_rate)
5778 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5780 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5781 sizeof(*p_hwfn->qm_info.wfq_data) *
5782 p_hwfn->qm_info.num_vports);
5785 int ecore_device_num_engines(struct ecore_dev *p_dev)
5787 return ECORE_IS_BB(p_dev) ? 2 : 1;
5790 int ecore_device_num_ports(struct ecore_dev *p_dev)
5792 return p_dev->num_ports;
5795 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5800 ((u8 *)fw_msb)[0] = mac[1];
5801 ((u8 *)fw_msb)[1] = mac[0];
5802 ((u8 *)fw_mid)[0] = mac[3];
5803 ((u8 *)fw_mid)[1] = mac[2];
5804 ((u8 *)fw_lsb)[0] = mac[5];
5805 ((u8 *)fw_lsb)[1] = mac[4];