2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
36 * registers involved are not split and thus configuration is a race where
37 * some of the PFs configuration might be lost.
38 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
39 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
40 * there's more than a single compiled ecore component in system].
42 static osal_spinlock_t qm_lock;
43 static bool qm_lock_init;
45 /******************** Doorbell Recovery *******************/
46 /* The doorbell recovery mechanism consists of a list of entries which represent
47 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
48 * entity needs to register with the mechanism and provide the parameters
49 * describing it's doorbell, including a location where last used doorbell data
50 * can be found. The doorbell execute function will traverse the list and
51 * doorbell all of the registered entries.
53 struct ecore_db_recovery_entry {
54 osal_list_entry_t list_entry;
55 void OSAL_IOMEM *db_addr;
57 enum ecore_db_rec_width db_width;
58 enum ecore_db_rec_space db_space;
62 /* display a single doorbell recovery entry */
63 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
64 struct ecore_db_recovery_entry *db_entry,
67 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
68 action, db_entry, db_entry->db_addr, db_entry->db_data,
69 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
70 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
74 /* doorbell address sanity (address within doorbell bar range) */
75 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
78 /* make sure doorbell address is within the doorbell bar */
79 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
80 (u8 *)p_dev->doorbells + p_dev->db_size) {
82 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
83 db_addr, p_dev->doorbells,
84 (u8 *)p_dev->doorbells + p_dev->db_size);
88 /* make sure doorbell data pointer is not null */
90 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
97 /* find hwfn according to the doorbell address */
98 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
99 void OSAL_IOMEM *db_addr)
101 struct ecore_hwfn *p_hwfn;
103 /* In CMT doorbell bar is split down the middle between engine 0 and
106 if (p_dev->num_hwfns > 1)
107 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
108 &p_dev->hwfns[0] : &p_dev->hwfns[1];
110 p_hwfn = ECORE_LEADING_HWFN(p_dev);
115 /* add a new entry to the doorbell recovery mechanism */
116 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
117 void OSAL_IOMEM *db_addr,
119 enum ecore_db_rec_width db_width,
120 enum ecore_db_rec_space db_space)
122 struct ecore_db_recovery_entry *db_entry;
123 struct ecore_hwfn *p_hwfn;
125 /* shortcircuit VFs, for now */
127 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
128 return ECORE_SUCCESS;
131 /* sanitize doorbell address */
132 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
135 /* obtain hwfn from doorbell address */
136 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
139 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
141 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
146 db_entry->db_addr = db_addr;
147 db_entry->db_data = db_data;
148 db_entry->db_width = db_width;
149 db_entry->db_space = db_space;
150 db_entry->hwfn_idx = p_hwfn->my_id;
153 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
155 /* protect the list */
156 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
157 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
158 &p_hwfn->db_recovery_info.list);
159 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
161 return ECORE_SUCCESS;
164 /* remove an entry from the doorbell recovery mechanism */
165 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
166 void OSAL_IOMEM *db_addr,
169 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
170 enum _ecore_status_t rc = ECORE_INVAL;
171 struct ecore_hwfn *p_hwfn;
173 /* shortcircuit VFs, for now */
175 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
176 return ECORE_SUCCESS;
179 /* sanitize doorbell address */
180 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
183 /* obtain hwfn from doorbell address */
184 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
186 /* protect the list */
187 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
188 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
189 &p_hwfn->db_recovery_info.list,
191 struct ecore_db_recovery_entry) {
192 /* search according to db_data addr since db_addr is not unique
195 if (db_entry->db_data == db_data) {
196 ecore_db_recovery_dp_entry(p_hwfn, db_entry,
198 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
199 &p_hwfn->db_recovery_info.list);
205 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
207 if (rc == ECORE_INVAL)
209 DP_NOTICE(p_hwfn, false,
210 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
213 OSAL_FREE(p_dev, db_entry);
218 /* initialize the doorbell recovery mechanism */
219 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
221 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
223 /* make sure db_size was set in p_dev */
224 if (!p_hwfn->p_dev->db_size) {
225 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
229 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
230 #ifdef CONFIG_ECORE_LOCK_ALLOC
231 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
233 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
234 p_hwfn->db_recovery_info.db_recovery_counter = 0;
236 return ECORE_SUCCESS;
239 /* destroy the doorbell recovery mechanism */
240 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
242 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
244 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
245 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
246 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
247 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
248 db_entry = OSAL_LIST_FIRST_ENTRY(
249 &p_hwfn->db_recovery_info.list,
250 struct ecore_db_recovery_entry,
252 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
253 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
254 &p_hwfn->db_recovery_info.list);
255 OSAL_FREE(p_hwfn->p_dev, db_entry);
258 #ifdef CONFIG_ECORE_LOCK_ALLOC
259 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
261 p_hwfn->db_recovery_info.db_recovery_counter = 0;
264 /* print the content of the doorbell recovery mechanism */
265 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
267 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
269 DP_NOTICE(p_hwfn, false,
270 "Dispalying doorbell recovery database. Counter was %d\n",
271 p_hwfn->db_recovery_info.db_recovery_counter);
273 /* protect the list */
274 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
275 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
276 &p_hwfn->db_recovery_info.list,
278 struct ecore_db_recovery_entry) {
279 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
282 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
285 /* ring the doorbell of a single doorbell recovery entry */
286 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
287 struct ecore_db_recovery_entry *db_entry,
288 enum ecore_db_rec_exec db_exec)
290 /* Print according to width */
291 if (db_entry->db_width == DB_REC_WIDTH_32B)
292 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
293 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
294 db_entry->db_addr, *(u32 *)db_entry->db_data);
296 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
297 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
299 *(unsigned long *)(db_entry->db_data));
302 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
306 /* Flush the write combined buffer. Since there are multiple doorbelling
307 * entities using the same address, if we don't flush, a transaction
310 OSAL_WMB(p_hwfn->p_dev);
312 /* Ring the doorbell */
313 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
314 if (db_entry->db_width == DB_REC_WIDTH_32B)
315 DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
316 *(u32 *)(db_entry->db_data));
318 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
319 *(u64 *)(db_entry->db_data));
322 /* Flush the write combined buffer. Next doorbell may come from a
323 * different entity to the same address...
325 OSAL_WMB(p_hwfn->p_dev);
328 /* traverse the doorbell recovery entry list and ring all the doorbells */
329 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
330 enum ecore_db_rec_exec db_exec)
332 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
334 if (db_exec != DB_REC_ONCE) {
335 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
336 p_hwfn->db_recovery_info.db_recovery_counter);
338 /* track amount of times recovery was executed */
339 p_hwfn->db_recovery_info.db_recovery_counter++;
342 /* protect the list */
343 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
344 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
345 &p_hwfn->db_recovery_info.list,
347 struct ecore_db_recovery_entry) {
348 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
349 if (db_exec == DB_REC_ONCE)
353 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
355 /******************** Doorbell Recovery end ****************/
358 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
359 * load the driver. The number was
364 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
367 BAR_ID_0, /* used for GRC */
368 BAR_ID_1 /* Used for doorbells */
371 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
372 struct ecore_ptt *p_ptt,
375 u32 bar_reg = (bar_id == BAR_ID_0 ?
376 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
379 if (IS_VF(p_hwfn->p_dev)) {
380 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
381 * read from actual register, but we're currently not using
382 * it for actual doorbelling.
387 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
389 return 1 << (val + 15);
391 /* The above registers were updated in the past only in CMT mode. Since
392 * they were found to be useful MFW started updating them from 8.7.7.0.
393 * In older MFW versions they are set to 0 which means disabled.
395 if (p_hwfn->p_dev->num_hwfns > 1) {
397 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
398 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
401 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
408 void ecore_init_dp(struct ecore_dev *p_dev,
409 u32 dp_module, u8 dp_level, void *dp_ctx)
413 p_dev->dp_level = dp_level;
414 p_dev->dp_module = dp_module;
415 p_dev->dp_ctx = dp_ctx;
416 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
417 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
419 p_hwfn->dp_level = dp_level;
420 p_hwfn->dp_module = dp_module;
421 p_hwfn->dp_ctx = dp_ctx;
425 void ecore_init_struct(struct ecore_dev *p_dev)
429 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
430 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
432 p_hwfn->p_dev = p_dev;
434 p_hwfn->b_active = false;
436 #ifdef CONFIG_ECORE_LOCK_ALLOC
437 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
439 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
442 /* hwfn 0 is always active */
443 p_dev->hwfns[0].b_active = true;
445 /* set the default cache alignment to 128 (may be overridden later) */
446 p_dev->cache_shift = 7;
449 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
451 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
453 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
454 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
455 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
456 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
459 void ecore_resc_free(struct ecore_dev *p_dev)
464 for_each_hwfn(p_dev, i)
465 ecore_l2_free(&p_dev->hwfns[i]);
469 OSAL_FREE(p_dev, p_dev->fw_data);
471 OSAL_FREE(p_dev, p_dev->reset_stats);
473 for_each_hwfn(p_dev, i) {
474 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
476 ecore_cxt_mngr_free(p_hwfn);
477 ecore_qm_info_free(p_hwfn);
478 ecore_spq_free(p_hwfn);
479 ecore_eq_free(p_hwfn);
480 ecore_consq_free(p_hwfn);
481 ecore_int_free(p_hwfn);
482 ecore_iov_free(p_hwfn);
483 ecore_l2_free(p_hwfn);
484 ecore_dmae_info_free(p_hwfn);
485 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
486 /* @@@TBD Flush work-queue ? */
488 /* destroy doorbell recovery mechanism */
489 ecore_db_recovery_teardown(p_hwfn);
493 /******************** QM initialization *******************/
495 /* bitmaps for indicating active traffic classes.
496 * Special case for Arrowhead 4 port
498 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
499 #define ACTIVE_TCS_BMAP 0x9f
500 /* 0..3 actually used, OOO and high priority stuff all use 3 */
501 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
503 /* determines the physical queue flags for a given PF. */
504 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
512 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
513 flags |= PQ_FLAGS_VFS;
516 switch (p_hwfn->hw_info.personality) {
518 flags |= PQ_FLAGS_MCOS;
521 flags |= PQ_FLAGS_OFLD;
523 case ECORE_PCI_ISCSI:
524 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
526 case ECORE_PCI_ETH_ROCE:
527 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
529 case ECORE_PCI_ETH_IWARP:
530 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
534 DP_ERR(p_hwfn, "unknown personality %d\n",
535 p_hwfn->hw_info.personality);
541 /* Getters for resource amounts necessary for qm initialization */
542 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
544 return p_hwfn->hw_info.num_hw_tc;
547 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
549 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
550 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
553 #define NUM_DEFAULT_RLS 1
555 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
557 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
560 /* num RLs can't exceed resource amount of rls or vports or the
563 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
564 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
566 /* make sure after we reserve the default and VF rls we'll have
569 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
570 DP_NOTICE(p_hwfn, false,
571 "no rate limiters left for PF rate limiting"
572 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
576 /* subtract rls necessary for VFs and one default one for the PF */
577 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
582 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
584 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
586 /* all pqs share the same vport (hence the 1 below), except for vfs
589 return (!!(PQ_FLAGS_RLS & pq_flags)) *
590 ecore_init_qm_get_num_pf_rls(p_hwfn) +
591 (!!(PQ_FLAGS_VFS & pq_flags)) *
592 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
595 /* calc amount of PQs according to the requested flags */
596 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
598 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
600 return (!!(PQ_FLAGS_RLS & pq_flags)) *
601 ecore_init_qm_get_num_pf_rls(p_hwfn) +
602 (!!(PQ_FLAGS_MCOS & pq_flags)) *
603 ecore_init_qm_get_num_tcs(p_hwfn) +
604 (!!(PQ_FLAGS_LB & pq_flags)) +
605 (!!(PQ_FLAGS_OOO & pq_flags)) +
606 (!!(PQ_FLAGS_ACK & pq_flags)) +
607 (!!(PQ_FLAGS_OFLD & pq_flags)) +
608 (!!(PQ_FLAGS_VFS & pq_flags)) *
609 ecore_init_qm_get_num_vfs(p_hwfn);
612 /* initialize the top level QM params */
613 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
615 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
618 /* pq and vport bases for this PF */
619 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
620 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
622 /* rate limiting and weighted fair queueing are always enabled */
623 qm_info->vport_rl_en = 1;
624 qm_info->vport_wfq_en = 1;
626 /* TC config is different for AH 4 port */
627 four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
629 /* in AH 4 port we have fewer TCs per port */
630 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
633 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
636 if (!qm_info->ooo_tc)
637 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
641 /* initialize qm vport params */
642 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
644 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
647 /* all vports participate in weighted fair queueing */
648 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
649 qm_info->qm_vport_params[i].vport_wfq = 1;
652 /* initialize qm port params */
653 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
655 /* Initialize qm port parameters */
656 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
658 /* indicate how ooo and high pri traffic is dealt with */
659 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
660 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
662 for (i = 0; i < num_ports; i++) {
663 struct init_qm_port_params *p_qm_port =
664 &p_hwfn->qm_info.qm_port_params[i];
666 p_qm_port->active = 1;
667 p_qm_port->active_phys_tcs = active_phys_tcs;
668 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
669 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
673 /* Reset the params which must be reset for qm init. QM init may be called as
674 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
675 * params may be affected by the init but would simply recalculate to the same
676 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
677 * affected as these amounts stay the same.
679 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
681 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
683 qm_info->num_pqs = 0;
684 qm_info->num_vports = 0;
685 qm_info->num_pf_rls = 0;
686 qm_info->num_vf_pqs = 0;
687 qm_info->first_vf_pq = 0;
688 qm_info->first_mcos_pq = 0;
689 qm_info->first_rl_pq = 0;
692 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
694 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
696 qm_info->num_vports++;
698 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
700 "vport overflow! qm_info->num_vports %d,"
701 " qm_init_get_num_vports() %d\n",
703 ecore_init_qm_get_num_vports(p_hwfn));
706 /* initialize a single pq and manage qm_info resources accounting.
707 * The pq_init_flags param determines whether the PQ is rate limited
709 * and whether a new vport is allocated to the pq or not (i.e. vport will be
713 /* flags for pq init */
714 #define PQ_INIT_SHARE_VPORT (1 << 0)
715 #define PQ_INIT_PF_RL (1 << 1)
716 #define PQ_INIT_VF_RL (1 << 2)
718 /* defines for pq init */
719 #define PQ_INIT_DEFAULT_WRR_GROUP 1
720 #define PQ_INIT_DEFAULT_TC 0
721 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
723 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
724 struct ecore_qm_info *qm_info,
725 u8 tc, u32 pq_init_flags)
727 u16 pq_idx = qm_info->num_pqs, max_pq =
728 ecore_init_qm_get_num_pqs(p_hwfn);
732 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
735 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
737 qm_info->qm_pq_params[pq_idx].tc_id = tc;
738 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
739 qm_info->qm_pq_params[pq_idx].rl_valid =
740 (pq_init_flags & PQ_INIT_PF_RL ||
741 pq_init_flags & PQ_INIT_VF_RL);
743 /* qm params accounting */
745 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
746 qm_info->num_vports++;
748 if (pq_init_flags & PQ_INIT_PF_RL)
749 qm_info->num_pf_rls++;
751 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
753 "vport overflow! qm_info->num_vports %d,"
754 " qm_init_get_num_vports() %d\n",
756 ecore_init_qm_get_num_vports(p_hwfn));
758 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
759 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
760 " qm_init_get_num_pf_rls() %d\n",
762 ecore_init_qm_get_num_pf_rls(p_hwfn));
765 /* get pq index according to PQ_FLAGS */
766 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
769 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
771 /* Can't have multiple flags set here */
772 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
773 sizeof(pq_flags)) > 1)
778 return &qm_info->first_rl_pq;
780 return &qm_info->first_mcos_pq;
782 return &qm_info->pure_lb_pq;
784 return &qm_info->ooo_pq;
786 return &qm_info->pure_ack_pq;
788 return &qm_info->offload_pq;
790 return &qm_info->first_vf_pq;
796 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
800 /* save pq index in qm info */
801 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
802 u32 pq_flags, u16 pq_val)
804 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
806 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
809 /* get tx pq index, with the PQ TX base already set (ready for context init) */
810 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
812 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
814 return *base_pq_idx + CM_TX_PQ_BASE;
817 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
819 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
822 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
824 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
827 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
829 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
832 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
834 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
837 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
839 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
842 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
844 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
847 /* Functions for creating specific types of pqs */
848 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
850 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
852 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
855 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
856 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
859 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
861 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
863 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
866 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
867 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
870 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
872 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
874 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
877 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
878 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
881 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
883 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
885 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
888 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
889 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
892 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
894 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
897 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
900 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
901 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
902 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
905 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
907 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
908 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
910 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
913 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
915 qm_info->num_vf_pqs = num_vfs;
916 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
917 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
921 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
923 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
924 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
926 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
929 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
930 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
931 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
935 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
937 /* rate limited pqs, must come first (FW assumption) */
938 ecore_init_qm_rl_pqs(p_hwfn);
940 /* pqs for multi cos */
941 ecore_init_qm_mcos_pqs(p_hwfn);
943 /* pure loopback pq */
944 ecore_init_qm_lb_pq(p_hwfn);
946 /* out of order pq */
947 ecore_init_qm_ooo_pq(p_hwfn);
950 ecore_init_qm_pure_ack_pq(p_hwfn);
952 /* pq for offloaded protocol */
953 ecore_init_qm_offload_pq(p_hwfn);
955 /* done sharing vports */
956 ecore_init_qm_advance_vport(p_hwfn);
959 ecore_init_qm_vf_pqs(p_hwfn);
962 /* compare values of getters against resources amounts */
963 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
965 if (ecore_init_qm_get_num_vports(p_hwfn) >
966 RESC_NUM(p_hwfn, ECORE_VPORT)) {
967 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
971 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
972 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
976 return ECORE_SUCCESS;
980 * Function for verbose printing of the qm initialization results
982 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
984 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
985 struct init_qm_vport_params *vport;
986 struct init_qm_port_params *port;
987 struct init_qm_pq_params *pq;
990 /* top level params */
991 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
992 "qm init top level params: start_pq %d, start_vport %d,"
993 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
994 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
995 qm_info->offload_pq, qm_info->pure_ack_pq);
996 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
997 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
998 " num_vports %d, max_phys_tcs_per_port %d\n",
999 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
1000 qm_info->num_vf_pqs, qm_info->num_vports,
1001 qm_info->max_phys_tcs_per_port);
1002 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1003 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
1004 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1005 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
1006 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
1007 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1010 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
1011 port = &qm_info->qm_port_params[i];
1012 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1013 "port idx %d, active %d, active_phys_tcs %d,"
1014 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1016 i, port->active, port->active_phys_tcs,
1017 port->num_pbf_cmd_lines, port->num_btb_blocks,
1022 for (i = 0; i < qm_info->num_vports; i++) {
1023 vport = &qm_info->qm_vport_params[i];
1024 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1025 "vport idx %d, vport_rl %d, wfq %d,"
1026 " first_tx_pq_id [ ",
1027 qm_info->start_vport + i, vport->vport_rl,
1029 for (tc = 0; tc < NUM_OF_TCS; tc++)
1030 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1031 vport->first_tx_pq_id[tc]);
1032 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1036 for (i = 0; i < qm_info->num_pqs; i++) {
1037 pq = &qm_info->qm_pq_params[i];
1038 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1039 "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
1041 qm_info->start_pq + i, pq->vport_id, pq->tc_id,
1042 pq->wrr_group, pq->rl_valid);
1046 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1048 /* reset params required for init run */
1049 ecore_init_qm_reset_params(p_hwfn);
1051 /* init QM top level params */
1052 ecore_init_qm_params(p_hwfn);
1054 /* init QM port params */
1055 ecore_init_qm_port_params(p_hwfn);
1057 /* init QM vport params */
1058 ecore_init_qm_vport_params(p_hwfn);
1060 /* init QM physical queue params */
1061 ecore_init_qm_pq_params(p_hwfn);
1063 /* display all that init */
1064 ecore_dp_init_qm_params(p_hwfn);
1067 /* This function reconfigures the QM pf on the fly.
1068 * For this purpose we:
1069 * 1. reconfigure the QM database
1070 * 2. set new values to runtime array
1071 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1072 * 4. activate init tool in QM_PF stage
1073 * 5. send an sdm_qm_cmd through rbc interface to release the QM
1075 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1076 struct ecore_ptt *p_ptt)
1078 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1080 enum _ecore_status_t rc;
1082 /* initialize ecore's qm data structure */
1083 ecore_init_qm_info(p_hwfn);
1085 /* stop PF's qm queues */
1086 OSAL_SPIN_LOCK(&qm_lock);
1087 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1088 qm_info->start_pq, qm_info->num_pqs);
1089 OSAL_SPIN_UNLOCK(&qm_lock);
1093 /* clear the QM_PF runtime phase leftovers from previous init */
1094 ecore_init_clear_rt_data(p_hwfn);
1096 /* prepare QM portion of runtime array */
1097 ecore_qm_init_pf(p_hwfn, p_ptt);
1099 /* activate init tool on runtime array */
1100 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1101 p_hwfn->hw_info.hw_mode);
1102 if (rc != ECORE_SUCCESS)
1105 /* start PF's qm queues */
1106 OSAL_SPIN_LOCK(&qm_lock);
1107 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1108 qm_info->start_pq, qm_info->num_pqs);
1109 OSAL_SPIN_UNLOCK(&qm_lock);
1113 return ECORE_SUCCESS;
1116 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1118 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1119 enum _ecore_status_t rc;
1121 rc = ecore_init_qm_sanity(p_hwfn);
1122 if (rc != ECORE_SUCCESS)
1125 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1126 sizeof(struct init_qm_pq_params) *
1127 ecore_init_qm_get_num_pqs(p_hwfn));
1128 if (!qm_info->qm_pq_params)
1131 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1132 sizeof(struct init_qm_vport_params) *
1133 ecore_init_qm_get_num_vports(p_hwfn));
1134 if (!qm_info->qm_vport_params)
1137 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1138 sizeof(struct init_qm_port_params) *
1139 p_hwfn->p_dev->num_ports_in_engines);
1140 if (!qm_info->qm_port_params)
1143 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1144 sizeof(struct ecore_wfq_data) *
1145 ecore_init_qm_get_num_vports(p_hwfn));
1146 if (!qm_info->wfq_data)
1149 return ECORE_SUCCESS;
1152 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1153 ecore_qm_info_free(p_hwfn);
1156 /******************** End QM initialization ***************/
1158 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1160 enum _ecore_status_t rc = ECORE_SUCCESS;
1164 for_each_hwfn(p_dev, i) {
1165 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1166 if (rc != ECORE_SUCCESS)
1172 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1173 sizeof(*p_dev->fw_data));
1174 if (!p_dev->fw_data)
1177 for_each_hwfn(p_dev, i) {
1178 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1179 u32 n_eqes, num_cons;
1181 /* initialize the doorbell recovery mechanism */
1182 rc = ecore_db_recovery_setup(p_hwfn);
1186 /* First allocate the context manager structure */
1187 rc = ecore_cxt_mngr_alloc(p_hwfn);
1191 /* Set the HW cid/tid numbers (in the context manager)
1192 * Must be done prior to any further computations.
1194 rc = ecore_cxt_set_pf_params(p_hwfn);
1198 rc = ecore_alloc_qm_data(p_hwfn);
1203 ecore_init_qm_info(p_hwfn);
1205 /* Compute the ILT client partition */
1206 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1210 /* CID map / ILT shadow table / T2
1211 * The talbes sizes are determined by the computations above
1213 rc = ecore_cxt_tables_alloc(p_hwfn);
1217 /* SPQ, must follow ILT because initializes SPQ context */
1218 rc = ecore_spq_alloc(p_hwfn);
1222 /* SP status block allocation */
1223 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1226 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1230 rc = ecore_iov_alloc(p_hwfn);
1235 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1236 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1237 /* Calculate the EQ size
1238 * ---------------------
1239 * Each ICID may generate up to one event at a time i.e.
1240 * the event must be handled/cleared before a new one
1241 * can be generated. We calculate the sum of events per
1242 * protocol and create an EQ deep enough to handle the
1244 * - Core - according to SPQ.
1245 * - RoCE - per QP there are a couple of ICIDs, one
1246 * responder and one requester, each can
1247 * generate an EQE => n_eqes_qp = 2 * n_qp.
1248 * Each CQ can generate an EQE. There are 2 CQs
1249 * per QP => n_eqes_cq = 2 * n_qp.
1250 * Hence the RoCE total is 4 * n_qp or
1252 * - ENet - There can be up to two events per VF. One
1253 * for VF-PF channel and another for VF FLR
1254 * initial cleanup. The number of VFs is
1255 * bounded by MAX_NUM_VFS_BB, and is much
1256 * smaller than RoCE's so we avoid exact
1259 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1261 ecore_cxt_get_proto_cid_count(
1267 num_cons = ecore_cxt_get_proto_cid_count(
1272 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1273 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1275 ecore_cxt_get_proto_cid_count(p_hwfn,
1278 n_eqes += 2 * num_cons;
1281 if (n_eqes > 0xFFFF) {
1282 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1283 "The maximum of a u16 chain is 0x%x\n",
1288 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1292 rc = ecore_consq_alloc(p_hwfn);
1296 rc = ecore_l2_alloc(p_hwfn);
1297 if (rc != ECORE_SUCCESS)
1300 /* DMA info initialization */
1301 rc = ecore_dmae_info_alloc(p_hwfn);
1303 DP_NOTICE(p_hwfn, true,
1304 "Failed to allocate memory for dmae_info"
1309 /* DCBX initialization */
1310 rc = ecore_dcbx_info_alloc(p_hwfn);
1312 DP_NOTICE(p_hwfn, true,
1313 "Failed to allocate memory for dcbx structure\n");
1318 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1319 sizeof(*p_dev->reset_stats));
1320 if (!p_dev->reset_stats) {
1321 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1325 return ECORE_SUCCESS;
1330 ecore_resc_free(p_dev);
1334 void ecore_resc_setup(struct ecore_dev *p_dev)
1339 for_each_hwfn(p_dev, i)
1340 ecore_l2_setup(&p_dev->hwfns[i]);
1344 for_each_hwfn(p_dev, i) {
1345 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1347 ecore_cxt_mngr_setup(p_hwfn);
1348 ecore_spq_setup(p_hwfn);
1349 ecore_eq_setup(p_hwfn);
1350 ecore_consq_setup(p_hwfn);
1352 /* Read shadow of current MFW mailbox */
1353 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1354 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1355 p_hwfn->mcp_info->mfw_mb_cur,
1356 p_hwfn->mcp_info->mfw_mb_length);
1358 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1360 ecore_l2_setup(p_hwfn);
1361 ecore_iov_setup(p_hwfn);
1365 #define FINAL_CLEANUP_POLL_CNT (100)
1366 #define FINAL_CLEANUP_POLL_TIME (10)
1367 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1368 struct ecore_ptt *p_ptt,
1371 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1372 enum _ecore_status_t rc = ECORE_TIMEOUT;
1375 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1376 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1377 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1378 return ECORE_SUCCESS;
1382 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1383 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1388 command |= X_FINAL_CLEANUP_AGG_INT <<
1389 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1390 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1391 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1392 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1394 /* Make sure notification is not set before initiating final cleanup */
1396 if (REG_RD(p_hwfn, addr)) {
1397 DP_NOTICE(p_hwfn, false,
1398 "Unexpected; Found final cleanup notification");
1399 DP_NOTICE(p_hwfn, false,
1400 " before initiating final cleanup\n");
1401 REG_WR(p_hwfn, addr, 0);
1404 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1405 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1408 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1410 /* Poll until completion */
1411 while (!REG_RD(p_hwfn, addr) && count--)
1412 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1414 if (REG_RD(p_hwfn, addr))
1417 DP_NOTICE(p_hwfn, true,
1418 "Failed to receive FW final cleanup notification\n");
1420 /* Cleanup afterwards */
1421 REG_WR(p_hwfn, addr, 0);
1426 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1430 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1431 hw_mode |= 1 << MODE_BB;
1432 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1433 hw_mode |= 1 << MODE_K2;
1435 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1436 p_hwfn->p_dev->type);
1440 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1441 switch (p_hwfn->p_dev->num_ports_in_engines) {
1443 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1446 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1449 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1452 DP_NOTICE(p_hwfn, true,
1453 "num_ports_in_engine = %d not supported\n",
1454 p_hwfn->p_dev->num_ports_in_engines);
1458 switch (p_hwfn->p_dev->mf_mode) {
1459 case ECORE_MF_DEFAULT:
1461 hw_mode |= 1 << MODE_MF_SI;
1463 case ECORE_MF_OVLAN:
1464 hw_mode |= 1 << MODE_MF_SD;
1467 DP_NOTICE(p_hwfn, true,
1468 "Unsupported MF mode, init as DEFAULT\n");
1469 hw_mode |= 1 << MODE_MF_SI;
1473 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1474 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1475 hw_mode |= 1 << MODE_FPGA;
1477 if (p_hwfn->p_dev->b_is_emul_full)
1478 hw_mode |= 1 << MODE_EMUL_FULL;
1480 hw_mode |= 1 << MODE_EMUL_REDUCED;
1484 hw_mode |= 1 << MODE_ASIC;
1486 if (p_hwfn->p_dev->num_hwfns > 1)
1487 hw_mode |= 1 << MODE_100G;
1489 p_hwfn->hw_info.hw_mode = hw_mode;
1491 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1492 "Configuring function for hw_mode: 0x%08x\n",
1493 p_hwfn->hw_info.hw_mode);
1495 return ECORE_SUCCESS;
1499 /* MFW-replacement initializations for non-ASIC */
1500 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1501 struct ecore_ptt *p_ptt)
1503 struct ecore_dev *p_dev = p_hwfn->p_dev;
1507 if (CHIP_REV_IS_EMUL(p_dev)) {
1508 if (ECORE_IS_AH(p_dev))
1512 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1514 if (CHIP_REV_IS_EMUL(p_dev) &&
1515 (ECORE_IS_AH(p_dev)))
1516 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1519 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1520 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1521 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1522 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1524 if (CHIP_REV_IS_EMUL(p_dev)) {
1525 if (ECORE_IS_AH(p_dev)) {
1526 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1527 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1528 (p_dev->num_ports_in_engines >> 1));
1530 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1531 p_dev->num_ports_in_engines == 4 ? 0 : 3);
1536 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1537 for (i = 0; i < 100; i++) {
1539 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1543 DP_NOTICE(p_hwfn, true,
1544 "RBC done failed to complete in PSWRQ2\n");
1546 return ECORE_SUCCESS;
1550 /* Init run time data for all PFs and their VFs on an engine.
1551 * TBD - for VFs - Once we have parent PF info for each VF in
1552 * shmem available as CAU requires knowledge of parent PF for each VF.
1554 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1556 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1559 for_each_hwfn(p_dev, i) {
1560 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1561 struct ecore_igu_info *p_igu_info;
1562 struct ecore_igu_block *p_block;
1563 struct cau_sb_entry sb_entry;
1565 p_igu_info = p_hwfn->hw_info.p_igu_info;
1568 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1570 p_block = &p_igu_info->entry[igu_sb_id];
1572 if (!p_block->is_pf)
1575 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1576 p_block->function_id, 0, 0);
1577 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1583 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1584 struct ecore_ptt *p_ptt)
1586 u32 val, wr_mbs, cache_line_size;
1588 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1601 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1606 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1607 switch (cache_line_size) {
1622 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1626 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1628 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1629 OSAL_CACHE_LINE_SIZE, wr_mbs);
1631 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1633 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1634 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1638 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1639 struct ecore_ptt *p_ptt,
1642 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1643 struct ecore_dev *p_dev = p_hwfn->p_dev;
1644 u8 vf_id, max_num_vfs;
1647 enum _ecore_status_t rc = ECORE_SUCCESS;
1649 ecore_init_cau_rt_data(p_dev);
1651 /* Program GTT windows */
1652 ecore_gtt_init(p_hwfn, p_ptt);
1655 if (CHIP_REV_IS_EMUL(p_dev)) {
1656 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1657 if (rc != ECORE_SUCCESS)
1662 if (p_hwfn->mcp_info) {
1663 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1664 qm_info->pf_rl_en = 1;
1665 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1666 qm_info->pf_wfq_en = 1;
1669 ecore_qm_common_rt_init(p_hwfn,
1670 p_dev->num_ports_in_engines,
1671 qm_info->max_phys_tcs_per_port,
1672 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1673 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1674 qm_info->qm_port_params);
1676 ecore_cxt_hw_init_common(p_hwfn);
1678 ecore_init_cache_line_size(p_hwfn, p_ptt);
1680 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1681 if (rc != ECORE_SUCCESS)
1684 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1685 * need to decide with which value, maybe runtime
1687 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1688 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1690 if (ECORE_IS_BB(p_dev)) {
1691 /* Workaround clears ROCE search for all functions to prevent
1692 * involving non initialized function in processing ROCE packet.
1694 num_pfs = NUM_OF_ENG_PFS(p_dev);
1695 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1696 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1697 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1698 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1700 /* pretend to original PF */
1701 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1704 /* Workaround for avoiding CCFC execution error when getting packets
1705 * with CRC errors, and allowing instead the invoking of the FW error
1707 * This is not done inside the init tool since it currently can't
1708 * perform a pretending to VFs.
1710 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1711 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1712 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1713 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1714 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1715 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1716 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1717 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1719 /* pretend to original PF */
1720 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1726 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1727 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1729 #define PMEG_IF_BYTE_COUNT 8
1731 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1732 struct ecore_ptt *p_ptt,
1733 u32 addr, u64 data, u8 reg_type, u8 port)
1735 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1736 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1737 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1738 (8 << PMEG_IF_BYTE_COUNT),
1739 (reg_type << 25) | (addr << 8) | port,
1740 (u32)((data >> 32) & 0xffffffff),
1741 (u32)(data & 0xffffffff));
1743 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1744 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1745 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1746 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1747 (reg_type << 25) | (addr << 8) | port);
1748 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1749 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1750 (data >> 32) & 0xffffffff);
1753 #define XLPORT_MODE_REG (0x20a)
1754 #define XLPORT_MAC_CONTROL (0x210)
1755 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1756 #define XLPORT_ENABLE_REG (0x20b)
1758 #define XLMAC_CTRL (0x600)
1759 #define XLMAC_MODE (0x601)
1760 #define XLMAC_RX_MAX_SIZE (0x608)
1761 #define XLMAC_TX_CTRL (0x604)
1762 #define XLMAC_PAUSE_CTRL (0x60d)
1763 #define XLMAC_PFC_CTRL (0x60e)
1765 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1766 struct ecore_ptt *p_ptt)
1768 u8 loopback = 0, port = p_hwfn->port_id * 2;
1770 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1772 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1773 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1775 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1776 /* XLMAC: SOFT RESET */
1777 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1778 /* XLMAC: Port Speed >= 10Gbps */
1779 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1780 /* XLMAC: Max Size */
1781 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1782 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1783 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1785 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1786 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1787 0x30ffffc000ULL, 0, port);
1788 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1789 port); /* XLMAC: TX_EN, RX_EN */
1790 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1791 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1792 0x1003 | (loopback << 2), 0, port);
1793 /* Enabled Parallel PFC interface */
1794 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1796 /* XLPORT port enable */
1797 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1800 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1801 struct ecore_ptt *p_ptt)
1803 u8 port = p_hwfn->port_id;
1804 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1806 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1808 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1809 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1811 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1812 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1814 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1815 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1817 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1818 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1820 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1821 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1823 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1824 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1826 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1828 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1830 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1832 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1836 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1837 struct ecore_ptt *p_ptt)
1839 if (ECORE_IS_AH(p_hwfn->p_dev))
1840 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1842 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1845 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1846 struct ecore_ptt *p_ptt, u8 port)
1848 int port_offset = port ? 0x800 : 0;
1849 u32 xmac_rxctrl = 0;
1852 /* FIXME: move to common start */
1853 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1854 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1856 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1857 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1859 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1861 /* Set the number of ports on the Warp Core to 10G */
1862 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1864 /* Soft reset of XMAC */
1865 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1866 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1868 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1869 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1871 /* FIXME: move to common end */
1872 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1873 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1875 /* Set Max packet size: initialize XMAC block register for port 0 */
1876 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1878 /* CRC append for Tx packets: init XMAC block register for port 1 */
1879 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1881 /* Enable TX and RX: initialize XMAC block register for port 1 */
1882 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1883 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1884 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1885 XMAC_REG_RX_CTRL_BB + port_offset);
1886 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1887 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1891 static enum _ecore_status_t
1892 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1893 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1895 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1896 u32 dpi_bit_shift, dpi_count;
1899 /* Calculate DPI size
1900 * ------------------
1901 * The PWM region contains Doorbell Pages. The first is reserverd for
1902 * the kernel for, e.g, L2. The others are free to be used by non-
1903 * trusted applications, typically from user space. Each page, called a
1904 * doorbell page is sectioned into windows that allow doorbells to be
1905 * issued in parallel by the kernel/application. The size of such a
1906 * window (a.k.a. WID) is 1kB.
1908 * 1kB WID x N WIDS = DPI page size
1909 * DPI page size x N DPIs = PWM region size
1911 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1912 * in order to ensure that two applications won't share the same page.
1913 * It also must contain at least one WID per CPU to allow parallelism.
1914 * It also must be a power of 2, since it is stored as a bit shift.
1916 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1917 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1918 * containing 4 WIDs.
1920 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1921 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1922 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1923 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1924 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1926 dpi_count = pwm_region_size / dpi_page_size;
1928 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1929 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1932 p_hwfn->dpi_size = dpi_page_size;
1933 p_hwfn->dpi_count = dpi_count;
1935 /* Update registers */
1936 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1938 if (dpi_count < min_dpis)
1939 return ECORE_NORESOURCES;
1941 return ECORE_SUCCESS;
1944 enum ECORE_ROCE_EDPM_MODE {
1945 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1946 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1947 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1950 static enum _ecore_status_t
1951 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1952 struct ecore_ptt *p_ptt)
1954 u32 pwm_regsize, norm_regsize;
1955 u32 non_pwm_conn, min_addr_reg1;
1956 u32 db_bar_size, n_cpus;
1959 enum _ecore_status_t rc = ECORE_SUCCESS;
1962 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1963 if (p_hwfn->p_dev->num_hwfns > 1)
1966 /* Calculate doorbell regions
1967 * -----------------------------------
1968 * The doorbell BAR is made of two regions. The first is called normal
1969 * region and the second is called PWM region. In the normal region
1970 * each ICID has its own set of addresses so that writing to that
1971 * specific address identifies the ICID. In the Process Window Mode
1972 * region the ICID is given in the data written to the doorbell. The
1973 * above per PF register denotes the offset in the doorbell BAR in which
1974 * the PWM region begins.
1975 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1976 * non-PWM connection. The calculation below computes the total non-PWM
1977 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1978 * in units of 4,096 bytes.
1980 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1981 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1983 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1984 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1985 min_addr_reg1 = norm_regsize / 4096;
1986 pwm_regsize = db_bar_size - norm_regsize;
1988 /* Check that the normal and PWM sizes are valid */
1989 if (db_bar_size < norm_regsize) {
1990 DP_ERR(p_hwfn->p_dev,
1991 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1992 db_bar_size, norm_regsize);
1993 return ECORE_NORESOURCES;
1995 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1996 DP_ERR(p_hwfn->p_dev,
1997 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1998 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
2000 return ECORE_NORESOURCES;
2003 /* Calculate number of DPIs */
2004 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2005 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
2006 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
2007 /* Either EDPM is mandatory, or we are attempting to allocate a
2010 n_cpus = OSAL_NUM_ACTIVE_CPU();
2011 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2014 cond = ((rc != ECORE_SUCCESS) &&
2015 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2016 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2017 if (cond || p_hwfn->dcbx_no_edpm) {
2018 /* Either EDPM is disabled from user configuration, or it is
2019 * disabled via DCBx, or it is not mandatory and we failed to
2020 * allocated a WID per CPU.
2023 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2025 /* If we entered this flow due to DCBX then the DPM register is
2026 * already configured.
2031 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2032 norm_regsize, pwm_regsize);
2034 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2035 p_hwfn->dpi_size, p_hwfn->dpi_count,
2036 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2037 "disabled" : "enabled");
2039 /* Check return codes from above calls */
2040 if (rc != ECORE_SUCCESS) {
2042 "Failed to allocate enough DPIs\n");
2043 return ECORE_NORESOURCES;
2047 p_hwfn->dpi_start_offset = norm_regsize;
2049 /* Update registers */
2050 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2051 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2052 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2053 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2055 return ECORE_SUCCESS;
2058 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2059 struct ecore_ptt *p_ptt,
2062 enum _ecore_status_t rc = ECORE_SUCCESS;
2064 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2066 if (rc != ECORE_SUCCESS)
2069 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2072 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2073 return ECORE_SUCCESS;
2075 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2076 if (ECORE_IS_AH(p_hwfn->p_dev))
2077 return ECORE_SUCCESS;
2078 else if (ECORE_IS_BB(p_hwfn->p_dev))
2079 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2080 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2081 if (p_hwfn->p_dev->num_hwfns > 1) {
2082 /* Activate OPTE in CMT */
2085 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2087 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2088 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2089 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2090 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2091 ecore_wr(p_hwfn, p_ptt,
2092 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2093 ecore_wr(p_hwfn, p_ptt,
2094 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2095 ecore_wr(p_hwfn, p_ptt,
2096 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2100 ecore_emul_link_init(p_hwfn, p_ptt);
2102 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2109 static enum _ecore_status_t
2110 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2111 struct ecore_ptt *p_ptt,
2112 struct ecore_tunnel_info *p_tunn,
2115 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2117 u8 rel_pf_id = p_hwfn->rel_pf_id;
2119 enum _ecore_status_t rc = ECORE_SUCCESS;
2123 if (p_hwfn->mcp_info) {
2124 struct ecore_mcp_function_info *p_info;
2126 p_info = &p_hwfn->mcp_info->func_info;
2127 if (p_info->bandwidth_min)
2128 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2130 /* Update rate limit once we'll actually have a link */
2131 p_hwfn->qm_info.pf_rl = 100000;
2133 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2135 ecore_int_igu_init_rt(p_hwfn);
2137 /* Set VLAN in NIG if needed */
2138 if (hw_mode & (1 << MODE_MF_SD)) {
2139 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2140 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2141 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2142 p_hwfn->hw_info.ovlan);
2145 /* Enable classification by MAC if needed */
2146 if (hw_mode & (1 << MODE_MF_SI)) {
2147 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2148 "Configuring TAGMAC_CLS_TYPE\n");
2149 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2153 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
2154 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2155 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2156 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2157 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2158 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2160 /* perform debug configuration when chip is out of reset */
2161 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2163 /* PF Init sequence */
2164 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2168 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2169 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2173 /* Pure runtime initializations - directly to the HW */
2174 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2176 /* PCI relaxed ordering causes a decrease in the performance on some
2177 * systems. Till a root cause is found, disable this attribute in the
2181 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2183 * DP_NOTICE(p_hwfn, true,
2184 * "Failed to find the PCIe Cap\n");
2187 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2188 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2189 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2192 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2196 /* enable interrupts */
2197 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2198 if (rc != ECORE_SUCCESS)
2201 /* send function start command */
2202 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2203 p_hwfn->p_dev->mf_mode,
2204 allow_npar_tx_switch);
2206 DP_NOTICE(p_hwfn, true,
2207 "Function start ramrod failed\n");
2209 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2210 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2211 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2213 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2214 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2216 ecore_wr(p_hwfn, p_ptt,
2217 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2220 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2221 "PRS_REG_SEARCH registers after start PFn\n");
2222 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2223 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2224 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2225 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2226 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2227 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2228 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2229 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2230 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2231 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2232 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2233 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2234 prs_reg = ecore_rd(p_hwfn, p_ptt,
2235 PRS_REG_SEARCH_TCP_FIRST_FRAG);
2236 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2237 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2239 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2240 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2241 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2247 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2248 struct ecore_ptt *p_ptt,
2251 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2253 /* Configure the PF's internal FID_enable for master transactions */
2254 ecore_wr(p_hwfn, p_ptt,
2255 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2257 /* Wait until value is set - try for 1 second every 50us */
2258 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2259 val = ecore_rd(p_hwfn, p_ptt,
2260 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2267 if (val != set_val) {
2268 DP_NOTICE(p_hwfn, true,
2269 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2270 return ECORE_UNKNOWN_ERROR;
2273 return ECORE_SUCCESS;
2276 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2277 struct ecore_ptt *p_main_ptt)
2279 /* Read shadow of current MFW mailbox */
2280 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2281 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2282 p_hwfn->mcp_info->mfw_mb_cur,
2283 p_hwfn->mcp_info->mfw_mb_length);
2286 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2287 struct ecore_hw_init_params *p_params)
2289 if (p_params->p_tunn) {
2290 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2291 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2294 p_hwfn->b_int_enabled = 1;
2296 return ECORE_SUCCESS;
2299 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2300 struct ecore_ptt *p_ptt)
2302 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2303 1 << p_hwfn->abs_pf_id);
2307 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2308 struct ecore_drv_load_params *p_drv_load)
2310 /* Make sure that if ecore-client didn't provide inputs, all the
2311 * expected defaults are indeed zero.
2313 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2314 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2315 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2317 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2319 if (p_drv_load != OSAL_NULL) {
2320 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2321 ECORE_DRV_ROLE_KDUMP :
2323 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2324 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2325 p_load_req->override_force_load =
2326 p_drv_load->override_force_load;
2330 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2331 struct ecore_hw_init_params *p_params)
2333 struct ecore_load_req_params load_req_params;
2334 u32 load_code, resp, param, drv_mb_param;
2335 bool b_default_mtu = true;
2336 struct ecore_hwfn *p_hwfn;
2337 enum _ecore_status_t rc = ECORE_SUCCESS;
2340 if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
2341 (p_dev->num_hwfns > 1)) {
2342 DP_NOTICE(p_dev, false,
2343 "MSI mode is not supported for CMT devices\n");
2348 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2349 if (rc != ECORE_SUCCESS)
2353 for_each_hwfn(p_dev, i) {
2354 p_hwfn = &p_dev->hwfns[i];
2356 /* If management didn't provide a default, set one of our own */
2357 if (!p_hwfn->hw_info.mtu) {
2358 p_hwfn->hw_info.mtu = 1500;
2359 b_default_mtu = false;
2363 ecore_vf_start(p_hwfn, p_params);
2367 rc = ecore_calc_hw_mode(p_hwfn);
2368 if (rc != ECORE_SUCCESS)
2371 ecore_fill_load_req_params(&load_req_params,
2372 p_params->p_drv_load_params);
2373 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2375 if (rc != ECORE_SUCCESS) {
2376 DP_NOTICE(p_hwfn, true,
2377 "Failed sending a LOAD_REQ command\n");
2381 load_code = load_req_params.load_code;
2382 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2383 "Load request was sent. Load code: 0x%x\n",
2386 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2389 * When coming back from hiberbate state, the registers from
2390 * which shadow is read initially are not initialized. It turns
2391 * out that these registers get initialized during the call to
2392 * ecore_mcp_load_req request. So we need to reread them here
2393 * to get the proper shadow register value.
2394 * Note: This is a workaround for the missing MFW
2395 * initialization. It may be removed once the implementation
2398 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2400 /* Only relevant for recovery:
2401 * Clear the indication after the LOAD_REQ command is responded
2404 p_dev->recov_in_prog = false;
2406 p_hwfn->first_on_engine = (load_code ==
2407 FW_MSG_CODE_DRV_LOAD_ENGINE);
2409 if (!qm_lock_init) {
2410 OSAL_SPIN_LOCK_INIT(&qm_lock);
2411 qm_lock_init = true;
2414 /* Clean up chip from previous driver if such remains exist.
2415 * This is not needed when the PF is the first one on the
2416 * engine, since afterwards we are going to init the FW.
2418 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2419 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2420 p_hwfn->rel_pf_id, false);
2421 if (rc != ECORE_SUCCESS) {
2422 ecore_hw_err_notify(p_hwfn,
2423 ECORE_HW_ERR_RAMROD_FAIL);
2428 /* Log and clean previous pglue_b errors if such exist */
2429 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2430 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2432 /* Enable the PF's internal FID_enable in the PXP */
2433 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2435 if (rc != ECORE_SUCCESS)
2438 switch (load_code) {
2439 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2440 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2441 p_hwfn->hw_info.hw_mode);
2442 if (rc != ECORE_SUCCESS)
2445 case FW_MSG_CODE_DRV_LOAD_PORT:
2446 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2447 p_hwfn->hw_info.hw_mode);
2448 if (rc != ECORE_SUCCESS)
2451 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2452 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2454 p_hwfn->hw_info.hw_mode,
2455 p_params->b_hw_start,
2457 p_params->allow_npar_tx_switch);
2460 DP_NOTICE(p_hwfn, false,
2461 "Unexpected load code [0x%08x]", load_code);
2466 if (rc != ECORE_SUCCESS) {
2467 DP_NOTICE(p_hwfn, true,
2468 "init phase failed for loadcode 0x%x (rc %d)\n",
2473 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2474 if (rc != ECORE_SUCCESS)
2477 /* send DCBX attention request command */
2478 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2479 "sending phony dcbx set command to trigger DCBx attention handling\n");
2480 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2481 DRV_MSG_CODE_SET_DCBX,
2482 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2484 if (rc != ECORE_SUCCESS) {
2485 DP_NOTICE(p_hwfn, true,
2486 "Failed to send DCBX attention request\n");
2490 p_hwfn->hw_init_done = true;
2494 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2495 drv_mb_param = STORM_FW_VERSION;
2496 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2497 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2498 drv_mb_param, &resp, ¶m);
2499 if (rc != ECORE_SUCCESS)
2500 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2503 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2504 p_hwfn->hw_info.mtu);
2505 if (rc != ECORE_SUCCESS)
2506 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2508 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2510 ECORE_OV_DRIVER_STATE_DISABLED);
2511 if (rc != ECORE_SUCCESS)
2512 DP_INFO(p_hwfn, "Failed to update driver state\n");
2518 /* The MFW load lock should be released regardless of success or failure
2519 * of initialization.
2520 * TODO: replace this with an attempt to send cancel_load.
2522 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2526 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2527 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2528 struct ecore_hwfn *p_hwfn,
2529 struct ecore_ptt *p_ptt)
2534 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2535 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2536 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2538 if ((!ecore_rd(p_hwfn, p_ptt,
2539 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2540 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2543 /* Dependent on number of connection/tasks, possibly
2544 * 1ms sleep is required between polls
2549 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2552 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2553 " [Connection %02x Tasks %02x]\n",
2554 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2555 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2558 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2562 for_each_hwfn(p_dev, j) {
2563 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2564 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2566 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2570 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2571 struct ecore_ptt *p_ptt,
2572 u32 addr, u32 expected_val)
2574 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2576 if (val != expected_val) {
2577 DP_NOTICE(p_hwfn, true,
2578 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2579 addr, val, expected_val);
2580 return ECORE_UNKNOWN_ERROR;
2583 return ECORE_SUCCESS;
2586 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2588 struct ecore_hwfn *p_hwfn;
2589 struct ecore_ptt *p_ptt;
2590 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2593 for_each_hwfn(p_dev, j) {
2594 p_hwfn = &p_dev->hwfns[j];
2595 p_ptt = p_hwfn->p_main_ptt;
2597 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2600 ecore_vf_pf_int_cleanup(p_hwfn);
2601 rc = ecore_vf_pf_reset(p_hwfn);
2602 if (rc != ECORE_SUCCESS) {
2603 DP_NOTICE(p_hwfn, true,
2604 "ecore_vf_pf_reset failed. rc = %d.\n",
2606 rc2 = ECORE_UNKNOWN_ERROR;
2611 /* mark the hw as uninitialized... */
2612 p_hwfn->hw_init_done = false;
2614 /* Send unload command to MCP */
2615 if (!p_dev->recov_in_prog) {
2616 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2617 if (rc != ECORE_SUCCESS) {
2618 DP_NOTICE(p_hwfn, true,
2619 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2621 rc2 = ECORE_UNKNOWN_ERROR;
2625 OSAL_DPC_SYNC(p_hwfn);
2627 /* After this point no MFW attentions are expected, e.g. prevent
2628 * race between pf stop and dcbx pf update.
2631 rc = ecore_sp_pf_stop(p_hwfn);
2632 if (rc != ECORE_SUCCESS) {
2633 DP_NOTICE(p_hwfn, true,
2634 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2636 rc2 = ECORE_UNKNOWN_ERROR;
2639 /* perform debug action after PF stop was sent */
2640 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2642 /* close NIG to BRB gate */
2643 ecore_wr(p_hwfn, p_ptt,
2644 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2647 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2648 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2649 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2650 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2651 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2653 /* @@@TBD - clean transmission queues (5.b) */
2654 /* @@@TBD - clean BTB (5.c) */
2656 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2658 /* @@@TBD - verify DMAE requests are done (8) */
2660 /* Disable Attention Generation */
2661 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2662 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2663 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2664 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2665 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2666 if (rc != ECORE_SUCCESS) {
2667 DP_NOTICE(p_hwfn, true,
2668 "Failed to return IGU CAM to default\n");
2669 rc2 = ECORE_UNKNOWN_ERROR;
2672 /* Need to wait 1ms to guarantee SBs are cleared */
2675 if (!p_dev->recov_in_prog) {
2676 ecore_verify_reg_val(p_hwfn, p_ptt,
2677 QM_REG_USG_CNT_PF_TX, 0);
2678 ecore_verify_reg_val(p_hwfn, p_ptt,
2679 QM_REG_USG_CNT_PF_OTHER, 0);
2680 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2683 /* Disable PF in HW blocks */
2684 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2685 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2687 if (!p_dev->recov_in_prog) {
2688 ecore_mcp_unload_done(p_hwfn, p_ptt);
2689 if (rc != ECORE_SUCCESS) {
2690 DP_NOTICE(p_hwfn, true,
2691 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2693 rc2 = ECORE_UNKNOWN_ERROR;
2698 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2699 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2700 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2702 /* Clear the PF's internal FID_enable in the PXP.
2703 * In CMT this should only be done for first hw-function, and
2704 * only after all transactions have stopped for all active
2707 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2709 if (rc != ECORE_SUCCESS) {
2710 DP_NOTICE(p_hwfn, true,
2711 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2713 rc2 = ECORE_UNKNOWN_ERROR;
2720 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2724 for_each_hwfn(p_dev, j) {
2725 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2726 struct ecore_ptt *p_ptt;
2729 ecore_vf_pf_int_cleanup(p_hwfn);
2732 p_ptt = ecore_ptt_acquire(p_hwfn);
2736 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2737 "Shutting down the fastpath\n");
2739 ecore_wr(p_hwfn, p_ptt,
2740 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2742 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2743 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2744 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2745 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2746 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2748 /* @@@TBD - clean transmission queues (5.b) */
2749 /* @@@TBD - clean BTB (5.c) */
2751 /* @@@TBD - verify DMAE requests are done (8) */
2753 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2754 /* Need to wait 1ms to guarantee SBs are cleared */
2756 ecore_ptt_release(p_hwfn, p_ptt);
2759 return ECORE_SUCCESS;
2762 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2764 struct ecore_ptt *p_ptt;
2766 if (IS_VF(p_hwfn->p_dev))
2767 return ECORE_SUCCESS;
2769 p_ptt = ecore_ptt_acquire(p_hwfn);
2773 /* If roce info is allocated it means roce is initialized and should
2774 * be enabled in searcher.
2776 if (p_hwfn->p_rdma_info) {
2777 if (p_hwfn->b_rdma_enabled_in_prs)
2778 ecore_wr(p_hwfn, p_ptt,
2779 p_hwfn->rdma_prs_search_reg, 0x1);
2780 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2783 /* Re-open incoming traffic */
2784 ecore_wr(p_hwfn, p_ptt,
2785 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2786 ecore_ptt_release(p_hwfn, p_ptt);
2788 return ECORE_SUCCESS;
2791 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2792 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2794 ecore_ptt_pool_free(p_hwfn);
2795 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2798 /* Setup bar access */
2799 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2801 /* clear indirect access */
2802 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2803 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2804 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2805 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2806 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2807 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2808 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2809 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2810 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2812 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2813 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2814 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2815 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2816 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2817 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2818 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2819 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2822 /* Clean previous pglue_b errors if such exist */
2823 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2825 /* enable internal target-read */
2826 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2827 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2830 static void get_function_id(struct ecore_hwfn *p_hwfn)
2833 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2834 PXP_PF_ME_OPAQUE_ADDR);
2836 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2838 /* Bits 16-19 from the ME registers are the pf_num */
2839 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2840 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2841 PXP_CONCRETE_FID_PFID);
2842 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2843 PXP_CONCRETE_FID_PORT);
2845 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2846 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2847 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2850 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2852 u32 *feat_num = p_hwfn->hw_info.feat_num;
2853 struct ecore_sb_cnt_info sb_cnt;
2856 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2857 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2859 /* L2 Queues require each: 1 status block. 1 L2 queue */
2860 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2861 /* Start by allocating VF queues, then PF's */
2862 feat_num[ECORE_VF_L2_QUE] =
2864 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2866 feat_num[ECORE_PF_L2_QUE] =
2868 sb_cnt.cnt - non_l2_sbs,
2869 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2870 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2873 feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2876 feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2880 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2881 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2882 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2883 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2884 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2885 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2886 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2890 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2893 case ECORE_L2_QUEUE:
2907 case ECORE_RDMA_CNQ_RAM:
2908 return "RDMA_CNQ_RAM";
2911 case ECORE_LL2_QUEUE:
2913 case ECORE_CMDQS_CQS:
2915 case ECORE_RDMA_STATS_QUEUE:
2916 return "RDMA_STATS_QUEUE";
2922 return "UNKNOWN_RESOURCE";
2926 static enum _ecore_status_t
2927 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2928 struct ecore_ptt *p_ptt,
2929 enum ecore_resources res_id,
2933 enum _ecore_status_t rc;
2935 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2936 resc_max_val, p_mcp_resp);
2937 if (rc != ECORE_SUCCESS) {
2938 DP_NOTICE(p_hwfn, true,
2939 "MFW response failure for a max value setting of resource %d [%s]\n",
2940 res_id, ecore_hw_get_resc_name(res_id));
2944 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2946 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2947 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2949 return ECORE_SUCCESS;
2952 static enum _ecore_status_t
2953 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2954 struct ecore_ptt *p_ptt)
2956 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2957 u32 resc_max_val, mcp_resp;
2959 enum _ecore_status_t rc;
2961 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2964 case ECORE_LL2_QUEUE:
2965 case ECORE_RDMA_CNQ_RAM:
2966 case ECORE_RDMA_STATS_QUEUE:
2974 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2975 resc_max_val, &mcp_resp);
2976 if (rc != ECORE_SUCCESS)
2979 /* There's no point to continue to the next resource if the
2980 * command is not supported by the MFW.
2981 * We do continue if the command is supported but the resource
2982 * is unknown to the MFW. Such a resource will be later
2983 * configured with the default allocation values.
2985 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2986 return ECORE_NOTIMPL;
2989 return ECORE_SUCCESS;
2993 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2994 enum ecore_resources res_id,
2995 u32 *p_resc_num, u32 *p_resc_start)
2997 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2998 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3001 case ECORE_L2_QUEUE:
3002 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3003 MAX_NUM_L2_QUEUES_BB) / num_funcs;
3006 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3007 MAX_NUM_VPORTS_BB) / num_funcs;
3010 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3011 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3014 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3015 MAX_QM_TX_QUEUES_BB) / num_funcs;
3018 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3022 /* Each VFC resource can accommodate both a MAC and a VLAN */
3023 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3026 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3027 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3029 case ECORE_LL2_QUEUE:
3030 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3032 case ECORE_RDMA_CNQ_RAM:
3033 case ECORE_CMDQS_CQS:
3034 /* CNQ/CMDQS are the same resource */
3036 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3038 case ECORE_RDMA_STATS_QUEUE:
3040 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3041 MAX_NUM_VPORTS_BB) / num_funcs;
3058 /* Since we want its value to reflect whether MFW supports
3059 * the new scheme, have a default of 0.
3064 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3068 return ECORE_SUCCESS;
3071 static enum _ecore_status_t
3072 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3073 bool drv_resc_alloc)
3075 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3076 u32 mcp_resp, *p_resc_num, *p_resc_start;
3077 enum _ecore_status_t rc;
3079 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3080 p_resc_start = &RESC_START(p_hwfn, res_id);
3082 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3084 if (rc != ECORE_SUCCESS) {
3086 "Failed to get default amount for resource %d [%s]\n",
3087 res_id, ecore_hw_get_resc_name(res_id));
3092 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3093 *p_resc_num = dflt_resc_num;
3094 *p_resc_start = dflt_resc_start;
3099 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3100 &mcp_resp, p_resc_num, p_resc_start);
3101 if (rc != ECORE_SUCCESS) {
3102 DP_NOTICE(p_hwfn, true,
3103 "MFW response failure for an allocation request for"
3104 " resource %d [%s]\n",
3105 res_id, ecore_hw_get_resc_name(res_id));
3109 /* Default driver values are applied in the following cases:
3110 * - The resource allocation MB command is not supported by the MFW
3111 * - There is an internal error in the MFW while processing the request
3112 * - The resource ID is unknown to the MFW
3114 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3116 "Failed to receive allocation info for resource %d [%s]."
3117 " mcp_resp = 0x%x. Applying default values"
3119 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3120 dflt_resc_num, dflt_resc_start);
3122 *p_resc_num = dflt_resc_num;
3123 *p_resc_start = dflt_resc_start;
3127 if ((*p_resc_num != dflt_resc_num ||
3128 *p_resc_start != dflt_resc_start) &&
3129 res_id != ECORE_SB) {
3131 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3132 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3133 *p_resc_start, dflt_resc_num, dflt_resc_start,
3134 drv_resc_alloc ? " - Applying default values" : "");
3135 if (drv_resc_alloc) {
3136 *p_resc_num = dflt_resc_num;
3137 *p_resc_start = dflt_resc_start;
3141 return ECORE_SUCCESS;
3144 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3145 bool drv_resc_alloc)
3147 enum _ecore_status_t rc;
3150 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3151 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3152 if (rc != ECORE_SUCCESS)
3156 return ECORE_SUCCESS;
3159 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3160 struct ecore_ptt *p_ptt,
3161 bool drv_resc_alloc)
3163 struct ecore_resc_unlock_params resc_unlock_params;
3164 struct ecore_resc_lock_params resc_lock_params;
3165 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3167 enum _ecore_status_t rc;
3169 u32 *resc_start = p_hwfn->hw_info.resc_start;
3170 u32 *resc_num = p_hwfn->hw_info.resc_num;
3171 /* For AH, an equal share of the ILT lines between the maximal number of
3172 * PFs is not enough for RoCE. This would be solved by the future
3173 * resource allocation scheme, but isn't currently present for
3174 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3175 * to work - the BB number of ILT lines divided by its max PFs number.
3177 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3180 /* Setting the max values of the soft resources and the following
3181 * resources allocation queries should be atomic. Since several PFs can
3182 * run in parallel - a resource lock is needed.
3183 * If either the resource lock or resource set value commands are not
3184 * supported - skip the the max values setting, release the lock if
3185 * needed, and proceed to the queries. Other failures, including a
3186 * failure to acquire the lock, will cause this function to fail.
3187 * Old drivers that don't acquire the lock can run in parallel, and
3188 * their allocation values won't be affected by the updated max values.
3190 ecore_mcp_resc_lock_default_init(p_hwfn, &resc_lock_params,
3191 &resc_unlock_params,
3192 ECORE_RESC_LOCK_RESC_ALLOC, false);
3194 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3195 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3197 } else if (rc == ECORE_NOTIMPL) {
3199 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3200 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3201 DP_NOTICE(p_hwfn, false,
3202 "Failed to acquire the resource lock for the resource allocation commands\n");
3204 goto unlock_and_exit;
3206 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3207 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3208 DP_NOTICE(p_hwfn, false,
3209 "Failed to set the max values of the soft resources\n");
3210 goto unlock_and_exit;
3211 } else if (rc == ECORE_NOTIMPL) {
3213 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3214 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3215 &resc_unlock_params);
3216 if (rc != ECORE_SUCCESS)
3218 "Failed to release the resource lock for the resource allocation commands\n");
3222 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3223 if (rc != ECORE_SUCCESS)
3224 goto unlock_and_exit;
3226 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3227 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3228 &resc_unlock_params);
3229 if (rc != ECORE_SUCCESS)
3231 "Failed to release the resource lock for the resource allocation commands\n");
3235 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3236 /* Reduced build contains less PQs */
3237 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3238 resc_num[ECORE_PQ] = 32;
3239 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3240 p_hwfn->enabled_func_idx;
3243 /* For AH emulation, since we have a possible maximal number of
3244 * 16 enabled PFs, in case there are not enough ILT lines -
3245 * allocate only first PF as RoCE and have all the other ETH
3246 * only with less ILT lines.
3248 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3249 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3250 resc_num[ECORE_ILT],
3251 roce_min_ilt_lines);
3254 /* Correct the common ILT calculation if PF0 has more */
3255 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3256 p_hwfn->p_dev->b_is_emul_full &&
3257 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3258 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3259 resc_num[ECORE_ILT];
3262 /* Sanity for ILT */
3263 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3264 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3265 DP_NOTICE(p_hwfn, true,
3266 "Can't assign ILT pages [%08x,...,%08x]\n",
3267 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3273 /* This will also learn the number of SBs from MFW */
3274 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3277 ecore_hw_set_feat(p_hwfn);
3279 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3280 "The numbers for each resource are:\n");
3281 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3282 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3283 ecore_hw_get_resc_name(res_id),
3284 RESC_NUM(p_hwfn, res_id),
3285 RESC_START(p_hwfn, res_id));
3287 return ECORE_SUCCESS;
3290 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3291 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3292 &resc_unlock_params);
3296 static enum _ecore_status_t
3297 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3298 struct ecore_ptt *p_ptt,
3299 struct ecore_hw_prepare_params *p_params)
3301 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3302 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3303 struct ecore_mcp_link_capabilities *p_caps;
3304 struct ecore_mcp_link_params *link;
3305 enum _ecore_status_t rc;
3307 /* Read global nvm_cfg address */
3308 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3310 /* Verify MCP has initialized it */
3311 if (!nvm_cfg_addr) {
3312 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3313 if (p_params->b_relaxed_probe)
3314 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3318 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
3320 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3322 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3323 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
3326 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3328 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3329 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3330 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3331 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3333 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3334 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3336 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3337 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3339 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3340 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3342 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3343 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3345 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3346 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3348 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3349 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3351 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3352 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3354 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3355 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3357 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3358 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3360 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3361 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3364 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3369 /* Read DCBX configuration */
3370 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3371 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3372 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3374 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3375 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3376 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3377 switch (dcbx_mode) {
3378 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3379 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3381 case NVM_CFG1_PORT_DCBX_MODE_CEE:
3382 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3384 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3385 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3388 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3391 /* Read default link configuration */
3392 link = &p_hwfn->mcp_info->link_input;
3393 p_caps = &p_hwfn->mcp_info->link_capabilities;
3394 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3395 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3396 link_temp = ecore_rd(p_hwfn, p_ptt,
3398 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3399 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3400 link->speed.advertised_speeds = link_temp;
3401 p_caps->speed_capabilities = link->speed.advertised_speeds;
3403 link_temp = ecore_rd(p_hwfn, p_ptt,
3405 OFFSETOF(struct nvm_cfg1_port, link_settings));
3406 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3407 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3408 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3409 link->speed.autoneg = true;
3411 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3412 link->speed.forced_speed = 1000;
3414 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3415 link->speed.forced_speed = 10000;
3417 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3418 link->speed.forced_speed = 25000;
3420 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3421 link->speed.forced_speed = 40000;
3423 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3424 link->speed.forced_speed = 50000;
3426 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3427 link->speed.forced_speed = 100000;
3430 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3433 p_caps->default_speed = link->speed.forced_speed;
3434 p_caps->default_speed_autoneg = link->speed.autoneg;
3436 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3437 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3438 link->pause.autoneg = !!(link_temp &
3439 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3440 link->pause.forced_rx = !!(link_temp &
3441 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3442 link->pause.forced_tx = !!(link_temp &
3443 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3444 link->loopback_mode = 0;
3446 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3447 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3448 OFFSETOF(struct nvm_cfg1_port, ext_phy));
3449 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3450 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3451 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3452 link->eee.enable = true;
3453 switch (link_temp) {
3454 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3455 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3456 link->eee.enable = false;
3458 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3459 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3461 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3462 p_caps->eee_lpi_timer =
3463 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3465 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3466 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3470 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3471 link->eee.tx_lpi_enable = link->eee.enable;
3472 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3474 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3477 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3478 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3479 link->speed.forced_speed, link->speed.advertised_speeds,
3480 link->speed.autoneg, link->pause.autoneg,
3481 p_caps->default_eee, p_caps->eee_lpi_timer);
3483 /* Read Multi-function information from shmem */
3484 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3485 OFFSETOF(struct nvm_cfg1, glob) +
3486 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3488 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3490 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3491 NVM_CFG1_GLOB_MF_MODE_OFFSET;
3494 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3495 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3497 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3498 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3500 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3501 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3504 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3505 p_hwfn->p_dev->mf_mode);
3507 /* Read Multi-function information from shmem */
3508 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3509 OFFSETOF(struct nvm_cfg1, glob) +
3510 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3512 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3513 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3514 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3515 &p_hwfn->hw_info.device_capabilities);
3516 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3517 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3518 &p_hwfn->hw_info.device_capabilities);
3519 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3520 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3521 &p_hwfn->hw_info.device_capabilities);
3522 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3523 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3524 &p_hwfn->hw_info.device_capabilities);
3525 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3526 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3527 &p_hwfn->hw_info.device_capabilities);
3529 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3530 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3532 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3538 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3539 struct ecore_ptt *p_ptt)
3541 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3542 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3543 struct ecore_dev *p_dev = p_hwfn->p_dev;
3545 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3547 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3548 * in the other bits are selected.
3549 * Bits 1-15 are for functions 1-15, respectively, and their value is
3550 * '0' only for enabled functions (function 0 always exists and
3552 * In case of CMT in BB, only the "even" functions are enabled, and thus
3553 * the number of functions for both hwfns is learnt from the same bits.
3555 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3556 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3557 MISCS_REG_FUNCTION_HIDE_BB_K2);
3559 reg_function_hide = 0;
3562 if (reg_function_hide & 0x1) {
3563 if (ECORE_IS_BB(p_dev)) {
3564 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3576 /* Get the number of the enabled functions on the engine */
3577 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3584 /* Get the PF index within the enabled functions */
3585 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3586 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3594 p_hwfn->num_funcs_on_engine = num_funcs;
3595 p_hwfn->enabled_func_idx = enabled_func_idx;
3598 if (CHIP_REV_IS_FPGA(p_dev)) {
3599 DP_NOTICE(p_hwfn, false,
3600 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3601 p_hwfn->num_funcs_on_engine = 4;
3605 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3606 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3607 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3608 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3611 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3612 struct ecore_ptt *p_ptt)
3617 /* Read the port mode */
3618 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3620 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3621 (p_hwfn->p_dev->num_hwfns > 1))
3622 /* In CMT on emulation, assume 1 port */
3626 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3628 if (port_mode < 3) {
3629 p_hwfn->p_dev->num_ports_in_engines = 1;
3630 } else if (port_mode <= 5) {
3631 p_hwfn->p_dev->num_ports_in_engines = 2;
3633 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3634 p_hwfn->p_dev->num_ports_in_engines);
3636 /* Default num_ports_in_engines to something */
3637 p_hwfn->p_dev->num_ports_in_engines = 1;
3641 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3642 struct ecore_ptt *p_ptt)
3647 p_hwfn->p_dev->num_ports_in_engines = 0;
3650 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3651 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3652 switch ((port & 0xf000) >> 12) {
3654 p_hwfn->p_dev->num_ports_in_engines = 1;
3657 p_hwfn->p_dev->num_ports_in_engines = 2;
3660 p_hwfn->p_dev->num_ports_in_engines = 4;
3663 DP_NOTICE(p_hwfn, false,
3664 "Unknown port mode in ECO_RESERVED %08x\n",
3669 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3670 port = ecore_rd(p_hwfn, p_ptt,
3671 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3674 p_hwfn->p_dev->num_ports_in_engines++;
3678 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3679 struct ecore_ptt *p_ptt)
3681 if (ECORE_IS_BB(p_hwfn->p_dev))
3682 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3684 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3687 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3688 struct ecore_ptt *p_ptt)
3690 struct ecore_mcp_link_capabilities *p_caps;
3693 p_caps = &p_hwfn->mcp_info->link_capabilities;
3694 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3697 p_caps->eee_speed_caps = 0;
3698 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3699 OFFSETOF(struct public_port, eee_status));
3700 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3701 EEE_SUPPORTED_SPEED_OFFSET;
3702 if (eee_status & EEE_1G_SUPPORTED)
3703 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3704 if (eee_status & EEE_10G_ADV)
3705 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3708 static enum _ecore_status_t
3709 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3710 enum ecore_pci_personality personality,
3711 struct ecore_hw_prepare_params *p_params)
3713 bool drv_resc_alloc = p_params->drv_resc_alloc;
3714 enum _ecore_status_t rc;
3716 /* Since all information is common, only first hwfns should do this */
3717 if (IS_LEAD_HWFN(p_hwfn)) {
3718 rc = ecore_iov_hw_info(p_hwfn);
3719 if (rc != ECORE_SUCCESS) {
3720 if (p_params->b_relaxed_probe)
3721 p_params->p_relaxed_res =
3722 ECORE_HW_PREPARE_BAD_IOV;
3728 /* TODO In get_hw_info, amoungst others:
3729 * Get MCP FW revision and determine according to it the supported
3730 * featrues (e.g. DCB)
3732 * ecore_get_pcie_width_speed, WOL capability.
3733 * Number of global CQ-s (for storage
3735 ecore_hw_info_port_num(p_hwfn, p_ptt);
3737 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3740 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3742 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3743 if (rc != ECORE_SUCCESS)
3749 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3750 if (rc != ECORE_SUCCESS) {
3751 if (p_params->b_relaxed_probe)
3752 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3758 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3760 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3761 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3764 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3766 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3767 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3771 if (ecore_mcp_is_init(p_hwfn)) {
3772 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3773 p_hwfn->hw_info.ovlan =
3774 p_hwfn->mcp_info->func_info.ovlan;
3776 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3778 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3781 if (personality != ECORE_PCI_DEFAULT) {
3782 p_hwfn->hw_info.personality = personality;
3783 } else if (ecore_mcp_is_init(p_hwfn)) {
3784 enum ecore_pci_personality protocol;
3786 protocol = p_hwfn->mcp_info->func_info.protocol;
3787 p_hwfn->hw_info.personality = protocol;
3791 /* To overcome ILT lack for emulation, until at least until we'll have
3792 * a definite answer from system about it, allow only PF0 to be RoCE.
3794 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3795 if (!p_hwfn->rel_pf_id)
3796 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3798 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3802 /* although in BB some constellations may support more than 4 tcs,
3803 * that can result in performance penalty in some cases. 4
3804 * represents a good tradeoff between performance and flexibility.
3806 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3808 /* start out with a single active tc. This can be increased either
3809 * by dcbx negotiation or by upper layer driver
3811 p_hwfn->hw_info.num_active_tc = 1;
3813 ecore_get_num_funcs(p_hwfn, p_ptt);
3815 if (ecore_mcp_is_init(p_hwfn))
3816 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3818 /* In case of forcing the driver's default resource allocation, calling
3819 * ecore_hw_get_resc() should come after initializing the personality
3820 * and after getting the number of functions, since the calculation of
3821 * the resources/features depends on them.
3822 * This order is not harmful if not forcing.
3824 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3825 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3827 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3833 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3834 struct ecore_ptt *p_ptt)
3836 struct ecore_dev *p_dev = p_hwfn->p_dev;
3840 /* Read Vendor Id / Device Id */
3841 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3843 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3846 /* Determine type */
3847 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3848 switch (device_id_mask) {
3849 case ECORE_DEV_ID_MASK_BB:
3850 p_dev->type = ECORE_DEV_TYPE_BB;
3852 case ECORE_DEV_ID_MASK_AH:
3853 p_dev->type = ECORE_DEV_TYPE_AH;
3856 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3858 return ECORE_ABORTED;
3861 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_ptt,
3862 MISCS_REG_CHIP_NUM);
3863 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_ptt,
3864 MISCS_REG_CHIP_REV);
3866 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3868 /* Learn number of HW-functions */
3869 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3871 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3872 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3873 p_dev->num_hwfns = 2;
3875 p_dev->num_hwfns = 1;
3879 if (CHIP_REV_IS_EMUL(p_dev)) {
3880 /* For some reason we have problems with this register
3881 * in B0 emulation; Simply assume no CMT
3883 DP_NOTICE(p_dev->hwfns, false,
3884 "device on emul - assume no CMT\n");
3885 p_dev->num_hwfns = 1;
3889 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_ptt,
3890 MISCS_REG_CHIP_TEST_REG) >> 4;
3891 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3892 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_ptt,
3893 MISCS_REG_CHIP_METAL);
3894 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3895 DP_INFO(p_dev->hwfns,
3896 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3897 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3898 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3899 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3902 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3903 DP_NOTICE(p_dev->hwfns, false,
3904 "The chip type/rev (BB A0) is not supported!\n");
3905 return ECORE_ABORTED;
3908 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3909 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3911 if (CHIP_REV_IS_EMUL(p_dev)) {
3912 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3913 if (tmp & (1 << 29)) {
3914 DP_NOTICE(p_hwfn, false,
3915 "Emulation: Running on a FULL build\n");
3916 p_dev->b_is_emul_full = true;
3918 DP_NOTICE(p_hwfn, false,
3919 "Emulation: Running on a REDUCED build\n");
3924 return ECORE_SUCCESS;
3927 #ifndef LINUX_REMOVE
3928 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3935 for_each_hwfn(p_dev, j) {
3936 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3938 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3939 "Mark hw/fw uninitialized\n");
3941 p_hwfn->hw_init_done = false;
3942 p_hwfn->first_on_engine = false;
3944 ecore_ptt_invalidate(p_hwfn);
3949 static enum _ecore_status_t
3950 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3951 void OSAL_IOMEM * p_regview,
3952 void OSAL_IOMEM * p_doorbells,
3953 struct ecore_hw_prepare_params *p_params)
3955 struct ecore_mdump_retain_data mdump_retain;
3956 struct ecore_dev *p_dev = p_hwfn->p_dev;
3957 struct ecore_mdump_info mdump_info;
3958 enum _ecore_status_t rc = ECORE_SUCCESS;
3960 /* Split PCI bars evenly between hwfns */
3961 p_hwfn->regview = p_regview;
3962 p_hwfn->doorbells = p_doorbells;
3965 return ecore_vf_hw_prepare(p_hwfn);
3967 /* Validate that chip access is feasible */
3968 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3970 "Reading the ME register returns all Fs; Preventing further chip access\n");
3971 if (p_params->b_relaxed_probe)
3972 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3976 get_function_id(p_hwfn);
3978 /* Allocate PTT pool */
3979 rc = ecore_ptt_pool_alloc(p_hwfn);
3981 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3982 if (p_params->b_relaxed_probe)
3983 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3987 /* Allocate the main PTT */
3988 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3990 /* First hwfn learns basic information, e.g., number of hwfns */
3991 if (!p_hwfn->my_id) {
3992 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3993 if (rc != ECORE_SUCCESS) {
3994 if (p_params->b_relaxed_probe)
3995 p_params->p_relaxed_res =
3996 ECORE_HW_PREPARE_FAILED_DEV;
4001 ecore_hw_hwfn_prepare(p_hwfn);
4003 /* Initialize MCP structure */
4004 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4006 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
4007 if (p_params->b_relaxed_probe)
4008 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4012 /* Read the device configuration information from the HW and SHMEM */
4013 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4014 p_params->personality, p_params);
4016 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
4020 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4021 * called, since among others it sets the ports number in an engine.
4023 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4024 !p_dev->recov_in_prog) {
4025 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4026 if (rc != ECORE_SUCCESS)
4027 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4030 /* Check if mdump logs/data are present and update the epoch value */
4031 if (IS_LEAD_HWFN(p_hwfn)) {
4033 if (!CHIP_REV_IS_EMUL(p_dev)) {
4035 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4037 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4038 DP_NOTICE(p_hwfn, false,
4039 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4041 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4043 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4044 DP_NOTICE(p_hwfn, false,
4045 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4046 mdump_retain.epoch, mdump_retain.pf,
4047 mdump_retain.status);
4049 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4056 /* Allocate the init RT array and initialize the init-ops engine */
4057 rc = ecore_init_alloc(p_hwfn);
4059 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
4060 if (p_params->b_relaxed_probe)
4061 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4065 if (CHIP_REV_IS_FPGA(p_dev)) {
4066 DP_NOTICE(p_hwfn, false,
4067 "FPGA: workaround; Prevent DMAE parities\n");
4068 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4071 DP_NOTICE(p_hwfn, false,
4072 "FPGA: workaround: Set VF bar0 size\n");
4073 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4074 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4080 if (IS_LEAD_HWFN(p_hwfn))
4081 ecore_iov_free_hw_info(p_dev);
4082 ecore_mcp_free(p_hwfn);
4084 ecore_hw_hwfn_free(p_hwfn);
4089 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4090 struct ecore_hw_prepare_params *p_params)
4092 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4093 enum _ecore_status_t rc;
4095 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4096 p_dev->allow_mdump = p_params->allow_mdump;
4098 if (p_params->b_relaxed_probe)
4099 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4101 /* Store the precompiled init data ptrs */
4103 ecore_init_iro_array(p_dev);
4105 /* Initialize the first hwfn - will learn number of hwfns */
4106 rc = ecore_hw_prepare_single(p_hwfn,
4108 p_dev->doorbells, p_params);
4109 if (rc != ECORE_SUCCESS)
4112 p_params->personality = p_hwfn->hw_info.personality;
4114 /* initilalize 2nd hwfn if necessary */
4115 if (p_dev->num_hwfns > 1) {
4116 void OSAL_IOMEM *p_regview, *p_doorbell;
4117 u8 OSAL_IOMEM *addr;
4119 /* adjust bar offset for second engine */
4120 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4121 ecore_hw_bar_size(p_hwfn,
4124 p_regview = (void OSAL_IOMEM *)addr;
4126 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4127 ecore_hw_bar_size(p_hwfn,
4130 p_doorbell = (void OSAL_IOMEM *)addr;
4132 /* prepare second hw function */
4133 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4134 p_doorbell, p_params);
4136 /* in case of error, need to free the previously
4137 * initiliazed hwfn 0.
4139 if (rc != ECORE_SUCCESS) {
4140 if (p_params->b_relaxed_probe)
4141 p_params->p_relaxed_res =
4142 ECORE_HW_PREPARE_FAILED_ENG2;
4145 ecore_init_free(p_hwfn);
4146 ecore_mcp_free(p_hwfn);
4147 ecore_hw_hwfn_free(p_hwfn);
4149 DP_NOTICE(p_dev, true,
4150 "What do we need to free when VF hwfn1 init fails\n");
4159 void ecore_hw_remove(struct ecore_dev *p_dev)
4161 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4165 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4166 ECORE_OV_DRIVER_STATE_NOT_LOADED);
4168 for_each_hwfn(p_dev, i) {
4169 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4172 ecore_vf_pf_release(p_hwfn);
4176 ecore_init_free(p_hwfn);
4177 ecore_hw_hwfn_free(p_hwfn);
4178 ecore_mcp_free(p_hwfn);
4180 #ifdef CONFIG_ECORE_LOCK_ALLOC
4181 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
4185 ecore_iov_free_hw_info(p_dev);
4188 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4189 struct ecore_chain *p_chain)
4191 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4192 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4193 struct ecore_chain_next *p_next;
4199 size = p_chain->elem_size * p_chain->usable_per_page;
4201 for (i = 0; i < p_chain->page_cnt; i++) {
4205 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4206 p_virt_next = p_next->next_virt;
4207 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4209 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4210 ECORE_CHAIN_PAGE_SIZE);
4212 p_virt = p_virt_next;
4213 p_phys = p_phys_next;
4217 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4218 struct ecore_chain *p_chain)
4220 if (!p_chain->p_virt_addr)
4223 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4224 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4227 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4228 struct ecore_chain *p_chain)
4230 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4231 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4232 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4234 if (!pp_virt_addr_tbl)
4240 for (i = 0; i < page_cnt; i++) {
4241 if (!pp_virt_addr_tbl[i])
4244 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4245 *(dma_addr_t *)p_pbl_virt,
4246 ECORE_CHAIN_PAGE_SIZE);
4248 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4251 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4253 if (!p_chain->b_external_pbl)
4254 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4255 p_chain->pbl_sp.p_phys_table, pbl_size);
4257 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4260 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4262 switch (p_chain->mode) {
4263 case ECORE_CHAIN_MODE_NEXT_PTR:
4264 ecore_chain_free_next_ptr(p_dev, p_chain);
4266 case ECORE_CHAIN_MODE_SINGLE:
4267 ecore_chain_free_single(p_dev, p_chain);
4269 case ECORE_CHAIN_MODE_PBL:
4270 ecore_chain_free_pbl(p_dev, p_chain);
4275 static enum _ecore_status_t
4276 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4277 enum ecore_chain_cnt_type cnt_type,
4278 osal_size_t elem_size, u32 page_cnt)
4280 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4282 /* The actual chain size can be larger than the maximal possible value
4283 * after rounding up the requested elements number to pages, and after
4284 * taking into acount the unusuable elements (next-ptr elements).
4285 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4286 * size/capacity fields are of a u32 type.
4288 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4289 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4290 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4291 chain_size > ECORE_U32_MAX)) {
4292 DP_NOTICE(p_dev, true,
4293 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4294 (unsigned long)chain_size);
4298 return ECORE_SUCCESS;
4301 static enum _ecore_status_t
4302 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4304 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4305 dma_addr_t p_phys = 0;
4308 for (i = 0; i < p_chain->page_cnt; i++) {
4309 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4310 ECORE_CHAIN_PAGE_SIZE);
4312 DP_NOTICE(p_dev, true,
4313 "Failed to allocate chain memory\n");
4318 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4319 ecore_chain_reset(p_chain);
4321 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4325 p_virt_prev = p_virt;
4327 /* Last page's next element should point to the beginning of the
4330 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4331 p_chain->p_virt_addr,
4332 p_chain->p_phys_addr);
4334 return ECORE_SUCCESS;
4337 static enum _ecore_status_t
4338 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4340 dma_addr_t p_phys = 0;
4341 void *p_virt = OSAL_NULL;
4343 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4345 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4349 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4350 ecore_chain_reset(p_chain);
4352 return ECORE_SUCCESS;
4355 static enum _ecore_status_t
4356 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4357 struct ecore_chain *p_chain,
4358 struct ecore_chain_ext_pbl *ext_pbl)
4360 void *p_virt = OSAL_NULL;
4361 u8 *p_pbl_virt = OSAL_NULL;
4362 void **pp_virt_addr_tbl = OSAL_NULL;
4363 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4364 u32 page_cnt = p_chain->page_cnt, size, i;
4366 size = page_cnt * sizeof(*pp_virt_addr_tbl);
4367 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4368 if (!pp_virt_addr_tbl) {
4369 DP_NOTICE(p_dev, true,
4370 "Failed to allocate memory for the chain virtual addresses table\n");
4374 /* The allocation of the PBL table is done with its full size, since it
4375 * is expected to be successive.
4376 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4377 * failure, since pp_virt_addr_tbl was previously allocated, and it
4378 * should be saved to allow its freeing during the error flow.
4380 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4382 if (ext_pbl == OSAL_NULL) {
4383 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4385 p_pbl_virt = ext_pbl->p_pbl_virt;
4386 p_pbl_phys = ext_pbl->p_pbl_phys;
4387 p_chain->b_external_pbl = true;
4390 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4393 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4397 for (i = 0; i < page_cnt; i++) {
4398 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4399 ECORE_CHAIN_PAGE_SIZE);
4401 DP_NOTICE(p_dev, true,
4402 "Failed to allocate chain memory\n");
4407 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4408 ecore_chain_reset(p_chain);
4411 /* Fill the PBL table with the physical address of the page */
4412 *(dma_addr_t *)p_pbl_virt = p_phys;
4413 /* Keep the virtual address of the page */
4414 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4416 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4419 return ECORE_SUCCESS;
4422 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4423 enum ecore_chain_use_mode intended_use,
4424 enum ecore_chain_mode mode,
4425 enum ecore_chain_cnt_type cnt_type,
4426 u32 num_elems, osal_size_t elem_size,
4427 struct ecore_chain *p_chain,
4428 struct ecore_chain_ext_pbl *ext_pbl)
4431 enum _ecore_status_t rc = ECORE_SUCCESS;
4433 if (mode == ECORE_CHAIN_MODE_SINGLE)
4436 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4438 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4441 DP_NOTICE(p_dev, true,
4442 "Cannot allocate a chain with the given arguments:\n"
4443 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4444 intended_use, mode, cnt_type, num_elems, elem_size);
4448 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4449 mode, cnt_type, p_dev->dp_ctx);
4452 case ECORE_CHAIN_MODE_NEXT_PTR:
4453 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4455 case ECORE_CHAIN_MODE_SINGLE:
4456 rc = ecore_chain_alloc_single(p_dev, p_chain);
4458 case ECORE_CHAIN_MODE_PBL:
4459 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4465 return ECORE_SUCCESS;
4468 ecore_chain_free(p_dev, p_chain);
4472 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4473 u16 src_id, u16 *dst_id)
4475 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4478 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4479 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4480 DP_NOTICE(p_hwfn, true,
4481 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4487 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4489 return ECORE_SUCCESS;
4492 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4493 u8 src_id, u8 *dst_id)
4495 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4498 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4499 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4500 DP_NOTICE(p_hwfn, true,
4501 "vport id [%d] is not valid, available indices [%d - %d]\n",
4507 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4509 return ECORE_SUCCESS;
4512 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4513 u8 src_id, u8 *dst_id)
4515 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4518 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4519 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4520 DP_NOTICE(p_hwfn, true,
4521 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4527 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4529 return ECORE_SUCCESS;
4532 static enum _ecore_status_t
4533 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4534 struct ecore_ptt *p_ptt, u32 high, u32 low,
4540 /* Find a free entry and utilize it */
4541 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4542 en = ecore_rd(p_hwfn, p_ptt,
4543 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4547 ecore_wr(p_hwfn, p_ptt,
4548 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4549 2 * i * sizeof(u32), low);
4550 ecore_wr(p_hwfn, p_ptt,
4551 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4552 (2 * i + 1) * sizeof(u32), high);
4553 ecore_wr(p_hwfn, p_ptt,
4554 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4555 i * sizeof(u32), 0);
4556 ecore_wr(p_hwfn, p_ptt,
4557 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4558 i * sizeof(u32), 0);
4559 ecore_wr(p_hwfn, p_ptt,
4560 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4561 i * sizeof(u32), 1);
4565 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4566 return ECORE_NORESOURCES;
4570 return ECORE_SUCCESS;
4573 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4574 struct ecore_ptt *p_ptt, u8 *p_filter)
4576 u32 high, low, entry_num;
4577 enum _ecore_status_t rc;
4579 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4580 return ECORE_SUCCESS;
4582 high = p_filter[1] | (p_filter[0] << 8);
4583 low = p_filter[5] | (p_filter[4] << 8) |
4584 (p_filter[3] << 16) | (p_filter[2] << 24);
4586 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4587 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4589 if (rc != ECORE_SUCCESS) {
4590 DP_NOTICE(p_hwfn, false,
4591 "Failed to find an empty LLH filter to utilize\n");
4595 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4596 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4597 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4598 p_filter[4], p_filter[5], entry_num);
4600 return ECORE_SUCCESS;
4603 static enum _ecore_status_t
4604 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4605 struct ecore_ptt *p_ptt, u32 high, u32 low,
4610 /* Find the entry and clean it */
4611 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4612 if (ecore_rd(p_hwfn, p_ptt,
4613 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4614 2 * i * sizeof(u32)) != low)
4616 if (ecore_rd(p_hwfn, p_ptt,
4617 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4618 (2 * i + 1) * sizeof(u32)) != high)
4621 ecore_wr(p_hwfn, p_ptt,
4622 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4623 ecore_wr(p_hwfn, p_ptt,
4624 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4625 2 * i * sizeof(u32), 0);
4626 ecore_wr(p_hwfn, p_ptt,
4627 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4628 (2 * i + 1) * sizeof(u32), 0);
4632 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4637 return ECORE_SUCCESS;
4640 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4641 struct ecore_ptt *p_ptt, u8 *p_filter)
4643 u32 high, low, entry_num;
4644 enum _ecore_status_t rc;
4646 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4649 high = p_filter[1] | (p_filter[0] << 8);
4650 low = p_filter[5] | (p_filter[4] << 8) |
4651 (p_filter[3] << 16) | (p_filter[2] << 24);
4653 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4654 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4656 if (rc != ECORE_SUCCESS) {
4657 DP_NOTICE(p_hwfn, false,
4658 "Tried to remove a non-configured filter\n");
4663 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4664 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4665 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4666 p_filter[4], p_filter[5], entry_num);
4669 static enum _ecore_status_t
4670 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4671 struct ecore_ptt *p_ptt,
4672 enum ecore_llh_port_filter_type_t type,
4673 u32 high, u32 low, u32 *p_entry_num)
4678 /* Find a free entry and utilize it */
4679 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4680 en = ecore_rd(p_hwfn, p_ptt,
4681 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4685 ecore_wr(p_hwfn, p_ptt,
4686 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4687 2 * i * sizeof(u32), low);
4688 ecore_wr(p_hwfn, p_ptt,
4689 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4690 (2 * i + 1) * sizeof(u32), high);
4691 ecore_wr(p_hwfn, p_ptt,
4692 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4693 i * sizeof(u32), 1);
4694 ecore_wr(p_hwfn, p_ptt,
4695 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4696 i * sizeof(u32), 1 << type);
4697 ecore_wr(p_hwfn, p_ptt,
4698 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4702 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4703 return ECORE_NORESOURCES;
4707 return ECORE_SUCCESS;
4710 enum _ecore_status_t
4711 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4712 struct ecore_ptt *p_ptt,
4713 u16 source_port_or_eth_type,
4715 enum ecore_llh_port_filter_type_t type)
4717 u32 high, low, entry_num;
4718 enum _ecore_status_t rc;
4720 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4721 return ECORE_SUCCESS;
4727 case ECORE_LLH_FILTER_ETHERTYPE:
4728 high = source_port_or_eth_type;
4730 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4731 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4732 low = source_port_or_eth_type << 16;
4734 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4735 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4738 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4739 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4740 low = (source_port_or_eth_type << 16) | dest_port;
4743 DP_NOTICE(p_hwfn, true,
4744 "Non valid LLH protocol filter type %d\n", type);
4748 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4749 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4750 high, low, &entry_num);
4751 if (rc != ECORE_SUCCESS) {
4752 DP_NOTICE(p_hwfn, false,
4753 "Failed to find an empty LLH filter to utilize\n");
4757 case ECORE_LLH_FILTER_ETHERTYPE:
4758 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4759 "ETH type %x is added at %d\n",
4760 source_port_or_eth_type, entry_num);
4762 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4763 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4764 "TCP src port %x is added at %d\n",
4765 source_port_or_eth_type, entry_num);
4767 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4768 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4769 "UDP src port %x is added at %d\n",
4770 source_port_or_eth_type, entry_num);
4772 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4773 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4774 "TCP dst port %x is added at %d\n", dest_port,
4777 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4778 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4779 "UDP dst port %x is added at %d\n", dest_port,
4782 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4783 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4784 "TCP src/dst ports %x/%x are added at %d\n",
4785 source_port_or_eth_type, dest_port, entry_num);
4787 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4788 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4789 "UDP src/dst ports %x/%x are added at %d\n",
4790 source_port_or_eth_type, dest_port, entry_num);
4794 return ECORE_SUCCESS;
4797 static enum _ecore_status_t
4798 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4799 struct ecore_ptt *p_ptt,
4800 enum ecore_llh_port_filter_type_t type,
4801 u32 high, u32 low, u32 *p_entry_num)
4805 /* Find the entry and clean it */
4806 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4807 if (!ecore_rd(p_hwfn, p_ptt,
4808 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4811 if (!ecore_rd(p_hwfn, p_ptt,
4812 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4815 if (!(ecore_rd(p_hwfn, p_ptt,
4816 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4817 i * sizeof(u32)) & (1 << type)))
4819 if (ecore_rd(p_hwfn, p_ptt,
4820 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4821 2 * i * sizeof(u32)) != low)
4823 if (ecore_rd(p_hwfn, p_ptt,
4824 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4825 (2 * i + 1) * sizeof(u32)) != high)
4828 ecore_wr(p_hwfn, p_ptt,
4829 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4830 ecore_wr(p_hwfn, p_ptt,
4831 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4832 i * sizeof(u32), 0);
4833 ecore_wr(p_hwfn, p_ptt,
4834 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4835 i * sizeof(u32), 0);
4836 ecore_wr(p_hwfn, p_ptt,
4837 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4838 2 * i * sizeof(u32), 0);
4839 ecore_wr(p_hwfn, p_ptt,
4840 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4841 (2 * i + 1) * sizeof(u32), 0);
4845 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4850 return ECORE_SUCCESS;
4854 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4855 struct ecore_ptt *p_ptt,
4856 u16 source_port_or_eth_type,
4858 enum ecore_llh_port_filter_type_t type)
4860 u32 high, low, entry_num;
4861 enum _ecore_status_t rc;
4863 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4870 case ECORE_LLH_FILTER_ETHERTYPE:
4871 high = source_port_or_eth_type;
4873 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4874 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4875 low = source_port_or_eth_type << 16;
4877 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4878 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4881 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4882 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4883 low = (source_port_or_eth_type << 16) | dest_port;
4886 DP_NOTICE(p_hwfn, true,
4887 "Non valid LLH protocol filter type %d\n", type);
4891 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4892 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4895 if (rc != ECORE_SUCCESS) {
4896 DP_NOTICE(p_hwfn, false,
4897 "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4898 type, source_port_or_eth_type, dest_port);
4902 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4903 "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4904 type, source_port_or_eth_type, dest_port, entry_num);
4907 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4908 struct ecore_ptt *p_ptt)
4912 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4915 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4916 ecore_wr(p_hwfn, p_ptt,
4917 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4918 i * sizeof(u32), 0);
4919 ecore_wr(p_hwfn, p_ptt,
4920 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4921 2 * i * sizeof(u32), 0);
4922 ecore_wr(p_hwfn, p_ptt,
4923 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4924 (2 * i + 1) * sizeof(u32), 0);
4928 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4929 struct ecore_ptt *p_ptt)
4931 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4934 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4935 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
4938 enum _ecore_status_t
4939 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4940 struct ecore_ptt *p_ptt)
4942 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4943 ecore_wr(p_hwfn, p_ptt,
4944 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4945 1 << p_hwfn->abs_pf_id / 2);
4946 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4947 return ECORE_SUCCESS;
4950 DP_NOTICE(p_hwfn, false,
4951 "This function can't be set as default\n");
4955 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4956 struct ecore_ptt *p_ptt,
4957 u32 hw_addr, void *p_eth_qzone,
4958 osal_size_t eth_qzone_size,
4961 struct coalescing_timeset *p_coal_timeset;
4963 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4964 DP_NOTICE(p_hwfn, true,
4965 "Coalescing configuration not enabled\n");
4969 p_coal_timeset = p_eth_qzone;
4970 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4971 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4972 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4973 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4975 return ECORE_SUCCESS;
4978 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4979 u16 rx_coal, u16 tx_coal,
4982 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
4983 enum _ecore_status_t rc = ECORE_SUCCESS;
4984 struct ecore_ptt *p_ptt;
4986 /* TODO - Configuring a single queue's coalescing but
4987 * claiming all queues are abiding same configuration
4988 * for PF and VF both.
4991 if (IS_VF(p_hwfn->p_dev))
4992 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
4995 p_ptt = ecore_ptt_acquire(p_hwfn);
5000 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5003 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5007 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5010 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5013 ecore_ptt_release(p_hwfn, p_ptt);
5018 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5019 struct ecore_ptt *p_ptt,
5021 struct ecore_queue_cid *p_cid)
5023 struct ustorm_eth_queue_zone eth_qzone;
5024 u8 timeset, timer_res;
5026 enum _ecore_status_t rc;
5028 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5029 if (coalesce <= 0x7F) {
5031 } else if (coalesce <= 0xFF) {
5033 } else if (coalesce <= 0x1FF) {
5036 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5039 timeset = (u8)(coalesce >> timer_res);
5041 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5042 p_cid->sb_igu_id, false);
5043 if (rc != ECORE_SUCCESS)
5046 address = BAR0_MAP_REG_USDM_RAM +
5047 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5049 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5050 sizeof(struct ustorm_eth_queue_zone), timeset);
5051 if (rc != ECORE_SUCCESS)
5058 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5059 struct ecore_ptt *p_ptt,
5061 struct ecore_queue_cid *p_cid)
5063 struct xstorm_eth_queue_zone eth_qzone;
5064 u8 timeset, timer_res;
5066 enum _ecore_status_t rc;
5068 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5069 if (coalesce <= 0x7F) {
5071 } else if (coalesce <= 0xFF) {
5073 } else if (coalesce <= 0x1FF) {
5076 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5080 timeset = (u8)(coalesce >> timer_res);
5082 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5083 p_cid->sb_igu_id, true);
5084 if (rc != ECORE_SUCCESS)
5087 address = BAR0_MAP_REG_XSDM_RAM +
5088 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5090 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5091 sizeof(struct xstorm_eth_queue_zone), timeset);
5096 /* Calculate final WFQ values for all vports and configure it.
5097 * After this configuration each vport must have
5098 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5100 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5101 struct ecore_ptt *p_ptt,
5104 struct init_qm_vport_params *vport_params;
5107 vport_params = p_hwfn->qm_info.qm_vport_params;
5109 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5110 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5112 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5114 ecore_init_vport_wfq(p_hwfn, p_ptt,
5115 vport_params[i].first_tx_pq_id,
5116 vport_params[i].vport_wfq);
5121 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
5125 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5126 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5129 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5130 struct ecore_ptt *p_ptt,
5133 struct init_qm_vport_params *vport_params;
5136 vport_params = p_hwfn->qm_info.qm_vport_params;
5138 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5139 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
5140 ecore_init_vport_wfq(p_hwfn, p_ptt,
5141 vport_params[i].first_tx_pq_id,
5142 vport_params[i].vport_wfq);
5146 /* This function performs several validations for WFQ
5147 * configuration and required min rate for a given vport
5148 * 1. req_rate must be greater than one percent of min_pf_rate.
5149 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5150 * rates to get less than one percent of min_pf_rate.
5151 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5153 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5154 u16 vport_id, u32 req_rate,
5157 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5158 int non_requested_count = 0, req_count = 0, i, num_vports;
5160 num_vports = p_hwfn->qm_info.num_vports;
5162 /* Accounting for the vports which are configured for WFQ explicitly */
5164 for (i = 0; i < num_vports; i++) {
5167 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5169 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5170 total_req_min_rate += tmp_speed;
5174 /* Include current vport data as well */
5176 total_req_min_rate += req_rate;
5177 non_requested_count = num_vports - req_count;
5179 /* validate possible error cases */
5180 if (req_rate > min_pf_rate) {
5181 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5182 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5183 vport_id, req_rate, min_pf_rate);
5187 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5188 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5189 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5190 vport_id, req_rate, min_pf_rate);
5194 /* TBD - for number of vports greater than 100 */
5195 if (num_vports > ECORE_WFQ_UNIT) {
5196 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5197 "Number of vports is greater than %d\n",
5202 if (total_req_min_rate > min_pf_rate) {
5203 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5204 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5205 total_req_min_rate, min_pf_rate);
5209 /* Data left for non requested vports */
5210 total_left_rate = min_pf_rate - total_req_min_rate;
5211 left_rate_per_vp = total_left_rate / non_requested_count;
5213 /* validate if non requested get < 1% of min bw */
5214 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5215 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5216 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5217 left_rate_per_vp, min_pf_rate);
5221 /* now req_rate for given vport passes all scenarios.
5222 * assign final wfq rates to all vports.
5224 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5225 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5227 for (i = 0; i < num_vports; i++) {
5228 if (p_hwfn->qm_info.wfq_data[i].configured)
5231 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5234 return ECORE_SUCCESS;
5237 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5238 struct ecore_ptt *p_ptt,
5239 u16 vp_id, u32 rate)
5241 struct ecore_mcp_link_state *p_link;
5242 int rc = ECORE_SUCCESS;
5244 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5246 if (!p_link->min_pf_rate) {
5247 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5248 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5252 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5254 if (rc == ECORE_SUCCESS)
5255 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5256 p_link->min_pf_rate);
5258 DP_NOTICE(p_hwfn, false,
5259 "Validation failed while configuring min rate\n");
5264 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5265 struct ecore_ptt *p_ptt,
5268 bool use_wfq = false;
5269 int rc = ECORE_SUCCESS;
5272 /* Validate all pre configured vports for wfq */
5273 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5276 if (!p_hwfn->qm_info.wfq_data[i].configured)
5279 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5282 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5283 if (rc != ECORE_SUCCESS) {
5284 DP_NOTICE(p_hwfn, false,
5285 "WFQ validation failed while configuring min rate\n");
5290 if (rc == ECORE_SUCCESS && use_wfq)
5291 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5293 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5298 /* Main API for ecore clients to configure vport min rate.
5299 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5300 * rate - Speed in Mbps needs to be assigned to a given vport.
5302 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5304 int i, rc = ECORE_INVAL;
5306 /* TBD - for multiple hardware functions - that is 100 gig */
5307 if (p_dev->num_hwfns > 1) {
5308 DP_NOTICE(p_dev, false,
5309 "WFQ configuration is not supported for this device\n");
5313 for_each_hwfn(p_dev, i) {
5314 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5315 struct ecore_ptt *p_ptt;
5317 p_ptt = ecore_ptt_acquire(p_hwfn);
5319 return ECORE_TIMEOUT;
5321 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5323 if (rc != ECORE_SUCCESS) {
5324 ecore_ptt_release(p_hwfn, p_ptt);
5328 ecore_ptt_release(p_hwfn, p_ptt);
5334 /* API to configure WFQ from mcp link change */
5335 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5336 struct ecore_ptt *p_ptt,
5341 /* TBD - for multiple hardware functions - that is 100 gig */
5342 if (p_dev->num_hwfns > 1) {
5343 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5344 "WFQ configuration is not supported for this device\n");
5348 for_each_hwfn(p_dev, i) {
5349 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5351 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5356 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5357 struct ecore_ptt *p_ptt,
5358 struct ecore_mcp_link_state *p_link,
5361 int rc = ECORE_SUCCESS;
5363 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5365 if (!p_link->line_speed && (max_bw != 100))
5368 p_link->speed = (p_link->line_speed * max_bw) / 100;
5369 p_hwfn->qm_info.pf_rl = p_link->speed;
5371 /* Since the limiter also affects Tx-switched traffic, we don't want it
5372 * to limit such traffic in case there's no actual limit.
5373 * In that case, set limit to imaginary high boundary.
5376 p_hwfn->qm_info.pf_rl = 100000;
5378 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5379 p_hwfn->qm_info.pf_rl);
5381 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5382 "Configured MAX bandwidth to be %08x Mb/sec\n",
5388 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5389 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5391 int i, rc = ECORE_INVAL;
5393 if (max_bw < 1 || max_bw > 100) {
5394 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5398 for_each_hwfn(p_dev, i) {
5399 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5400 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5401 struct ecore_mcp_link_state *p_link;
5402 struct ecore_ptt *p_ptt;
5404 p_link = &p_lead->mcp_info->link_output;
5406 p_ptt = ecore_ptt_acquire(p_hwfn);
5408 return ECORE_TIMEOUT;
5410 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5413 ecore_ptt_release(p_hwfn, p_ptt);
5415 if (rc != ECORE_SUCCESS)
5422 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5423 struct ecore_ptt *p_ptt,
5424 struct ecore_mcp_link_state *p_link,
5427 int rc = ECORE_SUCCESS;
5429 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5430 p_hwfn->qm_info.pf_wfq = min_bw;
5432 if (!p_link->line_speed)
5435 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5437 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5439 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5440 "Configured MIN bandwidth to be %d Mb/sec\n",
5441 p_link->min_pf_rate);
5446 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5447 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5449 int i, rc = ECORE_INVAL;
5451 if (min_bw < 1 || min_bw > 100) {
5452 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5456 for_each_hwfn(p_dev, i) {
5457 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5458 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5459 struct ecore_mcp_link_state *p_link;
5460 struct ecore_ptt *p_ptt;
5462 p_link = &p_lead->mcp_info->link_output;
5464 p_ptt = ecore_ptt_acquire(p_hwfn);
5466 return ECORE_TIMEOUT;
5468 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5470 if (rc != ECORE_SUCCESS) {
5471 ecore_ptt_release(p_hwfn, p_ptt);
5475 if (p_link->min_pf_rate) {
5476 u32 min_rate = p_link->min_pf_rate;
5478 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5483 ecore_ptt_release(p_hwfn, p_ptt);
5489 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5491 struct ecore_mcp_link_state *p_link;
5493 p_link = &p_hwfn->mcp_info->link_output;
5495 if (p_link->min_pf_rate)
5496 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5497 p_link->min_pf_rate);
5499 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5500 sizeof(*p_hwfn->qm_info.wfq_data) *
5501 p_hwfn->qm_info.num_vports);
5504 int ecore_device_num_engines(struct ecore_dev *p_dev)
5506 return ECORE_IS_BB(p_dev) ? 2 : 1;
5509 int ecore_device_num_ports(struct ecore_dev *p_dev)
5511 /* in CMT always only one port */
5512 if (p_dev->num_hwfns > 1)
5515 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
5518 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5523 ((u8 *)fw_msb)[0] = mac[1];
5524 ((u8 *)fw_msb)[1] = mac[0];
5525 ((u8 *)fw_mid)[0] = mac[3];
5526 ((u8 *)fw_mid)[1] = mac[2];
5527 ((u8 *)fw_lsb)[0] = mac[5];
5528 ((u8 *)fw_lsb)[1] = mac[4];