2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
35 * registers involved are not split and thus configuration is a race where
36 * some of the PFs configuration might be lost.
37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
39 * there's more than a single compiled ecore component in system].
41 static osal_spinlock_t qm_lock;
42 static bool qm_lock_init;
45 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
46 * load the driver. The number was
51 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
54 BAR_ID_0, /* used for GRC */
55 BAR_ID_1 /* Used for doorbells */
58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
60 u32 bar_reg = (bar_id == BAR_ID_0 ?
61 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
64 if (IS_VF(p_hwfn->p_dev)) {
65 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
66 * read from actual register, but we're currently not using
67 * it for actual doorbelling.
72 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
74 return 1 << (val + 15);
76 /* The above registers were updated in the past only in CMT mode. Since
77 * they were found to be useful MFW started updating them from 8.7.7.0.
78 * In older MFW versions they are set to 0 which means disabled.
80 if (p_hwfn->p_dev->num_hwfns > 1) {
81 DP_NOTICE(p_hwfn, false,
82 "BAR size not configured. Assuming BAR size of 256kB"
83 " for GRC and 512kB for DB\n");
84 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
86 DP_NOTICE(p_hwfn, false,
87 "BAR size not configured. Assuming BAR size of 512kB"
88 " for GRC and 512kB for DB\n");
95 void ecore_init_dp(struct ecore_dev *p_dev,
96 u32 dp_module, u8 dp_level, void *dp_ctx)
100 p_dev->dp_level = dp_level;
101 p_dev->dp_module = dp_module;
102 p_dev->dp_ctx = dp_ctx;
103 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
104 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
106 p_hwfn->dp_level = dp_level;
107 p_hwfn->dp_module = dp_module;
108 p_hwfn->dp_ctx = dp_ctx;
112 void ecore_init_struct(struct ecore_dev *p_dev)
116 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
117 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
119 p_hwfn->p_dev = p_dev;
121 p_hwfn->b_active = false;
123 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
124 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
127 /* hwfn 0 is always active */
128 p_dev->hwfns[0].b_active = true;
130 /* set the default cache alignment to 128 (may be overridden later) */
131 p_dev->cache_shift = 7;
134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
136 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
138 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
139 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
141 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
144 void ecore_resc_free(struct ecore_dev *p_dev)
151 OSAL_FREE(p_dev, p_dev->fw_data);
153 OSAL_FREE(p_dev, p_dev->reset_stats);
155 for_each_hwfn(p_dev, i) {
156 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
158 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
159 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
162 for_each_hwfn(p_dev, i) {
163 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
165 ecore_cxt_mngr_free(p_hwfn);
166 ecore_qm_info_free(p_hwfn);
167 ecore_spq_free(p_hwfn);
168 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
169 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
170 ecore_int_free(p_hwfn);
171 #ifdef CONFIG_ECORE_LL2
172 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
174 ecore_iov_free(p_hwfn);
175 ecore_dmae_info_free(p_hwfn);
176 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
177 /* @@@TBD Flush work-queue ? */
181 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
184 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
185 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
186 struct init_qm_port_params *p_qm_port;
187 bool init_rdma_offload_pq = false;
188 bool init_pure_ack_pq = false;
189 bool init_ooo_pq = false;
190 u16 num_pqs, protocol_pqs;
196 /* @TMP - saving the existing min/max bw config before resetting the
197 * qm_info to restore them.
199 pf_rl = qm_info->pf_rl;
200 pf_wfq = qm_info->pf_wfq;
202 #ifdef CONFIG_ECORE_SRIOV
203 if (p_hwfn->p_dev->p_iov_info)
204 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
206 OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
209 /* @TMP - Don't allocate QM queues for VFs on emulation */
210 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
211 DP_NOTICE(p_hwfn, false,
212 "Emulation - skip configuring QM queues for VFs\n");
217 /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
218 * active, we want physical queues allocated for all of them, since we
219 * don't have a good recycle flow. Non ethernet PFs require only a
220 * single physical queue.
222 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
223 p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
224 p_hwfn->hw_info.personality == ECORE_PCI_ETH)
225 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
229 num_pqs = protocol_pqs + num_vfs + 1; /* The '1' is for pure-LB */
230 num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
232 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
233 num_pqs++; /* for RoCE queue */
234 init_rdma_offload_pq = true;
235 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
236 /* Due to FW assumption that rl==vport, we limit the
237 * number of rate limiters by the minimum between its
238 * allocated number and the allocated number of vports.
239 * Another limitation is the number of supported qps
240 * with rate limiters in FW.
243 (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
244 RESC_NUM(p_hwfn, ECORE_VPORT));
246 /* we subtract num_vfs because each one requires a rate
247 * limiter, and one default rate limiter.
249 if (num_pf_rls < num_vfs + 1) {
250 DP_ERR(p_hwfn, "No RL for DCQCN");
251 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
252 num_pf_rls, num_vfs);
255 num_pf_rls -= num_vfs + 1;
258 num_pqs += num_pf_rls;
259 qm_info->num_pf_rls = (u8)num_pf_rls;
262 if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
263 num_pqs += 3; /* for iwarp queue / pure-ack / ooo */
264 init_rdma_offload_pq = true;
265 init_pure_ack_pq = true;
269 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
270 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
271 init_pure_ack_pq = true;
275 /* Sanity checking that setup requires legal number of resources */
276 if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
278 "Need too many Physical queues - 0x%04x avail %04x",
279 num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
283 /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
284 * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
286 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
287 b_sleepable ? GFP_KERNEL :
289 sizeof(struct init_qm_pq_params) *
291 if (!qm_info->qm_pq_params)
294 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
295 b_sleepable ? GFP_KERNEL :
298 init_qm_vport_params) *
300 if (!qm_info->qm_vport_params)
303 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
304 b_sleepable ? GFP_KERNEL :
306 sizeof(struct init_qm_port_params)
308 if (!qm_info->qm_port_params)
311 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
312 b_sleepable ? GFP_KERNEL :
314 sizeof(struct ecore_wfq_data) *
317 if (!qm_info->wfq_data)
320 vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
322 /* First init rate limited queues ( Due to RoCE assumption of
325 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
326 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
327 qm_info->qm_pq_params[curr_queue].tc_id =
328 p_hwfn->hw_info.offload_tc;
329 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
330 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
334 for (i = 0; i < protocol_pqs; i++) {
335 struct init_qm_pq_params *params =
336 &qm_info->qm_pq_params[curr_queue++];
338 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
339 p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
340 p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
341 params->vport_id = vport_id;
343 /* Note: this assumes that if we had a configuration
344 * with N tcs and subsequently another configuration
345 * With Fewer TCs, the in flight traffic (in QM queues,
346 * in FW, from driver to FW) will still trickle out and
347 * not get "stuck" in the QM. This is determined by the
348 * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
349 * supposed to be cleared in this map, allowing traffic
350 * to flush out. If this is not the case, we would need
351 * to set the TC of unused queues to 0, and reconfigure
352 * QM every time num of TCs changes. Unused queues in
353 * this context would mean those intended for TCs where
354 * tc_id > hw_info.num_active_tcs.
356 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
358 params->vport_id = vport_id;
359 params->tc_id = p_hwfn->hw_info.offload_tc;
360 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
364 /* Then init pure-LB PQ */
365 qm_info->pure_lb_pq = curr_queue;
366 qm_info->qm_pq_params[curr_queue].vport_id =
367 (u8)RESC_START(p_hwfn, ECORE_VPORT);
368 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
369 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
372 qm_info->offload_pq = 0; /* Already initialized for iSCSI/FCoE */
373 if (init_rdma_offload_pq) {
374 qm_info->offload_pq = curr_queue;
375 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
376 qm_info->qm_pq_params[curr_queue].tc_id =
377 p_hwfn->hw_info.offload_tc;
378 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
382 if (init_pure_ack_pq) {
383 qm_info->pure_ack_pq = curr_queue;
384 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
385 qm_info->qm_pq_params[curr_queue].tc_id =
386 p_hwfn->hw_info.offload_tc;
387 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
392 qm_info->ooo_pq = curr_queue;
393 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
394 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
395 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
399 /* Then init per-VF PQs */
400 vf_offset = curr_queue;
401 for (i = 0; i < num_vfs; i++) {
402 /* First vport is used by the PF */
403 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
404 /* @@@TBD VF Multi-cos */
405 qm_info->qm_pq_params[curr_queue].tc_id = 0;
406 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
407 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
411 qm_info->vf_queues_offset = vf_offset;
412 qm_info->num_pqs = num_pqs;
413 qm_info->num_vports = num_vports;
415 /* Initialize qm port parameters */
416 num_ports = p_hwfn->p_dev->num_ports_in_engines;
417 for (i = 0; i < num_ports; i++) {
418 p_qm_port = &qm_info->qm_port_params[i];
419 p_qm_port->active = 1;
420 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
424 p_qm_port->active_phys_tcs = 0xf;
426 p_qm_port->active_phys_tcs = 0x9f;
427 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
428 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
431 if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
432 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
434 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
436 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
438 qm_info->num_vf_pqs = num_vfs;
439 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
441 for (i = 0; i < qm_info->num_vports; i++)
442 qm_info->qm_vport_params[i].vport_wfq = 1;
444 qm_info->vport_rl_en = 1;
445 qm_info->vport_wfq_en = 1;
446 qm_info->pf_rl = pf_rl;
447 qm_info->pf_wfq = pf_wfq;
449 return ECORE_SUCCESS;
452 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
453 ecore_qm_info_free(p_hwfn);
457 /* This function reconfigures the QM pf on the fly.
458 * For this purpose we:
459 * 1. reconfigure the QM database
460 * 2. set new values to runtime arrat
461 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
462 * 4. activate init tool in QM_PF stage
463 * 5. send an sdm_qm_cmd through rbc interface to release the QM
465 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
466 struct ecore_ptt *p_ptt)
468 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
470 enum _ecore_status_t rc;
472 /* qm_info is allocated in ecore_init_qm_info() which is already called
473 * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
474 * The allocated size may change each init, so we free it before next
477 ecore_qm_info_free(p_hwfn);
479 /* initialize ecore's qm data structure */
480 rc = ecore_init_qm_info(p_hwfn, false);
481 if (rc != ECORE_SUCCESS)
484 /* stop PF's qm queues */
485 OSAL_SPIN_LOCK(&qm_lock);
486 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
487 qm_info->start_pq, qm_info->num_pqs);
488 OSAL_SPIN_UNLOCK(&qm_lock);
492 /* clear the QM_PF runtime phase leftovers from previous init */
493 ecore_init_clear_rt_data(p_hwfn);
495 /* prepare QM portion of runtime array */
496 ecore_qm_init_pf(p_hwfn);
498 /* activate init tool on runtime array */
499 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
500 p_hwfn->hw_info.hw_mode);
501 if (rc != ECORE_SUCCESS)
504 /* start PF's qm queues */
505 OSAL_SPIN_LOCK(&qm_lock);
506 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
507 qm_info->start_pq, qm_info->num_pqs);
508 OSAL_SPIN_UNLOCK(&qm_lock);
512 return ECORE_SUCCESS;
515 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
517 struct ecore_consq *p_consq;
518 struct ecore_eq *p_eq;
519 #ifdef CONFIG_ECORE_LL2
520 struct ecore_ll2_info *p_ll2_info;
522 enum _ecore_status_t rc = ECORE_SUCCESS;
528 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
529 sizeof(*p_dev->fw_data));
533 /* Allocate Memory for the Queue->CID mapping */
534 for_each_hwfn(p_dev, i) {
535 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
536 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
537 int tx_size, rx_size;
539 /* @@@TMP - resc management, change to actual required size */
540 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
541 num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
542 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
543 rx_size = sizeof(struct ecore_hw_cid_data) *
544 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
546 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
548 if (!p_hwfn->p_tx_cids) {
549 DP_NOTICE(p_hwfn, true,
550 "Failed to allocate memory for Tx Cids\n");
554 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
556 if (!p_hwfn->p_rx_cids) {
557 DP_NOTICE(p_hwfn, true,
558 "Failed to allocate memory for Rx Cids\n");
563 for_each_hwfn(p_dev, i) {
564 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
565 u32 n_eqes, num_cons;
567 /* First allocate the context manager structure */
568 rc = ecore_cxt_mngr_alloc(p_hwfn);
572 /* Set the HW cid/tid numbers (in the contest manager)
573 * Must be done prior to any further computations.
575 rc = ecore_cxt_set_pf_params(p_hwfn);
579 /* Prepare and process QM requirements */
580 rc = ecore_init_qm_info(p_hwfn, true);
584 /* Compute the ILT client partition */
585 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
589 /* CID map / ILT shadow table / T2
590 * The talbes sizes are determined by the computations above
592 rc = ecore_cxt_tables_alloc(p_hwfn);
596 /* SPQ, must follow ILT because initializes SPQ context */
597 rc = ecore_spq_alloc(p_hwfn);
601 /* SP status block allocation */
602 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
605 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
609 rc = ecore_iov_alloc(p_hwfn);
614 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
615 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
616 (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
617 /* Calculate the EQ size
618 * ---------------------
619 * Each ICID may generate up to one event at a time i.e.
620 * the event must be handled/cleared before a new one
621 * can be generated. We calculate the sum of events per
622 * protocol and create an EQ deep enough to handle the
624 * - Core - according to SPQ.
625 * - RoCE - per QP there are a couple of ICIDs, one
626 * responder and one requester, each can
627 * generate an EQE => n_eqes_qp = 2 * n_qp.
628 * Each CQ can generate an EQE. There are 2 CQs
629 * per QP => n_eqes_cq = 2 * n_qp.
630 * Hence the RoCE total is 4 * n_qp or
632 * - ENet - There can be up to two events per VF. One
633 * for VF-PF channel and another for VF FLR
634 * initial cleanup. The number of VFs is
635 * bounded by MAX_NUM_VFS_BB, and is much
636 * smaller than RoCE's so we avoid exact
639 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
641 ecore_cxt_get_proto_cid_count(
647 num_cons = ecore_cxt_get_proto_cid_count(
652 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
653 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
655 ecore_cxt_get_proto_cid_count(p_hwfn,
658 n_eqes += 2 * num_cons;
661 if (n_eqes > 0xFFFF) {
662 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
663 "The maximum of a u16 chain is 0x%x\n",
668 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
673 p_consq = ecore_consq_alloc(p_hwfn);
676 p_hwfn->p_consq = p_consq;
678 #ifdef CONFIG_ECORE_LL2
679 if (p_hwfn->using_ll2) {
680 p_ll2_info = ecore_ll2_alloc(p_hwfn);
683 p_hwfn->p_ll2_info = p_ll2_info;
687 /* DMA info initialization */
688 rc = ecore_dmae_info_alloc(p_hwfn);
690 DP_NOTICE(p_hwfn, true,
691 "Failed to allocate memory for dmae_info structure\n");
695 /* DCBX initialization */
696 rc = ecore_dcbx_info_alloc(p_hwfn);
698 DP_NOTICE(p_hwfn, true,
699 "Failed to allocate memory for dcbx structure\n");
704 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
705 sizeof(*p_dev->reset_stats));
706 if (!p_dev->reset_stats) {
707 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
711 return ECORE_SUCCESS;
716 ecore_resc_free(p_dev);
720 void ecore_resc_setup(struct ecore_dev *p_dev)
727 for_each_hwfn(p_dev, i) {
728 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
730 ecore_cxt_mngr_setup(p_hwfn);
731 ecore_spq_setup(p_hwfn);
732 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
733 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
735 /* Read shadow of current MFW mailbox */
736 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
737 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
738 p_hwfn->mcp_info->mfw_mb_cur,
739 p_hwfn->mcp_info->mfw_mb_length);
741 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
743 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
744 #ifdef CONFIG_ECORE_LL2
745 if (p_hwfn->using_ll2)
746 ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
751 #define FINAL_CLEANUP_POLL_CNT (100)
752 #define FINAL_CLEANUP_POLL_TIME (10)
753 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
754 struct ecore_ptt *p_ptt,
757 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
758 enum _ecore_status_t rc = ECORE_TIMEOUT;
761 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
762 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
763 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
764 return ECORE_SUCCESS;
768 addr = GTT_BAR0_MAP_REG_USDM_RAM +
769 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
774 command |= X_FINAL_CLEANUP_AGG_INT <<
775 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
776 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
777 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
778 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
780 /* Make sure notification is not set before initiating final cleanup */
782 if (REG_RD(p_hwfn, addr)) {
783 DP_NOTICE(p_hwfn, false,
784 "Unexpected; Found final cleanup notification");
785 DP_NOTICE(p_hwfn, false,
786 " before initiating final cleanup\n");
787 REG_WR(p_hwfn, addr, 0);
790 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
791 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
794 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
796 /* Poll until completion */
797 while (!REG_RD(p_hwfn, addr) && count--)
798 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
800 if (REG_RD(p_hwfn, addr))
803 DP_NOTICE(p_hwfn, true,
804 "Failed to receive FW final cleanup notification\n");
806 /* Cleanup afterwards */
807 REG_WR(p_hwfn, addr, 0);
812 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
816 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
817 hw_mode |= 1 << MODE_BB;
818 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
819 hw_mode |= 1 << MODE_K2;
821 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
822 p_hwfn->p_dev->type);
826 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
827 switch (p_hwfn->p_dev->num_ports_in_engines) {
829 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
832 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
835 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
838 DP_NOTICE(p_hwfn, true,
839 "num_ports_in_engine = %d not supported\n",
840 p_hwfn->p_dev->num_ports_in_engines);
844 switch (p_hwfn->p_dev->mf_mode) {
845 case ECORE_MF_DEFAULT:
847 hw_mode |= 1 << MODE_MF_SI;
850 hw_mode |= 1 << MODE_MF_SD;
853 DP_NOTICE(p_hwfn, true,
854 "Unsupported MF mode, init as DEFAULT\n");
855 hw_mode |= 1 << MODE_MF_SI;
859 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
860 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
861 hw_mode |= 1 << MODE_FPGA;
863 if (p_hwfn->p_dev->b_is_emul_full)
864 hw_mode |= 1 << MODE_EMUL_FULL;
866 hw_mode |= 1 << MODE_EMUL_REDUCED;
870 hw_mode |= 1 << MODE_ASIC;
872 if (p_hwfn->p_dev->num_hwfns > 1)
873 hw_mode |= 1 << MODE_100G;
875 p_hwfn->hw_info.hw_mode = hw_mode;
877 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
878 "Configuring function for hw_mode: 0x%08x\n",
879 p_hwfn->hw_info.hw_mode);
881 return ECORE_SUCCESS;
885 /* MFW-replacement initializations for non-ASIC */
886 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
887 struct ecore_ptt *p_ptt)
889 struct ecore_dev *p_dev = p_hwfn->p_dev;
893 if (CHIP_REV_IS_EMUL(p_dev)) {
894 if (ECORE_IS_AH(p_dev))
898 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
900 if (CHIP_REV_IS_EMUL(p_dev) &&
901 (ECORE_IS_AH(p_dev)))
902 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
905 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
906 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
907 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
908 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
910 if (CHIP_REV_IS_EMUL(p_dev)) {
911 if (ECORE_IS_AH(p_dev)) {
912 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
913 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
914 (p_dev->num_ports_in_engines >> 1));
916 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
917 p_dev->num_ports_in_engines == 4 ? 0 : 3);
922 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
923 for (i = 0; i < 100; i++) {
925 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
929 DP_NOTICE(p_hwfn, true,
930 "RBC done failed to complete in PSWRQ2\n");
932 return ECORE_SUCCESS;
936 /* Init run time data for all PFs and their VFs on an engine.
937 * TBD - for VFs - Once we have parent PF info for each VF in
938 * shmem available as CAU requires knowledge of parent PF for each VF.
940 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
942 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
945 for_each_hwfn(p_dev, i) {
946 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
947 struct ecore_igu_info *p_igu_info;
948 struct ecore_igu_block *p_block;
949 struct cau_sb_entry sb_entry;
951 p_igu_info = p_hwfn->hw_info.p_igu_info;
953 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
955 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
960 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
961 p_block->function_id, 0, 0);
962 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
967 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
968 struct ecore_ptt *p_ptt,
971 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
972 struct ecore_dev *p_dev = p_hwfn->p_dev;
973 u8 vf_id, max_num_vfs;
976 enum _ecore_status_t rc = ECORE_SUCCESS;
978 ecore_init_cau_rt_data(p_dev);
980 /* Program GTT windows */
981 ecore_gtt_init(p_hwfn);
984 if (CHIP_REV_IS_EMUL(p_dev)) {
985 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
986 if (rc != ECORE_SUCCESS)
991 if (p_hwfn->mcp_info) {
992 if (p_hwfn->mcp_info->func_info.bandwidth_max)
993 qm_info->pf_rl_en = 1;
994 if (p_hwfn->mcp_info->func_info.bandwidth_min)
995 qm_info->pf_wfq_en = 1;
998 ecore_qm_common_rt_init(p_hwfn,
999 p_dev->num_ports_in_engines,
1000 qm_info->max_phys_tcs_per_port,
1001 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1002 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1003 qm_info->qm_port_params);
1005 ecore_cxt_hw_init_common(p_hwfn);
1007 /* Close gate from NIG to BRB/Storm; By default they are open, but
1008 * we close them to prevent NIG from passing data to reset blocks.
1009 * Should have been done in the ENGINE phase, but init-tool lacks
1010 * proper port-pretend capabilities.
1012 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1013 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1014 ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1015 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1016 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1017 ecore_port_unpretend(p_hwfn, p_ptt);
1019 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1020 if (rc != ECORE_SUCCESS)
1023 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1024 * need to decide with which value, maybe runtime
1026 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1027 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1029 if (ECORE_IS_BB(p_dev)) {
1030 /* Workaround clears ROCE search for all functions to prevent
1031 * involving non initialized function in processing ROCE packet.
1033 num_pfs = NUM_OF_ENG_PFS(p_dev);
1034 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1035 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1036 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1037 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1039 /* pretend to original PF */
1040 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1043 /* Workaround for avoiding CCFC execution error when getting packets
1044 * with CRC errors, and allowing instead the invoking of the FW error
1046 * This is not done inside the init tool since it currently can't
1047 * perform a pretending to VFs.
1049 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1050 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1051 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1052 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1053 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1054 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1055 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1056 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1058 /* pretend to original PF */
1059 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1065 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1066 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1068 #define PMEG_IF_BYTE_COUNT 8
1070 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1071 struct ecore_ptt *p_ptt,
1072 u32 addr, u64 data, u8 reg_type, u8 port)
1074 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1075 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1076 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1077 (8 << PMEG_IF_BYTE_COUNT),
1078 (reg_type << 25) | (addr << 8) | port,
1079 (u32)((data >> 32) & 0xffffffff),
1080 (u32)(data & 0xffffffff));
1082 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1083 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1084 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1085 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1086 (reg_type << 25) | (addr << 8) | port);
1087 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1088 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1089 (data >> 32) & 0xffffffff);
1092 #define XLPORT_MODE_REG (0x20a)
1093 #define XLPORT_MAC_CONTROL (0x210)
1094 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1095 #define XLPORT_ENABLE_REG (0x20b)
1097 #define XLMAC_CTRL (0x600)
1098 #define XLMAC_MODE (0x601)
1099 #define XLMAC_RX_MAX_SIZE (0x608)
1100 #define XLMAC_TX_CTRL (0x604)
1101 #define XLMAC_PAUSE_CTRL (0x60d)
1102 #define XLMAC_PFC_CTRL (0x60e)
1104 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1105 struct ecore_ptt *p_ptt)
1107 u8 loopback = 0, port = p_hwfn->port_id * 2;
1109 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1111 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1112 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1114 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1115 /* XLMAC: SOFT RESET */
1116 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1117 /* XLMAC: Port Speed >= 10Gbps */
1118 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1119 /* XLMAC: Max Size */
1120 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1121 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1122 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1124 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1125 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1126 0x30ffffc000ULL, 0, port);
1127 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1128 port); /* XLMAC: TX_EN, RX_EN */
1129 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1130 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1131 0x1003 | (loopback << 2), 0, port);
1132 /* Enabled Parallel PFC interface */
1133 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1135 /* XLPORT port enable */
1136 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1139 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1140 struct ecore_ptt *p_ptt)
1142 u8 port = p_hwfn->port_id;
1143 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1145 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1147 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1148 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1150 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1151 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1153 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1154 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1156 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1157 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1159 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1160 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1162 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1163 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1165 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1167 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1169 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1171 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1175 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1176 struct ecore_ptt *p_ptt)
1178 if (ECORE_IS_AH(p_hwfn->p_dev))
1179 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1181 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1184 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1185 struct ecore_ptt *p_ptt, u8 port)
1187 int port_offset = port ? 0x800 : 0;
1188 u32 xmac_rxctrl = 0;
1191 /* FIXME: move to common start */
1192 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1193 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1195 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1196 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1198 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1200 /* Set the number of ports on the Warp Core to 10G */
1201 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1203 /* Soft reset of XMAC */
1204 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1205 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1207 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1208 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1210 /* FIXME: move to common end */
1211 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1212 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1214 /* Set Max packet size: initialize XMAC block register for port 0 */
1215 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1217 /* CRC append for Tx packets: init XMAC block register for port 1 */
1218 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1220 /* Enable TX and RX: initialize XMAC block register for port 1 */
1221 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1222 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1223 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1224 XMAC_REG_RX_CTRL_BB + port_offset);
1225 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1226 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1230 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1231 struct ecore_ptt *p_ptt,
1234 enum _ecore_status_t rc = ECORE_SUCCESS;
1236 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1238 if (rc != ECORE_SUCCESS)
1241 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1242 return ECORE_SUCCESS;
1244 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1245 if (ECORE_IS_AH(p_hwfn->p_dev))
1246 return ECORE_SUCCESS;
1247 else if (ECORE_IS_BB(p_hwfn->p_dev))
1248 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1249 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1250 if (p_hwfn->p_dev->num_hwfns > 1) {
1251 /* Activate OPTE in CMT */
1254 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1256 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1257 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1258 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1259 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1260 ecore_wr(p_hwfn, p_ptt,
1261 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1262 ecore_wr(p_hwfn, p_ptt,
1263 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1264 ecore_wr(p_hwfn, p_ptt,
1265 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1269 ecore_emul_link_init(p_hwfn, p_ptt);
1271 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1278 static enum _ecore_status_t
1279 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1280 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1282 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1283 u32 dpi_bit_shift, dpi_count;
1286 /* Calculate DPI size
1287 * ------------------
1288 * The PWM region contains Doorbell Pages. The first is reserverd for
1289 * the kernel for, e.g, L2. The others are free to be used by non-
1290 * trusted applications, typically from user space. Each page, called a
1291 * doorbell page is sectioned into windows that allow doorbells to be
1292 * issued in parallel by the kernel/application. The size of such a
1293 * window (a.k.a. WID) is 1kB.
1295 * 1kB WID x N WIDS = DPI page size
1296 * DPI page size x N DPIs = PWM region size
1298 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1299 * in order to ensure that two applications won't share the same page.
1300 * It also must contain at least one WID per CPU to allow parallelism.
1301 * It also must be a power of 2, since it is stored as a bit shift.
1303 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1304 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1305 * containing 4 WIDs.
1307 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1308 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1309 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1310 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1311 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1313 dpi_count = pwm_region_size / dpi_page_size;
1315 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1316 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1319 p_hwfn->dpi_size = dpi_page_size;
1320 p_hwfn->dpi_count = dpi_count;
1322 /* Update registers */
1323 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1325 if (dpi_count < min_dpis)
1326 return ECORE_NORESOURCES;
1328 return ECORE_SUCCESS;
1331 enum ECORE_ROCE_EDPM_MODE {
1332 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1333 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1334 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1337 static enum _ecore_status_t
1338 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1339 struct ecore_ptt *p_ptt)
1341 u32 pwm_regsize, norm_regsize;
1342 u32 non_pwm_conn, min_addr_reg1;
1343 u32 db_bar_size, n_cpus;
1346 int rc = ECORE_SUCCESS;
1349 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1350 if (p_hwfn->p_dev->num_hwfns > 1)
1353 /* Calculate doorbell regions
1354 * -----------------------------------
1355 * The doorbell BAR is made of two regions. The first is called normal
1356 * region and the second is called PWM region. In the normal region
1357 * each ICID has its own set of addresses so that writing to that
1358 * specific address identifies the ICID. In the Process Window Mode
1359 * region the ICID is given in the data written to the doorbell. The
1360 * above per PF register denotes the offset in the doorbell BAR in which
1361 * the PWM region begins.
1362 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1363 * non-PWM connection. The calculation below computes the total non-PWM
1364 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1365 * in units of 4,096 bytes.
1367 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1368 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1370 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1371 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1372 min_addr_reg1 = norm_regsize / 4096;
1373 pwm_regsize = db_bar_size - norm_regsize;
1375 /* Check that the normal and PWM sizes are valid */
1376 if (db_bar_size < norm_regsize) {
1377 DP_ERR(p_hwfn->p_dev,
1378 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1379 db_bar_size, norm_regsize);
1380 return ECORE_NORESOURCES;
1382 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1383 DP_ERR(p_hwfn->p_dev,
1384 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1385 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1387 return ECORE_NORESOURCES;
1390 /* Calculate number of DPIs */
1391 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1392 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1393 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1394 /* Either EDPM is mandatory, or we are attempting to allocate a
1397 n_cpus = OSAL_NUM_ACTIVE_CPU();
1398 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1401 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1402 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1403 if (cond || p_hwfn->dcbx_no_edpm) {
1404 /* Either EDPM is disabled from user configuration, or it is
1405 * disabled via DCBx, or it is not mandatory and we failed to
1406 * allocated a WID per CPU.
1409 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1411 /* If we entered this flow due to DCBX then the DPM register is
1412 * already configured.
1417 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1418 norm_regsize, pwm_regsize);
1420 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1421 p_hwfn->dpi_size, p_hwfn->dpi_count,
1422 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1423 "disabled" : "enabled");
1425 /* Check return codes from above calls */
1428 "Failed to allocate enough DPIs\n");
1429 return ECORE_NORESOURCES;
1433 p_hwfn->dpi_start_offset = norm_regsize;
1435 /* Update registers */
1436 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1437 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1438 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1439 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1441 return ECORE_SUCCESS;
1444 static enum _ecore_status_t
1445 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1446 struct ecore_ptt *p_ptt,
1447 struct ecore_tunn_start_params *p_tunn,
1450 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1452 u8 rel_pf_id = p_hwfn->rel_pf_id;
1454 enum _ecore_status_t rc = ECORE_SUCCESS;
1458 if (p_hwfn->mcp_info) {
1459 struct ecore_mcp_function_info *p_info;
1461 p_info = &p_hwfn->mcp_info->func_info;
1462 if (p_info->bandwidth_min)
1463 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1465 /* Update rate limit once we'll actually have a link */
1466 p_hwfn->qm_info.pf_rl = 100000;
1468 ecore_cxt_hw_init_pf(p_hwfn);
1470 ecore_int_igu_init_rt(p_hwfn);
1472 /* Set VLAN in NIG if needed */
1473 if (hw_mode & (1 << MODE_MF_SD)) {
1474 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1475 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1476 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1477 p_hwfn->hw_info.ovlan);
1480 /* Enable classification by MAC if needed */
1481 if (hw_mode & (1 << MODE_MF_SI)) {
1482 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1483 "Configuring TAGMAC_CLS_TYPE\n");
1484 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1488 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1489 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1490 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1491 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1492 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1493 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1495 /* perform debug configuration when chip is out of reset */
1496 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1498 /* Cleanup chip from previous driver if such remains exist */
1499 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1500 if (rc != ECORE_SUCCESS) {
1501 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1505 /* PF Init sequence */
1506 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1510 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1511 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1515 /* Pure runtime initializations - directly to the HW */
1516 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1518 /* PCI relaxed ordering causes a decrease in the performance on some
1519 * systems. Till a root cause is found, disable this attribute in the
1523 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1525 * DP_NOTICE(p_hwfn, true,
1526 * "Failed to find the PCIe Cap\n");
1529 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1530 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1531 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1534 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1538 /* enable interrupts */
1539 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1540 if (rc != ECORE_SUCCESS)
1543 /* send function start command */
1544 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1545 allow_npar_tx_switch);
1547 DP_NOTICE(p_hwfn, true,
1548 "Function start ramrod failed\n");
1550 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1551 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1552 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1554 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1555 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1557 ecore_wr(p_hwfn, p_ptt,
1558 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1561 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1562 "PRS_REG_SEARCH registers after start PFn\n");
1563 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1564 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1565 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1566 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1567 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1568 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1569 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1570 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1571 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1572 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1573 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1574 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1575 prs_reg = ecore_rd(p_hwfn, p_ptt,
1576 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1577 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1578 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1580 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1581 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1582 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1588 static enum _ecore_status_t
1589 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1590 struct ecore_ptt *p_ptt, u8 enable)
1592 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1594 /* Change PF in PXP */
1595 ecore_wr(p_hwfn, p_ptt,
1596 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1598 /* wait until value is set - try for 1 second every 50us */
1599 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1600 val = ecore_rd(p_hwfn, p_ptt,
1601 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1608 if (val != set_val) {
1609 DP_NOTICE(p_hwfn, true,
1610 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1611 return ECORE_UNKNOWN_ERROR;
1614 return ECORE_SUCCESS;
1617 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1618 struct ecore_ptt *p_main_ptt)
1620 /* Read shadow of current MFW mailbox */
1621 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1622 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1623 p_hwfn->mcp_info->mfw_mb_cur,
1624 p_hwfn->mcp_info->mfw_mb_length);
1627 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1628 struct ecore_hw_init_params *p_params)
1630 enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1631 u32 load_code, param, drv_mb_param;
1632 bool b_default_mtu = true;
1633 struct ecore_hwfn *p_hwfn;
1636 if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1637 (p_dev->num_hwfns > 1)) {
1638 DP_NOTICE(p_dev, false,
1639 "MSI mode is not supported for CMT devices\n");
1644 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1645 if (rc != ECORE_SUCCESS)
1649 for_each_hwfn(p_dev, i) {
1650 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1652 /* If management didn't provide a default, set one of our own */
1653 if (!p_hwfn->hw_info.mtu) {
1654 p_hwfn->hw_info.mtu = 1500;
1655 b_default_mtu = false;
1659 p_hwfn->b_int_enabled = 1;
1663 /* Enable DMAE in PXP */
1664 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1665 if (rc != ECORE_SUCCESS)
1668 rc = ecore_calc_hw_mode(p_hwfn);
1669 if (rc != ECORE_SUCCESS)
1672 /* @@@TBD need to add here:
1673 * Check for fan failure
1676 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1678 DP_NOTICE(p_hwfn, true,
1679 "Failed sending LOAD_REQ command\n");
1684 * When coming back from hiberbate state, the registers from
1685 * which shadow is read initially are not initialized. It turns
1686 * out that these registers get initialized during the call to
1687 * ecore_mcp_load_req request. So we need to reread them here
1688 * to get the proper shadow register value.
1689 * Note: This is a workaround for the missing MFW
1690 * initialization. It may be removed once the implementation
1693 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1695 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1696 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1699 /* Only relevant for recovery:
1700 * Clear the indication after the LOAD_REQ command is responded
1703 p_dev->recov_in_prog = false;
1705 p_hwfn->first_on_engine = (load_code ==
1706 FW_MSG_CODE_DRV_LOAD_ENGINE);
1708 if (!qm_lock_init) {
1709 OSAL_SPIN_LOCK_INIT(&qm_lock);
1710 qm_lock_init = true;
1713 switch (load_code) {
1714 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1715 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1716 p_hwfn->hw_info.hw_mode);
1720 case FW_MSG_CODE_DRV_LOAD_PORT:
1721 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1722 p_hwfn->hw_info.hw_mode);
1726 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1727 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1729 p_hwfn->hw_info.hw_mode,
1730 p_params->b_hw_start,
1732 p_params->allow_npar_tx_switch);
1739 if (rc != ECORE_SUCCESS)
1740 DP_NOTICE(p_hwfn, true,
1741 "init phase failed for loadcode 0x%x (rc %d)\n",
1744 /* ACK mfw regardless of success or failure of initialization */
1745 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1746 DRV_MSG_CODE_LOAD_DONE,
1747 0, &load_code, ¶m);
1748 if (rc != ECORE_SUCCESS)
1750 if (mfw_rc != ECORE_SUCCESS) {
1751 DP_NOTICE(p_hwfn, true,
1752 "Failed sending LOAD_DONE command\n");
1756 /* send DCBX attention request command */
1757 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1758 "sending phony dcbx set command to trigger DCBx attention handling\n");
1759 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1760 DRV_MSG_CODE_SET_DCBX,
1761 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1762 &load_code, ¶m);
1763 if (mfw_rc != ECORE_SUCCESS) {
1764 DP_NOTICE(p_hwfn, true,
1765 "Failed to send DCBX attention request\n");
1769 p_hwfn->hw_init_done = true;
1773 p_hwfn = ECORE_LEADING_HWFN(p_dev);
1774 drv_mb_param = (FW_MAJOR_VERSION << 24) |
1775 (FW_MINOR_VERSION << 16) |
1776 (FW_REVISION_VERSION << 8) |
1777 (FW_ENGINEERING_VERSION);
1778 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1779 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1780 drv_mb_param, &load_code, ¶m);
1781 if (rc != ECORE_SUCCESS)
1782 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1785 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1786 p_hwfn->hw_info.mtu);
1787 if (rc != ECORE_SUCCESS)
1788 DP_INFO(p_hwfn, "Failed to update default mtu\n");
1790 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
1792 ECORE_OV_DRIVER_STATE_DISABLED);
1793 if (rc != ECORE_SUCCESS)
1794 DP_INFO(p_hwfn, "Failed to update driver state\n");
1800 #define ECORE_HW_STOP_RETRY_LIMIT (10)
1801 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1802 struct ecore_hwfn *p_hwfn,
1803 struct ecore_ptt *p_ptt)
1808 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1809 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1810 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1812 if ((!ecore_rd(p_hwfn, p_ptt,
1813 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1814 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1817 /* Dependent on number of connection/tasks, possibly
1818 * 1ms sleep is required between polls
1823 if (i < ECORE_HW_STOP_RETRY_LIMIT)
1826 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
1827 " [Connection %02x Tasks %02x]\n",
1828 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1829 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1832 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1836 for_each_hwfn(p_dev, j) {
1837 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1838 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1840 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1844 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1846 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1849 for_each_hwfn(p_dev, j) {
1850 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1851 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1853 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1856 ecore_vf_pf_int_cleanup(p_hwfn);
1860 /* mark the hw as uninitialized... */
1861 p_hwfn->hw_init_done = false;
1863 rc = ecore_sp_pf_stop(p_hwfn);
1865 DP_NOTICE(p_hwfn, true,
1866 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1868 /* perform debug action after PF stop was sent */
1869 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1871 /* close NIG to BRB gate */
1872 ecore_wr(p_hwfn, p_ptt,
1873 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1876 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1877 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1878 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1879 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1880 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1882 /* @@@TBD - clean transmission queues (5.b) */
1883 /* @@@TBD - clean BTB (5.c) */
1885 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1887 /* @@@TBD - verify DMAE requests are done (8) */
1889 /* Disable Attention Generation */
1890 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1891 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1892 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1893 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1894 /* Need to wait 1ms to guarantee SBs are cleared */
1899 /* Disable DMAE in PXP - in CMT, this should only be done for
1900 * first hw-function, and only after all transactions have
1901 * stopped for all active hw-functions.
1903 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1904 p_dev->hwfns[0].p_main_ptt, false);
1905 if (t_rc != ECORE_SUCCESS)
1912 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1916 for_each_hwfn(p_dev, j) {
1917 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1918 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1921 ecore_vf_pf_int_cleanup(p_hwfn);
1925 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1926 "Shutting down the fastpath\n");
1928 ecore_wr(p_hwfn, p_ptt,
1929 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1931 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1932 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1933 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1934 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1935 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1937 /* @@@TBD - clean transmission queues (5.b) */
1938 /* @@@TBD - clean BTB (5.c) */
1940 /* @@@TBD - verify DMAE requests are done (8) */
1942 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1943 /* Need to wait 1ms to guarantee SBs are cleared */
1948 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1950 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1952 if (IS_VF(p_hwfn->p_dev))
1955 /* If roce info is allocated it means roce is initialized and should
1956 * be enabled in searcher.
1958 if (p_hwfn->p_rdma_info) {
1959 if (p_hwfn->b_rdma_enabled_in_prs)
1960 ecore_wr(p_hwfn, p_ptt,
1961 p_hwfn->rdma_prs_search_reg, 0x1);
1962 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1965 /* Re-open incoming traffic */
1966 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1967 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1970 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1971 struct ecore_ptt *p_ptt, u32 reg,
1974 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1976 if (assert_val != expected) {
1977 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1979 return ECORE_UNKNOWN_ERROR;
1985 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1987 enum _ecore_status_t rc = ECORE_SUCCESS;
1988 u32 unload_resp, unload_param;
1991 for_each_hwfn(p_dev, i) {
1992 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1995 rc = ecore_vf_pf_reset(p_hwfn);
2001 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
2003 /* Check for incorrect states */
2004 if (!p_dev->recov_in_prog) {
2005 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2006 QM_REG_USG_CNT_PF_TX, 0);
2007 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2008 QM_REG_USG_CNT_PF_OTHER, 0);
2009 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2012 /* Disable PF in HW blocks */
2013 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2014 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2016 if (p_dev->recov_in_prog) {
2017 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2018 "Recovery is in progress -> skip sending unload_req/done\n");
2022 /* Send unload command to MCP */
2023 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2024 DRV_MSG_CODE_UNLOAD_REQ,
2025 DRV_MB_PARAM_UNLOAD_WOL_MCP,
2026 &unload_resp, &unload_param);
2027 if (rc != ECORE_SUCCESS) {
2028 DP_NOTICE(p_hwfn, true,
2029 "ecore_hw_reset: UNLOAD_REQ failed\n");
2030 /* @@TBD - what to do? for now, assume ENG. */
2031 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2034 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2035 DRV_MSG_CODE_UNLOAD_DONE,
2036 0, &unload_resp, &unload_param);
2037 if (rc != ECORE_SUCCESS) {
2039 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2040 /* @@@TBD - Should it really ASSERT here ? */
2048 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2049 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2051 ecore_ptt_pool_free(p_hwfn);
2052 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2055 /* Setup bar access */
2056 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2058 /* clear indirect access */
2059 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2060 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2061 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2062 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2063 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2064 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2065 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2066 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2067 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2069 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2070 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2071 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2072 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2073 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2074 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2075 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2076 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2079 /* Clean Previous errors if such exist */
2080 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2081 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2083 /* enable internal target-read */
2084 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2085 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2088 static void get_function_id(struct ecore_hwfn *p_hwfn)
2091 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2092 PXP_PF_ME_OPAQUE_ADDR);
2094 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2096 /* Bits 16-19 from the ME registers are the pf_num */
2097 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2098 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2099 PXP_CONCRETE_FID_PFID);
2100 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2101 PXP_CONCRETE_FID_PORT);
2103 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2104 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2105 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2108 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2110 u32 *feat_num = p_hwfn->hw_info.feat_num;
2111 struct ecore_sb_cnt_info sb_cnt_info;
2112 int num_features = 1;
2114 /* L2 Queues require each: 1 status block. 1 L2 queue */
2115 feat_num[ECORE_PF_L2_QUE] =
2117 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2118 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2120 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2121 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2122 feat_num[ECORE_VF_L2_QUE] =
2124 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2125 FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2126 sb_cnt_info.sb_iov_cnt);
2128 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2129 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2130 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2131 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2132 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2133 RESC_NUM(p_hwfn, ECORE_SB),
2137 static enum resource_id_enum
2138 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2140 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2144 mfw_res_id = RESOURCE_NUM_SB_E;
2146 case ECORE_L2_QUEUE:
2147 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2150 mfw_res_id = RESOURCE_NUM_VPORT_E;
2153 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2156 mfw_res_id = RESOURCE_NUM_PQ_E;
2159 mfw_res_id = RESOURCE_NUM_RL_E;
2163 /* Each VFC resource can accommodate both a MAC and a VLAN */
2164 mfw_res_id = RESOURCE_VFC_FILTER_E;
2167 mfw_res_id = RESOURCE_ILT_E;
2169 case ECORE_LL2_QUEUE:
2170 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2172 case ECORE_RDMA_CNQ_RAM:
2173 case ECORE_CMDQS_CQS:
2174 /* CNQ/CMDQS are the same resource */
2175 mfw_res_id = RESOURCE_CQS_E;
2177 case ECORE_RDMA_STATS_QUEUE:
2178 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2187 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2188 enum ecore_resources res_id)
2190 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2191 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2192 struct ecore_sb_cnt_info sb_cnt_info;
2193 u32 dflt_resc_num = 0;
2197 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2198 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2199 dflt_resc_num = sb_cnt_info.sb_cnt;
2201 case ECORE_L2_QUEUE:
2202 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2203 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2206 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2207 MAX_NUM_VPORTS_BB) / num_funcs;
2210 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2211 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2214 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2215 MAX_QM_TX_QUEUES_BB) / num_funcs;
2218 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2222 /* Each VFC resource can accommodate both a MAC and a VLAN */
2223 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2226 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2227 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2229 case ECORE_LL2_QUEUE:
2230 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2232 case ECORE_RDMA_CNQ_RAM:
2233 case ECORE_CMDQS_CQS:
2234 /* CNQ/CMDQS are the same resource */
2236 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2238 case ECORE_RDMA_STATS_QUEUE:
2240 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2241 MAX_NUM_VPORTS_BB) / num_funcs;
2247 return dflt_resc_num;
2250 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2255 case ECORE_L2_QUEUE:
2269 case ECORE_RDMA_CNQ_RAM:
2270 return "RDMA_CNQ_RAM";
2273 case ECORE_LL2_QUEUE:
2275 case ECORE_CMDQS_CQS:
2277 case ECORE_RDMA_STATS_QUEUE:
2278 return "RDMA_STATS_QUEUE";
2280 return "UNKNOWN_RESOURCE";
2284 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2285 enum ecore_resources res_id,
2286 bool drv_resc_alloc)
2288 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2289 u32 *p_resc_num, *p_resc_start;
2290 struct resource_info resc_info;
2291 enum _ecore_status_t rc;
2293 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2294 p_resc_start = &RESC_START(p_hwfn, res_id);
2296 dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2297 if (!dflt_resc_num) {
2299 "Failed to get default amount for resource %d [%s]\n",
2300 res_id, ecore_hw_get_resc_name(res_id));
2303 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2306 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2307 *p_resc_num = dflt_resc_num;
2308 *p_resc_start = dflt_resc_start;
2313 OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2314 resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2315 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2317 "Failed to match resource %d with MFW resources\n",
2322 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2323 &mcp_resp, &mcp_param);
2324 if (rc != ECORE_SUCCESS) {
2325 DP_NOTICE(p_hwfn, true,
2326 "MFW response failure for an allocation request for"
2327 " resource %d [%s]\n",
2328 res_id, ecore_hw_get_resc_name(res_id));
2332 /* Default driver values are applied in the following cases:
2333 * - The resource allocation MB command is not supported by the MFW
2334 * - There is an internal error in the MFW while processing the request
2335 * - The resource ID is unknown to the MFW
2337 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2338 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2341 "Resource %d [%s]: No allocation info was received"
2342 " [mcp_resp 0x%x]. Applying default values"
2343 " [num %d, start %d].\n",
2344 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2345 dflt_resc_num, dflt_resc_start);
2347 *p_resc_num = dflt_resc_num;
2348 *p_resc_start = dflt_resc_start;
2352 /* TBD - remove this when revising the handling of the SB resource */
2353 if (res_id == ECORE_SB) {
2354 /* Excluding the slowpath SB */
2355 resc_info.size -= 1;
2356 resc_info.offset -= p_hwfn->enabled_func_idx;
2359 *p_resc_num = resc_info.size;
2360 *p_resc_start = resc_info.offset;
2362 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2364 "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2365 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2366 *p_resc_start, dflt_resc_num, dflt_resc_start,
2367 drv_resc_alloc ? " - Applying default values" : "");
2368 if (drv_resc_alloc) {
2369 *p_resc_num = dflt_resc_num;
2370 *p_resc_start = dflt_resc_start;
2374 return ECORE_SUCCESS;
2377 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2378 bool drv_resc_alloc)
2380 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2381 enum _ecore_status_t rc;
2384 u32 *resc_start = p_hwfn->hw_info.resc_start;
2385 u32 *resc_num = p_hwfn->hw_info.resc_num;
2386 /* For AH, an equal share of the ILT lines between the maximal number of
2387 * PFs is not enough for RoCE. This would be solved by the future
2388 * resource allocation scheme, but isn't currently present for
2389 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2390 * to work - the BB number of ILT lines divided by its max PFs number.
2392 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2395 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2396 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2397 if (rc != ECORE_SUCCESS)
2402 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2403 /* Reduced build contains less PQs */
2404 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2405 resc_num[ECORE_PQ] = 32;
2406 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2407 p_hwfn->enabled_func_idx;
2410 /* For AH emulation, since we have a possible maximal number of
2411 * 16 enabled PFs, in case there are not enough ILT lines -
2412 * allocate only first PF as RoCE and have all the other ETH
2413 * only with less ILT lines.
2415 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2416 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2417 resc_num[ECORE_ILT],
2418 roce_min_ilt_lines);
2421 /* Correct the common ILT calculation if PF0 has more */
2422 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2423 p_hwfn->p_dev->b_is_emul_full &&
2424 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2425 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2426 resc_num[ECORE_ILT];
2429 /* Sanity for ILT */
2430 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2431 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2432 DP_NOTICE(p_hwfn, true,
2433 "Can't assign ILT pages [%08x,...,%08x]\n",
2434 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2440 ecore_hw_set_feat(p_hwfn);
2442 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2443 "The numbers for each resource are:\n");
2444 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2445 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2446 ecore_hw_get_resc_name(res_id),
2447 RESC_NUM(p_hwfn, res_id),
2448 RESC_START(p_hwfn, res_id));
2450 return ECORE_SUCCESS;
2453 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2454 struct ecore_ptt *p_ptt)
2456 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2457 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2458 struct ecore_mcp_link_params *link;
2460 /* Read global nvm_cfg address */
2461 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2463 /* Verify MCP has initialized it */
2464 if (!nvm_cfg_addr) {
2465 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2469 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2471 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2473 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2474 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2477 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2479 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2480 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2481 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2482 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2484 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2485 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2487 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2488 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2490 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2491 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2493 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2494 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2496 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2497 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2499 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2500 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2502 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2503 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2505 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2506 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2508 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2509 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2511 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2512 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2515 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2520 /* Read DCBX configuration */
2521 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2522 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2523 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2525 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2526 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2527 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2528 switch (dcbx_mode) {
2529 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2530 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2532 case NVM_CFG1_PORT_DCBX_MODE_CEE:
2533 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2535 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2536 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2539 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2542 /* Read default link configuration */
2543 link = &p_hwfn->mcp_info->link_input;
2544 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2545 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2546 link_temp = ecore_rd(p_hwfn, p_ptt,
2548 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2549 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2550 link->speed.advertised_speeds = link_temp;
2552 link_temp = link->speed.advertised_speeds;
2553 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2555 link_temp = ecore_rd(p_hwfn, p_ptt,
2557 OFFSETOF(struct nvm_cfg1_port, link_settings));
2558 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2559 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2560 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2561 link->speed.autoneg = true;
2563 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2564 link->speed.forced_speed = 1000;
2566 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2567 link->speed.forced_speed = 10000;
2569 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2570 link->speed.forced_speed = 25000;
2572 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2573 link->speed.forced_speed = 40000;
2575 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2576 link->speed.forced_speed = 50000;
2578 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2579 link->speed.forced_speed = 100000;
2582 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2585 p_hwfn->mcp_info->link_capabilities.default_speed =
2586 link->speed.forced_speed;
2587 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2588 link->speed.autoneg;
2590 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2591 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2592 link->pause.autoneg = !!(link_temp &
2593 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2594 link->pause.forced_rx = !!(link_temp &
2595 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2596 link->pause.forced_tx = !!(link_temp &
2597 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2598 link->loopback_mode = 0;
2600 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2601 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2602 link->speed.forced_speed, link->speed.advertised_speeds,
2603 link->speed.autoneg, link->pause.autoneg);
2605 /* Read Multi-function information from shmem */
2606 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2607 OFFSETOF(struct nvm_cfg1, glob) +
2608 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2610 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2612 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2613 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2616 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2617 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2619 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2620 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2622 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2623 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2626 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2627 p_hwfn->p_dev->mf_mode);
2629 /* Read Multi-function information from shmem */
2630 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2631 OFFSETOF(struct nvm_cfg1, glob) +
2632 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2634 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2635 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2636 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2637 &p_hwfn->hw_info.device_capabilities);
2638 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2639 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2640 &p_hwfn->hw_info.device_capabilities);
2641 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2642 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2643 &p_hwfn->hw_info.device_capabilities);
2644 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2645 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2646 &p_hwfn->hw_info.device_capabilities);
2647 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2648 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2649 &p_hwfn->hw_info.device_capabilities);
2651 return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2654 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2655 struct ecore_ptt *p_ptt)
2657 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2658 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2659 struct ecore_dev *p_dev = p_hwfn->p_dev;
2661 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2663 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2664 * in the other bits are selected.
2665 * Bits 1-15 are for functions 1-15, respectively, and their value is
2666 * '0' only for enabled functions (function 0 always exists and
2668 * In case of CMT in BB, only the "even" functions are enabled, and thus
2669 * the number of functions for both hwfns is learnt from the same bits.
2671 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
2672 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
2673 MISCS_REG_FUNCTION_HIDE_BB_K2);
2675 reg_function_hide = 0;
2678 if (reg_function_hide & 0x1) {
2679 if (ECORE_IS_BB(p_dev)) {
2680 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2692 /* Get the number of the enabled functions on the engine */
2693 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2700 /* Get the PF index within the enabled functions */
2701 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2702 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2710 p_hwfn->num_funcs_on_engine = num_funcs;
2711 p_hwfn->enabled_func_idx = enabled_func_idx;
2714 if (CHIP_REV_IS_FPGA(p_dev)) {
2715 DP_NOTICE(p_hwfn, false,
2716 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2717 p_hwfn->num_funcs_on_engine = 4;
2721 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2722 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2723 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2724 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2727 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2728 struct ecore_ptt *p_ptt)
2733 /* Read the port mode */
2734 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2736 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2737 (p_hwfn->p_dev->num_hwfns > 1))
2738 /* In CMT on emulation, assume 1 port */
2742 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
2744 if (port_mode < 3) {
2745 p_hwfn->p_dev->num_ports_in_engines = 1;
2746 } else if (port_mode <= 5) {
2747 p_hwfn->p_dev->num_ports_in_engines = 2;
2749 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2750 p_hwfn->p_dev->num_ports_in_engines);
2752 /* Default num_ports_in_engines to something */
2753 p_hwfn->p_dev->num_ports_in_engines = 1;
2757 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
2758 struct ecore_ptt *p_ptt)
2763 p_hwfn->p_dev->num_ports_in_engines = 0;
2766 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2767 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2768 switch ((port & 0xf000) >> 12) {
2770 p_hwfn->p_dev->num_ports_in_engines = 1;
2773 p_hwfn->p_dev->num_ports_in_engines = 2;
2776 p_hwfn->p_dev->num_ports_in_engines = 4;
2779 DP_NOTICE(p_hwfn, false,
2780 "Unknown port mode in ECO_RESERVED %08x\n",
2785 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2786 port = ecore_rd(p_hwfn, p_ptt,
2787 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
2790 p_hwfn->p_dev->num_ports_in_engines++;
2794 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2795 struct ecore_ptt *p_ptt)
2797 if (ECORE_IS_BB(p_hwfn->p_dev))
2798 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2800 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
2803 static enum _ecore_status_t
2804 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2805 enum ecore_pci_personality personality, bool drv_resc_alloc)
2807 enum _ecore_status_t rc;
2809 /* Since all information is common, only first hwfns should do this */
2810 if (IS_LEAD_HWFN(p_hwfn)) {
2811 rc = ecore_iov_hw_info(p_hwfn);
2812 if (rc != ECORE_SUCCESS)
2816 /* TODO In get_hw_info, amoungst others:
2817 * Get MCP FW revision and determine according to it the supported
2818 * featrues (e.g. DCB)
2820 * ecore_get_pcie_width_speed, WOL capability.
2821 * Number of global CQ-s (for storage
2823 ecore_hw_info_port_num(p_hwfn, p_ptt);
2826 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
2828 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2829 if (rc != ECORE_SUCCESS)
2835 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2836 if (rc != ECORE_SUCCESS)
2840 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2842 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2843 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2846 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2848 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2849 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2853 if (ecore_mcp_is_init(p_hwfn)) {
2854 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2855 p_hwfn->hw_info.ovlan =
2856 p_hwfn->mcp_info->func_info.ovlan;
2858 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2861 if (personality != ECORE_PCI_DEFAULT) {
2862 p_hwfn->hw_info.personality = personality;
2863 } else if (ecore_mcp_is_init(p_hwfn)) {
2864 enum ecore_pci_personality protocol;
2866 protocol = p_hwfn->mcp_info->func_info.protocol;
2867 p_hwfn->hw_info.personality = protocol;
2871 /* To overcome ILT lack for emulation, until at least until we'll have
2872 * a definite answer from system about it, allow only PF0 to be RoCE.
2874 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2875 if (!p_hwfn->rel_pf_id)
2876 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2878 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2882 /* although in BB some constellations may support more than 4 tcs,
2883 * that can result in performance penalty in some cases. 4
2884 * represents a good tradeoff between performance and flexibility.
2886 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2888 /* start out with a single active tc. This can be increased either
2889 * by dcbx negotiation or by upper layer driver
2891 p_hwfn->hw_info.num_active_tc = 1;
2893 ecore_get_num_funcs(p_hwfn, p_ptt);
2895 if (ecore_mcp_is_init(p_hwfn))
2896 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2898 /* In case of forcing the driver's default resource allocation, calling
2899 * ecore_hw_get_resc() should come after initializing the personality
2900 * and after getting the number of functions, since the calculation of
2901 * the resources/features depends on them.
2902 * This order is not harmful if not forcing.
2904 return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2907 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2909 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2912 /* Read Vendor Id / Device Id */
2913 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2915 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2918 /* Determine type */
2919 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2920 p_dev->type = ECORE_DEV_TYPE_AH;
2922 p_dev->type = ECORE_DEV_TYPE_BB;
2924 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2925 MISCS_REG_CHIP_NUM);
2926 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2927 MISCS_REG_CHIP_REV);
2929 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2931 /* Learn number of HW-functions */
2932 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2933 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2935 if (tmp & (1 << p_hwfn->rel_pf_id)) {
2936 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2937 p_dev->num_hwfns = 2;
2939 p_dev->num_hwfns = 1;
2943 if (CHIP_REV_IS_EMUL(p_dev)) {
2944 /* For some reason we have problems with this register
2945 * in B0 emulation; Simply assume no CMT
2947 DP_NOTICE(p_dev->hwfns, false,
2948 "device on emul - assume no CMT\n");
2949 p_dev->num_hwfns = 1;
2953 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2954 MISCS_REG_CHIP_TEST_REG) >> 4;
2955 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2956 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2957 MISCS_REG_CHIP_METAL);
2958 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2959 DP_INFO(p_dev->hwfns,
2960 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2961 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2962 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
2963 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2966 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2967 DP_NOTICE(p_dev->hwfns, false,
2968 "The chip type/rev (BB A0) is not supported!\n");
2969 return ECORE_ABORTED;
2972 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2973 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2974 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2976 if (CHIP_REV_IS_EMUL(p_dev)) {
2977 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2978 MISCS_REG_ECO_RESERVED);
2979 if (tmp & (1 << 29)) {
2980 DP_NOTICE(p_hwfn, false,
2981 "Emulation: Running on a FULL build\n");
2982 p_dev->b_is_emul_full = true;
2984 DP_NOTICE(p_hwfn, false,
2985 "Emulation: Running on a REDUCED build\n");
2990 return ECORE_SUCCESS;
2993 #ifndef LINUX_REMOVE
2994 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3001 for_each_hwfn(p_dev, j) {
3002 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3004 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3005 "Mark hw/fw uninitialized\n");
3007 p_hwfn->hw_init_done = false;
3008 p_hwfn->first_on_engine = false;
3010 ecore_ptt_invalidate(p_hwfn);
3015 static enum _ecore_status_t
3016 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3017 void OSAL_IOMEM * p_regview,
3018 void OSAL_IOMEM * p_doorbells,
3019 struct ecore_hw_prepare_params *p_params)
3021 struct ecore_dev *p_dev = p_hwfn->p_dev;
3022 struct ecore_mdump_info mdump_info;
3023 enum _ecore_status_t rc = ECORE_SUCCESS;
3025 /* Split PCI bars evenly between hwfns */
3026 p_hwfn->regview = p_regview;
3027 p_hwfn->doorbells = p_doorbells;
3030 return ecore_vf_hw_prepare(p_hwfn);
3032 /* Validate that chip access is feasible */
3033 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3035 "Reading the ME register returns all Fs; Preventing further chip access\n");
3039 get_function_id(p_hwfn);
3041 /* Allocate PTT pool */
3042 rc = ecore_ptt_pool_alloc(p_hwfn);
3044 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3048 /* Allocate the main PTT */
3049 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3051 /* First hwfn learns basic information, e.g., number of hwfns */
3052 if (!p_hwfn->my_id) {
3053 rc = ecore_get_dev_info(p_dev);
3054 if (rc != ECORE_SUCCESS)
3058 ecore_hw_hwfn_prepare(p_hwfn);
3060 /* Initialize MCP structure */
3061 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3063 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3067 /* Read the device configuration information from the HW and SHMEM */
3068 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3069 p_params->personality, p_params->drv_resc_alloc);
3071 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3075 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3076 * called, since among others it sets the ports number in an engine.
3078 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3079 !p_dev->recov_in_prog) {
3080 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3081 if (rc != ECORE_SUCCESS)
3082 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3085 /* Check if mdump logs are present and update the epoch value */
3086 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3087 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3089 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3090 DP_NOTICE(p_hwfn, false,
3091 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3094 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3098 /* Allocate the init RT array and initialize the init-ops engine */
3099 rc = ecore_init_alloc(p_hwfn);
3101 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3105 if (CHIP_REV_IS_FPGA(p_dev)) {
3106 DP_NOTICE(p_hwfn, false,
3107 "FPGA: workaround; Prevent DMAE parities\n");
3108 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3111 DP_NOTICE(p_hwfn, false,
3112 "FPGA: workaround: Set VF bar0 size\n");
3113 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3114 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3120 if (IS_LEAD_HWFN(p_hwfn))
3121 ecore_iov_free_hw_info(p_dev);
3122 ecore_mcp_free(p_hwfn);
3124 ecore_hw_hwfn_free(p_hwfn);
3129 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3130 struct ecore_hw_prepare_params *p_params)
3132 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3133 enum _ecore_status_t rc;
3135 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3137 /* Store the precompiled init data ptrs */
3139 ecore_init_iro_array(p_dev);
3141 /* Initialize the first hwfn - will learn number of hwfns */
3142 rc = ecore_hw_prepare_single(p_hwfn,
3144 p_dev->doorbells, p_params);
3145 if (rc != ECORE_SUCCESS)
3148 p_params->personality = p_hwfn->hw_info.personality;
3150 /* initilalize 2nd hwfn if necessary */
3151 if (p_dev->num_hwfns > 1) {
3152 void OSAL_IOMEM *p_regview, *p_doorbell;
3153 u8 OSAL_IOMEM *addr;
3155 /* adjust bar offset for second engine */
3156 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3157 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3158 p_regview = (void OSAL_IOMEM *)addr;
3160 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3161 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3162 p_doorbell = (void OSAL_IOMEM *)addr;
3164 /* prepare second hw function */
3165 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3166 p_doorbell, p_params);
3168 /* in case of error, need to free the previously
3169 * initiliazed hwfn 0.
3171 if (rc != ECORE_SUCCESS) {
3173 ecore_init_free(p_hwfn);
3174 ecore_mcp_free(p_hwfn);
3175 ecore_hw_hwfn_free(p_hwfn);
3177 DP_NOTICE(p_dev, true,
3178 "What do we need to free when VF hwfn1 init fails\n");
3187 void ecore_hw_remove(struct ecore_dev *p_dev)
3189 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3193 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3194 ECORE_OV_DRIVER_STATE_NOT_LOADED);
3196 for_each_hwfn(p_dev, i) {
3197 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3200 ecore_vf_pf_release(p_hwfn);
3204 ecore_init_free(p_hwfn);
3205 ecore_hw_hwfn_free(p_hwfn);
3206 ecore_mcp_free(p_hwfn);
3208 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3211 ecore_iov_free_hw_info(p_dev);
3214 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3215 struct ecore_chain *p_chain)
3217 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3218 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3219 struct ecore_chain_next *p_next;
3225 size = p_chain->elem_size * p_chain->usable_per_page;
3227 for (i = 0; i < p_chain->page_cnt; i++) {
3231 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3232 p_virt_next = p_next->next_virt;
3233 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3235 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3236 ECORE_CHAIN_PAGE_SIZE);
3238 p_virt = p_virt_next;
3239 p_phys = p_phys_next;
3243 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3244 struct ecore_chain *p_chain)
3246 if (!p_chain->p_virt_addr)
3249 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3250 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3253 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3254 struct ecore_chain *p_chain)
3256 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3257 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3258 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3260 if (!pp_virt_addr_tbl)
3263 if (!p_chain->pbl.p_virt_table)
3266 for (i = 0; i < page_cnt; i++) {
3267 if (!pp_virt_addr_tbl[i])
3270 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3271 *(dma_addr_t *)p_pbl_virt,
3272 ECORE_CHAIN_PAGE_SIZE);
3274 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3277 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3279 if (!p_chain->pbl.external)
3280 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3281 p_chain->pbl.p_phys_table, pbl_size);
3283 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3286 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3288 switch (p_chain->mode) {
3289 case ECORE_CHAIN_MODE_NEXT_PTR:
3290 ecore_chain_free_next_ptr(p_dev, p_chain);
3292 case ECORE_CHAIN_MODE_SINGLE:
3293 ecore_chain_free_single(p_dev, p_chain);
3295 case ECORE_CHAIN_MODE_PBL:
3296 ecore_chain_free_pbl(p_dev, p_chain);
3301 static enum _ecore_status_t
3302 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3303 enum ecore_chain_cnt_type cnt_type,
3304 osal_size_t elem_size, u32 page_cnt)
3306 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3308 /* The actual chain size can be larger than the maximal possible value
3309 * after rounding up the requested elements number to pages, and after
3310 * taking into acount the unusuable elements (next-ptr elements).
3311 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3312 * size/capacity fields are of a u32 type.
3314 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3315 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3316 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3317 chain_size > ECORE_U32_MAX)) {
3318 DP_NOTICE(p_dev, true,
3319 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3320 (unsigned long)chain_size);
3324 return ECORE_SUCCESS;
3327 static enum _ecore_status_t
3328 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3330 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3331 dma_addr_t p_phys = 0;
3334 for (i = 0; i < p_chain->page_cnt; i++) {
3335 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3336 ECORE_CHAIN_PAGE_SIZE);
3338 DP_NOTICE(p_dev, true,
3339 "Failed to allocate chain memory\n");
3344 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3345 ecore_chain_reset(p_chain);
3347 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3351 p_virt_prev = p_virt;
3353 /* Last page's next element should point to the beginning of the
3356 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3357 p_chain->p_virt_addr,
3358 p_chain->p_phys_addr);
3360 return ECORE_SUCCESS;
3363 static enum _ecore_status_t
3364 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3366 dma_addr_t p_phys = 0;
3367 void *p_virt = OSAL_NULL;
3369 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3371 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3375 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3376 ecore_chain_reset(p_chain);
3378 return ECORE_SUCCESS;
3381 static enum _ecore_status_t
3382 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3383 struct ecore_chain *p_chain,
3384 struct ecore_chain_ext_pbl *ext_pbl)
3386 void *p_virt = OSAL_NULL;
3387 u8 *p_pbl_virt = OSAL_NULL;
3388 void **pp_virt_addr_tbl = OSAL_NULL;
3389 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3390 u32 page_cnt = p_chain->page_cnt, size, i;
3392 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3393 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3394 if (!pp_virt_addr_tbl) {
3395 DP_NOTICE(p_dev, true,
3396 "Failed to allocate memory for the chain virtual addresses table\n");
3399 OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3401 /* The allocation of the PBL table is done with its full size, since it
3402 * is expected to be successive.
3403 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3404 * failure, since pp_virt_addr_tbl was previously allocated, and it
3405 * should be saved to allow its freeing during the error flow.
3407 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3409 if (ext_pbl == OSAL_NULL) {
3410 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3412 p_pbl_virt = ext_pbl->p_pbl_virt;
3413 p_pbl_phys = ext_pbl->p_pbl_phys;
3414 p_chain->pbl.external = true;
3417 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3420 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3424 for (i = 0; i < page_cnt; i++) {
3425 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3426 ECORE_CHAIN_PAGE_SIZE);
3428 DP_NOTICE(p_dev, true,
3429 "Failed to allocate chain memory\n");
3434 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3435 ecore_chain_reset(p_chain);
3438 /* Fill the PBL table with the physical address of the page */
3439 *(dma_addr_t *)p_pbl_virt = p_phys;
3440 /* Keep the virtual address of the page */
3441 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3443 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3446 return ECORE_SUCCESS;
3449 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3450 enum ecore_chain_use_mode intended_use,
3451 enum ecore_chain_mode mode,
3452 enum ecore_chain_cnt_type cnt_type,
3453 u32 num_elems, osal_size_t elem_size,
3454 struct ecore_chain *p_chain,
3455 struct ecore_chain_ext_pbl *ext_pbl)
3458 enum _ecore_status_t rc = ECORE_SUCCESS;
3460 if (mode == ECORE_CHAIN_MODE_SINGLE)
3463 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3465 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3468 DP_NOTICE(p_dev, true,
3469 "Cannot allocate a chain with the given arguments:\n"
3470 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3471 intended_use, mode, cnt_type, num_elems, elem_size);
3475 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3476 mode, cnt_type, p_dev->dp_ctx);
3479 case ECORE_CHAIN_MODE_NEXT_PTR:
3480 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3482 case ECORE_CHAIN_MODE_SINGLE:
3483 rc = ecore_chain_alloc_single(p_dev, p_chain);
3485 case ECORE_CHAIN_MODE_PBL:
3486 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3492 return ECORE_SUCCESS;
3495 ecore_chain_free(p_dev, p_chain);
3499 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3500 u16 src_id, u16 *dst_id)
3502 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3505 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3506 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3507 DP_NOTICE(p_hwfn, true,
3508 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3514 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3516 return ECORE_SUCCESS;
3519 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3520 u8 src_id, u8 *dst_id)
3522 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3525 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3526 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3527 DP_NOTICE(p_hwfn, true,
3528 "vport id [%d] is not valid, available indices [%d - %d]\n",
3534 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3536 return ECORE_SUCCESS;
3539 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3540 u8 src_id, u8 *dst_id)
3542 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3545 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3546 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3547 DP_NOTICE(p_hwfn, true,
3548 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3554 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3556 return ECORE_SUCCESS;
3559 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3560 struct ecore_ptt *p_ptt,
3566 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3567 return ECORE_SUCCESS;
3569 high = p_filter[1] | (p_filter[0] << 8);
3570 low = p_filter[5] | (p_filter[4] << 8) |
3571 (p_filter[3] << 16) | (p_filter[2] << 24);
3573 /* Find a free entry and utilize it */
3574 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3575 en = ecore_rd(p_hwfn, p_ptt,
3576 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3579 ecore_wr(p_hwfn, p_ptt,
3580 NIG_REG_LLH_FUNC_FILTER_VALUE +
3581 2 * i * sizeof(u32), low);
3582 ecore_wr(p_hwfn, p_ptt,
3583 NIG_REG_LLH_FUNC_FILTER_VALUE +
3584 (2 * i + 1) * sizeof(u32), high);
3585 ecore_wr(p_hwfn, p_ptt,
3586 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3587 ecore_wr(p_hwfn, p_ptt,
3588 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3589 i * sizeof(u32), 0);
3590 ecore_wr(p_hwfn, p_ptt,
3591 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3594 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3595 DP_NOTICE(p_hwfn, false,
3596 "Failed to find an empty LLH filter to utilize\n");
3600 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3601 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3602 p_filter[0], p_filter[1], p_filter[2],
3603 p_filter[3], p_filter[4], p_filter[5], i);
3605 return ECORE_SUCCESS;
3608 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3609 struct ecore_ptt *p_ptt, u8 *p_filter)
3614 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3617 high = p_filter[1] | (p_filter[0] << 8);
3618 low = p_filter[5] | (p_filter[4] << 8) |
3619 (p_filter[3] << 16) | (p_filter[2] << 24);
3621 /* Find the entry and clean it */
3622 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3623 if (ecore_rd(p_hwfn, p_ptt,
3624 NIG_REG_LLH_FUNC_FILTER_VALUE +
3625 2 * i * sizeof(u32)) != low)
3627 if (ecore_rd(p_hwfn, p_ptt,
3628 NIG_REG_LLH_FUNC_FILTER_VALUE +
3629 (2 * i + 1) * sizeof(u32)) != high)
3632 ecore_wr(p_hwfn, p_ptt,
3633 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3634 ecore_wr(p_hwfn, p_ptt,
3635 NIG_REG_LLH_FUNC_FILTER_VALUE +
3636 2 * i * sizeof(u32), 0);
3637 ecore_wr(p_hwfn, p_ptt,
3638 NIG_REG_LLH_FUNC_FILTER_VALUE +
3639 (2 * i + 1) * sizeof(u32), 0);
3642 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3643 DP_NOTICE(p_hwfn, false,
3644 "Tried to remove a non-configured filter\n");
3647 enum _ecore_status_t
3648 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3649 struct ecore_ptt *p_ptt,
3650 u16 source_port_or_eth_type,
3652 enum ecore_llh_port_filter_type_t type)
3657 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3658 return ECORE_SUCCESS;
3663 case ECORE_LLH_FILTER_ETHERTYPE:
3664 high = source_port_or_eth_type;
3666 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3667 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3668 low = source_port_or_eth_type << 16;
3670 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3671 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3674 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3675 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3676 low = (source_port_or_eth_type << 16) | dest_port;
3679 DP_NOTICE(p_hwfn, true,
3680 "Non valid LLH protocol filter type %d\n", type);
3683 /* Find a free entry and utilize it */
3684 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3685 en = ecore_rd(p_hwfn, p_ptt,
3686 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3689 ecore_wr(p_hwfn, p_ptt,
3690 NIG_REG_LLH_FUNC_FILTER_VALUE +
3691 2 * i * sizeof(u32), low);
3692 ecore_wr(p_hwfn, p_ptt,
3693 NIG_REG_LLH_FUNC_FILTER_VALUE +
3694 (2 * i + 1) * sizeof(u32), high);
3695 ecore_wr(p_hwfn, p_ptt,
3696 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3697 ecore_wr(p_hwfn, p_ptt,
3698 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3699 i * sizeof(u32), 1 << type);
3700 ecore_wr(p_hwfn, p_ptt,
3701 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3704 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3705 DP_NOTICE(p_hwfn, false,
3706 "Failed to find an empty LLH filter to utilize\n");
3707 return ECORE_NORESOURCES;
3710 case ECORE_LLH_FILTER_ETHERTYPE:
3711 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3712 "ETH type %x is added at %d\n",
3713 source_port_or_eth_type, i);
3715 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3716 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3717 "TCP src port %x is added at %d\n",
3718 source_port_or_eth_type, i);
3720 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3721 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3722 "UDP src port %x is added at %d\n",
3723 source_port_or_eth_type, i);
3725 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3726 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3727 "TCP dst port %x is added at %d\n", dest_port, i);
3729 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3730 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3731 "UDP dst port %x is added at %d\n", dest_port, i);
3733 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3734 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3735 "TCP src/dst ports %x/%x are added at %d\n",
3736 source_port_or_eth_type, dest_port, i);
3738 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3739 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3740 "UDP src/dst ports %x/%x are added at %d\n",
3741 source_port_or_eth_type, dest_port, i);
3744 return ECORE_SUCCESS;
3748 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3749 struct ecore_ptt *p_ptt,
3750 u16 source_port_or_eth_type,
3752 enum ecore_llh_port_filter_type_t type)
3757 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3763 case ECORE_LLH_FILTER_ETHERTYPE:
3764 high = source_port_or_eth_type;
3766 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3767 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3768 low = source_port_or_eth_type << 16;
3770 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3771 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3774 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3775 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3776 low = (source_port_or_eth_type << 16) | dest_port;
3779 DP_NOTICE(p_hwfn, true,
3780 "Non valid LLH protocol filter type %d\n", type);
3784 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3785 if (!ecore_rd(p_hwfn, p_ptt,
3786 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3788 if (!ecore_rd(p_hwfn, p_ptt,
3789 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3791 if (!(ecore_rd(p_hwfn, p_ptt,
3792 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3793 i * sizeof(u32)) & (1 << type)))
3795 if (ecore_rd(p_hwfn, p_ptt,
3796 NIG_REG_LLH_FUNC_FILTER_VALUE +
3797 2 * i * sizeof(u32)) != low)
3799 if (ecore_rd(p_hwfn, p_ptt,
3800 NIG_REG_LLH_FUNC_FILTER_VALUE +
3801 (2 * i + 1) * sizeof(u32)) != high)
3804 ecore_wr(p_hwfn, p_ptt,
3805 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3806 ecore_wr(p_hwfn, p_ptt,
3807 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3808 ecore_wr(p_hwfn, p_ptt,
3809 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3810 i * sizeof(u32), 0);
3811 ecore_wr(p_hwfn, p_ptt,
3812 NIG_REG_LLH_FUNC_FILTER_VALUE +
3813 2 * i * sizeof(u32), 0);
3814 ecore_wr(p_hwfn, p_ptt,
3815 NIG_REG_LLH_FUNC_FILTER_VALUE +
3816 (2 * i + 1) * sizeof(u32), 0);
3820 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3821 DP_NOTICE(p_hwfn, false,
3822 "Tried to remove a non-configured filter\n");
3825 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3826 struct ecore_ptt *p_ptt)
3830 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3833 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3834 ecore_wr(p_hwfn, p_ptt,
3835 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3836 ecore_wr(p_hwfn, p_ptt,
3837 NIG_REG_LLH_FUNC_FILTER_VALUE +
3838 2 * i * sizeof(u32), 0);
3839 ecore_wr(p_hwfn, p_ptt,
3840 NIG_REG_LLH_FUNC_FILTER_VALUE +
3841 (2 * i + 1) * sizeof(u32), 0);
3845 enum _ecore_status_t
3846 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3847 struct ecore_ptt *p_ptt)
3849 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3850 ecore_wr(p_hwfn, p_ptt,
3851 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3852 1 << p_hwfn->abs_pf_id / 2);
3853 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3854 return ECORE_SUCCESS;
3857 DP_NOTICE(p_hwfn, false,
3858 "This function can't be set as default\n");
3862 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3863 struct ecore_ptt *p_ptt,
3864 u32 hw_addr, void *p_eth_qzone,
3865 osal_size_t eth_qzone_size,
3868 struct coalescing_timeset *p_coal_timeset;
3870 if (IS_VF(p_hwfn->p_dev)) {
3871 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3875 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3876 DP_NOTICE(p_hwfn, true,
3877 "Coalescing configuration not enabled\n");
3881 p_coal_timeset = p_eth_qzone;
3882 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3883 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3884 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3885 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3887 return ECORE_SUCCESS;
3890 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3891 struct ecore_ptt *p_ptt,
3892 u16 coalesce, u16 qid, u16 sb_id)
3894 struct ustorm_eth_queue_zone eth_qzone;
3895 u8 timeset, timer_res;
3898 enum _ecore_status_t rc;
3900 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3901 if (coalesce <= 0x7F) {
3903 } else if (coalesce <= 0xFF) {
3905 } else if (coalesce <= 0x1FF) {
3908 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3911 timeset = (u8)(coalesce >> timer_res);
3913 rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
3914 if (rc != ECORE_SUCCESS)
3917 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3918 if (rc != ECORE_SUCCESS)
3921 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3923 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3924 sizeof(struct ustorm_eth_queue_zone), timeset);
3925 if (rc != ECORE_SUCCESS)
3928 p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3933 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3934 struct ecore_ptt *p_ptt,
3935 u16 coalesce, u16 qid, u16 sb_id)
3937 struct xstorm_eth_queue_zone eth_qzone;
3938 u8 timeset, timer_res;
3941 enum _ecore_status_t rc;
3943 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3944 if (coalesce <= 0x7F) {
3946 } else if (coalesce <= 0xFF) {
3948 } else if (coalesce <= 0x1FF) {
3951 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3955 timeset = (u8)(coalesce >> timer_res);
3957 rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
3958 if (rc != ECORE_SUCCESS)
3961 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3962 if (rc != ECORE_SUCCESS)
3965 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3967 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3968 sizeof(struct xstorm_eth_queue_zone), timeset);
3969 if (rc != ECORE_SUCCESS)
3972 p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3977 /* Calculate final WFQ values for all vports and configure it.
3978 * After this configuration each vport must have
3979 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3981 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3982 struct ecore_ptt *p_ptt,
3985 struct init_qm_vport_params *vport_params;
3988 vport_params = p_hwfn->qm_info.qm_vport_params;
3990 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3991 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3993 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3995 ecore_init_vport_wfq(p_hwfn, p_ptt,
3996 vport_params[i].first_tx_pq_id,
3997 vport_params[i].vport_wfq);
4002 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4006 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4007 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4010 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4011 struct ecore_ptt *p_ptt,
4014 struct init_qm_vport_params *vport_params;
4017 vport_params = p_hwfn->qm_info.qm_vport_params;
4019 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4020 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4021 ecore_init_vport_wfq(p_hwfn, p_ptt,
4022 vport_params[i].first_tx_pq_id,
4023 vport_params[i].vport_wfq);
4027 /* This function performs several validations for WFQ
4028 * configuration and required min rate for a given vport
4029 * 1. req_rate must be greater than one percent of min_pf_rate.
4030 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4031 * rates to get less than one percent of min_pf_rate.
4032 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4034 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4035 u16 vport_id, u32 req_rate,
4038 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4039 int non_requested_count = 0, req_count = 0, i, num_vports;
4041 num_vports = p_hwfn->qm_info.num_vports;
4043 /* Accounting for the vports which are configured for WFQ explicitly */
4045 for (i = 0; i < num_vports; i++) {
4048 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4050 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4051 total_req_min_rate += tmp_speed;
4055 /* Include current vport data as well */
4057 total_req_min_rate += req_rate;
4058 non_requested_count = num_vports - req_count;
4060 /* validate possible error cases */
4061 if (req_rate > min_pf_rate) {
4062 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4063 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4064 vport_id, req_rate, min_pf_rate);
4068 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4069 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4070 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4071 vport_id, req_rate, min_pf_rate);
4075 /* TBD - for number of vports greater than 100 */
4076 if (num_vports > ECORE_WFQ_UNIT) {
4077 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4078 "Number of vports is greater than %d\n",
4083 if (total_req_min_rate > min_pf_rate) {
4084 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4085 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4086 total_req_min_rate, min_pf_rate);
4090 /* Data left for non requested vports */
4091 total_left_rate = min_pf_rate - total_req_min_rate;
4092 left_rate_per_vp = total_left_rate / non_requested_count;
4094 /* validate if non requested get < 1% of min bw */
4095 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4096 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4097 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4098 left_rate_per_vp, min_pf_rate);
4102 /* now req_rate for given vport passes all scenarios.
4103 * assign final wfq rates to all vports.
4105 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4106 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4108 for (i = 0; i < num_vports; i++) {
4109 if (p_hwfn->qm_info.wfq_data[i].configured)
4112 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4115 return ECORE_SUCCESS;
4118 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4119 struct ecore_ptt *p_ptt,
4120 u16 vp_id, u32 rate)
4122 struct ecore_mcp_link_state *p_link;
4123 int rc = ECORE_SUCCESS;
4125 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4127 if (!p_link->min_pf_rate) {
4128 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4129 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4133 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4135 if (rc == ECORE_SUCCESS)
4136 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4137 p_link->min_pf_rate);
4139 DP_NOTICE(p_hwfn, false,
4140 "Validation failed while configuring min rate\n");
4145 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4146 struct ecore_ptt *p_ptt,
4149 bool use_wfq = false;
4150 int rc = ECORE_SUCCESS;
4153 /* Validate all pre configured vports for wfq */
4154 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4157 if (!p_hwfn->qm_info.wfq_data[i].configured)
4160 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4163 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4164 if (rc != ECORE_SUCCESS) {
4165 DP_NOTICE(p_hwfn, false,
4166 "WFQ validation failed while configuring min rate\n");
4171 if (rc == ECORE_SUCCESS && use_wfq)
4172 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4174 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4179 /* Main API for ecore clients to configure vport min rate.
4180 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4181 * rate - Speed in Mbps needs to be assigned to a given vport.
4183 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4185 int i, rc = ECORE_INVAL;
4187 /* TBD - for multiple hardware functions - that is 100 gig */
4188 if (p_dev->num_hwfns > 1) {
4189 DP_NOTICE(p_dev, false,
4190 "WFQ configuration is not supported for this device\n");
4194 for_each_hwfn(p_dev, i) {
4195 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4196 struct ecore_ptt *p_ptt;
4198 p_ptt = ecore_ptt_acquire(p_hwfn);
4200 return ECORE_TIMEOUT;
4202 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4204 if (rc != ECORE_SUCCESS) {
4205 ecore_ptt_release(p_hwfn, p_ptt);
4209 ecore_ptt_release(p_hwfn, p_ptt);
4215 /* API to configure WFQ from mcp link change */
4216 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4221 /* TBD - for multiple hardware functions - that is 100 gig */
4222 if (p_dev->num_hwfns > 1) {
4223 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4224 "WFQ configuration is not supported for this device\n");
4228 for_each_hwfn(p_dev, i) {
4229 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4231 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4237 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4238 struct ecore_ptt *p_ptt,
4239 struct ecore_mcp_link_state *p_link,
4242 int rc = ECORE_SUCCESS;
4244 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4246 if (!p_link->line_speed && (max_bw != 100))
4249 p_link->speed = (p_link->line_speed * max_bw) / 100;
4250 p_hwfn->qm_info.pf_rl = p_link->speed;
4252 /* Since the limiter also affects Tx-switched traffic, we don't want it
4253 * to limit such traffic in case there's no actual limit.
4254 * In that case, set limit to imaginary high boundary.
4257 p_hwfn->qm_info.pf_rl = 100000;
4259 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4260 p_hwfn->qm_info.pf_rl);
4262 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4263 "Configured MAX bandwidth to be %08x Mb/sec\n",
4269 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4270 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4272 int i, rc = ECORE_INVAL;
4274 if (max_bw < 1 || max_bw > 100) {
4275 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4279 for_each_hwfn(p_dev, i) {
4280 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4281 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4282 struct ecore_mcp_link_state *p_link;
4283 struct ecore_ptt *p_ptt;
4285 p_link = &p_lead->mcp_info->link_output;
4287 p_ptt = ecore_ptt_acquire(p_hwfn);
4289 return ECORE_TIMEOUT;
4291 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4294 ecore_ptt_release(p_hwfn, p_ptt);
4296 if (rc != ECORE_SUCCESS)
4303 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4304 struct ecore_ptt *p_ptt,
4305 struct ecore_mcp_link_state *p_link,
4308 int rc = ECORE_SUCCESS;
4310 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4311 p_hwfn->qm_info.pf_wfq = min_bw;
4313 if (!p_link->line_speed)
4316 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4318 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4320 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4321 "Configured MIN bandwidth to be %d Mb/sec\n",
4322 p_link->min_pf_rate);
4327 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4328 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4330 int i, rc = ECORE_INVAL;
4332 if (min_bw < 1 || min_bw > 100) {
4333 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4337 for_each_hwfn(p_dev, i) {
4338 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4339 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4340 struct ecore_mcp_link_state *p_link;
4341 struct ecore_ptt *p_ptt;
4343 p_link = &p_lead->mcp_info->link_output;
4345 p_ptt = ecore_ptt_acquire(p_hwfn);
4347 return ECORE_TIMEOUT;
4349 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4351 if (rc != ECORE_SUCCESS) {
4352 ecore_ptt_release(p_hwfn, p_ptt);
4356 if (p_link->min_pf_rate) {
4357 u32 min_rate = p_link->min_pf_rate;
4359 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4364 ecore_ptt_release(p_hwfn, p_ptt);
4370 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4372 struct ecore_mcp_link_state *p_link;
4374 p_link = &p_hwfn->mcp_info->link_output;
4376 if (p_link->min_pf_rate)
4377 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4378 p_link->min_pf_rate);
4380 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4381 sizeof(*p_hwfn->qm_info.wfq_data) *
4382 p_hwfn->qm_info.num_vports);
4385 int ecore_device_num_engines(struct ecore_dev *p_dev)
4387 return ECORE_IS_BB(p_dev) ? 2 : 1;
4390 int ecore_device_num_ports(struct ecore_dev *p_dev)
4392 /* in CMT always only one port */
4393 if (p_dev->num_hwfns > 1)
4396 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4399 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4404 ((u8 *)fw_msb)[0] = mac[1];
4405 ((u8 *)fw_msb)[1] = mac[0];
4406 ((u8 *)fw_mid)[0] = mac[3];
4407 ((u8 *)fw_mid)[1] = mac[2];
4408 ((u8 *)fw_lsb)[0] = mac[5];
4409 ((u8 *)fw_lsb)[1] = mac[4];