2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
36 * registers involved are not split and thus configuration is a race where
37 * some of the PFs configuration might be lost.
38 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
39 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
40 * there's more than a single compiled ecore component in system].
42 static osal_spinlock_t qm_lock;
43 static bool qm_lock_init;
45 /******************** Doorbell Recovery *******************/
46 /* The doorbell recovery mechanism consists of a list of entries which represent
47 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
48 * entity needs to register with the mechanism and provide the parameters
49 * describing it's doorbell, including a location where last used doorbell data
50 * can be found. The doorbell execute function will traverse the list and
51 * doorbell all of the registered entries.
53 struct ecore_db_recovery_entry {
54 osal_list_entry_t list_entry;
55 void OSAL_IOMEM *db_addr;
57 enum ecore_db_rec_width db_width;
58 enum ecore_db_rec_space db_space;
62 /* display a single doorbell recovery entry */
63 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
64 struct ecore_db_recovery_entry *db_entry,
67 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
68 action, db_entry, db_entry->db_addr, db_entry->db_data,
69 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
70 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
74 /* doorbell address sanity (address within doorbell bar range) */
75 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
78 /* make sure doorbell address is within the doorbell bar */
79 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
80 (u8 *)p_dev->doorbells + p_dev->db_size) {
82 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
83 db_addr, p_dev->doorbells,
84 (u8 *)p_dev->doorbells + p_dev->db_size);
88 /* make sure doorbell data pointer is not null */
90 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
97 /* find hwfn according to the doorbell address */
98 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
99 void OSAL_IOMEM *db_addr)
101 struct ecore_hwfn *p_hwfn;
103 /* In CMT doorbell bar is split down the middle between engine 0 and
106 if (ECORE_IS_CMT(p_dev))
107 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
108 &p_dev->hwfns[0] : &p_dev->hwfns[1];
110 p_hwfn = ECORE_LEADING_HWFN(p_dev);
115 /* add a new entry to the doorbell recovery mechanism */
116 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
117 void OSAL_IOMEM *db_addr,
119 enum ecore_db_rec_width db_width,
120 enum ecore_db_rec_space db_space)
122 struct ecore_db_recovery_entry *db_entry;
123 struct ecore_hwfn *p_hwfn;
125 /* shortcircuit VFs, for now */
127 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
128 return ECORE_SUCCESS;
131 /* sanitize doorbell address */
132 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
135 /* obtain hwfn from doorbell address */
136 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
139 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
141 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
146 db_entry->db_addr = db_addr;
147 db_entry->db_data = db_data;
148 db_entry->db_width = db_width;
149 db_entry->db_space = db_space;
150 db_entry->hwfn_idx = p_hwfn->my_id;
153 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
155 /* protect the list */
156 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
157 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
158 &p_hwfn->db_recovery_info.list);
159 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
161 return ECORE_SUCCESS;
164 /* remove an entry from the doorbell recovery mechanism */
165 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
166 void OSAL_IOMEM *db_addr,
169 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
170 enum _ecore_status_t rc = ECORE_INVAL;
171 struct ecore_hwfn *p_hwfn;
173 /* shortcircuit VFs, for now */
175 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
176 return ECORE_SUCCESS;
179 /* sanitize doorbell address */
180 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
183 /* obtain hwfn from doorbell address */
184 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
186 /* protect the list */
187 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
188 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
189 &p_hwfn->db_recovery_info.list,
191 struct ecore_db_recovery_entry) {
192 /* search according to db_data addr since db_addr is not unique
195 if (db_entry->db_data == db_data) {
196 ecore_db_recovery_dp_entry(p_hwfn, db_entry,
198 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
199 &p_hwfn->db_recovery_info.list);
205 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
207 if (rc == ECORE_INVAL)
209 DP_NOTICE(p_hwfn, false,
210 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
213 OSAL_FREE(p_dev, db_entry);
218 /* initialize the doorbell recovery mechanism */
219 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
221 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
223 /* make sure db_size was set in p_dev */
224 if (!p_hwfn->p_dev->db_size) {
225 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
229 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
230 #ifdef CONFIG_ECORE_LOCK_ALLOC
231 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
233 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
234 p_hwfn->db_recovery_info.db_recovery_counter = 0;
236 return ECORE_SUCCESS;
239 /* destroy the doorbell recovery mechanism */
240 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
242 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
244 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
245 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
246 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
247 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
248 db_entry = OSAL_LIST_FIRST_ENTRY(
249 &p_hwfn->db_recovery_info.list,
250 struct ecore_db_recovery_entry,
252 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
253 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
254 &p_hwfn->db_recovery_info.list);
255 OSAL_FREE(p_hwfn->p_dev, db_entry);
258 #ifdef CONFIG_ECORE_LOCK_ALLOC
259 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
261 p_hwfn->db_recovery_info.db_recovery_counter = 0;
264 /* print the content of the doorbell recovery mechanism */
265 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
267 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
269 DP_NOTICE(p_hwfn, false,
270 "Dispalying doorbell recovery database. Counter was %d\n",
271 p_hwfn->db_recovery_info.db_recovery_counter);
273 /* protect the list */
274 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
275 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
276 &p_hwfn->db_recovery_info.list,
278 struct ecore_db_recovery_entry) {
279 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
282 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
285 /* ring the doorbell of a single doorbell recovery entry */
286 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
287 struct ecore_db_recovery_entry *db_entry,
288 enum ecore_db_rec_exec db_exec)
290 /* Print according to width */
291 if (db_entry->db_width == DB_REC_WIDTH_32B)
292 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
293 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
294 db_entry->db_addr, *(u32 *)db_entry->db_data);
296 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
297 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
299 *(unsigned long *)(db_entry->db_data));
302 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
306 /* Flush the write combined buffer. Since there are multiple doorbelling
307 * entities using the same address, if we don't flush, a transaction
310 OSAL_WMB(p_hwfn->p_dev);
312 /* Ring the doorbell */
313 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
314 if (db_entry->db_width == DB_REC_WIDTH_32B)
315 DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
316 *(u32 *)(db_entry->db_data));
318 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
319 *(u64 *)(db_entry->db_data));
322 /* Flush the write combined buffer. Next doorbell may come from a
323 * different entity to the same address...
325 OSAL_WMB(p_hwfn->p_dev);
328 /* traverse the doorbell recovery entry list and ring all the doorbells */
329 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
330 enum ecore_db_rec_exec db_exec)
332 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
334 if (db_exec != DB_REC_ONCE) {
335 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
336 p_hwfn->db_recovery_info.db_recovery_counter);
338 /* track amount of times recovery was executed */
339 p_hwfn->db_recovery_info.db_recovery_counter++;
342 /* protect the list */
343 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
344 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
345 &p_hwfn->db_recovery_info.list,
347 struct ecore_db_recovery_entry) {
348 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
349 if (db_exec == DB_REC_ONCE)
353 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
355 /******************** Doorbell Recovery end ****************/
358 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
359 * load the driver. The number was
364 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
366 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
367 struct ecore_ptt *p_ptt,
370 u32 bar_reg = (bar_id == BAR_ID_0 ?
371 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
374 if (IS_VF(p_hwfn->p_dev))
375 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
377 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
379 return 1 << (val + 15);
381 /* The above registers were updated in the past only in CMT mode. Since
382 * they were found to be useful MFW started updating them from 8.7.7.0.
383 * In older MFW versions they are set to 0 which means disabled.
385 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
387 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
388 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
391 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
398 void ecore_init_dp(struct ecore_dev *p_dev,
399 u32 dp_module, u8 dp_level, void *dp_ctx)
403 p_dev->dp_level = dp_level;
404 p_dev->dp_module = dp_module;
405 p_dev->dp_ctx = dp_ctx;
406 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
407 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
409 p_hwfn->dp_level = dp_level;
410 p_hwfn->dp_module = dp_module;
411 p_hwfn->dp_ctx = dp_ctx;
415 void ecore_init_struct(struct ecore_dev *p_dev)
419 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
420 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
422 p_hwfn->p_dev = p_dev;
424 p_hwfn->b_active = false;
426 #ifdef CONFIG_ECORE_LOCK_ALLOC
427 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
429 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
432 /* hwfn 0 is always active */
433 p_dev->hwfns[0].b_active = true;
435 /* set the default cache alignment to 128 (may be overridden later) */
436 p_dev->cache_shift = 7;
439 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
441 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
443 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
444 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
445 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
446 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
449 void ecore_resc_free(struct ecore_dev *p_dev)
454 for_each_hwfn(p_dev, i)
455 ecore_l2_free(&p_dev->hwfns[i]);
459 OSAL_FREE(p_dev, p_dev->fw_data);
461 OSAL_FREE(p_dev, p_dev->reset_stats);
463 for_each_hwfn(p_dev, i) {
464 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
466 ecore_cxt_mngr_free(p_hwfn);
467 ecore_qm_info_free(p_hwfn);
468 ecore_spq_free(p_hwfn);
469 ecore_eq_free(p_hwfn);
470 ecore_consq_free(p_hwfn);
471 ecore_int_free(p_hwfn);
472 ecore_iov_free(p_hwfn);
473 ecore_l2_free(p_hwfn);
474 ecore_dmae_info_free(p_hwfn);
475 ecore_dcbx_info_free(p_hwfn);
476 /* @@@TBD Flush work-queue ? */
478 /* destroy doorbell recovery mechanism */
479 ecore_db_recovery_teardown(p_hwfn);
483 /******************** QM initialization *******************/
485 /* bitmaps for indicating active traffic classes.
486 * Special case for Arrowhead 4 port
488 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
489 #define ACTIVE_TCS_BMAP 0x9f
490 /* 0..3 actually used, OOO and high priority stuff all use 3 */
491 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
493 /* determines the physical queue flags for a given PF. */
494 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
502 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
503 flags |= PQ_FLAGS_VFS;
506 switch (p_hwfn->hw_info.personality) {
508 flags |= PQ_FLAGS_MCOS;
511 flags |= PQ_FLAGS_OFLD;
513 case ECORE_PCI_ISCSI:
514 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
516 case ECORE_PCI_ETH_ROCE:
517 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
519 case ECORE_PCI_ETH_IWARP:
520 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
524 DP_ERR(p_hwfn, "unknown personality %d\n",
525 p_hwfn->hw_info.personality);
531 /* Getters for resource amounts necessary for qm initialization */
532 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
534 return p_hwfn->hw_info.num_hw_tc;
537 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
539 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
540 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
543 #define NUM_DEFAULT_RLS 1
545 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
547 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
550 /* num RLs can't exceed resource amount of rls or vports or the
553 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
554 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
556 /* make sure after we reserve the default and VF rls we'll have
559 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
560 DP_NOTICE(p_hwfn, false,
561 "no rate limiters left for PF rate limiting"
562 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
566 /* subtract rls necessary for VFs and one default one for the PF */
567 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
572 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
574 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
576 /* all pqs share the same vport (hence the 1 below), except for vfs
579 return (!!(PQ_FLAGS_RLS & pq_flags)) *
580 ecore_init_qm_get_num_pf_rls(p_hwfn) +
581 (!!(PQ_FLAGS_VFS & pq_flags)) *
582 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
585 /* calc amount of PQs according to the requested flags */
586 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
588 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
590 return (!!(PQ_FLAGS_RLS & pq_flags)) *
591 ecore_init_qm_get_num_pf_rls(p_hwfn) +
592 (!!(PQ_FLAGS_MCOS & pq_flags)) *
593 ecore_init_qm_get_num_tcs(p_hwfn) +
594 (!!(PQ_FLAGS_LB & pq_flags)) +
595 (!!(PQ_FLAGS_OOO & pq_flags)) +
596 (!!(PQ_FLAGS_ACK & pq_flags)) +
597 (!!(PQ_FLAGS_OFLD & pq_flags)) +
598 (!!(PQ_FLAGS_VFS & pq_flags)) *
599 ecore_init_qm_get_num_vfs(p_hwfn);
602 /* initialize the top level QM params */
603 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
605 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
608 /* pq and vport bases for this PF */
609 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
610 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
612 /* rate limiting and weighted fair queueing are always enabled */
613 qm_info->vport_rl_en = 1;
614 qm_info->vport_wfq_en = 1;
616 /* TC config is different for AH 4 port */
617 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
619 /* in AH 4 port we have fewer TCs per port */
620 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
623 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
626 if (!qm_info->ooo_tc)
627 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
631 /* initialize qm vport params */
632 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
634 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
637 /* all vports participate in weighted fair queueing */
638 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
639 qm_info->qm_vport_params[i].vport_wfq = 1;
642 /* initialize qm port params */
643 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
645 /* Initialize qm port parameters */
646 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
648 /* indicate how ooo and high pri traffic is dealt with */
649 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
650 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
652 for (i = 0; i < num_ports; i++) {
653 struct init_qm_port_params *p_qm_port =
654 &p_hwfn->qm_info.qm_port_params[i];
656 p_qm_port->active = 1;
657 p_qm_port->active_phys_tcs = active_phys_tcs;
658 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
659 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
663 /* Reset the params which must be reset for qm init. QM init may be called as
664 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
665 * params may be affected by the init but would simply recalculate to the same
666 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
667 * affected as these amounts stay the same.
669 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
671 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
673 qm_info->num_pqs = 0;
674 qm_info->num_vports = 0;
675 qm_info->num_pf_rls = 0;
676 qm_info->num_vf_pqs = 0;
677 qm_info->first_vf_pq = 0;
678 qm_info->first_mcos_pq = 0;
679 qm_info->first_rl_pq = 0;
682 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
684 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
686 qm_info->num_vports++;
688 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
690 "vport overflow! qm_info->num_vports %d,"
691 " qm_init_get_num_vports() %d\n",
693 ecore_init_qm_get_num_vports(p_hwfn));
696 /* initialize a single pq and manage qm_info resources accounting.
697 * The pq_init_flags param determines whether the PQ is rate limited
699 * and whether a new vport is allocated to the pq or not (i.e. vport will be
703 /* flags for pq init */
704 #define PQ_INIT_SHARE_VPORT (1 << 0)
705 #define PQ_INIT_PF_RL (1 << 1)
706 #define PQ_INIT_VF_RL (1 << 2)
708 /* defines for pq init */
709 #define PQ_INIT_DEFAULT_WRR_GROUP 1
710 #define PQ_INIT_DEFAULT_TC 0
711 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
713 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
714 struct ecore_qm_info *qm_info,
715 u8 tc, u32 pq_init_flags)
717 u16 pq_idx = qm_info->num_pqs, max_pq =
718 ecore_init_qm_get_num_pqs(p_hwfn);
722 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
725 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
727 qm_info->qm_pq_params[pq_idx].tc_id = tc;
728 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
729 qm_info->qm_pq_params[pq_idx].rl_valid =
730 (pq_init_flags & PQ_INIT_PF_RL ||
731 pq_init_flags & PQ_INIT_VF_RL);
733 /* qm params accounting */
735 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
736 qm_info->num_vports++;
738 if (pq_init_flags & PQ_INIT_PF_RL)
739 qm_info->num_pf_rls++;
741 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
743 "vport overflow! qm_info->num_vports %d,"
744 " qm_init_get_num_vports() %d\n",
746 ecore_init_qm_get_num_vports(p_hwfn));
748 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
749 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
750 " qm_init_get_num_pf_rls() %d\n",
752 ecore_init_qm_get_num_pf_rls(p_hwfn));
755 /* get pq index according to PQ_FLAGS */
756 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
759 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
761 /* Can't have multiple flags set here */
762 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
763 sizeof(pq_flags)) > 1)
768 return &qm_info->first_rl_pq;
770 return &qm_info->first_mcos_pq;
772 return &qm_info->pure_lb_pq;
774 return &qm_info->ooo_pq;
776 return &qm_info->pure_ack_pq;
778 return &qm_info->offload_pq;
780 return &qm_info->first_vf_pq;
786 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
790 /* save pq index in qm info */
791 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
792 u32 pq_flags, u16 pq_val)
794 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
796 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
799 /* get tx pq index, with the PQ TX base already set (ready for context init) */
800 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
802 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
804 return *base_pq_idx + CM_TX_PQ_BASE;
807 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
809 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
812 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
814 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
817 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
819 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
822 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
824 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
827 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
829 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
832 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
834 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
837 /* Functions for creating specific types of pqs */
838 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
840 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
842 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
845 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
846 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
849 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
851 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
853 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
856 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
857 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
860 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
862 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
864 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
867 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
868 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
871 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
873 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
875 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
878 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
879 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
882 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
884 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
887 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
890 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
891 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
892 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
895 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
897 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
898 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
900 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
903 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
905 qm_info->num_vf_pqs = num_vfs;
906 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
907 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
911 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
913 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
914 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
916 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
919 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
920 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
921 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
925 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
927 /* rate limited pqs, must come first (FW assumption) */
928 ecore_init_qm_rl_pqs(p_hwfn);
930 /* pqs for multi cos */
931 ecore_init_qm_mcos_pqs(p_hwfn);
933 /* pure loopback pq */
934 ecore_init_qm_lb_pq(p_hwfn);
936 /* out of order pq */
937 ecore_init_qm_ooo_pq(p_hwfn);
940 ecore_init_qm_pure_ack_pq(p_hwfn);
942 /* pq for offloaded protocol */
943 ecore_init_qm_offload_pq(p_hwfn);
945 /* done sharing vports */
946 ecore_init_qm_advance_vport(p_hwfn);
949 ecore_init_qm_vf_pqs(p_hwfn);
952 /* compare values of getters against resources amounts */
953 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
955 if (ecore_init_qm_get_num_vports(p_hwfn) >
956 RESC_NUM(p_hwfn, ECORE_VPORT)) {
957 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
961 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
962 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
966 return ECORE_SUCCESS;
970 * Function for verbose printing of the qm initialization results
972 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
974 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
975 struct init_qm_vport_params *vport;
976 struct init_qm_port_params *port;
977 struct init_qm_pq_params *pq;
980 /* top level params */
981 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
982 "qm init top level params: start_pq %d, start_vport %d,"
983 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
984 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
985 qm_info->offload_pq, qm_info->pure_ack_pq);
986 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
987 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
988 " num_vports %d, max_phys_tcs_per_port %d\n",
989 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
990 qm_info->num_vf_pqs, qm_info->num_vports,
991 qm_info->max_phys_tcs_per_port);
992 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
993 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
994 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
995 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
996 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
997 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1000 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1001 port = &qm_info->qm_port_params[i];
1002 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1003 "port idx %d, active %d, active_phys_tcs %d,"
1004 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1006 i, port->active, port->active_phys_tcs,
1007 port->num_pbf_cmd_lines, port->num_btb_blocks,
1012 for (i = 0; i < qm_info->num_vports; i++) {
1013 vport = &qm_info->qm_vport_params[i];
1014 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1015 "vport idx %d, vport_rl %d, wfq %d,"
1016 " first_tx_pq_id [ ",
1017 qm_info->start_vport + i, vport->vport_rl,
1019 for (tc = 0; tc < NUM_OF_TCS; tc++)
1020 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1021 vport->first_tx_pq_id[tc]);
1022 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1026 for (i = 0; i < qm_info->num_pqs; i++) {
1027 pq = &qm_info->qm_pq_params[i];
1028 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1029 "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
1031 qm_info->start_pq + i, pq->vport_id, pq->tc_id,
1032 pq->wrr_group, pq->rl_valid);
1036 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1038 /* reset params required for init run */
1039 ecore_init_qm_reset_params(p_hwfn);
1041 /* init QM top level params */
1042 ecore_init_qm_params(p_hwfn);
1044 /* init QM port params */
1045 ecore_init_qm_port_params(p_hwfn);
1047 /* init QM vport params */
1048 ecore_init_qm_vport_params(p_hwfn);
1050 /* init QM physical queue params */
1051 ecore_init_qm_pq_params(p_hwfn);
1053 /* display all that init */
1054 ecore_dp_init_qm_params(p_hwfn);
1057 /* This function reconfigures the QM pf on the fly.
1058 * For this purpose we:
1059 * 1. reconfigure the QM database
1060 * 2. set new values to runtime array
1061 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1062 * 4. activate init tool in QM_PF stage
1063 * 5. send an sdm_qm_cmd through rbc interface to release the QM
1065 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1066 struct ecore_ptt *p_ptt)
1068 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1070 enum _ecore_status_t rc;
1072 /* initialize ecore's qm data structure */
1073 ecore_init_qm_info(p_hwfn);
1075 /* stop PF's qm queues */
1076 OSAL_SPIN_LOCK(&qm_lock);
1077 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1078 qm_info->start_pq, qm_info->num_pqs);
1079 OSAL_SPIN_UNLOCK(&qm_lock);
1083 /* clear the QM_PF runtime phase leftovers from previous init */
1084 ecore_init_clear_rt_data(p_hwfn);
1086 /* prepare QM portion of runtime array */
1087 ecore_qm_init_pf(p_hwfn, p_ptt);
1089 /* activate init tool on runtime array */
1090 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1091 p_hwfn->hw_info.hw_mode);
1092 if (rc != ECORE_SUCCESS)
1095 /* start PF's qm queues */
1096 OSAL_SPIN_LOCK(&qm_lock);
1097 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1098 qm_info->start_pq, qm_info->num_pqs);
1099 OSAL_SPIN_UNLOCK(&qm_lock);
1103 return ECORE_SUCCESS;
1106 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1108 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1109 enum _ecore_status_t rc;
1111 rc = ecore_init_qm_sanity(p_hwfn);
1112 if (rc != ECORE_SUCCESS)
1115 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1116 sizeof(struct init_qm_pq_params) *
1117 ecore_init_qm_get_num_pqs(p_hwfn));
1118 if (!qm_info->qm_pq_params)
1121 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1122 sizeof(struct init_qm_vport_params) *
1123 ecore_init_qm_get_num_vports(p_hwfn));
1124 if (!qm_info->qm_vport_params)
1127 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1128 sizeof(struct init_qm_port_params) *
1129 p_hwfn->p_dev->num_ports_in_engine);
1130 if (!qm_info->qm_port_params)
1133 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1134 sizeof(struct ecore_wfq_data) *
1135 ecore_init_qm_get_num_vports(p_hwfn));
1136 if (!qm_info->wfq_data)
1139 return ECORE_SUCCESS;
1142 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1143 ecore_qm_info_free(p_hwfn);
1146 /******************** End QM initialization ***************/
1148 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1150 enum _ecore_status_t rc = ECORE_SUCCESS;
1154 for_each_hwfn(p_dev, i) {
1155 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1156 if (rc != ECORE_SUCCESS)
1162 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1163 sizeof(*p_dev->fw_data));
1164 if (!p_dev->fw_data)
1167 for_each_hwfn(p_dev, i) {
1168 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1169 u32 n_eqes, num_cons;
1171 /* initialize the doorbell recovery mechanism */
1172 rc = ecore_db_recovery_setup(p_hwfn);
1176 /* First allocate the context manager structure */
1177 rc = ecore_cxt_mngr_alloc(p_hwfn);
1181 /* Set the HW cid/tid numbers (in the context manager)
1182 * Must be done prior to any further computations.
1184 rc = ecore_cxt_set_pf_params(p_hwfn);
1188 rc = ecore_alloc_qm_data(p_hwfn);
1193 ecore_init_qm_info(p_hwfn);
1195 /* Compute the ILT client partition */
1196 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1200 /* CID map / ILT shadow table / T2
1201 * The talbes sizes are determined by the computations above
1203 rc = ecore_cxt_tables_alloc(p_hwfn);
1207 /* SPQ, must follow ILT because initializes SPQ context */
1208 rc = ecore_spq_alloc(p_hwfn);
1212 /* SP status block allocation */
1213 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1216 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1220 rc = ecore_iov_alloc(p_hwfn);
1225 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1226 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1227 /* Calculate the EQ size
1228 * ---------------------
1229 * Each ICID may generate up to one event at a time i.e.
1230 * the event must be handled/cleared before a new one
1231 * can be generated. We calculate the sum of events per
1232 * protocol and create an EQ deep enough to handle the
1234 * - Core - according to SPQ.
1235 * - RoCE - per QP there are a couple of ICIDs, one
1236 * responder and one requester, each can
1237 * generate an EQE => n_eqes_qp = 2 * n_qp.
1238 * Each CQ can generate an EQE. There are 2 CQs
1239 * per QP => n_eqes_cq = 2 * n_qp.
1240 * Hence the RoCE total is 4 * n_qp or
1242 * - ENet - There can be up to two events per VF. One
1243 * for VF-PF channel and another for VF FLR
1244 * initial cleanup. The number of VFs is
1245 * bounded by MAX_NUM_VFS_BB, and is much
1246 * smaller than RoCE's so we avoid exact
1249 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1251 ecore_cxt_get_proto_cid_count(
1257 num_cons = ecore_cxt_get_proto_cid_count(
1262 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1263 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1265 ecore_cxt_get_proto_cid_count(p_hwfn,
1268 n_eqes += 2 * num_cons;
1271 if (n_eqes > 0xFFFF) {
1272 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1273 "The maximum of a u16 chain is 0x%x\n",
1278 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1282 rc = ecore_consq_alloc(p_hwfn);
1286 rc = ecore_l2_alloc(p_hwfn);
1287 if (rc != ECORE_SUCCESS)
1290 /* DMA info initialization */
1291 rc = ecore_dmae_info_alloc(p_hwfn);
1293 DP_NOTICE(p_hwfn, true,
1294 "Failed to allocate memory for dmae_info"
1299 /* DCBX initialization */
1300 rc = ecore_dcbx_info_alloc(p_hwfn);
1302 DP_NOTICE(p_hwfn, true,
1303 "Failed to allocate memory for dcbx structure\n");
1308 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1309 sizeof(*p_dev->reset_stats));
1310 if (!p_dev->reset_stats) {
1311 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1315 return ECORE_SUCCESS;
1320 ecore_resc_free(p_dev);
1324 void ecore_resc_setup(struct ecore_dev *p_dev)
1329 for_each_hwfn(p_dev, i)
1330 ecore_l2_setup(&p_dev->hwfns[i]);
1334 for_each_hwfn(p_dev, i) {
1335 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1337 ecore_cxt_mngr_setup(p_hwfn);
1338 ecore_spq_setup(p_hwfn);
1339 ecore_eq_setup(p_hwfn);
1340 ecore_consq_setup(p_hwfn);
1342 /* Read shadow of current MFW mailbox */
1343 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1344 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1345 p_hwfn->mcp_info->mfw_mb_cur,
1346 p_hwfn->mcp_info->mfw_mb_length);
1348 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1350 ecore_l2_setup(p_hwfn);
1351 ecore_iov_setup(p_hwfn);
1355 #define FINAL_CLEANUP_POLL_CNT (100)
1356 #define FINAL_CLEANUP_POLL_TIME (10)
1357 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1358 struct ecore_ptt *p_ptt,
1361 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1362 enum _ecore_status_t rc = ECORE_TIMEOUT;
1365 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1366 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1367 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1368 return ECORE_SUCCESS;
1372 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1373 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1378 command |= X_FINAL_CLEANUP_AGG_INT <<
1379 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1380 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1381 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1382 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1384 /* Make sure notification is not set before initiating final cleanup */
1386 if (REG_RD(p_hwfn, addr)) {
1387 DP_NOTICE(p_hwfn, false,
1388 "Unexpected; Found final cleanup notification");
1389 DP_NOTICE(p_hwfn, false,
1390 " before initiating final cleanup\n");
1391 REG_WR(p_hwfn, addr, 0);
1394 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1395 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1398 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1400 /* Poll until completion */
1401 while (!REG_RD(p_hwfn, addr) && count--)
1402 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1404 if (REG_RD(p_hwfn, addr))
1407 DP_NOTICE(p_hwfn, true,
1408 "Failed to receive FW final cleanup notification\n");
1410 /* Cleanup afterwards */
1411 REG_WR(p_hwfn, addr, 0);
1416 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1420 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1421 hw_mode |= 1 << MODE_BB;
1422 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1423 hw_mode |= 1 << MODE_K2;
1425 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1426 p_hwfn->p_dev->type);
1430 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1431 switch (p_hwfn->p_dev->num_ports_in_engine) {
1433 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1436 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1439 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1442 DP_NOTICE(p_hwfn, true,
1443 "num_ports_in_engine = %d not supported\n",
1444 p_hwfn->p_dev->num_ports_in_engine);
1448 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1449 &p_hwfn->p_dev->mf_bits))
1450 hw_mode |= 1 << MODE_MF_SD;
1452 hw_mode |= 1 << MODE_MF_SI;
1455 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1456 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1457 hw_mode |= 1 << MODE_FPGA;
1459 if (p_hwfn->p_dev->b_is_emul_full)
1460 hw_mode |= 1 << MODE_EMUL_FULL;
1462 hw_mode |= 1 << MODE_EMUL_REDUCED;
1466 hw_mode |= 1 << MODE_ASIC;
1468 if (ECORE_IS_CMT(p_hwfn->p_dev))
1469 hw_mode |= 1 << MODE_100G;
1471 p_hwfn->hw_info.hw_mode = hw_mode;
1473 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1474 "Configuring function for hw_mode: 0x%08x\n",
1475 p_hwfn->hw_info.hw_mode);
1477 return ECORE_SUCCESS;
1481 /* MFW-replacement initializations for non-ASIC */
1482 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1483 struct ecore_ptt *p_ptt)
1485 struct ecore_dev *p_dev = p_hwfn->p_dev;
1489 if (CHIP_REV_IS_EMUL(p_dev)) {
1490 if (ECORE_IS_AH(p_dev))
1494 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1496 if (CHIP_REV_IS_EMUL(p_dev) &&
1497 (ECORE_IS_AH(p_dev)))
1498 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1501 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1502 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1503 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1504 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1506 if (CHIP_REV_IS_EMUL(p_dev)) {
1507 if (ECORE_IS_AH(p_dev)) {
1508 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1509 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1510 (p_dev->num_ports_in_engine >> 1));
1512 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1513 p_dev->num_ports_in_engine == 4 ? 0 : 3);
1518 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1519 for (i = 0; i < 100; i++) {
1521 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1525 DP_NOTICE(p_hwfn, true,
1526 "RBC done failed to complete in PSWRQ2\n");
1528 return ECORE_SUCCESS;
1532 /* Init run time data for all PFs and their VFs on an engine.
1533 * TBD - for VFs - Once we have parent PF info for each VF in
1534 * shmem available as CAU requires knowledge of parent PF for each VF.
1536 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1538 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1541 for_each_hwfn(p_dev, i) {
1542 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1543 struct ecore_igu_info *p_igu_info;
1544 struct ecore_igu_block *p_block;
1545 struct cau_sb_entry sb_entry;
1547 p_igu_info = p_hwfn->hw_info.p_igu_info;
1550 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1552 p_block = &p_igu_info->entry[igu_sb_id];
1554 if (!p_block->is_pf)
1557 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1558 p_block->function_id, 0, 0);
1559 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1565 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1566 struct ecore_ptt *p_ptt)
1568 u32 val, wr_mbs, cache_line_size;
1570 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1583 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1588 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1589 switch (cache_line_size) {
1604 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1608 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1610 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1611 OSAL_CACHE_LINE_SIZE, wr_mbs);
1613 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1615 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1616 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1620 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1621 struct ecore_ptt *p_ptt,
1624 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1625 struct ecore_dev *p_dev = p_hwfn->p_dev;
1626 u8 vf_id, max_num_vfs;
1629 enum _ecore_status_t rc = ECORE_SUCCESS;
1631 ecore_init_cau_rt_data(p_dev);
1633 /* Program GTT windows */
1634 ecore_gtt_init(p_hwfn, p_ptt);
1637 if (CHIP_REV_IS_EMUL(p_dev)) {
1638 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1639 if (rc != ECORE_SUCCESS)
1644 if (p_hwfn->mcp_info) {
1645 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1646 qm_info->pf_rl_en = 1;
1647 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1648 qm_info->pf_wfq_en = 1;
1651 ecore_qm_common_rt_init(p_hwfn,
1652 p_dev->num_ports_in_engine,
1653 qm_info->max_phys_tcs_per_port,
1654 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1655 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1656 qm_info->qm_port_params);
1658 ecore_cxt_hw_init_common(p_hwfn);
1660 ecore_init_cache_line_size(p_hwfn, p_ptt);
1662 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1663 if (rc != ECORE_SUCCESS)
1666 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1667 * need to decide with which value, maybe runtime
1669 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1670 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1672 if (ECORE_IS_BB(p_dev)) {
1673 /* Workaround clears ROCE search for all functions to prevent
1674 * involving non initialized function in processing ROCE packet.
1676 num_pfs = NUM_OF_ENG_PFS(p_dev);
1677 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1678 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1679 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1680 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1682 /* pretend to original PF */
1683 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1686 /* Workaround for avoiding CCFC execution error when getting packets
1687 * with CRC errors, and allowing instead the invoking of the FW error
1689 * This is not done inside the init tool since it currently can't
1690 * perform a pretending to VFs.
1692 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1693 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1694 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1695 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1696 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1697 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1698 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1699 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1701 /* pretend to original PF */
1702 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1708 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1709 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1711 #define PMEG_IF_BYTE_COUNT 8
1713 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1714 struct ecore_ptt *p_ptt,
1715 u32 addr, u64 data, u8 reg_type, u8 port)
1717 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1718 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1719 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1720 (8 << PMEG_IF_BYTE_COUNT),
1721 (reg_type << 25) | (addr << 8) | port,
1722 (u32)((data >> 32) & 0xffffffff),
1723 (u32)(data & 0xffffffff));
1725 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1726 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1727 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1728 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1729 (reg_type << 25) | (addr << 8) | port);
1730 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1731 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1732 (data >> 32) & 0xffffffff);
1735 #define XLPORT_MODE_REG (0x20a)
1736 #define XLPORT_MAC_CONTROL (0x210)
1737 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1738 #define XLPORT_ENABLE_REG (0x20b)
1740 #define XLMAC_CTRL (0x600)
1741 #define XLMAC_MODE (0x601)
1742 #define XLMAC_RX_MAX_SIZE (0x608)
1743 #define XLMAC_TX_CTRL (0x604)
1744 #define XLMAC_PAUSE_CTRL (0x60d)
1745 #define XLMAC_PFC_CTRL (0x60e)
1747 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1748 struct ecore_ptt *p_ptt)
1750 u8 loopback = 0, port = p_hwfn->port_id * 2;
1752 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1754 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1755 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1757 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1758 /* XLMAC: SOFT RESET */
1759 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1760 /* XLMAC: Port Speed >= 10Gbps */
1761 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1762 /* XLMAC: Max Size */
1763 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1764 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1765 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1767 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1768 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1769 0x30ffffc000ULL, 0, port);
1770 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1771 port); /* XLMAC: TX_EN, RX_EN */
1772 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1773 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1774 0x1003 | (loopback << 2), 0, port);
1775 /* Enabled Parallel PFC interface */
1776 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1778 /* XLPORT port enable */
1779 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1782 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1783 struct ecore_ptt *p_ptt)
1785 u8 port = p_hwfn->port_id;
1786 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1788 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1790 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1791 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1793 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1794 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1796 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1797 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1799 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1800 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1802 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1803 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1805 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1806 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1808 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1810 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1812 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1814 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1818 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1819 struct ecore_ptt *p_ptt)
1821 if (ECORE_IS_AH(p_hwfn->p_dev))
1822 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1824 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1827 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1828 struct ecore_ptt *p_ptt, u8 port)
1830 int port_offset = port ? 0x800 : 0;
1831 u32 xmac_rxctrl = 0;
1834 /* FIXME: move to common start */
1835 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1836 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1838 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1839 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1841 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1843 /* Set the number of ports on the Warp Core to 10G */
1844 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1846 /* Soft reset of XMAC */
1847 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1848 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1850 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1851 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1853 /* FIXME: move to common end */
1854 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1855 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1857 /* Set Max packet size: initialize XMAC block register for port 0 */
1858 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1860 /* CRC append for Tx packets: init XMAC block register for port 1 */
1861 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1863 /* Enable TX and RX: initialize XMAC block register for port 1 */
1864 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1865 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1866 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1867 XMAC_REG_RX_CTRL_BB + port_offset);
1868 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1869 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1873 static enum _ecore_status_t
1874 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1875 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1877 u32 dpi_bit_shift, dpi_count, dpi_page_size;
1881 /* Calculate DPI size
1882 * ------------------
1883 * The PWM region contains Doorbell Pages. The first is reserverd for
1884 * the kernel for, e.g, L2. The others are free to be used by non-
1885 * trusted applications, typically from user space. Each page, called a
1886 * doorbell page is sectioned into windows that allow doorbells to be
1887 * issued in parallel by the kernel/application. The size of such a
1888 * window (a.k.a. WID) is 1kB.
1890 * 1kB WID x N WIDS = DPI page size
1891 * DPI page size x N DPIs = PWM region size
1893 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1894 * in order to ensure that two applications won't share the same page.
1895 * It also must contain at least one WID per CPU to allow parallelism.
1896 * It also must be a power of 2, since it is stored as a bit shift.
1898 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1899 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1900 * containing 4 WIDs.
1902 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1903 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1904 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1905 ~(OSAL_PAGE_SIZE - 1);
1906 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1907 dpi_count = pwm_region_size / dpi_page_size;
1909 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1910 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1913 p_hwfn->dpi_size = dpi_page_size;
1914 p_hwfn->dpi_count = dpi_count;
1916 /* Update registers */
1917 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1919 if (dpi_count < min_dpis)
1920 return ECORE_NORESOURCES;
1922 return ECORE_SUCCESS;
1925 enum ECORE_ROCE_EDPM_MODE {
1926 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1927 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1928 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1931 static enum _ecore_status_t
1932 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1933 struct ecore_ptt *p_ptt)
1935 u32 pwm_regsize, norm_regsize;
1936 u32 non_pwm_conn, min_addr_reg1;
1937 u32 db_bar_size, n_cpus;
1940 enum _ecore_status_t rc = ECORE_SUCCESS;
1943 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1944 if (ECORE_IS_CMT(p_hwfn->p_dev))
1947 /* Calculate doorbell regions
1948 * -----------------------------------
1949 * The doorbell BAR is made of two regions. The first is called normal
1950 * region and the second is called PWM region. In the normal region
1951 * each ICID has its own set of addresses so that writing to that
1952 * specific address identifies the ICID. In the Process Window Mode
1953 * region the ICID is given in the data written to the doorbell. The
1954 * above per PF register denotes the offset in the doorbell BAR in which
1955 * the PWM region begins.
1956 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1957 * non-PWM connection. The calculation below computes the total non-PWM
1958 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1959 * in units of 4,096 bytes.
1961 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1962 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1964 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1965 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
1967 min_addr_reg1 = norm_regsize / 4096;
1968 pwm_regsize = db_bar_size - norm_regsize;
1970 /* Check that the normal and PWM sizes are valid */
1971 if (db_bar_size < norm_regsize) {
1972 DP_ERR(p_hwfn->p_dev,
1973 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1974 db_bar_size, norm_regsize);
1975 return ECORE_NORESOURCES;
1977 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1978 DP_ERR(p_hwfn->p_dev,
1979 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1980 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1982 return ECORE_NORESOURCES;
1985 /* Calculate number of DPIs */
1986 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1987 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1988 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1989 /* Either EDPM is mandatory, or we are attempting to allocate a
1992 n_cpus = OSAL_NUM_CPUS();
1993 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1996 cond = ((rc != ECORE_SUCCESS) &&
1997 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1998 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1999 if (cond || p_hwfn->dcbx_no_edpm) {
2000 /* Either EDPM is disabled from user configuration, or it is
2001 * disabled via DCBx, or it is not mandatory and we failed to
2002 * allocated a WID per CPU.
2005 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2007 /* If we entered this flow due to DCBX then the DPM register is
2008 * already configured.
2013 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2014 norm_regsize, pwm_regsize);
2016 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2017 p_hwfn->dpi_size, p_hwfn->dpi_count,
2018 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2019 "disabled" : "enabled");
2021 /* Check return codes from above calls */
2022 if (rc != ECORE_SUCCESS) {
2024 "Failed to allocate enough DPIs\n");
2025 return ECORE_NORESOURCES;
2029 p_hwfn->dpi_start_offset = norm_regsize;
2031 /* Update registers */
2032 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2033 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2034 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2035 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2037 return ECORE_SUCCESS;
2040 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2041 struct ecore_ptt *p_ptt,
2044 u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2046 enum _ecore_status_t rc = ECORE_SUCCESS;
2049 /* In CMT for non-RoCE packets - use connection based classification */
2050 val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2051 for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2052 ppf_to_eng_sel[i] = val;
2053 STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2056 /* In CMT the gate should be cleared by the 2nd hwfn */
2057 if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2058 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2060 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2062 if (rc != ECORE_SUCCESS)
2065 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2068 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2069 return ECORE_SUCCESS;
2071 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2072 if (ECORE_IS_AH(p_hwfn->p_dev))
2073 return ECORE_SUCCESS;
2074 else if (ECORE_IS_BB(p_hwfn->p_dev))
2075 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2076 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2077 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2078 /* Activate OPTE in CMT */
2081 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2083 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2084 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2085 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2086 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2087 ecore_wr(p_hwfn, p_ptt,
2088 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2089 ecore_wr(p_hwfn, p_ptt,
2090 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2091 ecore_wr(p_hwfn, p_ptt,
2092 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2096 ecore_emul_link_init(p_hwfn, p_ptt);
2098 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2105 static enum _ecore_status_t
2106 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2107 struct ecore_ptt *p_ptt,
2108 struct ecore_tunnel_info *p_tunn,
2111 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2113 u8 rel_pf_id = p_hwfn->rel_pf_id;
2115 enum _ecore_status_t rc = ECORE_SUCCESS;
2119 if (p_hwfn->mcp_info) {
2120 struct ecore_mcp_function_info *p_info;
2122 p_info = &p_hwfn->mcp_info->func_info;
2123 if (p_info->bandwidth_min)
2124 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2126 /* Update rate limit once we'll actually have a link */
2127 p_hwfn->qm_info.pf_rl = 100000;
2129 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2131 ecore_int_igu_init_rt(p_hwfn);
2133 /* Set VLAN in NIG if needed */
2134 if (hw_mode & (1 << MODE_MF_SD)) {
2135 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2136 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2137 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2138 p_hwfn->hw_info.ovlan);
2140 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2141 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2142 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2146 /* Enable classification by MAC if needed */
2147 if (hw_mode & (1 << MODE_MF_SI)) {
2148 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2149 "Configuring TAGMAC_CLS_TYPE\n");
2150 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2154 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
2155 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2156 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2157 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2158 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2159 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2161 /* perform debug configuration when chip is out of reset */
2162 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2164 /* PF Init sequence */
2165 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2169 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2170 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2174 /* Pure runtime initializations - directly to the HW */
2175 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2177 /* PCI relaxed ordering causes a decrease in the performance on some
2178 * systems. Till a root cause is found, disable this attribute in the
2182 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2184 * DP_NOTICE(p_hwfn, true,
2185 * "Failed to find the PCIe Cap\n");
2188 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2189 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2190 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2193 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2197 /* enable interrupts */
2198 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2199 if (rc != ECORE_SUCCESS)
2202 /* send function start command */
2203 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2204 allow_npar_tx_switch);
2206 DP_NOTICE(p_hwfn, true,
2207 "Function start ramrod failed\n");
2209 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2210 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2211 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2213 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2214 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2216 ecore_wr(p_hwfn, p_ptt,
2217 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2220 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2221 "PRS_REG_SEARCH registers after start PFn\n");
2222 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2223 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2224 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2225 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2226 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2227 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2228 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2229 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2230 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2231 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2232 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2233 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2234 prs_reg = ecore_rd(p_hwfn, p_ptt,
2235 PRS_REG_SEARCH_TCP_FIRST_FRAG);
2236 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2237 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2239 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2240 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2241 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2247 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2248 struct ecore_ptt *p_ptt,
2251 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2253 /* Configure the PF's internal FID_enable for master transactions */
2254 ecore_wr(p_hwfn, p_ptt,
2255 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2257 /* Wait until value is set - try for 1 second every 50us */
2258 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2259 val = ecore_rd(p_hwfn, p_ptt,
2260 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2267 if (val != set_val) {
2268 DP_NOTICE(p_hwfn, true,
2269 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2270 return ECORE_UNKNOWN_ERROR;
2273 return ECORE_SUCCESS;
2276 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2277 struct ecore_ptt *p_main_ptt)
2279 /* Read shadow of current MFW mailbox */
2280 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2281 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2282 p_hwfn->mcp_info->mfw_mb_cur,
2283 p_hwfn->mcp_info->mfw_mb_length);
2286 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2287 struct ecore_ptt *p_ptt)
2289 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2290 1 << p_hwfn->abs_pf_id);
2294 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2295 struct ecore_drv_load_params *p_drv_load)
2297 /* Make sure that if ecore-client didn't provide inputs, all the
2298 * expected defaults are indeed zero.
2300 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2301 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2302 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2304 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2306 if (p_drv_load != OSAL_NULL) {
2307 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2308 ECORE_DRV_ROLE_KDUMP :
2310 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2311 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2312 p_load_req->override_force_load =
2313 p_drv_load->override_force_load;
2317 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2318 struct ecore_hw_init_params *p_params)
2320 if (p_params->p_tunn) {
2321 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2322 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2325 p_hwfn->b_int_enabled = 1;
2327 return ECORE_SUCCESS;
2330 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2331 struct ecore_hw_init_params *p_params)
2333 struct ecore_load_req_params load_req_params;
2334 u32 load_code, resp, param, drv_mb_param;
2335 bool b_default_mtu = true;
2336 struct ecore_hwfn *p_hwfn;
2337 enum _ecore_status_t rc = ECORE_SUCCESS;
2340 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2341 DP_NOTICE(p_dev, false,
2342 "MSI mode is not supported for CMT devices\n");
2347 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2348 if (rc != ECORE_SUCCESS)
2352 for_each_hwfn(p_dev, i) {
2353 p_hwfn = &p_dev->hwfns[i];
2355 /* If management didn't provide a default, set one of our own */
2356 if (!p_hwfn->hw_info.mtu) {
2357 p_hwfn->hw_info.mtu = 1500;
2358 b_default_mtu = false;
2362 ecore_vf_start(p_hwfn, p_params);
2366 rc = ecore_calc_hw_mode(p_hwfn);
2367 if (rc != ECORE_SUCCESS)
2370 ecore_fill_load_req_params(&load_req_params,
2371 p_params->p_drv_load_params);
2372 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2374 if (rc != ECORE_SUCCESS) {
2375 DP_NOTICE(p_hwfn, true,
2376 "Failed sending a LOAD_REQ command\n");
2380 load_code = load_req_params.load_code;
2381 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2382 "Load request was sent. Load code: 0x%x\n",
2385 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2388 * When coming back from hiberbate state, the registers from
2389 * which shadow is read initially are not initialized. It turns
2390 * out that these registers get initialized during the call to
2391 * ecore_mcp_load_req request. So we need to reread them here
2392 * to get the proper shadow register value.
2393 * Note: This is a workaround for the missing MFW
2394 * initialization. It may be removed once the implementation
2397 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2399 /* Only relevant for recovery:
2400 * Clear the indication after the LOAD_REQ command is responded
2403 p_dev->recov_in_prog = false;
2405 p_hwfn->first_on_engine = (load_code ==
2406 FW_MSG_CODE_DRV_LOAD_ENGINE);
2408 if (!qm_lock_init) {
2409 OSAL_SPIN_LOCK_INIT(&qm_lock);
2410 qm_lock_init = true;
2413 /* Clean up chip from previous driver if such remains exist.
2414 * This is not needed when the PF is the first one on the
2415 * engine, since afterwards we are going to init the FW.
2417 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2418 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2419 p_hwfn->rel_pf_id, false);
2420 if (rc != ECORE_SUCCESS) {
2421 ecore_hw_err_notify(p_hwfn,
2422 ECORE_HW_ERR_RAMROD_FAIL);
2427 /* Log and clean previous pglue_b errors if such exist */
2428 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2429 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2431 /* Enable the PF's internal FID_enable in the PXP */
2432 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2434 if (rc != ECORE_SUCCESS)
2437 switch (load_code) {
2438 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2439 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2440 p_hwfn->hw_info.hw_mode);
2441 if (rc != ECORE_SUCCESS)
2444 case FW_MSG_CODE_DRV_LOAD_PORT:
2445 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2446 p_hwfn->hw_info.hw_mode);
2447 if (rc != ECORE_SUCCESS)
2450 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2451 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2453 p_hwfn->hw_info.hw_mode,
2454 p_params->b_hw_start,
2456 p_params->allow_npar_tx_switch);
2459 DP_NOTICE(p_hwfn, false,
2460 "Unexpected load code [0x%08x]", load_code);
2465 if (rc != ECORE_SUCCESS) {
2466 DP_NOTICE(p_hwfn, true,
2467 "init phase failed for loadcode 0x%x (rc %d)\n",
2472 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2473 if (rc != ECORE_SUCCESS)
2476 /* send DCBX attention request command */
2477 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2478 "sending phony dcbx set command to trigger DCBx attention handling\n");
2479 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2480 DRV_MSG_CODE_SET_DCBX,
2481 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2483 if (rc != ECORE_SUCCESS) {
2484 DP_NOTICE(p_hwfn, true,
2485 "Failed to send DCBX attention request\n");
2489 p_hwfn->hw_init_done = true;
2493 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2494 drv_mb_param = STORM_FW_VERSION;
2495 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2496 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2497 drv_mb_param, &resp, ¶m);
2498 if (rc != ECORE_SUCCESS)
2499 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2502 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2503 p_hwfn->hw_info.mtu);
2504 if (rc != ECORE_SUCCESS)
2505 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2507 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2509 ECORE_OV_DRIVER_STATE_DISABLED);
2510 if (rc != ECORE_SUCCESS)
2511 DP_INFO(p_hwfn, "Failed to update driver state\n");
2517 /* The MFW load lock should be released regardless of success or failure
2518 * of initialization.
2519 * TODO: replace this with an attempt to send cancel_load.
2521 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2525 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2526 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2527 struct ecore_hwfn *p_hwfn,
2528 struct ecore_ptt *p_ptt)
2533 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2534 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2535 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2537 if ((!ecore_rd(p_hwfn, p_ptt,
2538 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2539 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2542 /* Dependent on number of connection/tasks, possibly
2543 * 1ms sleep is required between polls
2548 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2551 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2552 " [Connection %02x Tasks %02x]\n",
2553 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2554 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2557 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2561 for_each_hwfn(p_dev, j) {
2562 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2563 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2565 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2569 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2570 struct ecore_ptt *p_ptt,
2571 u32 addr, u32 expected_val)
2573 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2575 if (val != expected_val) {
2576 DP_NOTICE(p_hwfn, true,
2577 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2578 addr, val, expected_val);
2579 return ECORE_UNKNOWN_ERROR;
2582 return ECORE_SUCCESS;
2585 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2587 struct ecore_hwfn *p_hwfn;
2588 struct ecore_ptt *p_ptt;
2589 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2592 for_each_hwfn(p_dev, j) {
2593 p_hwfn = &p_dev->hwfns[j];
2594 p_ptt = p_hwfn->p_main_ptt;
2596 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2599 ecore_vf_pf_int_cleanup(p_hwfn);
2600 rc = ecore_vf_pf_reset(p_hwfn);
2601 if (rc != ECORE_SUCCESS) {
2602 DP_NOTICE(p_hwfn, true,
2603 "ecore_vf_pf_reset failed. rc = %d.\n",
2605 rc2 = ECORE_UNKNOWN_ERROR;
2610 /* mark the hw as uninitialized... */
2611 p_hwfn->hw_init_done = false;
2613 /* Send unload command to MCP */
2614 if (!p_dev->recov_in_prog) {
2615 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2616 if (rc != ECORE_SUCCESS) {
2617 DP_NOTICE(p_hwfn, true,
2618 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2620 rc2 = ECORE_UNKNOWN_ERROR;
2624 OSAL_DPC_SYNC(p_hwfn);
2626 /* After this point no MFW attentions are expected, e.g. prevent
2627 * race between pf stop and dcbx pf update.
2630 rc = ecore_sp_pf_stop(p_hwfn);
2631 if (rc != ECORE_SUCCESS) {
2632 DP_NOTICE(p_hwfn, true,
2633 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2635 rc2 = ECORE_UNKNOWN_ERROR;
2638 /* perform debug action after PF stop was sent */
2639 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2641 /* close NIG to BRB gate */
2642 ecore_wr(p_hwfn, p_ptt,
2643 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2646 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2647 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2648 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2649 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2650 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2652 /* @@@TBD - clean transmission queues (5.b) */
2653 /* @@@TBD - clean BTB (5.c) */
2655 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2657 /* @@@TBD - verify DMAE requests are done (8) */
2659 /* Disable Attention Generation */
2660 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2661 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2662 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2663 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2664 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2665 if (rc != ECORE_SUCCESS) {
2666 DP_NOTICE(p_hwfn, true,
2667 "Failed to return IGU CAM to default\n");
2668 rc2 = ECORE_UNKNOWN_ERROR;
2671 /* Need to wait 1ms to guarantee SBs are cleared */
2674 if (!p_dev->recov_in_prog) {
2675 ecore_verify_reg_val(p_hwfn, p_ptt,
2676 QM_REG_USG_CNT_PF_TX, 0);
2677 ecore_verify_reg_val(p_hwfn, p_ptt,
2678 QM_REG_USG_CNT_PF_OTHER, 0);
2679 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2682 /* Disable PF in HW blocks */
2683 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2684 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2686 if (!p_dev->recov_in_prog) {
2687 ecore_mcp_unload_done(p_hwfn, p_ptt);
2688 if (rc != ECORE_SUCCESS) {
2689 DP_NOTICE(p_hwfn, true,
2690 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2692 rc2 = ECORE_UNKNOWN_ERROR;
2697 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2698 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2699 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2701 /* Clear the PF's internal FID_enable in the PXP.
2702 * In CMT this should only be done for first hw-function, and
2703 * only after all transactions have stopped for all active
2706 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2708 if (rc != ECORE_SUCCESS) {
2709 DP_NOTICE(p_hwfn, true,
2710 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2712 rc2 = ECORE_UNKNOWN_ERROR;
2719 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2723 for_each_hwfn(p_dev, j) {
2724 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2725 struct ecore_ptt *p_ptt;
2728 ecore_vf_pf_int_cleanup(p_hwfn);
2731 p_ptt = ecore_ptt_acquire(p_hwfn);
2735 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2736 "Shutting down the fastpath\n");
2738 ecore_wr(p_hwfn, p_ptt,
2739 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2741 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2742 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2743 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2744 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2745 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2747 /* @@@TBD - clean transmission queues (5.b) */
2748 /* @@@TBD - clean BTB (5.c) */
2750 /* @@@TBD - verify DMAE requests are done (8) */
2752 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2753 /* Need to wait 1ms to guarantee SBs are cleared */
2755 ecore_ptt_release(p_hwfn, p_ptt);
2758 return ECORE_SUCCESS;
2761 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2763 struct ecore_ptt *p_ptt;
2765 if (IS_VF(p_hwfn->p_dev))
2766 return ECORE_SUCCESS;
2768 p_ptt = ecore_ptt_acquire(p_hwfn);
2772 /* If roce info is allocated it means roce is initialized and should
2773 * be enabled in searcher.
2775 if (p_hwfn->p_rdma_info) {
2776 if (p_hwfn->b_rdma_enabled_in_prs)
2777 ecore_wr(p_hwfn, p_ptt,
2778 p_hwfn->rdma_prs_search_reg, 0x1);
2779 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2782 /* Re-open incoming traffic */
2783 ecore_wr(p_hwfn, p_ptt,
2784 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2785 ecore_ptt_release(p_hwfn, p_ptt);
2787 return ECORE_SUCCESS;
2790 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2791 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2793 ecore_ptt_pool_free(p_hwfn);
2794 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2797 /* Setup bar access */
2798 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2800 /* clear indirect access */
2801 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2802 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2803 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2804 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2805 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2806 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2807 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2808 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2809 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2811 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2812 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2813 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2814 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2815 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2816 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2817 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2818 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2821 /* Clean previous pglue_b errors if such exist */
2822 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2824 /* enable internal target-read */
2825 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2826 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2829 static void get_function_id(struct ecore_hwfn *p_hwfn)
2832 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2833 PXP_PF_ME_OPAQUE_ADDR);
2835 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2837 /* Bits 16-19 from the ME registers are the pf_num */
2838 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2839 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2840 PXP_CONCRETE_FID_PFID);
2841 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2842 PXP_CONCRETE_FID_PORT);
2844 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2845 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2846 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2849 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2851 u32 *feat_num = p_hwfn->hw_info.feat_num;
2852 struct ecore_sb_cnt_info sb_cnt;
2855 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2856 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2858 /* L2 Queues require each: 1 status block. 1 L2 queue */
2859 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2860 /* Start by allocating VF queues, then PF's */
2861 feat_num[ECORE_VF_L2_QUE] =
2863 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2865 feat_num[ECORE_PF_L2_QUE] =
2867 sb_cnt.cnt - non_l2_sbs,
2868 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2869 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2872 feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2875 feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2879 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2880 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2881 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2882 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2883 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2884 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2885 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2889 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2892 case ECORE_L2_QUEUE:
2906 case ECORE_RDMA_CNQ_RAM:
2907 return "RDMA_CNQ_RAM";
2910 case ECORE_LL2_QUEUE:
2912 case ECORE_CMDQS_CQS:
2914 case ECORE_RDMA_STATS_QUEUE:
2915 return "RDMA_STATS_QUEUE";
2921 return "UNKNOWN_RESOURCE";
2925 static enum _ecore_status_t
2926 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2927 struct ecore_ptt *p_ptt,
2928 enum ecore_resources res_id,
2932 enum _ecore_status_t rc;
2934 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2935 resc_max_val, p_mcp_resp);
2936 if (rc != ECORE_SUCCESS) {
2937 DP_NOTICE(p_hwfn, true,
2938 "MFW response failure for a max value setting of resource %d [%s]\n",
2939 res_id, ecore_hw_get_resc_name(res_id));
2943 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2945 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2946 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2948 return ECORE_SUCCESS;
2951 static enum _ecore_status_t
2952 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2953 struct ecore_ptt *p_ptt)
2955 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2956 u32 resc_max_val, mcp_resp;
2958 enum _ecore_status_t rc;
2960 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2963 case ECORE_LL2_QUEUE:
2964 case ECORE_RDMA_CNQ_RAM:
2965 case ECORE_RDMA_STATS_QUEUE:
2973 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2974 resc_max_val, &mcp_resp);
2975 if (rc != ECORE_SUCCESS)
2978 /* There's no point to continue to the next resource if the
2979 * command is not supported by the MFW.
2980 * We do continue if the command is supported but the resource
2981 * is unknown to the MFW. Such a resource will be later
2982 * configured with the default allocation values.
2984 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2985 return ECORE_NOTIMPL;
2988 return ECORE_SUCCESS;
2992 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2993 enum ecore_resources res_id,
2994 u32 *p_resc_num, u32 *p_resc_start)
2996 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2997 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3000 case ECORE_L2_QUEUE:
3001 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3002 MAX_NUM_L2_QUEUES_BB) / num_funcs;
3005 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3006 MAX_NUM_VPORTS_BB) / num_funcs;
3009 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3010 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3013 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3014 MAX_QM_TX_QUEUES_BB) / num_funcs;
3017 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3021 /* Each VFC resource can accommodate both a MAC and a VLAN */
3022 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3025 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3026 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3028 case ECORE_LL2_QUEUE:
3029 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3031 case ECORE_RDMA_CNQ_RAM:
3032 case ECORE_CMDQS_CQS:
3033 /* CNQ/CMDQS are the same resource */
3035 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3037 case ECORE_RDMA_STATS_QUEUE:
3039 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3040 MAX_NUM_VPORTS_BB) / num_funcs;
3057 /* Since we want its value to reflect whether MFW supports
3058 * the new scheme, have a default of 0.
3063 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3067 return ECORE_SUCCESS;
3070 static enum _ecore_status_t
3071 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3072 bool drv_resc_alloc)
3074 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3075 u32 mcp_resp, *p_resc_num, *p_resc_start;
3076 enum _ecore_status_t rc;
3078 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3079 p_resc_start = &RESC_START(p_hwfn, res_id);
3081 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3083 if (rc != ECORE_SUCCESS) {
3085 "Failed to get default amount for resource %d [%s]\n",
3086 res_id, ecore_hw_get_resc_name(res_id));
3091 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3092 *p_resc_num = dflt_resc_num;
3093 *p_resc_start = dflt_resc_start;
3098 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3099 &mcp_resp, p_resc_num, p_resc_start);
3100 if (rc != ECORE_SUCCESS) {
3101 DP_NOTICE(p_hwfn, true,
3102 "MFW response failure for an allocation request for"
3103 " resource %d [%s]\n",
3104 res_id, ecore_hw_get_resc_name(res_id));
3108 /* Default driver values are applied in the following cases:
3109 * - The resource allocation MB command is not supported by the MFW
3110 * - There is an internal error in the MFW while processing the request
3111 * - The resource ID is unknown to the MFW
3113 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3115 "Failed to receive allocation info for resource %d [%s]."
3116 " mcp_resp = 0x%x. Applying default values"
3118 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3119 dflt_resc_num, dflt_resc_start);
3121 *p_resc_num = dflt_resc_num;
3122 *p_resc_start = dflt_resc_start;
3126 if ((*p_resc_num != dflt_resc_num ||
3127 *p_resc_start != dflt_resc_start) &&
3128 res_id != ECORE_SB) {
3130 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3131 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3132 *p_resc_start, dflt_resc_num, dflt_resc_start,
3133 drv_resc_alloc ? " - Applying default values" : "");
3134 if (drv_resc_alloc) {
3135 *p_resc_num = dflt_resc_num;
3136 *p_resc_start = dflt_resc_start;
3140 return ECORE_SUCCESS;
3143 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3144 bool drv_resc_alloc)
3146 enum _ecore_status_t rc;
3149 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3150 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3151 if (rc != ECORE_SUCCESS)
3155 return ECORE_SUCCESS;
3158 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3159 struct ecore_ptt *p_ptt,
3160 bool drv_resc_alloc)
3162 struct ecore_resc_unlock_params resc_unlock_params;
3163 struct ecore_resc_lock_params resc_lock_params;
3164 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3166 enum _ecore_status_t rc;
3168 u32 *resc_start = p_hwfn->hw_info.resc_start;
3169 u32 *resc_num = p_hwfn->hw_info.resc_num;
3170 /* For AH, an equal share of the ILT lines between the maximal number of
3171 * PFs is not enough for RoCE. This would be solved by the future
3172 * resource allocation scheme, but isn't currently present for
3173 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3174 * to work - the BB number of ILT lines divided by its max PFs number.
3176 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3179 /* Setting the max values of the soft resources and the following
3180 * resources allocation queries should be atomic. Since several PFs can
3181 * run in parallel - a resource lock is needed.
3182 * If either the resource lock or resource set value commands are not
3183 * supported - skip the the max values setting, release the lock if
3184 * needed, and proceed to the queries. Other failures, including a
3185 * failure to acquire the lock, will cause this function to fail.
3186 * Old drivers that don't acquire the lock can run in parallel, and
3187 * their allocation values won't be affected by the updated max values.
3189 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3190 ECORE_RESC_LOCK_RESC_ALLOC, false);
3192 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3193 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3195 } else if (rc == ECORE_NOTIMPL) {
3197 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3198 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3199 DP_NOTICE(p_hwfn, false,
3200 "Failed to acquire the resource lock for the resource allocation commands\n");
3202 goto unlock_and_exit;
3204 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3205 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3206 DP_NOTICE(p_hwfn, false,
3207 "Failed to set the max values of the soft resources\n");
3208 goto unlock_and_exit;
3209 } else if (rc == ECORE_NOTIMPL) {
3211 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3212 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3213 &resc_unlock_params);
3214 if (rc != ECORE_SUCCESS)
3216 "Failed to release the resource lock for the resource allocation commands\n");
3220 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3221 if (rc != ECORE_SUCCESS)
3222 goto unlock_and_exit;
3224 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3225 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3226 &resc_unlock_params);
3227 if (rc != ECORE_SUCCESS)
3229 "Failed to release the resource lock for the resource allocation commands\n");
3233 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3234 /* Reduced build contains less PQs */
3235 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3236 resc_num[ECORE_PQ] = 32;
3237 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3238 p_hwfn->enabled_func_idx;
3241 /* For AH emulation, since we have a possible maximal number of
3242 * 16 enabled PFs, in case there are not enough ILT lines -
3243 * allocate only first PF as RoCE and have all the other ETH
3244 * only with less ILT lines.
3246 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3247 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3248 resc_num[ECORE_ILT],
3249 roce_min_ilt_lines);
3252 /* Correct the common ILT calculation if PF0 has more */
3253 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3254 p_hwfn->p_dev->b_is_emul_full &&
3255 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3256 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3257 resc_num[ECORE_ILT];
3260 /* Sanity for ILT */
3261 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3262 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3263 DP_NOTICE(p_hwfn, true,
3264 "Can't assign ILT pages [%08x,...,%08x]\n",
3265 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3271 /* This will also learn the number of SBs from MFW */
3272 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3275 ecore_hw_set_feat(p_hwfn);
3277 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3278 "The numbers for each resource are:\n");
3279 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3280 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3281 ecore_hw_get_resc_name(res_id),
3282 RESC_NUM(p_hwfn, res_id),
3283 RESC_START(p_hwfn, res_id));
3285 return ECORE_SUCCESS;
3288 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3289 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3290 &resc_unlock_params);
3294 static enum _ecore_status_t
3295 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3296 struct ecore_ptt *p_ptt,
3297 struct ecore_hw_prepare_params *p_params)
3299 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3300 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3301 struct ecore_mcp_link_capabilities *p_caps;
3302 struct ecore_mcp_link_params *link;
3303 enum _ecore_status_t rc;
3305 /* Read global nvm_cfg address */
3306 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3308 /* Verify MCP has initialized it */
3309 if (!nvm_cfg_addr) {
3310 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3311 if (p_params->b_relaxed_probe)
3312 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3316 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
3318 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3320 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3321 OFFSETOF(struct nvm_cfg1, glob) +
3322 OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3324 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3326 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3327 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3328 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3329 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3331 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3332 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3334 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3335 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3337 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3338 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3340 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3341 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3343 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3344 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3346 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3347 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3349 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3350 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3352 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3353 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3355 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3356 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3358 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3359 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3362 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3367 /* Read DCBX configuration */
3368 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3369 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3370 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3372 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3373 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3374 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3375 switch (dcbx_mode) {
3376 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3377 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3379 case NVM_CFG1_PORT_DCBX_MODE_CEE:
3380 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3382 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3383 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3386 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3389 /* Read default link configuration */
3390 link = &p_hwfn->mcp_info->link_input;
3391 p_caps = &p_hwfn->mcp_info->link_capabilities;
3392 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3393 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3394 link_temp = ecore_rd(p_hwfn, p_ptt,
3396 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3397 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3398 link->speed.advertised_speeds = link_temp;
3399 p_caps->speed_capabilities = link->speed.advertised_speeds;
3401 link_temp = ecore_rd(p_hwfn, p_ptt,
3403 OFFSETOF(struct nvm_cfg1_port, link_settings));
3404 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3405 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3406 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3407 link->speed.autoneg = true;
3409 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3410 link->speed.forced_speed = 1000;
3412 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3413 link->speed.forced_speed = 10000;
3415 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3416 link->speed.forced_speed = 25000;
3418 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3419 link->speed.forced_speed = 40000;
3421 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3422 link->speed.forced_speed = 50000;
3424 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3425 link->speed.forced_speed = 100000;
3428 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3431 p_caps->default_speed = link->speed.forced_speed;
3432 p_caps->default_speed_autoneg = link->speed.autoneg;
3434 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3435 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3436 link->pause.autoneg = !!(link_temp &
3437 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3438 link->pause.forced_rx = !!(link_temp &
3439 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3440 link->pause.forced_tx = !!(link_temp &
3441 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3442 link->loopback_mode = 0;
3444 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3445 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3446 OFFSETOF(struct nvm_cfg1_port, ext_phy));
3447 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3448 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3449 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3450 link->eee.enable = true;
3451 switch (link_temp) {
3452 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3453 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3454 link->eee.enable = false;
3456 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3457 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3459 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3460 p_caps->eee_lpi_timer =
3461 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3463 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3464 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3468 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3469 link->eee.tx_lpi_enable = link->eee.enable;
3470 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3472 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3475 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3476 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3477 link->speed.forced_speed, link->speed.advertised_speeds,
3478 link->speed.autoneg, link->pause.autoneg,
3479 p_caps->default_eee, p_caps->eee_lpi_timer);
3481 /* Read Multi-function information from shmem */
3482 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3483 OFFSETOF(struct nvm_cfg1, glob) +
3484 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3486 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3488 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3489 NVM_CFG1_GLOB_MF_MODE_OFFSET;
3492 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3493 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3495 case NVM_CFG1_GLOB_MF_MODE_UFP:
3496 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3497 1 << ECORE_MF_UFP_SPECIFIC;
3500 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3501 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3502 1 << ECORE_MF_LLH_PROTO_CLSS |
3503 1 << ECORE_MF_LL2_NON_UNICAST |
3504 1 << ECORE_MF_INTER_PF_SWITCH |
3505 1 << ECORE_MF_DISABLE_ARFS;
3507 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3508 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3509 1 << ECORE_MF_LLH_PROTO_CLSS |
3510 1 << ECORE_MF_LL2_NON_UNICAST;
3511 if (ECORE_IS_BB(p_hwfn->p_dev))
3512 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3515 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3516 p_hwfn->p_dev->mf_bits);
3518 if (ECORE_IS_CMT(p_hwfn->p_dev))
3519 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3521 /* It's funny since we have another switch, but it's easier
3522 * to throw this away in linux this way. Long term, it might be
3523 * better to have have getters for needed ECORE_MF_* fields,
3524 * convert client code and eliminate this.
3527 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3528 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3530 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3531 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3533 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3534 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3536 case NVM_CFG1_GLOB_MF_MODE_UFP:
3537 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3541 /* Read Multi-function information from shmem */
3542 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3543 OFFSETOF(struct nvm_cfg1, glob) +
3544 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3546 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3547 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3548 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3549 &p_hwfn->hw_info.device_capabilities);
3550 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3551 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3552 &p_hwfn->hw_info.device_capabilities);
3553 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3554 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3555 &p_hwfn->hw_info.device_capabilities);
3556 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3557 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3558 &p_hwfn->hw_info.device_capabilities);
3559 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3560 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3561 &p_hwfn->hw_info.device_capabilities);
3563 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3564 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3566 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3572 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3573 struct ecore_ptt *p_ptt)
3575 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3576 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3577 struct ecore_dev *p_dev = p_hwfn->p_dev;
3579 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3581 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3582 * in the other bits are selected.
3583 * Bits 1-15 are for functions 1-15, respectively, and their value is
3584 * '0' only for enabled functions (function 0 always exists and
3586 * In case of CMT in BB, only the "even" functions are enabled, and thus
3587 * the number of functions for both hwfns is learnt from the same bits.
3589 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3590 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3591 MISCS_REG_FUNCTION_HIDE_BB_K2);
3593 reg_function_hide = 0;
3596 if (reg_function_hide & 0x1) {
3597 if (ECORE_IS_BB(p_dev)) {
3598 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3610 /* Get the number of the enabled functions on the engine */
3611 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3618 /* Get the PF index within the enabled functions */
3619 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3620 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3628 p_hwfn->num_funcs_on_engine = num_funcs;
3629 p_hwfn->enabled_func_idx = enabled_func_idx;
3632 if (CHIP_REV_IS_FPGA(p_dev)) {
3633 DP_NOTICE(p_hwfn, false,
3634 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3635 p_hwfn->num_funcs_on_engine = 4;
3639 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3640 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3641 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3642 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3645 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3646 struct ecore_ptt *p_ptt)
3648 struct ecore_dev *p_dev = p_hwfn->p_dev;
3652 /* Read the port mode */
3653 if (CHIP_REV_IS_FPGA(p_dev))
3655 else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3656 /* In CMT on emulation, assume 1 port */
3660 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3662 if (port_mode < 3) {
3663 p_dev->num_ports_in_engine = 1;
3664 } else if (port_mode <= 5) {
3665 p_dev->num_ports_in_engine = 2;
3667 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3668 p_dev->num_ports_in_engine);
3670 /* Default num_ports_in_engine to something */
3671 p_dev->num_ports_in_engine = 1;
3675 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3676 struct ecore_ptt *p_ptt)
3678 struct ecore_dev *p_dev = p_hwfn->p_dev;
3682 p_dev->num_ports_in_engine = 0;
3685 if (CHIP_REV_IS_EMUL(p_dev)) {
3686 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3687 switch ((port & 0xf000) >> 12) {
3689 p_dev->num_ports_in_engine = 1;
3692 p_dev->num_ports_in_engine = 2;
3695 p_dev->num_ports_in_engine = 4;
3698 DP_NOTICE(p_hwfn, false,
3699 "Unknown port mode in ECO_RESERVED %08x\n",
3704 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3705 port = ecore_rd(p_hwfn, p_ptt,
3706 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3709 p_dev->num_ports_in_engine++;
3712 if (!p_dev->num_ports_in_engine) {
3713 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3715 /* Default num_ports_in_engine to something */
3716 p_dev->num_ports_in_engine = 1;
3720 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3721 struct ecore_ptt *p_ptt)
3723 struct ecore_dev *p_dev = p_hwfn->p_dev;
3725 /* Determine the number of ports per engine */
3726 if (ECORE_IS_BB(p_dev))
3727 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3729 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3731 /* Get the total number of ports of the device */
3732 if (ECORE_IS_CMT(p_dev)) {
3733 /* In CMT there is always only one port */
3734 p_dev->num_ports = 1;
3736 } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3737 p_dev->num_ports = p_dev->num_ports_in_engine *
3738 ecore_device_num_engines(p_dev);
3741 u32 addr, global_offsize, global_addr;
3743 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3745 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3746 global_addr = SECTION_ADDR(global_offsize, 0);
3747 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3748 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3752 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3753 struct ecore_ptt *p_ptt)
3755 struct ecore_mcp_link_capabilities *p_caps;
3758 p_caps = &p_hwfn->mcp_info->link_capabilities;
3759 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3762 p_caps->eee_speed_caps = 0;
3763 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3764 OFFSETOF(struct public_port, eee_status));
3765 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3766 EEE_SUPPORTED_SPEED_OFFSET;
3767 if (eee_status & EEE_1G_SUPPORTED)
3768 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3769 if (eee_status & EEE_10G_ADV)
3770 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3773 static enum _ecore_status_t
3774 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3775 enum ecore_pci_personality personality,
3776 struct ecore_hw_prepare_params *p_params)
3778 bool drv_resc_alloc = p_params->drv_resc_alloc;
3779 enum _ecore_status_t rc;
3781 /* Since all information is common, only first hwfns should do this */
3782 if (IS_LEAD_HWFN(p_hwfn)) {
3783 rc = ecore_iov_hw_info(p_hwfn);
3784 if (rc != ECORE_SUCCESS) {
3785 if (p_params->b_relaxed_probe)
3786 p_params->p_relaxed_res =
3787 ECORE_HW_PREPARE_BAD_IOV;
3793 if (IS_LEAD_HWFN(p_hwfn))
3794 ecore_hw_info_port_num(p_hwfn, p_ptt);
3796 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3799 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3801 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3802 if (rc != ECORE_SUCCESS)
3808 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3809 if (rc != ECORE_SUCCESS) {
3810 if (p_params->b_relaxed_probe)
3811 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3817 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3819 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3820 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3823 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3825 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3826 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3830 if (ecore_mcp_is_init(p_hwfn)) {
3831 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3832 p_hwfn->hw_info.ovlan =
3833 p_hwfn->mcp_info->func_info.ovlan;
3835 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3837 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3839 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
3842 if (personality != ECORE_PCI_DEFAULT) {
3843 p_hwfn->hw_info.personality = personality;
3844 } else if (ecore_mcp_is_init(p_hwfn)) {
3845 enum ecore_pci_personality protocol;
3847 protocol = p_hwfn->mcp_info->func_info.protocol;
3848 p_hwfn->hw_info.personality = protocol;
3852 /* To overcome ILT lack for emulation, until at least until we'll have
3853 * a definite answer from system about it, allow only PF0 to be RoCE.
3855 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3856 if (!p_hwfn->rel_pf_id)
3857 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3859 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3863 /* although in BB some constellations may support more than 4 tcs,
3864 * that can result in performance penalty in some cases. 4
3865 * represents a good tradeoff between performance and flexibility.
3867 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3869 /* start out with a single active tc. This can be increased either
3870 * by dcbx negotiation or by upper layer driver
3872 p_hwfn->hw_info.num_active_tc = 1;
3874 ecore_get_num_funcs(p_hwfn, p_ptt);
3876 if (ecore_mcp_is_init(p_hwfn))
3877 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3879 /* In case of forcing the driver's default resource allocation, calling
3880 * ecore_hw_get_resc() should come after initializing the personality
3881 * and after getting the number of functions, since the calculation of
3882 * the resources/features depends on them.
3883 * This order is not harmful if not forcing.
3885 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3886 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3888 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3894 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3895 struct ecore_ptt *p_ptt)
3897 struct ecore_dev *p_dev = p_hwfn->p_dev;
3901 /* Read Vendor Id / Device Id */
3902 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3904 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3907 /* Determine type */
3908 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3909 switch (device_id_mask) {
3910 case ECORE_DEV_ID_MASK_BB:
3911 p_dev->type = ECORE_DEV_TYPE_BB;
3913 case ECORE_DEV_ID_MASK_AH:
3914 p_dev->type = ECORE_DEV_TYPE_AH;
3917 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3919 return ECORE_ABORTED;
3922 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3923 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
3924 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3925 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
3927 /* Learn number of HW-functions */
3928 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3930 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3931 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3932 p_dev->num_hwfns = 2;
3934 p_dev->num_hwfns = 1;
3938 if (CHIP_REV_IS_EMUL(p_dev)) {
3939 /* For some reason we have problems with this register
3940 * in B0 emulation; Simply assume no CMT
3942 DP_NOTICE(p_dev->hwfns, false,
3943 "device on emul - assume no CMT\n");
3944 p_dev->num_hwfns = 1;
3948 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
3949 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
3950 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3951 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
3953 DP_INFO(p_dev->hwfns,
3954 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
3955 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3956 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3957 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3960 if (ECORE_IS_BB_A0(p_dev)) {
3961 DP_NOTICE(p_dev->hwfns, false,
3962 "The chip type/rev (BB A0) is not supported!\n");
3963 return ECORE_ABORTED;
3966 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3967 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3969 if (CHIP_REV_IS_EMUL(p_dev)) {
3970 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3971 if (tmp & (1 << 29)) {
3972 DP_NOTICE(p_hwfn, false,
3973 "Emulation: Running on a FULL build\n");
3974 p_dev->b_is_emul_full = true;
3976 DP_NOTICE(p_hwfn, false,
3977 "Emulation: Running on a REDUCED build\n");
3982 return ECORE_SUCCESS;
3985 #ifndef LINUX_REMOVE
3986 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3993 for_each_hwfn(p_dev, j) {
3994 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3996 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3997 "Mark hw/fw uninitialized\n");
3999 p_hwfn->hw_init_done = false;
4001 ecore_ptt_invalidate(p_hwfn);
4006 static enum _ecore_status_t
4007 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4008 void OSAL_IOMEM * p_regview,
4009 void OSAL_IOMEM * p_doorbells,
4010 struct ecore_hw_prepare_params *p_params)
4012 struct ecore_mdump_retain_data mdump_retain;
4013 struct ecore_dev *p_dev = p_hwfn->p_dev;
4014 struct ecore_mdump_info mdump_info;
4015 enum _ecore_status_t rc = ECORE_SUCCESS;
4017 /* Split PCI bars evenly between hwfns */
4018 p_hwfn->regview = p_regview;
4019 p_hwfn->doorbells = p_doorbells;
4022 return ecore_vf_hw_prepare(p_hwfn);
4024 /* Validate that chip access is feasible */
4025 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4027 "Reading the ME register returns all Fs; Preventing further chip access\n");
4028 if (p_params->b_relaxed_probe)
4029 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4033 get_function_id(p_hwfn);
4035 /* Allocate PTT pool */
4036 rc = ecore_ptt_pool_alloc(p_hwfn);
4038 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
4039 if (p_params->b_relaxed_probe)
4040 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4044 /* Allocate the main PTT */
4045 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4047 /* First hwfn learns basic information, e.g., number of hwfns */
4048 if (!p_hwfn->my_id) {
4049 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4050 if (rc != ECORE_SUCCESS) {
4051 if (p_params->b_relaxed_probe)
4052 p_params->p_relaxed_res =
4053 ECORE_HW_PREPARE_FAILED_DEV;
4058 ecore_hw_hwfn_prepare(p_hwfn);
4060 /* Initialize MCP structure */
4061 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4063 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
4064 if (p_params->b_relaxed_probe)
4065 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4069 /* Read the device configuration information from the HW and SHMEM */
4070 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4071 p_params->personality, p_params);
4073 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
4077 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4078 * called, since among others it sets the ports number in an engine.
4080 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4081 !p_dev->recov_in_prog) {
4082 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4083 if (rc != ECORE_SUCCESS)
4084 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4087 /* Check if mdump logs/data are present and update the epoch value */
4088 if (IS_LEAD_HWFN(p_hwfn)) {
4090 if (!CHIP_REV_IS_EMUL(p_dev)) {
4092 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4094 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4095 DP_NOTICE(p_hwfn, false,
4096 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4098 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4100 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4101 DP_NOTICE(p_hwfn, false,
4102 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4103 mdump_retain.epoch, mdump_retain.pf,
4104 mdump_retain.status);
4106 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4113 /* Allocate the init RT array and initialize the init-ops engine */
4114 rc = ecore_init_alloc(p_hwfn);
4116 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
4117 if (p_params->b_relaxed_probe)
4118 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4122 if (CHIP_REV_IS_FPGA(p_dev)) {
4123 DP_NOTICE(p_hwfn, false,
4124 "FPGA: workaround; Prevent DMAE parities\n");
4125 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4128 DP_NOTICE(p_hwfn, false,
4129 "FPGA: workaround: Set VF bar0 size\n");
4130 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4131 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4137 if (IS_LEAD_HWFN(p_hwfn))
4138 ecore_iov_free_hw_info(p_dev);
4139 ecore_mcp_free(p_hwfn);
4141 ecore_hw_hwfn_free(p_hwfn);
4146 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4147 struct ecore_hw_prepare_params *p_params)
4149 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4150 enum _ecore_status_t rc;
4152 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4153 p_dev->allow_mdump = p_params->allow_mdump;
4155 if (p_params->b_relaxed_probe)
4156 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4158 /* Store the precompiled init data ptrs */
4160 ecore_init_iro_array(p_dev);
4162 /* Initialize the first hwfn - will learn number of hwfns */
4163 rc = ecore_hw_prepare_single(p_hwfn,
4165 p_dev->doorbells, p_params);
4166 if (rc != ECORE_SUCCESS)
4169 p_params->personality = p_hwfn->hw_info.personality;
4171 /* initilalize 2nd hwfn if necessary */
4172 if (ECORE_IS_CMT(p_dev)) {
4173 void OSAL_IOMEM *p_regview, *p_doorbell;
4174 u8 OSAL_IOMEM *addr;
4176 /* adjust bar offset for second engine */
4177 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4178 ecore_hw_bar_size(p_hwfn,
4181 p_regview = (void OSAL_IOMEM *)addr;
4183 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4184 ecore_hw_bar_size(p_hwfn,
4187 p_doorbell = (void OSAL_IOMEM *)addr;
4189 /* prepare second hw function */
4190 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4191 p_doorbell, p_params);
4193 /* in case of error, need to free the previously
4194 * initiliazed hwfn 0.
4196 if (rc != ECORE_SUCCESS) {
4197 if (p_params->b_relaxed_probe)
4198 p_params->p_relaxed_res =
4199 ECORE_HW_PREPARE_FAILED_ENG2;
4202 ecore_init_free(p_hwfn);
4203 ecore_mcp_free(p_hwfn);
4204 ecore_hw_hwfn_free(p_hwfn);
4206 DP_NOTICE(p_dev, true,
4207 "What do we need to free when VF hwfn1 init fails\n");
4216 void ecore_hw_remove(struct ecore_dev *p_dev)
4218 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4222 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4223 ECORE_OV_DRIVER_STATE_NOT_LOADED);
4225 for_each_hwfn(p_dev, i) {
4226 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4229 ecore_vf_pf_release(p_hwfn);
4233 ecore_init_free(p_hwfn);
4234 ecore_hw_hwfn_free(p_hwfn);
4235 ecore_mcp_free(p_hwfn);
4237 #ifdef CONFIG_ECORE_LOCK_ALLOC
4238 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
4242 ecore_iov_free_hw_info(p_dev);
4245 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4246 struct ecore_chain *p_chain)
4248 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4249 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4250 struct ecore_chain_next *p_next;
4256 size = p_chain->elem_size * p_chain->usable_per_page;
4258 for (i = 0; i < p_chain->page_cnt; i++) {
4262 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4263 p_virt_next = p_next->next_virt;
4264 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4266 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4267 ECORE_CHAIN_PAGE_SIZE);
4269 p_virt = p_virt_next;
4270 p_phys = p_phys_next;
4274 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4275 struct ecore_chain *p_chain)
4277 if (!p_chain->p_virt_addr)
4280 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4281 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4284 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4285 struct ecore_chain *p_chain)
4287 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4288 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4289 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4291 if (!pp_virt_addr_tbl)
4297 for (i = 0; i < page_cnt; i++) {
4298 if (!pp_virt_addr_tbl[i])
4301 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4302 *(dma_addr_t *)p_pbl_virt,
4303 ECORE_CHAIN_PAGE_SIZE);
4305 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4308 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4310 if (!p_chain->b_external_pbl)
4311 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4312 p_chain->pbl_sp.p_phys_table, pbl_size);
4314 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4317 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4319 switch (p_chain->mode) {
4320 case ECORE_CHAIN_MODE_NEXT_PTR:
4321 ecore_chain_free_next_ptr(p_dev, p_chain);
4323 case ECORE_CHAIN_MODE_SINGLE:
4324 ecore_chain_free_single(p_dev, p_chain);
4326 case ECORE_CHAIN_MODE_PBL:
4327 ecore_chain_free_pbl(p_dev, p_chain);
4332 static enum _ecore_status_t
4333 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4334 enum ecore_chain_cnt_type cnt_type,
4335 osal_size_t elem_size, u32 page_cnt)
4337 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4339 /* The actual chain size can be larger than the maximal possible value
4340 * after rounding up the requested elements number to pages, and after
4341 * taking into acount the unusuable elements (next-ptr elements).
4342 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4343 * size/capacity fields are of a u32 type.
4345 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4346 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4347 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4348 chain_size > ECORE_U32_MAX)) {
4349 DP_NOTICE(p_dev, true,
4350 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4351 (unsigned long)chain_size);
4355 return ECORE_SUCCESS;
4358 static enum _ecore_status_t
4359 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4361 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4362 dma_addr_t p_phys = 0;
4365 for (i = 0; i < p_chain->page_cnt; i++) {
4366 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4367 ECORE_CHAIN_PAGE_SIZE);
4369 DP_NOTICE(p_dev, true,
4370 "Failed to allocate chain memory\n");
4375 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4376 ecore_chain_reset(p_chain);
4378 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4382 p_virt_prev = p_virt;
4384 /* Last page's next element should point to the beginning of the
4387 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4388 p_chain->p_virt_addr,
4389 p_chain->p_phys_addr);
4391 return ECORE_SUCCESS;
4394 static enum _ecore_status_t
4395 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4397 dma_addr_t p_phys = 0;
4398 void *p_virt = OSAL_NULL;
4400 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4402 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4406 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4407 ecore_chain_reset(p_chain);
4409 return ECORE_SUCCESS;
4412 static enum _ecore_status_t
4413 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4414 struct ecore_chain *p_chain,
4415 struct ecore_chain_ext_pbl *ext_pbl)
4417 u32 page_cnt = p_chain->page_cnt, size, i;
4418 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4419 void **pp_virt_addr_tbl = OSAL_NULL;
4420 u8 *p_pbl_virt = OSAL_NULL;
4421 void *p_virt = OSAL_NULL;
4423 size = page_cnt * sizeof(*pp_virt_addr_tbl);
4424 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4425 if (!pp_virt_addr_tbl) {
4426 DP_NOTICE(p_dev, true,
4427 "Failed to allocate memory for the chain virtual addresses table\n");
4431 /* The allocation of the PBL table is done with its full size, since it
4432 * is expected to be successive.
4433 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4434 * failure, since pp_virt_addr_tbl was previously allocated, and it
4435 * should be saved to allow its freeing during the error flow.
4437 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4439 if (ext_pbl == OSAL_NULL) {
4440 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4442 p_pbl_virt = ext_pbl->p_pbl_virt;
4443 p_pbl_phys = ext_pbl->p_pbl_phys;
4444 p_chain->b_external_pbl = true;
4447 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4450 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4454 for (i = 0; i < page_cnt; i++) {
4455 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4456 ECORE_CHAIN_PAGE_SIZE);
4458 DP_NOTICE(p_dev, true,
4459 "Failed to allocate chain memory\n");
4464 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4465 ecore_chain_reset(p_chain);
4468 /* Fill the PBL table with the physical address of the page */
4469 *(dma_addr_t *)p_pbl_virt = p_phys;
4470 /* Keep the virtual address of the page */
4471 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4473 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4476 return ECORE_SUCCESS;
4479 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4480 enum ecore_chain_use_mode intended_use,
4481 enum ecore_chain_mode mode,
4482 enum ecore_chain_cnt_type cnt_type,
4483 u32 num_elems, osal_size_t elem_size,
4484 struct ecore_chain *p_chain,
4485 struct ecore_chain_ext_pbl *ext_pbl)
4488 enum _ecore_status_t rc = ECORE_SUCCESS;
4490 if (mode == ECORE_CHAIN_MODE_SINGLE)
4493 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4495 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4498 DP_NOTICE(p_dev, true,
4499 "Cannot allocate a chain with the given arguments:\n"
4500 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4501 intended_use, mode, cnt_type, num_elems, elem_size);
4505 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4506 mode, cnt_type, p_dev->dp_ctx);
4509 case ECORE_CHAIN_MODE_NEXT_PTR:
4510 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4512 case ECORE_CHAIN_MODE_SINGLE:
4513 rc = ecore_chain_alloc_single(p_dev, p_chain);
4515 case ECORE_CHAIN_MODE_PBL:
4516 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4522 return ECORE_SUCCESS;
4525 ecore_chain_free(p_dev, p_chain);
4529 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4530 u16 src_id, u16 *dst_id)
4532 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4535 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4536 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4537 DP_NOTICE(p_hwfn, true,
4538 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4544 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4546 return ECORE_SUCCESS;
4549 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4550 u8 src_id, u8 *dst_id)
4552 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4555 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4556 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4557 DP_NOTICE(p_hwfn, true,
4558 "vport id [%d] is not valid, available indices [%d - %d]\n",
4564 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4566 return ECORE_SUCCESS;
4569 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4570 u8 src_id, u8 *dst_id)
4572 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4575 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4576 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4577 DP_NOTICE(p_hwfn, true,
4578 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4584 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4586 return ECORE_SUCCESS;
4589 static enum _ecore_status_t
4590 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4591 struct ecore_ptt *p_ptt, u32 high, u32 low,
4597 /* Find a free entry and utilize it */
4598 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4599 en = ecore_rd(p_hwfn, p_ptt,
4600 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4604 ecore_wr(p_hwfn, p_ptt,
4605 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4606 2 * i * sizeof(u32), low);
4607 ecore_wr(p_hwfn, p_ptt,
4608 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4609 (2 * i + 1) * sizeof(u32), high);
4610 ecore_wr(p_hwfn, p_ptt,
4611 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4612 i * sizeof(u32), 0);
4613 ecore_wr(p_hwfn, p_ptt,
4614 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4615 i * sizeof(u32), 0);
4616 ecore_wr(p_hwfn, p_ptt,
4617 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4618 i * sizeof(u32), 1);
4622 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4623 return ECORE_NORESOURCES;
4627 return ECORE_SUCCESS;
4630 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4631 struct ecore_ptt *p_ptt, u8 *p_filter)
4633 u32 high, low, entry_num;
4634 enum _ecore_status_t rc;
4636 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4637 &p_hwfn->p_dev->mf_bits))
4638 return ECORE_SUCCESS;
4640 high = p_filter[1] | (p_filter[0] << 8);
4641 low = p_filter[5] | (p_filter[4] << 8) |
4642 (p_filter[3] << 16) | (p_filter[2] << 24);
4644 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4645 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4647 if (rc != ECORE_SUCCESS) {
4648 DP_NOTICE(p_hwfn, false,
4649 "Failed to find an empty LLH filter to utilize\n");
4653 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4654 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4655 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4656 p_filter[4], p_filter[5], entry_num);
4658 return ECORE_SUCCESS;
4661 static enum _ecore_status_t
4662 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4663 struct ecore_ptt *p_ptt, u32 high, u32 low,
4668 /* Find the entry and clean it */
4669 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4670 if (ecore_rd(p_hwfn, p_ptt,
4671 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4672 2 * i * sizeof(u32)) != low)
4674 if (ecore_rd(p_hwfn, p_ptt,
4675 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4676 (2 * i + 1) * sizeof(u32)) != high)
4679 ecore_wr(p_hwfn, p_ptt,
4680 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4681 ecore_wr(p_hwfn, p_ptt,
4682 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4683 2 * i * sizeof(u32), 0);
4684 ecore_wr(p_hwfn, p_ptt,
4685 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4686 (2 * i + 1) * sizeof(u32), 0);
4690 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4695 return ECORE_SUCCESS;
4698 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4699 struct ecore_ptt *p_ptt, u8 *p_filter)
4701 u32 high, low, entry_num;
4702 enum _ecore_status_t rc;
4704 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4705 &p_hwfn->p_dev->mf_bits))
4708 high = p_filter[1] | (p_filter[0] << 8);
4709 low = p_filter[5] | (p_filter[4] << 8) |
4710 (p_filter[3] << 16) | (p_filter[2] << 24);
4712 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4713 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4715 if (rc != ECORE_SUCCESS) {
4716 DP_NOTICE(p_hwfn, false,
4717 "Tried to remove a non-configured filter\n");
4722 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4723 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4724 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4725 p_filter[4], p_filter[5], entry_num);
4728 static enum _ecore_status_t
4729 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4730 struct ecore_ptt *p_ptt,
4731 enum ecore_llh_port_filter_type_t type,
4732 u32 high, u32 low, u32 *p_entry_num)
4737 /* Find a free entry and utilize it */
4738 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4739 en = ecore_rd(p_hwfn, p_ptt,
4740 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4744 ecore_wr(p_hwfn, p_ptt,
4745 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4746 2 * i * sizeof(u32), low);
4747 ecore_wr(p_hwfn, p_ptt,
4748 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4749 (2 * i + 1) * sizeof(u32), high);
4750 ecore_wr(p_hwfn, p_ptt,
4751 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4752 i * sizeof(u32), 1);
4753 ecore_wr(p_hwfn, p_ptt,
4754 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4755 i * sizeof(u32), 1 << type);
4756 ecore_wr(p_hwfn, p_ptt,
4757 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4761 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4762 return ECORE_NORESOURCES;
4766 return ECORE_SUCCESS;
4769 enum _ecore_status_t
4770 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4771 struct ecore_ptt *p_ptt,
4772 u16 source_port_or_eth_type,
4774 enum ecore_llh_port_filter_type_t type)
4776 u32 high, low, entry_num;
4777 enum _ecore_status_t rc;
4779 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4780 &p_hwfn->p_dev->mf_bits))
4781 return ECORE_SUCCESS;
4787 case ECORE_LLH_FILTER_ETHERTYPE:
4788 high = source_port_or_eth_type;
4790 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4791 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4792 low = source_port_or_eth_type << 16;
4794 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4795 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4798 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4799 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4800 low = (source_port_or_eth_type << 16) | dest_port;
4803 DP_NOTICE(p_hwfn, true,
4804 "Non valid LLH protocol filter type %d\n", type);
4808 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4809 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4810 high, low, &entry_num);
4811 if (rc != ECORE_SUCCESS) {
4812 DP_NOTICE(p_hwfn, false,
4813 "Failed to find an empty LLH filter to utilize\n");
4817 case ECORE_LLH_FILTER_ETHERTYPE:
4818 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4819 "ETH type %x is added at %d\n",
4820 source_port_or_eth_type, entry_num);
4822 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4823 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4824 "TCP src port %x is added at %d\n",
4825 source_port_or_eth_type, entry_num);
4827 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4828 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4829 "UDP src port %x is added at %d\n",
4830 source_port_or_eth_type, entry_num);
4832 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4833 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4834 "TCP dst port %x is added at %d\n", dest_port,
4837 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4838 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4839 "UDP dst port %x is added at %d\n", dest_port,
4842 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4843 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4844 "TCP src/dst ports %x/%x are added at %d\n",
4845 source_port_or_eth_type, dest_port, entry_num);
4847 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4848 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4849 "UDP src/dst ports %x/%x are added at %d\n",
4850 source_port_or_eth_type, dest_port, entry_num);
4854 return ECORE_SUCCESS;
4857 static enum _ecore_status_t
4858 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4859 struct ecore_ptt *p_ptt,
4860 enum ecore_llh_port_filter_type_t type,
4861 u32 high, u32 low, u32 *p_entry_num)
4865 /* Find the entry and clean it */
4866 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4867 if (!ecore_rd(p_hwfn, p_ptt,
4868 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4871 if (!ecore_rd(p_hwfn, p_ptt,
4872 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4875 if (!(ecore_rd(p_hwfn, p_ptt,
4876 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4877 i * sizeof(u32)) & (1 << type)))
4879 if (ecore_rd(p_hwfn, p_ptt,
4880 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4881 2 * i * sizeof(u32)) != low)
4883 if (ecore_rd(p_hwfn, p_ptt,
4884 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4885 (2 * i + 1) * sizeof(u32)) != high)
4888 ecore_wr(p_hwfn, p_ptt,
4889 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4890 ecore_wr(p_hwfn, p_ptt,
4891 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4892 i * sizeof(u32), 0);
4893 ecore_wr(p_hwfn, p_ptt,
4894 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4895 i * sizeof(u32), 0);
4896 ecore_wr(p_hwfn, p_ptt,
4897 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4898 2 * i * sizeof(u32), 0);
4899 ecore_wr(p_hwfn, p_ptt,
4900 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4901 (2 * i + 1) * sizeof(u32), 0);
4905 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4910 return ECORE_SUCCESS;
4914 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4915 struct ecore_ptt *p_ptt,
4916 u16 source_port_or_eth_type,
4918 enum ecore_llh_port_filter_type_t type)
4920 u32 high, low, entry_num;
4921 enum _ecore_status_t rc;
4923 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4924 &p_hwfn->p_dev->mf_bits))
4931 case ECORE_LLH_FILTER_ETHERTYPE:
4932 high = source_port_or_eth_type;
4934 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4935 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4936 low = source_port_or_eth_type << 16;
4938 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4939 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4942 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4943 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4944 low = (source_port_or_eth_type << 16) | dest_port;
4947 DP_NOTICE(p_hwfn, true,
4948 "Non valid LLH protocol filter type %d\n", type);
4952 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4953 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4956 if (rc != ECORE_SUCCESS) {
4957 DP_NOTICE(p_hwfn, false,
4958 "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4959 type, source_port_or_eth_type, dest_port);
4963 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4964 "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4965 type, source_port_or_eth_type, dest_port, entry_num);
4968 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4969 struct ecore_ptt *p_ptt)
4973 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4976 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4977 ecore_wr(p_hwfn, p_ptt,
4978 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4979 i * sizeof(u32), 0);
4980 ecore_wr(p_hwfn, p_ptt,
4981 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4982 2 * i * sizeof(u32), 0);
4983 ecore_wr(p_hwfn, p_ptt,
4984 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4985 (2 * i + 1) * sizeof(u32), 0);
4989 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4990 struct ecore_ptt *p_ptt)
4992 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4993 &p_hwfn->p_dev->mf_bits) &&
4994 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4995 &p_hwfn->p_dev->mf_bits))
4998 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4999 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5002 enum _ecore_status_t
5003 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5004 struct ecore_ptt *p_ptt)
5006 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5007 ecore_wr(p_hwfn, p_ptt,
5008 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5009 1 << p_hwfn->abs_pf_id / 2);
5010 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5011 return ECORE_SUCCESS;
5014 DP_NOTICE(p_hwfn, false,
5015 "This function can't be set as default\n");
5019 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5020 struct ecore_ptt *p_ptt,
5021 u32 hw_addr, void *p_eth_qzone,
5022 osal_size_t eth_qzone_size,
5025 struct coalescing_timeset *p_coal_timeset;
5027 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5028 DP_NOTICE(p_hwfn, true,
5029 "Coalescing configuration not enabled\n");
5033 p_coal_timeset = p_eth_qzone;
5034 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5035 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5036 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5037 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5039 return ECORE_SUCCESS;
5042 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5043 u16 rx_coal, u16 tx_coal,
5046 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5047 enum _ecore_status_t rc = ECORE_SUCCESS;
5048 struct ecore_ptt *p_ptt;
5050 /* TODO - Configuring a single queue's coalescing but
5051 * claiming all queues are abiding same configuration
5052 * for PF and VF both.
5055 if (IS_VF(p_hwfn->p_dev))
5056 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5059 p_ptt = ecore_ptt_acquire(p_hwfn);
5064 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5067 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5071 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5074 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5077 ecore_ptt_release(p_hwfn, p_ptt);
5082 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5083 struct ecore_ptt *p_ptt,
5085 struct ecore_queue_cid *p_cid)
5087 struct ustorm_eth_queue_zone eth_qzone;
5088 u8 timeset, timer_res;
5090 enum _ecore_status_t rc;
5092 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5093 if (coalesce <= 0x7F) {
5095 } else if (coalesce <= 0xFF) {
5097 } else if (coalesce <= 0x1FF) {
5100 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5103 timeset = (u8)(coalesce >> timer_res);
5105 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5106 p_cid->sb_igu_id, false);
5107 if (rc != ECORE_SUCCESS)
5110 address = BAR0_MAP_REG_USDM_RAM +
5111 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5113 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5114 sizeof(struct ustorm_eth_queue_zone), timeset);
5115 if (rc != ECORE_SUCCESS)
5122 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5123 struct ecore_ptt *p_ptt,
5125 struct ecore_queue_cid *p_cid)
5127 struct xstorm_eth_queue_zone eth_qzone;
5128 u8 timeset, timer_res;
5130 enum _ecore_status_t rc;
5132 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5133 if (coalesce <= 0x7F) {
5135 } else if (coalesce <= 0xFF) {
5137 } else if (coalesce <= 0x1FF) {
5140 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5144 timeset = (u8)(coalesce >> timer_res);
5146 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5147 p_cid->sb_igu_id, true);
5148 if (rc != ECORE_SUCCESS)
5151 address = BAR0_MAP_REG_XSDM_RAM +
5152 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5154 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5155 sizeof(struct xstorm_eth_queue_zone), timeset);
5160 /* Calculate final WFQ values for all vports and configure it.
5161 * After this configuration each vport must have
5162 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5164 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5165 struct ecore_ptt *p_ptt,
5168 struct init_qm_vport_params *vport_params;
5171 vport_params = p_hwfn->qm_info.qm_vport_params;
5173 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5174 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5176 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5178 ecore_init_vport_wfq(p_hwfn, p_ptt,
5179 vport_params[i].first_tx_pq_id,
5180 vport_params[i].vport_wfq);
5184 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5188 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5189 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5192 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5193 struct ecore_ptt *p_ptt)
5195 struct init_qm_vport_params *vport_params;
5198 vport_params = p_hwfn->qm_info.qm_vport_params;
5200 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5201 ecore_init_wfq_default_param(p_hwfn);
5202 ecore_init_vport_wfq(p_hwfn, p_ptt,
5203 vport_params[i].first_tx_pq_id,
5204 vport_params[i].vport_wfq);
5208 /* This function performs several validations for WFQ
5209 * configuration and required min rate for a given vport
5210 * 1. req_rate must be greater than one percent of min_pf_rate.
5211 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5212 * rates to get less than one percent of min_pf_rate.
5213 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5215 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5216 u16 vport_id, u32 req_rate,
5219 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5220 int non_requested_count = 0, req_count = 0, i, num_vports;
5222 num_vports = p_hwfn->qm_info.num_vports;
5224 /* Accounting for the vports which are configured for WFQ explicitly */
5226 for (i = 0; i < num_vports; i++) {
5229 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5231 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5232 total_req_min_rate += tmp_speed;
5236 /* Include current vport data as well */
5238 total_req_min_rate += req_rate;
5239 non_requested_count = num_vports - req_count;
5241 /* validate possible error cases */
5242 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5243 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5244 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5245 vport_id, req_rate, min_pf_rate);
5249 /* TBD - for number of vports greater than 100 */
5250 if (num_vports > ECORE_WFQ_UNIT) {
5251 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5252 "Number of vports is greater than %d\n",
5257 if (total_req_min_rate > min_pf_rate) {
5258 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5259 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5260 total_req_min_rate, min_pf_rate);
5264 /* Data left for non requested vports */
5265 total_left_rate = min_pf_rate - total_req_min_rate;
5266 left_rate_per_vp = total_left_rate / non_requested_count;
5268 /* validate if non requested get < 1% of min bw */
5269 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5270 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5271 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5272 left_rate_per_vp, min_pf_rate);
5276 /* now req_rate for given vport passes all scenarios.
5277 * assign final wfq rates to all vports.
5279 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5280 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5282 for (i = 0; i < num_vports; i++) {
5283 if (p_hwfn->qm_info.wfq_data[i].configured)
5286 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5289 return ECORE_SUCCESS;
5292 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5293 struct ecore_ptt *p_ptt,
5294 u16 vp_id, u32 rate)
5296 struct ecore_mcp_link_state *p_link;
5297 int rc = ECORE_SUCCESS;
5299 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5301 if (!p_link->min_pf_rate) {
5302 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5303 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5307 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5309 if (rc == ECORE_SUCCESS)
5310 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5311 p_link->min_pf_rate);
5313 DP_NOTICE(p_hwfn, false,
5314 "Validation failed while configuring min rate\n");
5319 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5320 struct ecore_ptt *p_ptt,
5323 bool use_wfq = false;
5324 int rc = ECORE_SUCCESS;
5327 /* Validate all pre configured vports for wfq */
5328 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5331 if (!p_hwfn->qm_info.wfq_data[i].configured)
5334 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5337 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5338 if (rc != ECORE_SUCCESS) {
5339 DP_NOTICE(p_hwfn, false,
5340 "WFQ validation failed while configuring min rate\n");
5345 if (rc == ECORE_SUCCESS && use_wfq)
5346 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5348 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5353 /* Main API for ecore clients to configure vport min rate.
5354 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5355 * rate - Speed in Mbps needs to be assigned to a given vport.
5357 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5359 int i, rc = ECORE_INVAL;
5361 /* TBD - for multiple hardware functions - that is 100 gig */
5362 if (ECORE_IS_CMT(p_dev)) {
5363 DP_NOTICE(p_dev, false,
5364 "WFQ configuration is not supported for this device\n");
5368 for_each_hwfn(p_dev, i) {
5369 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5370 struct ecore_ptt *p_ptt;
5372 p_ptt = ecore_ptt_acquire(p_hwfn);
5374 return ECORE_TIMEOUT;
5376 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5378 if (rc != ECORE_SUCCESS) {
5379 ecore_ptt_release(p_hwfn, p_ptt);
5383 ecore_ptt_release(p_hwfn, p_ptt);
5389 /* API to configure WFQ from mcp link change */
5390 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5391 struct ecore_ptt *p_ptt,
5396 /* TBD - for multiple hardware functions - that is 100 gig */
5397 if (ECORE_IS_CMT(p_dev)) {
5398 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5399 "WFQ configuration is not supported for this device\n");
5403 for_each_hwfn(p_dev, i) {
5404 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5406 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5411 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5412 struct ecore_ptt *p_ptt,
5413 struct ecore_mcp_link_state *p_link,
5416 int rc = ECORE_SUCCESS;
5418 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5420 if (!p_link->line_speed && (max_bw != 100))
5423 p_link->speed = (p_link->line_speed * max_bw) / 100;
5424 p_hwfn->qm_info.pf_rl = p_link->speed;
5426 /* Since the limiter also affects Tx-switched traffic, we don't want it
5427 * to limit such traffic in case there's no actual limit.
5428 * In that case, set limit to imaginary high boundary.
5431 p_hwfn->qm_info.pf_rl = 100000;
5433 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5434 p_hwfn->qm_info.pf_rl);
5436 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5437 "Configured MAX bandwidth to be %08x Mb/sec\n",
5443 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5444 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5446 int i, rc = ECORE_INVAL;
5448 if (max_bw < 1 || max_bw > 100) {
5449 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5453 for_each_hwfn(p_dev, i) {
5454 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5455 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5456 struct ecore_mcp_link_state *p_link;
5457 struct ecore_ptt *p_ptt;
5459 p_link = &p_lead->mcp_info->link_output;
5461 p_ptt = ecore_ptt_acquire(p_hwfn);
5463 return ECORE_TIMEOUT;
5465 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5468 ecore_ptt_release(p_hwfn, p_ptt);
5470 if (rc != ECORE_SUCCESS)
5477 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5478 struct ecore_ptt *p_ptt,
5479 struct ecore_mcp_link_state *p_link,
5482 int rc = ECORE_SUCCESS;
5484 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5485 p_hwfn->qm_info.pf_wfq = min_bw;
5487 if (!p_link->line_speed)
5490 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5492 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5494 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5495 "Configured MIN bandwidth to be %d Mb/sec\n",
5496 p_link->min_pf_rate);
5501 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5502 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5504 int i, rc = ECORE_INVAL;
5506 if (min_bw < 1 || min_bw > 100) {
5507 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5511 for_each_hwfn(p_dev, i) {
5512 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5513 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5514 struct ecore_mcp_link_state *p_link;
5515 struct ecore_ptt *p_ptt;
5517 p_link = &p_lead->mcp_info->link_output;
5519 p_ptt = ecore_ptt_acquire(p_hwfn);
5521 return ECORE_TIMEOUT;
5523 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5525 if (rc != ECORE_SUCCESS) {
5526 ecore_ptt_release(p_hwfn, p_ptt);
5530 if (p_link->min_pf_rate) {
5531 u32 min_rate = p_link->min_pf_rate;
5533 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5538 ecore_ptt_release(p_hwfn, p_ptt);
5544 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5546 struct ecore_mcp_link_state *p_link;
5548 p_link = &p_hwfn->mcp_info->link_output;
5550 if (p_link->min_pf_rate)
5551 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5553 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5554 sizeof(*p_hwfn->qm_info.wfq_data) *
5555 p_hwfn->qm_info.num_vports);
5558 int ecore_device_num_engines(struct ecore_dev *p_dev)
5560 return ECORE_IS_BB(p_dev) ? 2 : 1;
5563 int ecore_device_num_ports(struct ecore_dev *p_dev)
5565 return p_dev->num_ports;
5568 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5573 ((u8 *)fw_msb)[0] = mac[1];
5574 ((u8 *)fw_msb)[1] = mac[0];
5575 ((u8 *)fw_mid)[0] = mac[3];
5576 ((u8 *)fw_mid)[1] = mac[2];
5577 ((u8 *)fw_lsb)[0] = mac[5];
5578 ((u8 *)fw_lsb)[1] = mac[4];