drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /* Configurable */
  45 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  46                                          * load the driver. The number was
  47                                          * arbitrarily set.
  48                                          */
  49
  50 /* Derived */
  51 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  52
  53 enum BAR_ID {
  54         BAR_ID_0,               /* used for GRC */
  55         BAR_ID_1                /* Used for doorbells */
  56 };
  57
  58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  59 {
  60         u32 bar_reg = (bar_id == BAR_ID_0 ?
  61                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  62         u32 val;
  63
  64         if (IS_VF(p_hwfn->p_dev)) {
  65                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  66                  * read from actual register, but we're currently not using
  67                  * it for actual doorbelling.
  68                  */
  69                 return 1 << 17;
  70         }
  71
  72         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  73         if (val)
  74                 return 1 << (val + 15);
  75
  76         /* The above registers were updated in the past only in CMT mode. Since
  77          * they were found to be useful MFW started updating them from 8.7.7.0.
  78          * In older MFW versions they are set to 0 which means disabled.
  79          */
  80         if (p_hwfn->p_dev->num_hwfns > 1) {
  81                 DP_NOTICE(p_hwfn, false,
  82                           "BAR size not configured. Assuming BAR size of 256kB"
  83                           " for GRC and 512kB for DB\n");
  84                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  85         } else {
  86                 DP_NOTICE(p_hwfn, false,
  87                           "BAR size not configured. Assuming BAR size of 512kB"
  88                           " for GRC and 512kB for DB\n");
  89                 val = 512 * 1024;
  90         }
  91
  92         return val;
  93 }
  94
  95 void ecore_init_dp(struct ecore_dev *p_dev,
  96                    u32 dp_module, u8 dp_level, void *dp_ctx)
  97 {
  98         u32 i;
  99
 100         p_dev->dp_level = dp_level;
 101         p_dev->dp_module = dp_module;
 102         p_dev->dp_ctx = dp_ctx;
 103         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 104                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 105
 106                 p_hwfn->dp_level = dp_level;
 107                 p_hwfn->dp_module = dp_module;
 108                 p_hwfn->dp_ctx = dp_ctx;
 109         }
 110 }
 111
 112 void ecore_init_struct(struct ecore_dev *p_dev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 118
 119                 p_hwfn->p_dev = p_dev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 124                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 125         }
 126
 127         /* hwfn 0 is always active */
 128         p_dev->hwfns[0].b_active = true;
 129
 130         /* set the default cache alignment to 128 (may be overridden later) */
 131         p_dev->cache_shift = 7;
 132 }
 133
 134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 135 {
 136         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 137
 138         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 142 }
 143
 144 void ecore_resc_free(struct ecore_dev *p_dev)
 145 {
 146         int i;
 147
 148         if (IS_VF(p_dev))
 149                 return;
 150
 151         OSAL_FREE(p_dev, p_dev->fw_data);
 152
 153         OSAL_FREE(p_dev, p_dev->reset_stats);
 154
 155         for_each_hwfn(p_dev, i) {
 156                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 157
 158                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 159                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 160         }
 161
 162         for_each_hwfn(p_dev, i) {
 163                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 164
 165                 ecore_cxt_mngr_free(p_hwfn);
 166                 ecore_qm_info_free(p_hwfn);
 167                 ecore_spq_free(p_hwfn);
 168                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 169                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 170                 ecore_int_free(p_hwfn);
 171 #ifdef CONFIG_ECORE_LL2
 172                 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 173 #endif
 174                 ecore_iov_free(p_hwfn);
 175                 ecore_dmae_info_free(p_hwfn);
 176                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 177                 /* @@@TBD Flush work-queue ? */
 178         }
 179 }
 180
 181 /******************** QM initialization *******************/
 182
 183 /* bitmaps for indicating active traffic classes.
 184  * Special case for Arrowhead 4 port
 185  */
 186 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 187 #define ACTIVE_TCS_BMAP 0x9f
 188 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 189 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 190
 191 /* determines the physical queue flags for a given PF. */
 192 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 193 {
 194         u32 flags;
 195
 196         /* common flags */
 197         flags = PQ_FLAGS_LB;
 198
 199         /* feature flags */
 200         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 201                 flags |= PQ_FLAGS_VFS;
 202
 203         /* protocol flags */
 204         switch (p_hwfn->hw_info.personality) {
 205         case ECORE_PCI_ETH:
 206                 flags |= PQ_FLAGS_MCOS;
 207                 break;
 208         case ECORE_PCI_FCOE:
 209                 flags |= PQ_FLAGS_OFLD;
 210                 break;
 211         case ECORE_PCI_ISCSI:
 212                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 213                 break;
 214         case ECORE_PCI_ETH_ROCE:
 215                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 216                 break;
 217         case ECORE_PCI_ETH_IWARP:
 218                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 219                          PQ_FLAGS_OFLD;
 220                 break;
 221         default:
 222                 DP_ERR(p_hwfn, "unknown personality %d\n",
 223                        p_hwfn->hw_info.personality);
 224                 return 0;
 225         }
 226         return flags;
 227 }
 228
 229 /* Getters for resource amounts necessary for qm initialization */
 230 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 231 {
 232         return p_hwfn->hw_info.num_hw_tc;
 233 }
 234
 235 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 236 {
 237         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 238                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 239 }
 240
 241 #define NUM_DEFAULT_RLS 1
 242
 243 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 244 {
 245         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 246
 247         /* @DPDK */
 248         /* num RLs can't exceed resource amount of rls or vports or the
 249          * dcqcn qps
 250          */
 251         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 252                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 253
 254         /* make sure after we reserve the default and VF rls we'll have
 255          * something left
 256          */
 257         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 258                 DP_NOTICE(p_hwfn, false,
 259                           "no rate limiters left for PF rate limiting"
 260                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 261                 return 0;
 262         }
 263
 264         /* subtract rls necessary for VFs and one default one for the PF */
 265         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 266
 267         return num_pf_rls;
 268 }
 269
 270 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 271 {
 272         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 273
 274         /* all pqs share the same vport (hence the 1 below), except for vfs
 275          * and pf_rl pqs
 276          */
 277         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 278                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 279                (!!(PQ_FLAGS_VFS & pq_flags)) *
 280                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 281 }
 282
 283 /* calc amount of PQs according to the requested flags */
 284 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 285 {
 286         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 287
 288         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 289                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 290                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 291                 ecore_init_qm_get_num_tcs(p_hwfn) +
 292                (!!(PQ_FLAGS_LB & pq_flags)) +
 293                (!!(PQ_FLAGS_OOO & pq_flags)) +
 294                (!!(PQ_FLAGS_ACK & pq_flags)) +
 295                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 296                (!!(PQ_FLAGS_VFS & pq_flags)) *
 297                 ecore_init_qm_get_num_vfs(p_hwfn);
 298 }
 299
 300 /* initialize the top level QM params */
 301 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 302 {
 303         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 304
 305         /* pq and vport bases for this PF */
 306         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 307         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 308
 309         /* rate limiting and weighted fair queueing are always enabled */
 310         qm_info->vport_rl_en = 1;
 311         qm_info->vport_wfq_en = 1;
 312
 313         /* in AH 4 port we have fewer TCs per port */
 314         qm_info->max_phys_tcs_per_port =
 315                 p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2 ?
 316                         NUM_PHYS_TCS_4PORT_K2 : NUM_OF_PHYS_TCS;
 317 }
 318
 319 /* initialize qm vport params */
 320 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 321 {
 322         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 323         u8 i;
 324
 325         /* all vports participate in weighted fair queueing */
 326         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 327                 qm_info->qm_vport_params[i].vport_wfq = 1;
 328 }
 329
 330 /* initialize qm port params */
 331 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 332 {
 333         /* Initialize qm port parameters */
 334         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
 335
 336         /* indicate how ooo and high pri traffic is dealt with */
 337         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 338                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 339
 340         for (i = 0; i < num_ports; i++) {
 341                 struct init_qm_port_params *p_qm_port =
 342                         &p_hwfn->qm_info.qm_port_params[i];
 343
 344                 p_qm_port->active = 1;
 345                 p_qm_port->active_phys_tcs = active_phys_tcs;
 346                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 347                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 348         }
 349 }
 350
 351 /* Reset the params which must be reset for qm init. QM init may be called as
 352  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 353  * params may be affected by the init but would simply recalculate to the same
 354  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 355  * affected as these amounts stay the same.
 356  */
 357 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 358 {
 359         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 360
 361         qm_info->num_pqs = 0;
 362         qm_info->num_vports = 0;
 363         qm_info->num_pf_rls = 0;
 364         qm_info->num_vf_pqs = 0;
 365         qm_info->first_vf_pq = 0;
 366         qm_info->first_mcos_pq = 0;
 367         qm_info->first_rl_pq = 0;
 368 }
 369
 370 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 371 {
 372         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 373
 374         qm_info->num_vports++;
 375
 376         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 377                 DP_ERR(p_hwfn,
 378                        "vport overflow! qm_info->num_vports %d,"
 379                        " qm_init_get_num_vports() %d\n",
 380                        qm_info->num_vports,
 381                        ecore_init_qm_get_num_vports(p_hwfn));
 382 }
 383
 384 /* initialize a single pq and manage qm_info resources accounting.
 385  * The pq_init_flags param determines whether the PQ is rate limited
 386  * (for VF or PF)
 387  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 388  * shared)
 389  */
 390
 391 /* flags for pq init */
 392 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 393 #define PQ_INIT_PF_RL           (1 << 1)
 394 #define PQ_INIT_VF_RL           (1 << 2)
 395
 396 /* defines for pq init */
 397 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 398 #define PQ_INIT_DEFAULT_TC              0
 399 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 400
 401 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 402                              struct ecore_qm_info *qm_info,
 403                              u8 tc, u32 pq_init_flags)
 404 {
 405         u16 pq_idx = qm_info->num_pqs, max_pq =
 406                                         ecore_init_qm_get_num_pqs(p_hwfn);
 407
 408         if (pq_idx > max_pq)
 409                 DP_ERR(p_hwfn,
 410                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 411
 412         /* init pq params */
 413         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 414                                                  qm_info->num_vports;
 415         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 416         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 417         qm_info->qm_pq_params[pq_idx].rl_valid =
 418                 (pq_init_flags & PQ_INIT_PF_RL ||
 419                  pq_init_flags & PQ_INIT_VF_RL);
 420
 421         /* qm params accounting */
 422         qm_info->num_pqs++;
 423         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 424                 qm_info->num_vports++;
 425
 426         if (pq_init_flags & PQ_INIT_PF_RL)
 427                 qm_info->num_pf_rls++;
 428
 429         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 430                 DP_ERR(p_hwfn,
 431                        "vport overflow! qm_info->num_vports %d,"
 432                        " qm_init_get_num_vports() %d\n",
 433                        qm_info->num_vports,
 434                        ecore_init_qm_get_num_vports(p_hwfn));
 435
 436         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 437                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 438                        " qm_init_get_num_pf_rls() %d\n",
 439                        qm_info->num_pf_rls,
 440                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 441 }
 442
 443 /* get pq index according to PQ_FLAGS */
 444 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 445                                              u32 pq_flags)
 446 {
 447         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 448
 449         /* Can't have multiple flags set here */
 450         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 451                                 sizeof(pq_flags)) > 1)
 452                 goto err;
 453
 454         switch (pq_flags) {
 455         case PQ_FLAGS_RLS:
 456                 return &qm_info->first_rl_pq;
 457         case PQ_FLAGS_MCOS:
 458                 return &qm_info->first_mcos_pq;
 459         case PQ_FLAGS_LB:
 460                 return &qm_info->pure_lb_pq;
 461         case PQ_FLAGS_OOO:
 462                 return &qm_info->ooo_pq;
 463         case PQ_FLAGS_ACK:
 464                 return &qm_info->pure_ack_pq;
 465         case PQ_FLAGS_OFLD:
 466                 return &qm_info->offload_pq;
 467         case PQ_FLAGS_VFS:
 468                 return &qm_info->first_vf_pq;
 469         default:
 470                 goto err;
 471         }
 472
 473 err:
 474         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 475         return OSAL_NULL;
 476 }
 477
 478 /* save pq index in qm info */
 479 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 480                                   u32 pq_flags, u16 pq_val)
 481 {
 482         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 483
 484         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 485 }
 486
 487 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 488 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 489 {
 490         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 491
 492         return *base_pq_idx + CM_TX_PQ_BASE;
 493 }
 494
 495 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 496 {
 497         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 498
 499         if (tc > max_tc)
 500                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 501
 502         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 503 }
 504
 505 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 506 {
 507         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 508
 509         if (vf > max_vf)
 510                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 511
 512         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 513 }
 514
 515 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 516 {
 517         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 518
 519         if (rl > max_rl)
 520                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 521
 522         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 523 }
 524
 525 /* Functions for creating specific types of pqs */
 526 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 527 {
 528         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 529
 530         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 531                 return;
 532
 533         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 534         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 535 }
 536
 537 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 538 {
 539         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 540
 541         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 542                 return;
 543
 544         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 545         ecore_init_qm_pq(p_hwfn, qm_info, DCBX_ISCSI_OOO_TC,
 546                          PQ_INIT_SHARE_VPORT);
 547 }
 548
 549 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 550 {
 551         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 552
 553         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 554                 return;
 555
 556         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 557         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 558 }
 559
 560 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 561 {
 562         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 563
 564         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 565                 return;
 566
 567         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 568         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 569 }
 570
 571 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 572 {
 573         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 574         u8 tc_idx;
 575
 576         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 577                 return;
 578
 579         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 580         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 581                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 582 }
 583
 584 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 585 {
 586         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 587         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 588
 589         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 590                 return;
 591
 592         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 593
 594         qm_info->num_vf_pqs = num_vfs;
 595         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 596                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 597                                  PQ_INIT_VF_RL);
 598 }
 599
 600 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 601 {
 602         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 603         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 604
 605         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 606                 return;
 607
 608         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 609         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 610                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 611                                  PQ_INIT_PF_RL);
 612 }
 613
 614 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 615 {
 616         /* rate limited pqs, must come first (FW assumption) */
 617         ecore_init_qm_rl_pqs(p_hwfn);
 618
 619         /* pqs for multi cos */
 620         ecore_init_qm_mcos_pqs(p_hwfn);
 621
 622         /* pure loopback pq */
 623         ecore_init_qm_lb_pq(p_hwfn);
 624
 625         /* out of order pq */
 626         ecore_init_qm_ooo_pq(p_hwfn);
 627
 628         /* pure ack pq */
 629         ecore_init_qm_pure_ack_pq(p_hwfn);
 630
 631         /* pq for offloaded protocol */
 632         ecore_init_qm_offload_pq(p_hwfn);
 633
 634         /* done sharing vports */
 635         ecore_init_qm_advance_vport(p_hwfn);
 636
 637         /* pqs for vfs */
 638         ecore_init_qm_vf_pqs(p_hwfn);
 639 }
 640
 641 /* compare values of getters against resources amounts */
 642 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 643 {
 644         if (ecore_init_qm_get_num_vports(p_hwfn) >
 645             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 646                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 647                 return ECORE_INVAL;
 648         }
 649
 650         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 651                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 652                 return ECORE_INVAL;
 653         }
 654
 655         return ECORE_SUCCESS;
 656 }
 657
 658 /*
 659  * Function for verbose printing of the qm initialization results
 660  */
 661 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 662 {
 663         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 664         struct init_qm_vport_params *vport;
 665         struct init_qm_port_params *port;
 666         struct init_qm_pq_params *pq;
 667         int i, tc;
 668
 669         /* top level params */
 670         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 671                    "qm init top level params: start_pq %d, start_vport %d,"
 672                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 673                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 674                    qm_info->offload_pq, qm_info->pure_ack_pq);
 675         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 676                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 677                    " num_vports %d, max_phys_tcs_per_port %d\n",
 678                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 679                    qm_info->num_vf_pqs, qm_info->num_vports,
 680                    qm_info->max_phys_tcs_per_port);
 681         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 682                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 683                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 684                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 685                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 686                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 687
 688         /* port table */
 689         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
 690                 port = &qm_info->qm_port_params[i];
 691                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 692                            "port idx %d, active %d, active_phys_tcs %d,"
 693                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
 694                            " reserved %d\n",
 695                            i, port->active, port->active_phys_tcs,
 696                            port->num_pbf_cmd_lines, port->num_btb_blocks,
 697                            port->reserved);
 698         }
 699
 700         /* vport table */
 701         for (i = 0; i < qm_info->num_vports; i++) {
 702                 vport = &qm_info->qm_vport_params[i];
 703                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 704                            "vport idx %d, vport_rl %d, wfq %d,"
 705                            " first_tx_pq_id [ ",
 706                            qm_info->start_vport + i, vport->vport_rl,
 707                            vport->vport_wfq);
 708                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 709                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
 710                                    vport->first_tx_pq_id[tc]);
 711                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
 712         }
 713
 714         /* pq table */
 715         for (i = 0; i < qm_info->num_pqs; i++) {
 716                 pq = &qm_info->qm_pq_params[i];
 717                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 718                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
 719                            " rl_valid %d\n",
 720                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
 721                            pq->wrr_group, pq->rl_valid);
 722         }
 723 }
 724
 725 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
 726 {
 727         /* reset params required for init run */
 728         ecore_init_qm_reset_params(p_hwfn);
 729
 730         /* init QM top level params */
 731         ecore_init_qm_params(p_hwfn);
 732
 733         /* init QM port params */
 734         ecore_init_qm_port_params(p_hwfn);
 735
 736         /* init QM vport params */
 737         ecore_init_qm_vport_params(p_hwfn);
 738
 739         /* init QM physical queue params */
 740         ecore_init_qm_pq_params(p_hwfn);
 741
 742         /* display all that init */
 743         ecore_dp_init_qm_params(p_hwfn);
 744 }
 745
 746 /* This function reconfigures the QM pf on the fly.
 747  * For this purpose we:
 748  * 1. reconfigure the QM database
 749  * 2. set new values to runtime array
 750  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 751  * 4. activate init tool in QM_PF stage
 752  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 753  */
 754 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 755                                      struct ecore_ptt *p_ptt)
 756 {
 757         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 758         enum _ecore_status_t rc;
 759         bool b_rc;
 760
 761         /* initialize ecore's qm data structure */
 762         ecore_init_qm_info(p_hwfn);
 763
 764         /* stop PF's qm queues */
 765         OSAL_SPIN_LOCK(&qm_lock);
 766         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 767                                       qm_info->start_pq, qm_info->num_pqs);
 768         OSAL_SPIN_UNLOCK(&qm_lock);
 769         if (!b_rc)
 770                 return ECORE_INVAL;
 771
 772         /* clear the QM_PF runtime phase leftovers from previous init */
 773         ecore_init_clear_rt_data(p_hwfn);
 774
 775         /* prepare QM portion of runtime array */
 776         ecore_qm_init_pf(p_hwfn);
 777
 778         /* activate init tool on runtime array */
 779         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 780                             p_hwfn->hw_info.hw_mode);
 781         if (rc != ECORE_SUCCESS)
 782                 return rc;
 783
 784         /* start PF's qm queues */
 785         OSAL_SPIN_LOCK(&qm_lock);
 786         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 787                                       qm_info->start_pq, qm_info->num_pqs);
 788         OSAL_SPIN_UNLOCK(&qm_lock);
 789         if (!b_rc)
 790                 return ECORE_INVAL;
 791
 792         return ECORE_SUCCESS;
 793 }
 794
 795 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
 796 {
 797         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 798         enum _ecore_status_t rc;
 799
 800         rc = ecore_init_qm_sanity(p_hwfn);
 801         if (rc != ECORE_SUCCESS)
 802                 goto alloc_err;
 803
 804         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 805                                             sizeof(struct init_qm_pq_params) *
 806                                             ecore_init_qm_get_num_pqs(p_hwfn));
 807         if (!qm_info->qm_pq_params)
 808                 goto alloc_err;
 809
 810         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 811                                        sizeof(struct init_qm_vport_params) *
 812                                        ecore_init_qm_get_num_vports(p_hwfn));
 813         if (!qm_info->qm_vport_params)
 814                 goto alloc_err;
 815
 816         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 817                                       sizeof(struct init_qm_port_params) *
 818                                       p_hwfn->p_dev->num_ports_in_engines);
 819         if (!qm_info->qm_port_params)
 820                 goto alloc_err;
 821
 822         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 823                                         sizeof(struct ecore_wfq_data) *
 824                                         ecore_init_qm_get_num_vports(p_hwfn));
 825         if (!qm_info->wfq_data)
 826                 goto alloc_err;
 827
 828         return ECORE_SUCCESS;
 829
 830 alloc_err:
 831         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 832         ecore_qm_info_free(p_hwfn);
 833         return ECORE_NOMEM;
 834 }
 835 /******************** End QM initialization ***************/
 836
 837 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 838 {
 839         struct ecore_consq *p_consq;
 840         struct ecore_eq *p_eq;
 841 #ifdef  CONFIG_ECORE_LL2
 842         struct ecore_ll2_info *p_ll2_info;
 843 #endif
 844         enum _ecore_status_t rc = ECORE_SUCCESS;
 845         int i;
 846
 847         if (IS_VF(p_dev))
 848                 return rc;
 849
 850         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 851                                      sizeof(*p_dev->fw_data));
 852         if (!p_dev->fw_data)
 853                 return ECORE_NOMEM;
 854
 855         /* Allocate Memory for the Queue->CID mapping */
 856         for_each_hwfn(p_dev, i) {
 857                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 858                 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 859                 int tx_size, rx_size;
 860
 861                 /* @@@TMP - resc management, change to actual required size */
 862                 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
 863                         num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
 864                 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
 865                 rx_size = sizeof(struct ecore_hw_cid_data) *
 866                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 867
 868                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 869                                                 tx_size);
 870                 if (!p_hwfn->p_tx_cids) {
 871                         DP_NOTICE(p_hwfn, true,
 872                                   "Failed to allocate memory for Tx Cids\n");
 873                         goto alloc_no_mem;
 874                 }
 875
 876                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 877                                                 rx_size);
 878                 if (!p_hwfn->p_rx_cids) {
 879                         DP_NOTICE(p_hwfn, true,
 880                                   "Failed to allocate memory for Rx Cids\n");
 881                         goto alloc_no_mem;
 882                 }
 883         }
 884
 885         for_each_hwfn(p_dev, i) {
 886                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 887                 u32 n_eqes, num_cons;
 888
 889                 /* First allocate the context manager structure */
 890                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 891                 if (rc)
 892                         goto alloc_err;
 893
 894                 /* Set the HW cid/tid numbers (in the contest manager)
 895                  * Must be done prior to any further computations.
 896                  */
 897                 rc = ecore_cxt_set_pf_params(p_hwfn);
 898                 if (rc)
 899                         goto alloc_err;
 900
 901                 rc = ecore_alloc_qm_data(p_hwfn);
 902                 if (rc)
 903                         goto alloc_err;
 904
 905                 /* init qm info */
 906                 ecore_init_qm_info(p_hwfn);
 907
 908                 /* Compute the ILT client partition */
 909                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 910                 if (rc)
 911                         goto alloc_err;
 912
 913                 /* CID map / ILT shadow table / T2
 914                  * The talbes sizes are determined by the computations above
 915                  */
 916                 rc = ecore_cxt_tables_alloc(p_hwfn);
 917                 if (rc)
 918                         goto alloc_err;
 919
 920                 /* SPQ, must follow ILT because initializes SPQ context */
 921                 rc = ecore_spq_alloc(p_hwfn);
 922                 if (rc)
 923                         goto alloc_err;
 924
 925                 /* SP status block allocation */
 926                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 927                                                            RESERVED_PTT_DPC);
 928
 929                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 930                 if (rc)
 931                         goto alloc_err;
 932
 933                 rc = ecore_iov_alloc(p_hwfn);
 934                 if (rc)
 935                         goto alloc_err;
 936
 937                 /* EQ */
 938                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 939                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
 940                         /* Calculate the EQ size
 941                          * ---------------------
 942                          * Each ICID may generate up to one event at a time i.e.
 943                          * the event must be handled/cleared before a new one
 944                          * can be generated. We calculate the sum of events per
 945                          * protocol and create an EQ deep enough to handle the
 946                          * worst case:
 947                          * - Core - according to SPQ.
 948                          * - RoCE - per QP there are a couple of ICIDs, one
 949                          *        responder and one requester, each can
 950                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
 951                          *        Each CQ can generate an EQE. There are 2 CQs
 952                          *        per QP => n_eqes_cq = 2 * n_qp.
 953                          *        Hence the RoCE total is 4 * n_qp or
 954                          *        2 * num_cons.
 955                          * - ENet - There can be up to two events per VF. One
 956                          *        for VF-PF channel and another for VF FLR
 957                          *        initial cleanup. The number of VFs is
 958                          *        bounded by MAX_NUM_VFS_BB, and is much
 959                          *        smaller than RoCE's so we avoid exact
 960                          *        calculation.
 961                          */
 962                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 963                                 num_cons =
 964                                     ecore_cxt_get_proto_cid_count(
 965                                                 p_hwfn,
 966                                                 PROTOCOLID_ROCE,
 967                                                 OSAL_NULL);
 968                                 num_cons *= 2;
 969                         } else {
 970                                 num_cons = ecore_cxt_get_proto_cid_count(
 971                                                 p_hwfn,
 972                                                 PROTOCOLID_IWARP,
 973                                                 OSAL_NULL);
 974                         }
 975                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 976                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 977                         num_cons =
 978                             ecore_cxt_get_proto_cid_count(p_hwfn,
 979                                                           PROTOCOLID_ISCSI,
 980                                                           OSAL_NULL);
 981                         n_eqes += 2 * num_cons;
 982                 }
 983
 984                 if (n_eqes > 0xFFFF) {
 985                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 986                                        "The maximum of a u16 chain is 0x%x\n",
 987                                n_eqes, 0xFFFF);
 988                         goto alloc_no_mem;
 989                 }
 990
 991                 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 992                 if (!p_eq)
 993                         goto alloc_no_mem;
 994                 p_hwfn->p_eq = p_eq;
 995
 996                 p_consq = ecore_consq_alloc(p_hwfn);
 997                 if (!p_consq)
 998                         goto alloc_no_mem;
 999                 p_hwfn->p_consq = p_consq;
1000
1001 #ifdef CONFIG_ECORE_LL2
1002                 if (p_hwfn->using_ll2) {
1003                         p_ll2_info = ecore_ll2_alloc(p_hwfn);
1004                         if (!p_ll2_info)
1005                                 goto alloc_no_mem;
1006                         p_hwfn->p_ll2_info = p_ll2_info;
1007                 }
1008 #endif
1009
1010                 /* DMA info initialization */
1011                 rc = ecore_dmae_info_alloc(p_hwfn);
1012                 if (rc) {
1013                         DP_NOTICE(p_hwfn, true,
1014                                   "Failed to allocate memory for dmae_info"
1015                                   " structure\n");
1016                         goto alloc_err;
1017                 }
1018
1019                 /* DCBX initialization */
1020                 rc = ecore_dcbx_info_alloc(p_hwfn);
1021                 if (rc) {
1022                         DP_NOTICE(p_hwfn, true,
1023                                   "Failed to allocate memory for dcbx structure\n");
1024                         goto alloc_err;
1025                 }
1026         }
1027
1028         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1029                                          sizeof(*p_dev->reset_stats));
1030         if (!p_dev->reset_stats) {
1031                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1032                 goto alloc_no_mem;
1033         }
1034
1035         return ECORE_SUCCESS;
1036
1037 alloc_no_mem:
1038         rc = ECORE_NOMEM;
1039 alloc_err:
1040         ecore_resc_free(p_dev);
1041         return rc;
1042 }
1043
1044 void ecore_resc_setup(struct ecore_dev *p_dev)
1045 {
1046         int i;
1047
1048         if (IS_VF(p_dev))
1049                 return;
1050
1051         for_each_hwfn(p_dev, i) {
1052                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1053
1054                 ecore_cxt_mngr_setup(p_hwfn);
1055                 ecore_spq_setup(p_hwfn);
1056                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
1057                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
1058
1059                 /* Read shadow of current MFW mailbox */
1060                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1061                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1062                             p_hwfn->mcp_info->mfw_mb_cur,
1063                             p_hwfn->mcp_info->mfw_mb_length);
1064
1065                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1066
1067                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1068 #ifdef CONFIG_ECORE_LL2
1069                 if (p_hwfn->using_ll2)
1070                         ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
1071 #endif
1072         }
1073 }
1074
1075 #define FINAL_CLEANUP_POLL_CNT  (100)
1076 #define FINAL_CLEANUP_POLL_TIME (10)
1077 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1078                                          struct ecore_ptt *p_ptt,
1079                                          u16 id, bool is_vf)
1080 {
1081         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1082         enum _ecore_status_t rc = ECORE_TIMEOUT;
1083
1084 #ifndef ASIC_ONLY
1085         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1086             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1087                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1088                 return ECORE_SUCCESS;
1089         }
1090 #endif
1091
1092         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1093             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1094
1095         if (is_vf)
1096                 id += 0x10;
1097
1098         command |= X_FINAL_CLEANUP_AGG_INT <<
1099             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1100         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1101         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1102         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1103
1104 /* Make sure notification is not set before initiating final cleanup */
1105
1106         if (REG_RD(p_hwfn, addr)) {
1107                 DP_NOTICE(p_hwfn, false,
1108                           "Unexpected; Found final cleanup notification");
1109                 DP_NOTICE(p_hwfn, false,
1110                           " before initiating final cleanup\n");
1111                 REG_WR(p_hwfn, addr, 0);
1112         }
1113
1114         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1115                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1116                    id, command);
1117
1118         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1119
1120         /* Poll until completion */
1121         while (!REG_RD(p_hwfn, addr) && count--)
1122                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1123
1124         if (REG_RD(p_hwfn, addr))
1125                 rc = ECORE_SUCCESS;
1126         else
1127                 DP_NOTICE(p_hwfn, true,
1128                           "Failed to receive FW final cleanup notification\n");
1129
1130         /* Cleanup afterwards */
1131         REG_WR(p_hwfn, addr, 0);
1132
1133         return rc;
1134 }
1135
1136 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1137 {
1138         int hw_mode = 0;
1139
1140         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1141                 hw_mode |= 1 << MODE_BB;
1142         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1143                 hw_mode |= 1 << MODE_K2;
1144         } else {
1145                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1146                           p_hwfn->p_dev->type);
1147                 return ECORE_INVAL;
1148         }
1149
1150         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1151         switch (p_hwfn->p_dev->num_ports_in_engines) {
1152         case 1:
1153                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1154                 break;
1155         case 2:
1156                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1157                 break;
1158         case 4:
1159                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1160                 break;
1161         default:
1162                 DP_NOTICE(p_hwfn, true,
1163                           "num_ports_in_engine = %d not supported\n",
1164                           p_hwfn->p_dev->num_ports_in_engines);
1165                 return ECORE_INVAL;
1166         }
1167
1168         switch (p_hwfn->p_dev->mf_mode) {
1169         case ECORE_MF_DEFAULT:
1170         case ECORE_MF_NPAR:
1171                 hw_mode |= 1 << MODE_MF_SI;
1172                 break;
1173         case ECORE_MF_OVLAN:
1174                 hw_mode |= 1 << MODE_MF_SD;
1175                 break;
1176         default:
1177                 DP_NOTICE(p_hwfn, true,
1178                           "Unsupported MF mode, init as DEFAULT\n");
1179                 hw_mode |= 1 << MODE_MF_SI;
1180         }
1181
1182 #ifndef ASIC_ONLY
1183         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1184                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1185                         hw_mode |= 1 << MODE_FPGA;
1186                 } else {
1187                         if (p_hwfn->p_dev->b_is_emul_full)
1188                                 hw_mode |= 1 << MODE_EMUL_FULL;
1189                         else
1190                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1191                 }
1192         } else
1193 #endif
1194                 hw_mode |= 1 << MODE_ASIC;
1195
1196         if (p_hwfn->p_dev->num_hwfns > 1)
1197                 hw_mode |= 1 << MODE_100G;
1198
1199         p_hwfn->hw_info.hw_mode = hw_mode;
1200
1201         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1202                    "Configuring function for hw_mode: 0x%08x\n",
1203                    p_hwfn->hw_info.hw_mode);
1204
1205         return ECORE_SUCCESS;
1206 }
1207
1208 #ifndef ASIC_ONLY
1209 /* MFW-replacement initializations for non-ASIC */
1210 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1211                                                struct ecore_ptt *p_ptt)
1212 {
1213         struct ecore_dev *p_dev = p_hwfn->p_dev;
1214         u32 pl_hv = 1;
1215         int i;
1216
1217         if (CHIP_REV_IS_EMUL(p_dev)) {
1218                 if (ECORE_IS_AH(p_dev))
1219                         pl_hv |= 0x600;
1220         }
1221
1222         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1223
1224         if (CHIP_REV_IS_EMUL(p_dev) &&
1225             (ECORE_IS_AH(p_dev)))
1226                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1227                          0x3ffffff);
1228
1229         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1230         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1231         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1232                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1233
1234         if (CHIP_REV_IS_EMUL(p_dev)) {
1235                 if (ECORE_IS_AH(p_dev)) {
1236                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1237                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1238                                  (p_dev->num_ports_in_engines >> 1));
1239
1240                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1241                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
1242                 }
1243         }
1244
1245         /* Poll on RBC */
1246         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1247         for (i = 0; i < 100; i++) {
1248                 OSAL_UDELAY(50);
1249                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1250                         break;
1251         }
1252         if (i == 100)
1253                 DP_NOTICE(p_hwfn, true,
1254                           "RBC done failed to complete in PSWRQ2\n");
1255
1256         return ECORE_SUCCESS;
1257 }
1258 #endif
1259
1260 /* Init run time data for all PFs and their VFs on an engine.
1261  * TBD - for VFs - Once we have parent PF info for each VF in
1262  * shmem available as CAU requires knowledge of parent PF for each VF.
1263  */
1264 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1265 {
1266         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1267         int i, sb_id;
1268
1269         for_each_hwfn(p_dev, i) {
1270                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1271                 struct ecore_igu_info *p_igu_info;
1272                 struct ecore_igu_block *p_block;
1273                 struct cau_sb_entry sb_entry;
1274
1275                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1276
1277                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1278                      sb_id++) {
1279                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1280
1281                         if (!p_block->is_pf)
1282                                 continue;
1283
1284                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1285                                                 p_block->function_id, 0, 0);
1286                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1287                 }
1288         }
1289 }
1290
1291 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1292                                                  struct ecore_ptt *p_ptt,
1293                                                  int hw_mode)
1294 {
1295         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1296         struct ecore_dev *p_dev = p_hwfn->p_dev;
1297         u8 vf_id, max_num_vfs;
1298         u16 num_pfs, pf_id;
1299         u32 concrete_fid;
1300         enum _ecore_status_t rc = ECORE_SUCCESS;
1301
1302         ecore_init_cau_rt_data(p_dev);
1303
1304         /* Program GTT windows */
1305         ecore_gtt_init(p_hwfn);
1306
1307 #ifndef ASIC_ONLY
1308         if (CHIP_REV_IS_EMUL(p_dev)) {
1309                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1310                 if (rc != ECORE_SUCCESS)
1311                         return rc;
1312         }
1313 #endif
1314
1315         if (p_hwfn->mcp_info) {
1316                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1317                         qm_info->pf_rl_en = 1;
1318                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1319                         qm_info->pf_wfq_en = 1;
1320         }
1321
1322         ecore_qm_common_rt_init(p_hwfn,
1323                                 p_dev->num_ports_in_engines,
1324                                 qm_info->max_phys_tcs_per_port,
1325                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1326                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1327                                 qm_info->qm_port_params);
1328
1329         ecore_cxt_hw_init_common(p_hwfn);
1330
1331         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1332         if (rc != ECORE_SUCCESS)
1333                 return rc;
1334
1335         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1336          * need to decide with which value, maybe runtime
1337          */
1338         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1339         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1340
1341         if (ECORE_IS_BB(p_dev)) {
1342                 /* Workaround clears ROCE search for all functions to prevent
1343                  * involving non initialized function in processing ROCE packet.
1344                  */
1345                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1346                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1347                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1348                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1349                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1350                 }
1351                 /* pretend to original PF */
1352                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1353         }
1354
1355         /* Workaround for avoiding CCFC execution error when getting packets
1356          * with CRC errors, and allowing instead the invoking of the FW error
1357          * handler.
1358          * This is not done inside the init tool since it currently can't
1359          * perform a pretending to VFs.
1360          */
1361         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1362         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1363                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1364                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1365                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1366                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1367                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1368                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1369         }
1370         /* pretend to original PF */
1371         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1372
1373         return rc;
1374 }
1375
1376 #ifndef ASIC_ONLY
1377 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1378 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1379
1380 #define PMEG_IF_BYTE_COUNT      8
1381
1382 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1383                              struct ecore_ptt *p_ptt,
1384                              u32 addr, u64 data, u8 reg_type, u8 port)
1385 {
1386         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1387                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1388                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1389                    (8 << PMEG_IF_BYTE_COUNT),
1390                    (reg_type << 25) | (addr << 8) | port,
1391                    (u32)((data >> 32) & 0xffffffff),
1392                    (u32)(data & 0xffffffff));
1393
1394         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1395                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1396                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1397         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1398                  (reg_type << 25) | (addr << 8) | port);
1399         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1400         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1401                  (data >> 32) & 0xffffffff);
1402 }
1403
1404 #define XLPORT_MODE_REG (0x20a)
1405 #define XLPORT_MAC_CONTROL (0x210)
1406 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1407 #define XLPORT_ENABLE_REG (0x20b)
1408
1409 #define XLMAC_CTRL (0x600)
1410 #define XLMAC_MODE (0x601)
1411 #define XLMAC_RX_MAX_SIZE (0x608)
1412 #define XLMAC_TX_CTRL (0x604)
1413 #define XLMAC_PAUSE_CTRL (0x60d)
1414 #define XLMAC_PFC_CTRL (0x60e)
1415
1416 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1417                                     struct ecore_ptt *p_ptt)
1418 {
1419         u8 loopback = 0, port = p_hwfn->port_id * 2;
1420
1421         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1422
1423         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1424         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1425                          port);
1426         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1427         /* XLMAC: SOFT RESET */
1428         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1429         /* XLMAC: Port Speed >= 10Gbps */
1430         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1431         /* XLMAC: Max Size */
1432         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1433         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1434                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1435                          0, port);
1436         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1437         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1438                          0x30ffffc000ULL, 0, port);
1439         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1440                          port); /* XLMAC: TX_EN, RX_EN */
1441         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1442         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1443                          0x1003 | (loopback << 2), 0, port);
1444         /* Enabled Parallel PFC interface */
1445         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1446
1447         /* XLPORT port enable */
1448         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1449 }
1450
1451 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1452                                        struct ecore_ptt *p_ptt)
1453 {
1454         u8 port = p_hwfn->port_id;
1455         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1456
1457         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1458
1459         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1460                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1461                  (port <<
1462                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1463                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1464
1465         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1466                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1467
1468         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1469                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1470
1471         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1472                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1473
1474         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1475                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1476
1477         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1478                  (0xA <<
1479                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1480                  (8 <<
1481                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1482
1483         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1484                  0xa853);
1485 }
1486
1487 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1488                                  struct ecore_ptt *p_ptt)
1489 {
1490         if (ECORE_IS_AH(p_hwfn->p_dev))
1491                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1492         else /* BB */
1493                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1494 }
1495
1496 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1497                                struct ecore_ptt *p_ptt,  u8 port)
1498 {
1499         int port_offset = port ? 0x800 : 0;
1500         u32 xmac_rxctrl = 0;
1501
1502         /* Reset of XMAC */
1503         /* FIXME: move to common start */
1504         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1505                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1506         OSAL_MSLEEP(1);
1507         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1508                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1509
1510         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1511
1512         /* Set the number of ports on the Warp Core to 10G */
1513         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1514
1515         /* Soft reset of XMAC */
1516         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1517                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1518         OSAL_MSLEEP(1);
1519         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1520                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1521
1522         /* FIXME: move to common end */
1523         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1524                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1525
1526         /* Set Max packet size: initialize XMAC block register for port 0 */
1527         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1528
1529         /* CRC append for Tx packets: init XMAC block register for port 1 */
1530         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1531
1532         /* Enable TX and RX: initialize XMAC block register for port 1 */
1533         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1534                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1535         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1536                                XMAC_REG_RX_CTRL_BB + port_offset);
1537         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1538         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1539 }
1540 #endif
1541
1542 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1543                                                struct ecore_ptt *p_ptt,
1544                                                int hw_mode)
1545 {
1546         enum _ecore_status_t rc = ECORE_SUCCESS;
1547
1548         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1549                             hw_mode);
1550         if (rc != ECORE_SUCCESS)
1551                 return rc;
1552 #ifndef ASIC_ONLY
1553         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1554                 return ECORE_SUCCESS;
1555
1556         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1557                 if (ECORE_IS_AH(p_hwfn->p_dev))
1558                         return ECORE_SUCCESS;
1559                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1560                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1561         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1562                 if (p_hwfn->p_dev->num_hwfns > 1) {
1563                         /* Activate OPTE in CMT */
1564                         u32 val;
1565
1566                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1567                         val |= 0x10;
1568                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1569                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1570                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1571                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1572                         ecore_wr(p_hwfn, p_ptt,
1573                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1574                         ecore_wr(p_hwfn, p_ptt,
1575                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1576                         ecore_wr(p_hwfn, p_ptt,
1577                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1578                                  0x55555555);
1579                 }
1580
1581                 ecore_emul_link_init(p_hwfn, p_ptt);
1582         } else {
1583                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1584         }
1585 #endif
1586
1587         return rc;
1588 }
1589
1590 static enum _ecore_status_t
1591 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1592                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1593 {
1594         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1595         u32 dpi_bit_shift, dpi_count;
1596         u32 min_dpis;
1597
1598         /* Calculate DPI size
1599          * ------------------
1600          * The PWM region contains Doorbell Pages. The first is reserverd for
1601          * the kernel for, e.g, L2. The others are free to be used by non-
1602          * trusted applications, typically from user space. Each page, called a
1603          * doorbell page is sectioned into windows that allow doorbells to be
1604          * issued in parallel by the kernel/application. The size of such a
1605          * window (a.k.a. WID) is 1kB.
1606          * Summary:
1607          *    1kB WID x N WIDS = DPI page size
1608          *    DPI page size x N DPIs = PWM region size
1609          * Notes:
1610          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1611          * in order to ensure that two applications won't share the same page.
1612          * It also must contain at least one WID per CPU to allow parallelism.
1613          * It also must be a power of 2, since it is stored as a bit shift.
1614          *
1615          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1616          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1617          * containing 4 WIDs.
1618          */
1619         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1620         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1621         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1622         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1623         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1624
1625         dpi_count = pwm_region_size / dpi_page_size;
1626
1627         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1628         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1629
1630         /* Update hwfn */
1631         p_hwfn->dpi_size = dpi_page_size;
1632         p_hwfn->dpi_count = dpi_count;
1633
1634         /* Update registers */
1635         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1636
1637         if (dpi_count < min_dpis)
1638                 return ECORE_NORESOURCES;
1639
1640         return ECORE_SUCCESS;
1641 }
1642
1643 enum ECORE_ROCE_EDPM_MODE {
1644         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1645         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1646         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1647 };
1648
1649 static enum _ecore_status_t
1650 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1651                               struct ecore_ptt *p_ptt)
1652 {
1653         u32 pwm_regsize, norm_regsize;
1654         u32 non_pwm_conn, min_addr_reg1;
1655         u32 db_bar_size, n_cpus;
1656         u32 roce_edpm_mode;
1657         u32 pf_dems_shift;
1658         int rc = ECORE_SUCCESS;
1659         u8 cond;
1660
1661         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1662         if (p_hwfn->p_dev->num_hwfns > 1)
1663                 db_bar_size /= 2;
1664
1665         /* Calculate doorbell regions
1666          * -----------------------------------
1667          * The doorbell BAR is made of two regions. The first is called normal
1668          * region and the second is called PWM region. In the normal region
1669          * each ICID has its own set of addresses so that writing to that
1670          * specific address identifies the ICID. In the Process Window Mode
1671          * region the ICID is given in the data written to the doorbell. The
1672          * above per PF register denotes the offset in the doorbell BAR in which
1673          * the PWM region begins.
1674          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1675          * non-PWM connection. The calculation below computes the total non-PWM
1676          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1677          * in units of 4,096 bytes.
1678          */
1679         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1680             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1681                                           OSAL_NULL) +
1682             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1683         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1684         min_addr_reg1 = norm_regsize / 4096;
1685         pwm_regsize = db_bar_size - norm_regsize;
1686
1687         /* Check that the normal and PWM sizes are valid */
1688         if (db_bar_size < norm_regsize) {
1689                 DP_ERR(p_hwfn->p_dev,
1690                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1691                        db_bar_size, norm_regsize);
1692                 return ECORE_NORESOURCES;
1693         }
1694         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1695                 DP_ERR(p_hwfn->p_dev,
1696                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1697                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1698                        norm_regsize);
1699                 return ECORE_NORESOURCES;
1700         }
1701
1702         /* Calculate number of DPIs */
1703         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1704         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1705             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1706                 /* Either EDPM is mandatory, or we are attempting to allocate a
1707                  * WID per CPU.
1708                  */
1709                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1710                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1711         }
1712
1713         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1714             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1715         if (cond || p_hwfn->dcbx_no_edpm) {
1716                 /* Either EDPM is disabled from user configuration, or it is
1717                  * disabled via DCBx, or it is not mandatory and we failed to
1718                  * allocated a WID per CPU.
1719                  */
1720                 n_cpus = 1;
1721                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1722
1723                 /* If we entered this flow due to DCBX then the DPM register is
1724                  * already configured.
1725                  */
1726         }
1727
1728         DP_INFO(p_hwfn,
1729                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1730                 norm_regsize, pwm_regsize);
1731         DP_INFO(p_hwfn,
1732                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1733                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1734                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1735                 "disabled" : "enabled");
1736
1737         /* Check return codes from above calls */
1738         if (rc) {
1739                 DP_ERR(p_hwfn,
1740                        "Failed to allocate enough DPIs\n");
1741                 return ECORE_NORESOURCES;
1742         }
1743
1744         /* Update hwfn */
1745         p_hwfn->dpi_start_offset = norm_regsize;
1746
1747         /* Update registers */
1748         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1749         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1750         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1751         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1752
1753         return ECORE_SUCCESS;
1754 }
1755
1756 static enum _ecore_status_t
1757 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1758                  struct ecore_ptt *p_ptt,
1759                  struct ecore_tunn_start_params *p_tunn,
1760                  int hw_mode,
1761                  bool b_hw_start,
1762                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1763 {
1764         u8 rel_pf_id = p_hwfn->rel_pf_id;
1765         u32 prs_reg;
1766         enum _ecore_status_t rc = ECORE_SUCCESS;
1767         u16 ctrl;
1768         int pos;
1769
1770         if (p_hwfn->mcp_info) {
1771                 struct ecore_mcp_function_info *p_info;
1772
1773                 p_info = &p_hwfn->mcp_info->func_info;
1774                 if (p_info->bandwidth_min)
1775                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1776
1777                 /* Update rate limit once we'll actually have a link */
1778                 p_hwfn->qm_info.pf_rl = 100000;
1779         }
1780         ecore_cxt_hw_init_pf(p_hwfn);
1781
1782         ecore_int_igu_init_rt(p_hwfn);
1783
1784         /* Set VLAN in NIG if needed */
1785         if (hw_mode & (1 << MODE_MF_SD)) {
1786                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1787                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1788                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1789                              p_hwfn->hw_info.ovlan);
1790         }
1791
1792         /* Enable classification by MAC if needed */
1793         if (hw_mode & (1 << MODE_MF_SI)) {
1794                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1795                            "Configuring TAGMAC_CLS_TYPE\n");
1796                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1797                              1);
1798         }
1799
1800         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1801         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1802                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1803         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1804                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1805         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1806
1807         /* perform debug configuration when chip is out of reset */
1808         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1809
1810         /* Cleanup chip from previous driver if such remains exist */
1811         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1812         if (rc != ECORE_SUCCESS) {
1813                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1814                 return rc;
1815         }
1816
1817         /* PF Init sequence */
1818         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1819         if (rc)
1820                 return rc;
1821
1822         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1823         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1824         if (rc)
1825                 return rc;
1826
1827         /* Pure runtime initializations - directly to the HW  */
1828         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1829
1830         /* PCI relaxed ordering causes a decrease in the performance on some
1831          * systems. Till a root cause is found, disable this attribute in the
1832          * PCI config space.
1833          */
1834         /* Not in use @DPDK
1835         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1836         * if (!pos) {
1837         *       DP_NOTICE(p_hwfn, true,
1838         *                 "Failed to find the PCIe Cap\n");
1839         *       return ECORE_IO;
1840         * }
1841         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1842         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1843         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1844         */
1845
1846         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1847         if (rc)
1848                 return rc;
1849         if (b_hw_start) {
1850                 /* enable interrupts */
1851                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1852                 if (rc != ECORE_SUCCESS)
1853                         return rc;
1854
1855                 /* send function start command */
1856                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1857                                        allow_npar_tx_switch);
1858                 if (rc) {
1859                         DP_NOTICE(p_hwfn, true,
1860                                   "Function start ramrod failed\n");
1861                 } else {
1862                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1863                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1864                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1865
1866                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1867                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1868                                          (1 << 2));
1869                                 ecore_wr(p_hwfn, p_ptt,
1870                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1871                                     0x100);
1872                         }
1873                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1874                                    "PRS_REG_SEARCH registers after start PFn\n");
1875                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1876                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1877                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1878                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1879                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1880                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1881                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1882                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1883                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1884                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1885                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1886                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1887                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1888                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1889                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1890                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1891                                    prs_reg);
1892                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1893                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1894                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1895                 }
1896         }
1897         return rc;
1898 }
1899
1900 static enum _ecore_status_t
1901 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1902                       struct ecore_ptt *p_ptt, u8 enable)
1903 {
1904         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1905
1906         /* Change PF in PXP */
1907         ecore_wr(p_hwfn, p_ptt,
1908                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1909
1910         /* wait until value is set - try for 1 second every 50us */
1911         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1912                 val = ecore_rd(p_hwfn, p_ptt,
1913                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1914                 if (val == set_val)
1915                         break;
1916
1917                 OSAL_UDELAY(50);
1918         }
1919
1920         if (val != set_val) {
1921                 DP_NOTICE(p_hwfn, true,
1922                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1923                 return ECORE_UNKNOWN_ERROR;
1924         }
1925
1926         return ECORE_SUCCESS;
1927 }
1928
1929 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1930                                   struct ecore_ptt *p_main_ptt)
1931 {
1932         /* Read shadow of current MFW mailbox */
1933         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1934         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1935                     p_hwfn->mcp_info->mfw_mb_cur,
1936                     p_hwfn->mcp_info->mfw_mb_length);
1937 }
1938
1939 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1940                                    struct ecore_hw_init_params *p_params)
1941 {
1942         enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1943         u32 load_code, param, drv_mb_param;
1944         bool b_default_mtu = true;
1945         struct ecore_hwfn *p_hwfn;
1946         int i;
1947
1948         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1949             (p_dev->num_hwfns > 1)) {
1950                 DP_NOTICE(p_dev, false,
1951                           "MSI mode is not supported for CMT devices\n");
1952                 return ECORE_INVAL;
1953         }
1954
1955         if (IS_PF(p_dev)) {
1956                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1957                 if (rc != ECORE_SUCCESS)
1958                         return rc;
1959         }
1960
1961         for_each_hwfn(p_dev, i) {
1962                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1963
1964                 /* If management didn't provide a default, set one of our own */
1965                 if (!p_hwfn->hw_info.mtu) {
1966                         p_hwfn->hw_info.mtu = 1500;
1967                         b_default_mtu = false;
1968                 }
1969
1970                 if (IS_VF(p_dev)) {
1971                         p_hwfn->b_int_enabled = 1;
1972                         continue;
1973                 }
1974
1975                 /* Enable DMAE in PXP */
1976                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1977                 if (rc != ECORE_SUCCESS)
1978                         return rc;
1979
1980                 rc = ecore_calc_hw_mode(p_hwfn);
1981                 if (rc != ECORE_SUCCESS)
1982                         return rc;
1983
1984                 /* @@@TBD need to add here:
1985                  * Check for fan failure
1986                  * Prev_unload
1987                  */
1988                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1989                 if (rc) {
1990                         DP_NOTICE(p_hwfn, true,
1991                                   "Failed sending LOAD_REQ command\n");
1992                         return rc;
1993                 }
1994
1995                 /* CQ75580:
1996                  * When coming back from hiberbate state, the registers from
1997                  * which shadow is read initially are not initialized. It turns
1998                  * out that these registers get initialized during the call to
1999                  * ecore_mcp_load_req request. So we need to reread them here
2000                  * to get the proper shadow register value.
2001                  * Note: This is a workaround for the missing MFW
2002                  * initialization. It may be removed once the implementation
2003                  * is done.
2004                  */
2005                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2006
2007                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2008                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
2009                            rc, load_code);
2010
2011                 /* Only relevant for recovery:
2012                  * Clear the indication after the LOAD_REQ command is responded
2013                  * by the MFW.
2014                  */
2015                 p_dev->recov_in_prog = false;
2016
2017                 p_hwfn->first_on_engine = (load_code ==
2018                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2019
2020                 if (!qm_lock_init) {
2021                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2022                         qm_lock_init = true;
2023                 }
2024
2025                 switch (load_code) {
2026                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2027                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2028                                                   p_hwfn->hw_info.hw_mode);
2029                         if (rc)
2030                                 break;
2031                         /* Fall into */
2032                 case FW_MSG_CODE_DRV_LOAD_PORT:
2033                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2034                                                 p_hwfn->hw_info.hw_mode);
2035                         if (rc)
2036                                 break;
2037                         /* Fall into */
2038                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2039                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2040                                               p_params->p_tunn,
2041                                               p_hwfn->hw_info.hw_mode,
2042                                               p_params->b_hw_start,
2043                                               p_params->int_mode,
2044                                               p_params->allow_npar_tx_switch);
2045                         break;
2046                 default:
2047                         rc = ECORE_NOTIMPL;
2048                         break;
2049                 }
2050
2051                 if (rc != ECORE_SUCCESS)
2052                         DP_NOTICE(p_hwfn, true,
2053                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2054                                   load_code, rc);
2055
2056                 /* ACK mfw regardless of success or failure of initialization */
2057                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2058                                        DRV_MSG_CODE_LOAD_DONE,
2059                                        0, &load_code, &param);
2060                 if (rc != ECORE_SUCCESS)
2061                         return rc;
2062                 if (mfw_rc != ECORE_SUCCESS) {
2063                         DP_NOTICE(p_hwfn, true,
2064                                   "Failed sending LOAD_DONE command\n");
2065                         return mfw_rc;
2066                 }
2067
2068                 /* send DCBX attention request command */
2069                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2070                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2071                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2072                                        DRV_MSG_CODE_SET_DCBX,
2073                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2074                                        &load_code, &param);
2075                 if (mfw_rc != ECORE_SUCCESS) {
2076                         DP_NOTICE(p_hwfn, true,
2077                                   "Failed to send DCBX attention request\n");
2078                         return mfw_rc;
2079                 }
2080
2081                 p_hwfn->hw_init_done = true;
2082         }
2083
2084         if (IS_PF(p_dev)) {
2085                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2086                 drv_mb_param = (FW_MAJOR_VERSION << 24) |
2087                                (FW_MINOR_VERSION << 16) |
2088                                (FW_REVISION_VERSION << 8) |
2089                                (FW_ENGINEERING_VERSION);
2090                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2091                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2092                                    drv_mb_param, &load_code, &param);
2093                 if (rc != ECORE_SUCCESS)
2094                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2095
2096                 if (!b_default_mtu)
2097                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2098                                                       p_hwfn->hw_info.mtu);
2099                 if (rc != ECORE_SUCCESS)
2100                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2101
2102                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2103                                                       p_hwfn->p_main_ptt,
2104                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2105                 if (rc != ECORE_SUCCESS)
2106                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2107         }
2108
2109         return rc;
2110 }
2111
2112 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2113 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2114                                  struct ecore_hwfn *p_hwfn,
2115                                  struct ecore_ptt *p_ptt)
2116 {
2117         int i;
2118
2119         /* close timers */
2120         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2121         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2122         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2123                                                                         i++) {
2124                 if ((!ecore_rd(p_hwfn, p_ptt,
2125                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2126                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2127                         break;
2128
2129                 /* Dependent on number of connection/tasks, possibly
2130                  * 1ms sleep is required between polls
2131                  */
2132                 OSAL_MSLEEP(1);
2133         }
2134
2135         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2136                 return;
2137
2138         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2139                   " [Connection %02x Tasks %02x]\n",
2140                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2141                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2142 }
2143
2144 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2145 {
2146         int j;
2147
2148         for_each_hwfn(p_dev, j) {
2149                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2150                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2151
2152                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2153         }
2154 }
2155
2156 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2157 {
2158         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
2159         int j;
2160
2161         for_each_hwfn(p_dev, j) {
2162                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2163                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2164
2165                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2166
2167                 if (IS_VF(p_dev)) {
2168                         ecore_vf_pf_int_cleanup(p_hwfn);
2169                         continue;
2170                 }
2171
2172                 /* mark the hw as uninitialized... */
2173                 p_hwfn->hw_init_done = false;
2174
2175                 rc = ecore_sp_pf_stop(p_hwfn);
2176                 if (rc)
2177                         DP_NOTICE(p_hwfn, true,
2178                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
2179
2180                 /* perform debug action after PF stop was sent */
2181                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
2182
2183                 /* close NIG to BRB gate */
2184                 ecore_wr(p_hwfn, p_ptt,
2185                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2186
2187                 /* close parser */
2188                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2189                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2190                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2191                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2192                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2193
2194                 /* @@@TBD - clean transmission queues (5.b) */
2195                 /* @@@TBD - clean BTB (5.c) */
2196
2197                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2198
2199                 /* @@@TBD - verify DMAE requests are done (8) */
2200
2201                 /* Disable Attention Generation */
2202                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2203                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2204                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2205                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2206                 /* Need to wait 1ms to guarantee SBs are cleared */
2207                 OSAL_MSLEEP(1);
2208         }
2209
2210         if (IS_PF(p_dev)) {
2211                 /* Disable DMAE in PXP - in CMT, this should only be done for
2212                  * first hw-function, and only after all transactions have
2213                  * stopped for all active hw-functions.
2214                  */
2215                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
2216                                              p_dev->hwfns[0].p_main_ptt, false);
2217                 if (t_rc != ECORE_SUCCESS)
2218                         rc = t_rc;
2219         }
2220
2221         return rc;
2222 }
2223
2224 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2225 {
2226         int j;
2227
2228         for_each_hwfn(p_dev, j) {
2229                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2230                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2231
2232                 if (IS_VF(p_dev)) {
2233                         ecore_vf_pf_int_cleanup(p_hwfn);
2234                         continue;
2235                 }
2236
2237                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2238                            "Shutting down the fastpath\n");
2239
2240                 ecore_wr(p_hwfn, p_ptt,
2241                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2242
2243                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2244                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2245                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2246                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2247                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2248
2249                 /* @@@TBD - clean transmission queues (5.b) */
2250                 /* @@@TBD - clean BTB (5.c) */
2251
2252                 /* @@@TBD - verify DMAE requests are done (8) */
2253
2254                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2255                 /* Need to wait 1ms to guarantee SBs are cleared */
2256                 OSAL_MSLEEP(1);
2257         }
2258 }
2259
2260 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2261 {
2262         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2263
2264         if (IS_VF(p_hwfn->p_dev))
2265                 return;
2266
2267         /* If roce info is allocated it means roce is initialized and should
2268          * be enabled in searcher.
2269          */
2270         if (p_hwfn->p_rdma_info) {
2271                 if (p_hwfn->b_rdma_enabled_in_prs)
2272                         ecore_wr(p_hwfn, p_ptt,
2273                                  p_hwfn->rdma_prs_search_reg, 0x1);
2274                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2275         }
2276
2277         /* Re-open incoming traffic */
2278         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2279                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2280 }
2281
2282 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
2283                                              struct ecore_ptt *p_ptt, u32 reg,
2284                                              bool expected)
2285 {
2286         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
2287
2288         if (assert_val != expected) {
2289                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
2290                           reg, expected);
2291                 return ECORE_UNKNOWN_ERROR;
2292         }
2293
2294         return 0;
2295 }
2296
2297 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
2298 {
2299         enum _ecore_status_t rc = ECORE_SUCCESS;
2300         u32 unload_resp, unload_param;
2301         int i;
2302
2303         for_each_hwfn(p_dev, i) {
2304                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2305
2306                 if (IS_VF(p_dev)) {
2307                         rc = ecore_vf_pf_reset(p_hwfn);
2308                         if (rc)
2309                                 return rc;
2310                         continue;
2311                 }
2312
2313                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
2314
2315                 /* Check for incorrect states */
2316                 if (!p_dev->recov_in_prog) {
2317                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2318                                          QM_REG_USG_CNT_PF_TX, 0);
2319                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2320                                          QM_REG_USG_CNT_PF_OTHER, 0);
2321                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2322                 }
2323
2324                 /* Disable PF in HW blocks */
2325                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2326                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2327
2328                 if (p_dev->recov_in_prog) {
2329                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2330                                    "Recovery is in progress -> skip sending unload_req/done\n");
2331                         break;
2332                 }
2333
2334                 /* Send unload command to MCP */
2335                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2336                                    DRV_MSG_CODE_UNLOAD_REQ,
2337                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
2338                                    &unload_resp, &unload_param);
2339                 if (rc != ECORE_SUCCESS) {
2340                         DP_NOTICE(p_hwfn, true,
2341                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
2342                         /* @@TBD - what to do? for now, assume ENG. */
2343                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2344                 }
2345
2346                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2347                                    DRV_MSG_CODE_UNLOAD_DONE,
2348                                    0, &unload_resp, &unload_param);
2349                 if (rc != ECORE_SUCCESS) {
2350                         DP_NOTICE(p_hwfn,
2351                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2352                         /* @@@TBD - Should it really ASSERT here ? */
2353                         return rc;
2354                 }
2355         }
2356
2357         return rc;
2358 }
2359
2360 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2361 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2362 {
2363         ecore_ptt_pool_free(p_hwfn);
2364         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2365 }
2366
2367 /* Setup bar access */
2368 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2369 {
2370         /* clear indirect access */
2371         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2372                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2373                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2374                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2375                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2376                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2377                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2378                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2379                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2380         } else {
2381                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2382                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2383                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2384                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2385                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2386                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2387                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2388                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2389         }
2390
2391         /* Clean Previous errors if such exist */
2392         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2393                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2394
2395         /* enable internal target-read */
2396         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2397                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2398 }
2399
2400 static void get_function_id(struct ecore_hwfn *p_hwfn)
2401 {
2402         /* ME Register */
2403         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2404                                                   PXP_PF_ME_OPAQUE_ADDR);
2405
2406         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2407
2408         /* Bits 16-19 from the ME registers are the pf_num */
2409         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2410         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2411                                       PXP_CONCRETE_FID_PFID);
2412         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2413                                     PXP_CONCRETE_FID_PORT);
2414
2415         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2416                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2417                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2418 }
2419
2420 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2421 {
2422         u32 *feat_num = p_hwfn->hw_info.feat_num;
2423         struct ecore_sb_cnt_info sb_cnt_info;
2424         int num_features = 1;
2425
2426         /* L2 Queues require each: 1 status block. 1 L2 queue */
2427         feat_num[ECORE_PF_L2_QUE] =
2428             OSAL_MIN_T(u32,
2429                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2430                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2431
2432         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2433         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2434         feat_num[ECORE_VF_L2_QUE] =
2435                 OSAL_MIN_T(u32,
2436                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2437                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2438                            sb_cnt_info.sb_iov_cnt);
2439
2440         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2441                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2442         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2443                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2444
2445         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2446                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2447                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2448                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2449                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2450                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2451                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2452                    RESC_NUM(p_hwfn, ECORE_SB));
2453 }
2454
2455 static enum resource_id_enum
2456 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2457 {
2458         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2459
2460         switch (res_id) {
2461         case ECORE_SB:
2462                 mfw_res_id = RESOURCE_NUM_SB_E;
2463                 break;
2464         case ECORE_L2_QUEUE:
2465                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2466                 break;
2467         case ECORE_VPORT:
2468                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2469                 break;
2470         case ECORE_RSS_ENG:
2471                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2472                 break;
2473         case ECORE_PQ:
2474                 mfw_res_id = RESOURCE_NUM_PQ_E;
2475                 break;
2476         case ECORE_RL:
2477                 mfw_res_id = RESOURCE_NUM_RL_E;
2478                 break;
2479         case ECORE_MAC:
2480         case ECORE_VLAN:
2481                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2482                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2483                 break;
2484         case ECORE_ILT:
2485                 mfw_res_id = RESOURCE_ILT_E;
2486                 break;
2487         case ECORE_LL2_QUEUE:
2488                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2489                 break;
2490         case ECORE_RDMA_CNQ_RAM:
2491         case ECORE_CMDQS_CQS:
2492                 /* CNQ/CMDQS are the same resource */
2493                 mfw_res_id = RESOURCE_CQS_E;
2494                 break;
2495         case ECORE_RDMA_STATS_QUEUE:
2496                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2497                 break;
2498         default:
2499                 break;
2500         }
2501
2502         return mfw_res_id;
2503 }
2504
2505 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2506                                       enum ecore_resources res_id)
2507 {
2508         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2509         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2510         struct ecore_sb_cnt_info sb_cnt_info;
2511         u32 dflt_resc_num = 0;
2512
2513         switch (res_id) {
2514         case ECORE_SB:
2515                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2516                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2517                 dflt_resc_num = sb_cnt_info.sb_cnt;
2518                 break;
2519         case ECORE_L2_QUEUE:
2520                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2521                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2522                 break;
2523         case ECORE_VPORT:
2524                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2525                                  MAX_NUM_VPORTS_BB) / num_funcs;
2526                 break;
2527         case ECORE_RSS_ENG:
2528                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2529                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2530                 break;
2531         case ECORE_PQ:
2532                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2533                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2534                 break;
2535         case ECORE_RL:
2536                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2537                 break;
2538         case ECORE_MAC:
2539         case ECORE_VLAN:
2540                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2541                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2542                 break;
2543         case ECORE_ILT:
2544                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2545                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2546                 break;
2547         case ECORE_LL2_QUEUE:
2548                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2549                 break;
2550         case ECORE_RDMA_CNQ_RAM:
2551         case ECORE_CMDQS_CQS:
2552                 /* CNQ/CMDQS are the same resource */
2553                 /* @DPDK */
2554                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2555                 break;
2556         case ECORE_RDMA_STATS_QUEUE:
2557                 /* @DPDK */
2558                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2559                                  MAX_NUM_VPORTS_BB) / num_funcs;
2560                 break;
2561         default:
2562                 break;
2563         }
2564
2565         return dflt_resc_num;
2566 }
2567
2568 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2569 {
2570         switch (res_id) {
2571         case ECORE_SB:
2572                 return "SB";
2573         case ECORE_L2_QUEUE:
2574                 return "L2_QUEUE";
2575         case ECORE_VPORT:
2576                 return "VPORT";
2577         case ECORE_RSS_ENG:
2578                 return "RSS_ENG";
2579         case ECORE_PQ:
2580                 return "PQ";
2581         case ECORE_RL:
2582                 return "RL";
2583         case ECORE_MAC:
2584                 return "MAC";
2585         case ECORE_VLAN:
2586                 return "VLAN";
2587         case ECORE_RDMA_CNQ_RAM:
2588                 return "RDMA_CNQ_RAM";
2589         case ECORE_ILT:
2590                 return "ILT";
2591         case ECORE_LL2_QUEUE:
2592                 return "LL2_QUEUE";
2593         case ECORE_CMDQS_CQS:
2594                 return "CMDQS_CQS";
2595         case ECORE_RDMA_STATS_QUEUE:
2596                 return "RDMA_STATS_QUEUE";
2597         default:
2598                 return "UNKNOWN_RESOURCE";
2599         }
2600 }
2601
2602 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2603                                                    enum ecore_resources res_id,
2604                                                    bool drv_resc_alloc)
2605 {
2606         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2607         u32 *p_resc_num, *p_resc_start;
2608         struct resource_info resc_info;
2609         enum _ecore_status_t rc;
2610
2611         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2612         p_resc_start = &RESC_START(p_hwfn, res_id);
2613
2614         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2615         if (!dflt_resc_num) {
2616                 DP_ERR(p_hwfn,
2617                        "Failed to get default amount for resource %d [%s]\n",
2618                         res_id, ecore_hw_get_resc_name(res_id));
2619                 return ECORE_INVAL;
2620         }
2621         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2622
2623 #ifndef ASIC_ONLY
2624         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2625                 *p_resc_num = dflt_resc_num;
2626                 *p_resc_start = dflt_resc_start;
2627                 goto out;
2628         }
2629 #endif
2630
2631         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2632         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2633         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2634                 DP_ERR(p_hwfn,
2635                        "Failed to match resource %d with MFW resources\n",
2636                        res_id);
2637                 return ECORE_INVAL;
2638         }
2639
2640         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2641                                      &mcp_resp, &mcp_param);
2642         if (rc != ECORE_SUCCESS) {
2643                 DP_NOTICE(p_hwfn, true,
2644                           "MFW response failure for an allocation request for"
2645                           " resource %d [%s]\n",
2646                           res_id, ecore_hw_get_resc_name(res_id));
2647                 return rc;
2648         }
2649
2650         /* Default driver values are applied in the following cases:
2651          * - The resource allocation MB command is not supported by the MFW
2652          * - There is an internal error in the MFW while processing the request
2653          * - The resource ID is unknown to the MFW
2654          */
2655         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2656             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2657                 /* @DPDK */
2658                 DP_INFO(p_hwfn,
2659                         "Resource %d [%s]: No allocation info was received"
2660                         " [mcp_resp 0x%x]. Applying default values"
2661                         " [num %d, start %d].\n",
2662                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2663                         dflt_resc_num, dflt_resc_start);
2664
2665                 *p_resc_num = dflt_resc_num;
2666                 *p_resc_start = dflt_resc_start;
2667                 goto out;
2668         }
2669
2670         /* TBD - remove this when revising the handling of the SB resource */
2671         if (res_id == ECORE_SB) {
2672                 /* Excluding the slowpath SB */
2673                 resc_info.size -= 1;
2674                 resc_info.offset -= p_hwfn->enabled_func_idx;
2675         }
2676
2677         *p_resc_num = resc_info.size;
2678         *p_resc_start = resc_info.offset;
2679
2680         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2681                 DP_INFO(p_hwfn,
2682                         "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2683                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2684                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2685                         drv_resc_alloc ? " - Applying default values" : "");
2686                 if (drv_resc_alloc) {
2687                         *p_resc_num = dflt_resc_num;
2688                         *p_resc_start = dflt_resc_start;
2689                 }
2690         }
2691 out:
2692         return ECORE_SUCCESS;
2693 }
2694
2695 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2696                                               bool drv_resc_alloc)
2697 {
2698         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2699         enum _ecore_status_t rc;
2700         u8 res_id;
2701 #ifndef ASIC_ONLY
2702         u32 *resc_start = p_hwfn->hw_info.resc_start;
2703         u32 *resc_num = p_hwfn->hw_info.resc_num;
2704         /* For AH, an equal share of the ILT lines between the maximal number of
2705          * PFs is not enough for RoCE. This would be solved by the future
2706          * resource allocation scheme, but isn't currently present for
2707          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2708          * to work - the BB number of ILT lines divided by its max PFs number.
2709          */
2710         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2711 #endif
2712
2713         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2714                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2715                 if (rc != ECORE_SUCCESS)
2716                         return rc;
2717         }
2718
2719 #ifndef ASIC_ONLY
2720         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2721                 /* Reduced build contains less PQs */
2722                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2723                         resc_num[ECORE_PQ] = 32;
2724                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2725                             p_hwfn->enabled_func_idx;
2726                 }
2727
2728                 /* For AH emulation, since we have a possible maximal number of
2729                  * 16 enabled PFs, in case there are not enough ILT lines -
2730                  * allocate only first PF as RoCE and have all the other ETH
2731                  * only with less ILT lines.
2732                  */
2733                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2734                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2735                                                          resc_num[ECORE_ILT],
2736                                                          roce_min_ilt_lines);
2737         }
2738
2739         /* Correct the common ILT calculation if PF0 has more */
2740         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2741             p_hwfn->p_dev->b_is_emul_full &&
2742             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2743                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2744                     resc_num[ECORE_ILT];
2745 #endif
2746
2747         /* Sanity for ILT */
2748         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2749             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2750                 DP_NOTICE(p_hwfn, true,
2751                           "Can't assign ILT pages [%08x,...,%08x]\n",
2752                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2753                                                                   ECORE_ILT) -
2754                           1);
2755                 return ECORE_INVAL;
2756         }
2757
2758         ecore_hw_set_feat(p_hwfn);
2759
2760         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2761                    "The numbers for each resource are:\n");
2762         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2763                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2764                            ecore_hw_get_resc_name(res_id),
2765                            RESC_NUM(p_hwfn, res_id),
2766                            RESC_START(p_hwfn, res_id));
2767
2768         return ECORE_SUCCESS;
2769 }
2770
2771 static enum _ecore_status_t
2772 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2773                       struct ecore_ptt *p_ptt,
2774                       struct ecore_hw_prepare_params *p_params)
2775 {
2776         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2777         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2778         struct ecore_mcp_link_params *link;
2779         enum _ecore_status_t rc;
2780
2781         /* Read global nvm_cfg address */
2782         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2783
2784         /* Verify MCP has initialized it */
2785         if (!nvm_cfg_addr) {
2786                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2787                 if (p_params->b_relaxed_probe)
2788                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2789                 return ECORE_INVAL;
2790         }
2791
2792 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2793
2794         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2795
2796         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2797             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2798                                                        core_cfg);
2799
2800         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2801
2802         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2803                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2804         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2805                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2806                 break;
2807         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2808                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2809                 break;
2810         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2811                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2812                 break;
2813         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2814                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2815                 break;
2816         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2817                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2818                 break;
2819         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2820                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2821                 break;
2822         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2823                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2824                 break;
2825         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2826                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2827                 break;
2828         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2829                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2830                 break;
2831         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2832                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2833                 break;
2834         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2835                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2836                 break;
2837         default:
2838                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2839                           core_cfg);
2840                 break;
2841         }
2842
2843         /* Read DCBX configuration */
2844         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2845                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2846         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2847                              port_cfg_addr +
2848                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2849         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2850                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2851         switch (dcbx_mode) {
2852         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2853                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2854                 break;
2855         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2856                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2857                 break;
2858         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2859                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2860                 break;
2861         default:
2862                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2863         }
2864
2865         /* Read default link configuration */
2866         link = &p_hwfn->mcp_info->link_input;
2867         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2868             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2869         link_temp = ecore_rd(p_hwfn, p_ptt,
2870                              port_cfg_addr +
2871                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2872         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2873         link->speed.advertised_speeds = link_temp;
2874
2875         link_temp = link->speed.advertised_speeds;
2876         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2877
2878         link_temp = ecore_rd(p_hwfn, p_ptt,
2879                              port_cfg_addr +
2880                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2881         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2882                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2883         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2884                 link->speed.autoneg = true;
2885                 break;
2886         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2887                 link->speed.forced_speed = 1000;
2888                 break;
2889         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2890                 link->speed.forced_speed = 10000;
2891                 break;
2892         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2893                 link->speed.forced_speed = 25000;
2894                 break;
2895         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2896                 link->speed.forced_speed = 40000;
2897                 break;
2898         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2899                 link->speed.forced_speed = 50000;
2900                 break;
2901         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2902                 link->speed.forced_speed = 100000;
2903                 break;
2904         default:
2905                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2906         }
2907
2908         p_hwfn->mcp_info->link_capabilities.default_speed =
2909             link->speed.forced_speed;
2910         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2911             link->speed.autoneg;
2912
2913         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2914         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2915         link->pause.autoneg = !!(link_temp &
2916                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2917         link->pause.forced_rx = !!(link_temp &
2918                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2919         link->pause.forced_tx = !!(link_temp &
2920                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2921         link->loopback_mode = 0;
2922
2923         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2924                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2925                    link->speed.forced_speed, link->speed.advertised_speeds,
2926                    link->speed.autoneg, link->pause.autoneg);
2927
2928         /* Read Multi-function information from shmem */
2929         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2930             OFFSETOF(struct nvm_cfg1, glob) +
2931             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2932
2933         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2934
2935         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2936             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2937
2938         switch (mf_mode) {
2939         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2940                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2941                 break;
2942         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2943                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2944                 break;
2945         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2946                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2947                 break;
2948         }
2949         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2950                 p_hwfn->p_dev->mf_mode);
2951
2952         /* Read Multi-function information from shmem */
2953         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2954             OFFSETOF(struct nvm_cfg1, glob) +
2955             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2956
2957         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2958         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2959                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2960                              &p_hwfn->hw_info.device_capabilities);
2961         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2962                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2963                              &p_hwfn->hw_info.device_capabilities);
2964         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2965                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2966                              &p_hwfn->hw_info.device_capabilities);
2967         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2968                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2969                              &p_hwfn->hw_info.device_capabilities);
2970         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2971                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2972                              &p_hwfn->hw_info.device_capabilities);
2973
2974         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2975         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
2976                 rc = ECORE_SUCCESS;
2977                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
2978         }
2979
2980         return rc;
2981 }
2982
2983 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2984                                 struct ecore_ptt *p_ptt)
2985 {
2986         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2987         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2988         struct ecore_dev *p_dev = p_hwfn->p_dev;
2989
2990         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2991
2992         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2993          * in the other bits are selected.
2994          * Bits 1-15 are for functions 1-15, respectively, and their value is
2995          * '0' only for enabled functions (function 0 always exists and
2996          * enabled).
2997          * In case of CMT in BB, only the "even" functions are enabled, and thus
2998          * the number of functions for both hwfns is learnt from the same bits.
2999          */
3000         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3001                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3002                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3003         } else { /* E5 */
3004                 reg_function_hide = 0;
3005         }
3006
3007         if (reg_function_hide & 0x1) {
3008                 if (ECORE_IS_BB(p_dev)) {
3009                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3010                                 num_funcs = 0;
3011                                 eng_mask = 0xaaaa;
3012                         } else {
3013                                 num_funcs = 1;
3014                                 eng_mask = 0x5554;
3015                         }
3016                 } else {
3017                         num_funcs = 1;
3018                         eng_mask = 0xfffe;
3019                 }
3020
3021                 /* Get the number of the enabled functions on the engine */
3022                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3023                 while (tmp) {
3024                         if (tmp & 0x1)
3025                                 num_funcs++;
3026                         tmp >>= 0x1;
3027                 }
3028
3029                 /* Get the PF index within the enabled functions */
3030                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3031                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3032                 while (tmp) {
3033                         if (tmp & 0x1)
3034                                 enabled_func_idx--;
3035                         tmp >>= 0x1;
3036                 }
3037         }
3038
3039         p_hwfn->num_funcs_on_engine = num_funcs;
3040         p_hwfn->enabled_func_idx = enabled_func_idx;
3041
3042 #ifndef ASIC_ONLY
3043         if (CHIP_REV_IS_FPGA(p_dev)) {
3044                 DP_NOTICE(p_hwfn, false,
3045                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3046                 p_hwfn->num_funcs_on_engine = 4;
3047         }
3048 #endif
3049
3050         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3051                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3052                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3053                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3054 }
3055
3056 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3057                                       struct ecore_ptt *p_ptt)
3058 {
3059         u32 port_mode;
3060
3061 #ifndef ASIC_ONLY
3062         /* Read the port mode */
3063         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3064                 port_mode = 4;
3065         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3066                  (p_hwfn->p_dev->num_hwfns > 1))
3067                 /* In CMT on emulation, assume 1 port */
3068                 port_mode = 1;
3069         else
3070 #endif
3071         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3072
3073         if (port_mode < 3) {
3074                 p_hwfn->p_dev->num_ports_in_engines = 1;
3075         } else if (port_mode <= 5) {
3076                 p_hwfn->p_dev->num_ports_in_engines = 2;
3077         } else {
3078                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3079                           p_hwfn->p_dev->num_ports_in_engines);
3080
3081                 /* Default num_ports_in_engines to something */
3082                 p_hwfn->p_dev->num_ports_in_engines = 1;
3083         }
3084 }
3085
3086 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3087                                          struct ecore_ptt *p_ptt)
3088 {
3089         u32 port;
3090         int i;
3091
3092         p_hwfn->p_dev->num_ports_in_engines = 0;
3093
3094 #ifndef ASIC_ONLY
3095         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3096                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3097                 switch ((port & 0xf000) >> 12) {
3098                 case 1:
3099                         p_hwfn->p_dev->num_ports_in_engines = 1;
3100                         break;
3101                 case 3:
3102                         p_hwfn->p_dev->num_ports_in_engines = 2;
3103                         break;
3104                 case 0xf:
3105                         p_hwfn->p_dev->num_ports_in_engines = 4;
3106                         break;
3107                 default:
3108                         DP_NOTICE(p_hwfn, false,
3109                                   "Unknown port mode in ECO_RESERVED %08x\n",
3110                                   port);
3111                 }
3112         } else
3113 #endif
3114                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3115                         port = ecore_rd(p_hwfn, p_ptt,
3116                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3117                                         (i * 4));
3118                         if (port & 1)
3119                                 p_hwfn->p_dev->num_ports_in_engines++;
3120                 }
3121 }
3122
3123 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3124                                    struct ecore_ptt *p_ptt)
3125 {
3126         if (ECORE_IS_BB(p_hwfn->p_dev))
3127                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3128         else
3129                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3130 }
3131
3132 static enum _ecore_status_t
3133 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3134                   enum ecore_pci_personality personality,
3135                   struct ecore_hw_prepare_params *p_params)
3136 {
3137         bool drv_resc_alloc = p_params->drv_resc_alloc;
3138         enum _ecore_status_t rc;
3139
3140         /* Since all information is common, only first hwfns should do this */
3141         if (IS_LEAD_HWFN(p_hwfn)) {
3142                 rc = ecore_iov_hw_info(p_hwfn);
3143                 if (rc != ECORE_SUCCESS) {
3144                         if (p_params->b_relaxed_probe)
3145                                 p_params->p_relaxed_res =
3146                                                 ECORE_HW_PREPARE_BAD_IOV;
3147                         else
3148                                 return rc;
3149                 }
3150         }
3151
3152         /* TODO In get_hw_info, amoungst others:
3153          * Get MCP FW revision and determine according to it the supported
3154          * featrues (e.g. DCB)
3155          * Get boot mode
3156          * ecore_get_pcie_width_speed, WOL capability.
3157          * Number of global CQ-s (for storage
3158          */
3159         ecore_hw_info_port_num(p_hwfn, p_ptt);
3160
3161 #ifndef ASIC_ONLY
3162         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3163 #endif
3164         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3165         if (rc != ECORE_SUCCESS)
3166                 return rc;
3167 #ifndef ASIC_ONLY
3168         }
3169 #endif
3170
3171         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3172         if (rc != ECORE_SUCCESS) {
3173                 if (p_params->b_relaxed_probe)
3174                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3175                 else
3176                         return rc;
3177         }
3178
3179 #ifndef ASIC_ONLY
3180         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3181 #endif
3182                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3183                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3184 #ifndef ASIC_ONLY
3185         } else {
3186                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3187
3188                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3189                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3190         }
3191 #endif
3192
3193         if (ecore_mcp_is_init(p_hwfn)) {
3194                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3195                         p_hwfn->hw_info.ovlan =
3196                             p_hwfn->mcp_info->func_info.ovlan;
3197
3198                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3199         }
3200
3201         if (personality != ECORE_PCI_DEFAULT) {
3202                 p_hwfn->hw_info.personality = personality;
3203         } else if (ecore_mcp_is_init(p_hwfn)) {
3204                 enum ecore_pci_personality protocol;
3205
3206                 protocol = p_hwfn->mcp_info->func_info.protocol;
3207                 p_hwfn->hw_info.personality = protocol;
3208         }
3209
3210 #ifndef ASIC_ONLY
3211         /* To overcome ILT lack for emulation, until at least until we'll have
3212          * a definite answer from system about it, allow only PF0 to be RoCE.
3213          */
3214         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3215                 if (!p_hwfn->rel_pf_id)
3216                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3217                 else
3218                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3219         }
3220 #endif
3221
3222         /* although in BB some constellations may support more than 4 tcs,
3223          * that can result in performance penalty in some cases. 4
3224          * represents a good tradeoff between performance and flexibility.
3225          */
3226         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3227
3228         /* start out with a single active tc. This can be increased either
3229          * by dcbx negotiation or by upper layer driver
3230          */
3231         p_hwfn->hw_info.num_active_tc = 1;
3232
3233         ecore_get_num_funcs(p_hwfn, p_ptt);
3234
3235         if (ecore_mcp_is_init(p_hwfn))
3236                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3237
3238         /* In case of forcing the driver's default resource allocation, calling
3239          * ecore_hw_get_resc() should come after initializing the personality
3240          * and after getting the number of functions, since the calculation of
3241          * the resources/features depends on them.
3242          * This order is not harmful if not forcing.
3243          */
3244         rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3245         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3246                 rc = ECORE_SUCCESS;
3247                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3248         }
3249
3250         return rc;
3251 }
3252
3253 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3254 {
3255         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3256         u32 tmp;
3257
3258         /* Read Vendor Id / Device Id */
3259         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3260                                   &p_dev->vendor_id);
3261         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3262                                   &p_dev->device_id);
3263
3264         /* Determine type */
3265         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
3266                 p_dev->type = ECORE_DEV_TYPE_AH;
3267         else
3268                 p_dev->type = ECORE_DEV_TYPE_BB;
3269
3270         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3271                                          MISCS_REG_CHIP_NUM);
3272         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3273                                          MISCS_REG_CHIP_REV);
3274
3275         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3276
3277         /* Learn number of HW-functions */
3278         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3279                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
3280
3281         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3282                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3283                 p_dev->num_hwfns = 2;
3284         } else {
3285                 p_dev->num_hwfns = 1;
3286         }
3287
3288 #ifndef ASIC_ONLY
3289         if (CHIP_REV_IS_EMUL(p_dev)) {
3290                 /* For some reason we have problems with this register
3291                  * in B0 emulation; Simply assume no CMT
3292                  */
3293                 DP_NOTICE(p_dev->hwfns, false,
3294                           "device on emul - assume no CMT\n");
3295                 p_dev->num_hwfns = 1;
3296         }
3297 #endif
3298
3299         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3300                                        MISCS_REG_CHIP_TEST_REG) >> 4;
3301         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3302         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3303                                            MISCS_REG_CHIP_METAL);
3304         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3305         DP_INFO(p_dev->hwfns,
3306                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3307                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3308                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3309                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3310                 p_dev->chip_metal);
3311
3312         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3313                 DP_NOTICE(p_dev->hwfns, false,
3314                           "The chip type/rev (BB A0) is not supported!\n");
3315                 return ECORE_ABORTED;
3316         }
3317 #ifndef ASIC_ONLY
3318         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3319                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3320                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3321
3322         if (CHIP_REV_IS_EMUL(p_dev)) {
3323                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3324                                MISCS_REG_ECO_RESERVED);
3325                 if (tmp & (1 << 29)) {
3326                         DP_NOTICE(p_hwfn, false,
3327                                   "Emulation: Running on a FULL build\n");
3328                         p_dev->b_is_emul_full = true;
3329                 } else {
3330                         DP_NOTICE(p_hwfn, false,
3331                                   "Emulation: Running on a REDUCED build\n");
3332                 }
3333         }
3334 #endif
3335
3336         return ECORE_SUCCESS;
3337 }
3338
3339 #ifndef LINUX_REMOVE
3340 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3341 {
3342         int j;
3343
3344         if (IS_VF(p_dev))
3345                 return;
3346
3347         for_each_hwfn(p_dev, j) {
3348                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3349
3350                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3351                            "Mark hw/fw uninitialized\n");
3352
3353                 p_hwfn->hw_init_done = false;
3354                 p_hwfn->first_on_engine = false;
3355
3356                 ecore_ptt_invalidate(p_hwfn);
3357         }
3358 }
3359 #endif
3360
3361 static enum _ecore_status_t
3362 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3363                         void OSAL_IOMEM * p_regview,
3364                         void OSAL_IOMEM * p_doorbells,
3365                         struct ecore_hw_prepare_params *p_params)
3366 {
3367         struct ecore_dev *p_dev = p_hwfn->p_dev;
3368         struct ecore_mdump_info mdump_info;
3369         enum _ecore_status_t rc = ECORE_SUCCESS;
3370
3371         /* Split PCI bars evenly between hwfns */
3372         p_hwfn->regview = p_regview;
3373         p_hwfn->doorbells = p_doorbells;
3374
3375         if (IS_VF(p_dev))
3376                 return ecore_vf_hw_prepare(p_hwfn);
3377
3378         /* Validate that chip access is feasible */
3379         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3380                 DP_ERR(p_hwfn,
3381                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3382                 if (p_params->b_relaxed_probe)
3383                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3384                 return ECORE_INVAL;
3385         }
3386
3387         get_function_id(p_hwfn);
3388
3389         /* Allocate PTT pool */
3390         rc = ecore_ptt_pool_alloc(p_hwfn);
3391         if (rc) {
3392                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3393                 if (p_params->b_relaxed_probe)
3394                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3395                 goto err0;
3396         }
3397
3398         /* Allocate the main PTT */
3399         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3400
3401         /* First hwfn learns basic information, e.g., number of hwfns */
3402         if (!p_hwfn->my_id) {
3403                 rc = ecore_get_dev_info(p_dev);
3404                 if (rc != ECORE_SUCCESS) {
3405                         if (p_params->b_relaxed_probe)
3406                                 p_params->p_relaxed_res =
3407                                         ECORE_HW_PREPARE_FAILED_DEV;
3408                         goto err1;
3409                 }
3410         }
3411
3412         ecore_hw_hwfn_prepare(p_hwfn);
3413
3414         /* Initialize MCP structure */
3415         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3416         if (rc) {
3417                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3418                 if (p_params->b_relaxed_probe)
3419                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3420                 goto err1;
3421         }
3422
3423         /* Read the device configuration information from the HW and SHMEM */
3424         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3425                                p_params->personality, p_params);
3426         if (rc) {
3427                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3428                 goto err2;
3429         }
3430
3431         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3432          * called, since among others it sets the ports number in an engine.
3433          */
3434         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3435             !p_dev->recov_in_prog) {
3436                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3437                 if (rc != ECORE_SUCCESS)
3438                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3439         }
3440
3441         /* Check if mdump logs are present and update the epoch value */
3442         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3443                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3444                                               &mdump_info);
3445                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3446                         DP_NOTICE(p_hwfn, false,
3447                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3448                 }
3449
3450                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3451                                            p_params->epoch);
3452         }
3453
3454         /* Allocate the init RT array and initialize the init-ops engine */
3455         rc = ecore_init_alloc(p_hwfn);
3456         if (rc) {
3457                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3458                 if (p_params->b_relaxed_probe)
3459                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3460                 goto err2;
3461         }
3462 #ifndef ASIC_ONLY
3463         if (CHIP_REV_IS_FPGA(p_dev)) {
3464                 DP_NOTICE(p_hwfn, false,
3465                           "FPGA: workaround; Prevent DMAE parities\n");
3466                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3467                          7);
3468
3469                 DP_NOTICE(p_hwfn, false,
3470                           "FPGA: workaround: Set VF bar0 size\n");
3471                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3472                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3473         }
3474 #endif
3475
3476         return rc;
3477 err2:
3478         if (IS_LEAD_HWFN(p_hwfn))
3479                 ecore_iov_free_hw_info(p_dev);
3480         ecore_mcp_free(p_hwfn);
3481 err1:
3482         ecore_hw_hwfn_free(p_hwfn);
3483 err0:
3484         return rc;
3485 }
3486
3487 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3488                                       struct ecore_hw_prepare_params *p_params)
3489 {
3490         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3491         enum _ecore_status_t rc;
3492
3493         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3494
3495         if (p_params->b_relaxed_probe)
3496                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3497
3498         /* Store the precompiled init data ptrs */
3499         if (IS_PF(p_dev))
3500                 ecore_init_iro_array(p_dev);
3501
3502         /* Initialize the first hwfn - will learn number of hwfns */
3503         rc = ecore_hw_prepare_single(p_hwfn,
3504                                      p_dev->regview,
3505                                      p_dev->doorbells, p_params);
3506         if (rc != ECORE_SUCCESS)
3507                 return rc;
3508
3509         p_params->personality = p_hwfn->hw_info.personality;
3510
3511         /* initilalize 2nd hwfn if necessary */
3512         if (p_dev->num_hwfns > 1) {
3513                 void OSAL_IOMEM *p_regview, *p_doorbell;
3514                 u8 OSAL_IOMEM *addr;
3515
3516                 /* adjust bar offset for second engine */
3517                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3518                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3519                 p_regview = (void OSAL_IOMEM *)addr;
3520
3521                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3522                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3523                 p_doorbell = (void OSAL_IOMEM *)addr;
3524
3525                 /* prepare second hw function */
3526                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3527                                              p_doorbell, p_params);
3528
3529                 /* in case of error, need to free the previously
3530                  * initiliazed hwfn 0.
3531                  */
3532                 if (rc != ECORE_SUCCESS) {
3533                         if (p_params->b_relaxed_probe)
3534                                 p_params->p_relaxed_res =
3535                                                 ECORE_HW_PREPARE_FAILED_ENG2;
3536
3537                         if (IS_PF(p_dev)) {
3538                                 ecore_init_free(p_hwfn);
3539                                 ecore_mcp_free(p_hwfn);
3540                                 ecore_hw_hwfn_free(p_hwfn);
3541                         } else {
3542                                 DP_NOTICE(p_dev, true,
3543                                           "What do we need to free when VF hwfn1 init fails\n");
3544                         }
3545                         return rc;
3546                 }
3547         }
3548
3549         return rc;
3550 }
3551
3552 void ecore_hw_remove(struct ecore_dev *p_dev)
3553 {
3554         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3555         int i;
3556
3557         if (IS_PF(p_dev))
3558                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3559                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3560
3561         for_each_hwfn(p_dev, i) {
3562                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3563
3564                 if (IS_VF(p_dev)) {
3565                         ecore_vf_pf_release(p_hwfn);
3566                         continue;
3567                 }
3568
3569                 ecore_init_free(p_hwfn);
3570                 ecore_hw_hwfn_free(p_hwfn);
3571                 ecore_mcp_free(p_hwfn);
3572
3573                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3574         }
3575
3576         ecore_iov_free_hw_info(p_dev);
3577 }
3578
3579 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3580                                       struct ecore_chain *p_chain)
3581 {
3582         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3583         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3584         struct ecore_chain_next *p_next;
3585         u32 size, i;
3586
3587         if (!p_virt)
3588                 return;
3589
3590         size = p_chain->elem_size * p_chain->usable_per_page;
3591
3592         for (i = 0; i < p_chain->page_cnt; i++) {
3593                 if (!p_virt)
3594                         break;
3595
3596                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3597                 p_virt_next = p_next->next_virt;
3598                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3599
3600                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3601                                        ECORE_CHAIN_PAGE_SIZE);
3602
3603                 p_virt = p_virt_next;
3604                 p_phys = p_phys_next;
3605         }
3606 }
3607
3608 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3609                                     struct ecore_chain *p_chain)
3610 {
3611         if (!p_chain->p_virt_addr)
3612                 return;
3613
3614         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3615                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3616 }
3617
3618 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3619                                  struct ecore_chain *p_chain)
3620 {
3621         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3622         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3623         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3624
3625         if (!pp_virt_addr_tbl)
3626                 return;
3627
3628         if (!p_chain->pbl.p_virt_table)
3629                 goto out;
3630
3631         for (i = 0; i < page_cnt; i++) {
3632                 if (!pp_virt_addr_tbl[i])
3633                         break;
3634
3635                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3636                                        *(dma_addr_t *)p_pbl_virt,
3637                                        ECORE_CHAIN_PAGE_SIZE);
3638
3639                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3640         }
3641
3642         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3643
3644         if (!p_chain->pbl.external)
3645                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3646                                        p_chain->pbl.p_phys_table, pbl_size);
3647 out:
3648         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3649 }
3650
3651 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3652 {
3653         switch (p_chain->mode) {
3654         case ECORE_CHAIN_MODE_NEXT_PTR:
3655                 ecore_chain_free_next_ptr(p_dev, p_chain);
3656                 break;
3657         case ECORE_CHAIN_MODE_SINGLE:
3658                 ecore_chain_free_single(p_dev, p_chain);
3659                 break;
3660         case ECORE_CHAIN_MODE_PBL:
3661                 ecore_chain_free_pbl(p_dev, p_chain);
3662                 break;
3663         }
3664 }
3665
3666 static enum _ecore_status_t
3667 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3668                                enum ecore_chain_cnt_type cnt_type,
3669                                osal_size_t elem_size, u32 page_cnt)
3670 {
3671         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3672
3673         /* The actual chain size can be larger than the maximal possible value
3674          * after rounding up the requested elements number to pages, and after
3675          * taking into acount the unusuable elements (next-ptr elements).
3676          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3677          * size/capacity fields are of a u32 type.
3678          */
3679         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3680              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3681             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3682              chain_size > ECORE_U32_MAX)) {
3683                 DP_NOTICE(p_dev, true,
3684                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3685                           (unsigned long)chain_size);
3686                 return ECORE_INVAL;
3687         }
3688
3689         return ECORE_SUCCESS;
3690 }
3691
3692 static enum _ecore_status_t
3693 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3694 {
3695         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3696         dma_addr_t p_phys = 0;
3697         u32 i;
3698
3699         for (i = 0; i < p_chain->page_cnt; i++) {
3700                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3701                                                  ECORE_CHAIN_PAGE_SIZE);
3702                 if (!p_virt) {
3703                         DP_NOTICE(p_dev, true,
3704                                   "Failed to allocate chain memory\n");
3705                         return ECORE_NOMEM;
3706                 }
3707
3708                 if (i == 0) {
3709                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3710                         ecore_chain_reset(p_chain);
3711                 } else {
3712                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3713                                                        p_virt, p_phys);
3714                 }
3715
3716                 p_virt_prev = p_virt;
3717         }
3718         /* Last page's next element should point to the beginning of the
3719          * chain.
3720          */
3721         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3722                                        p_chain->p_virt_addr,
3723                                        p_chain->p_phys_addr);
3724
3725         return ECORE_SUCCESS;
3726 }
3727
3728 static enum _ecore_status_t
3729 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3730 {
3731         dma_addr_t p_phys = 0;
3732         void *p_virt = OSAL_NULL;
3733
3734         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3735         if (!p_virt) {
3736                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3737                 return ECORE_NOMEM;
3738         }
3739
3740         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3741         ecore_chain_reset(p_chain);
3742
3743         return ECORE_SUCCESS;
3744 }
3745
3746 static enum _ecore_status_t
3747 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3748                       struct ecore_chain *p_chain,
3749                       struct ecore_chain_ext_pbl *ext_pbl)
3750 {
3751         void *p_virt = OSAL_NULL;
3752         u8 *p_pbl_virt = OSAL_NULL;
3753         void **pp_virt_addr_tbl = OSAL_NULL;
3754         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3755         u32 page_cnt = p_chain->page_cnt, size, i;
3756
3757         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3758         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3759         if (!pp_virt_addr_tbl) {
3760                 DP_NOTICE(p_dev, true,
3761                           "Failed to allocate memory for the chain virtual addresses table\n");
3762                 return ECORE_NOMEM;
3763         }
3764         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3765
3766         /* The allocation of the PBL table is done with its full size, since it
3767          * is expected to be successive.
3768          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3769          * failure, since pp_virt_addr_tbl was previously allocated, and it
3770          * should be saved to allow its freeing during the error flow.
3771          */
3772         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3773
3774         if (ext_pbl == OSAL_NULL) {
3775                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3776         } else {
3777                 p_pbl_virt = ext_pbl->p_pbl_virt;
3778                 p_pbl_phys = ext_pbl->p_pbl_phys;
3779                 p_chain->pbl.external = true;
3780         }
3781
3782         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3783                                  pp_virt_addr_tbl);
3784         if (!p_pbl_virt) {
3785                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3786                 return ECORE_NOMEM;
3787         }
3788
3789         for (i = 0; i < page_cnt; i++) {
3790                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3791                                                  ECORE_CHAIN_PAGE_SIZE);
3792                 if (!p_virt) {
3793                         DP_NOTICE(p_dev, true,
3794                                   "Failed to allocate chain memory\n");
3795                         return ECORE_NOMEM;
3796                 }
3797
3798                 if (i == 0) {
3799                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3800                         ecore_chain_reset(p_chain);
3801                 }
3802
3803                 /* Fill the PBL table with the physical address of the page */
3804                 *(dma_addr_t *)p_pbl_virt = p_phys;
3805                 /* Keep the virtual address of the page */
3806                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3807
3808                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3809         }
3810
3811         return ECORE_SUCCESS;
3812 }
3813
3814 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3815                                        enum ecore_chain_use_mode intended_use,
3816                                        enum ecore_chain_mode mode,
3817                                        enum ecore_chain_cnt_type cnt_type,
3818                                        u32 num_elems, osal_size_t elem_size,
3819                                        struct ecore_chain *p_chain,
3820                                        struct ecore_chain_ext_pbl *ext_pbl)
3821 {
3822         u32 page_cnt;
3823         enum _ecore_status_t rc = ECORE_SUCCESS;
3824
3825         if (mode == ECORE_CHAIN_MODE_SINGLE)
3826                 page_cnt = 1;
3827         else
3828                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3829
3830         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3831                                             page_cnt);
3832         if (rc) {
3833                 DP_NOTICE(p_dev, true,
3834                           "Cannot allocate a chain with the given arguments:\n"
3835                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3836                           intended_use, mode, cnt_type, num_elems, elem_size);
3837                 return rc;
3838         }
3839
3840         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3841                                 mode, cnt_type, p_dev->dp_ctx);
3842
3843         switch (mode) {
3844         case ECORE_CHAIN_MODE_NEXT_PTR:
3845                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3846                 break;
3847         case ECORE_CHAIN_MODE_SINGLE:
3848                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3849                 break;
3850         case ECORE_CHAIN_MODE_PBL:
3851                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3852                 break;
3853         }
3854         if (rc)
3855                 goto nomem;
3856
3857         return ECORE_SUCCESS;
3858
3859 nomem:
3860         ecore_chain_free(p_dev, p_chain);
3861         return rc;
3862 }
3863
3864 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3865                                        u16 src_id, u16 *dst_id)
3866 {
3867         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3868                 u16 min, max;
3869
3870                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3871                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3872                 DP_NOTICE(p_hwfn, true,
3873                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3874                           src_id, min, max);
3875
3876                 return ECORE_INVAL;
3877         }
3878
3879         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3880
3881         return ECORE_SUCCESS;
3882 }
3883
3884 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3885                                     u8 src_id, u8 *dst_id)
3886 {
3887         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3888                 u8 min, max;
3889
3890                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3891                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3892                 DP_NOTICE(p_hwfn, true,
3893                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3894                           src_id, min, max);
3895
3896                 return ECORE_INVAL;
3897         }
3898
3899         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3900
3901         return ECORE_SUCCESS;
3902 }
3903
3904 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3905                                       u8 src_id, u8 *dst_id)
3906 {
3907         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3908                 u8 min, max;
3909
3910                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3911                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3912                 DP_NOTICE(p_hwfn, true,
3913                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3914                           src_id, min, max);
3915
3916                 return ECORE_INVAL;
3917         }
3918
3919         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3920
3921         return ECORE_SUCCESS;
3922 }
3923
3924 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3925                                               struct ecore_ptt *p_ptt,
3926                                               u8 *p_filter)
3927 {
3928         u32 high, low, en;
3929         int i;
3930
3931         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3932                 return ECORE_SUCCESS;
3933
3934         high = p_filter[1] | (p_filter[0] << 8);
3935         low = p_filter[5] | (p_filter[4] << 8) |
3936             (p_filter[3] << 16) | (p_filter[2] << 24);
3937
3938         /* Find a free entry and utilize it */
3939         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3940                 en = ecore_rd(p_hwfn, p_ptt,
3941                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3942                 if (en)
3943                         continue;
3944                 ecore_wr(p_hwfn, p_ptt,
3945                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3946                          2 * i * sizeof(u32), low);
3947                 ecore_wr(p_hwfn, p_ptt,
3948                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3949                          (2 * i + 1) * sizeof(u32), high);
3950                 ecore_wr(p_hwfn, p_ptt,
3951                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3952                 ecore_wr(p_hwfn, p_ptt,
3953                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3954                          i * sizeof(u32), 0);
3955                 ecore_wr(p_hwfn, p_ptt,
3956                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3957                 break;
3958         }
3959         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3960                 DP_NOTICE(p_hwfn, false,
3961                           "Failed to find an empty LLH filter to utilize\n");
3962                 return ECORE_INVAL;
3963         }
3964
3965         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3966                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3967                    p_filter[0], p_filter[1], p_filter[2],
3968                    p_filter[3], p_filter[4], p_filter[5], i);
3969
3970         return ECORE_SUCCESS;
3971 }
3972
3973 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3974                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3975 {
3976         u32 high, low;
3977         int i;
3978
3979         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3980                 return;
3981
3982         high = p_filter[1] | (p_filter[0] << 8);
3983         low = p_filter[5] | (p_filter[4] << 8) |
3984             (p_filter[3] << 16) | (p_filter[2] << 24);
3985
3986         /* Find the entry and clean it */
3987         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3988                 if (ecore_rd(p_hwfn, p_ptt,
3989                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3990                              2 * i * sizeof(u32)) != low)
3991                         continue;
3992                 if (ecore_rd(p_hwfn, p_ptt,
3993                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3994                              (2 * i + 1) * sizeof(u32)) != high)
3995                         continue;
3996
3997                 ecore_wr(p_hwfn, p_ptt,
3998                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3999                 ecore_wr(p_hwfn, p_ptt,
4000                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4001                          2 * i * sizeof(u32), 0);
4002                 ecore_wr(p_hwfn, p_ptt,
4003                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4004                          (2 * i + 1) * sizeof(u32), 0);
4005                 break;
4006         }
4007         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4008                 DP_NOTICE(p_hwfn, false,
4009                           "Tried to remove a non-configured filter\n");
4010 }
4011
4012 enum _ecore_status_t
4013 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4014                               struct ecore_ptt *p_ptt,
4015                               u16 source_port_or_eth_type,
4016                               u16 dest_port,
4017                               enum ecore_llh_port_filter_type_t type)
4018 {
4019         u32 high, low, en;
4020         int i;
4021
4022         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4023                 return ECORE_SUCCESS;
4024
4025         high = 0;
4026         low = 0;
4027         switch (type) {
4028         case ECORE_LLH_FILTER_ETHERTYPE:
4029                 high = source_port_or_eth_type;
4030                 break;
4031         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4032         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4033                 low = source_port_or_eth_type << 16;
4034                 break;
4035         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4036         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4037                 low = dest_port;
4038                 break;
4039         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4040         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4041                 low = (source_port_or_eth_type << 16) | dest_port;
4042                 break;
4043         default:
4044                 DP_NOTICE(p_hwfn, true,
4045                           "Non valid LLH protocol filter type %d\n", type);
4046                 return ECORE_INVAL;
4047         }
4048         /* Find a free entry and utilize it */
4049         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4050                 en = ecore_rd(p_hwfn, p_ptt,
4051                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4052                 if (en)
4053                         continue;
4054                 ecore_wr(p_hwfn, p_ptt,
4055                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4056                          2 * i * sizeof(u32), low);
4057                 ecore_wr(p_hwfn, p_ptt,
4058                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4059                          (2 * i + 1) * sizeof(u32), high);
4060                 ecore_wr(p_hwfn, p_ptt,
4061                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4062                 ecore_wr(p_hwfn, p_ptt,
4063                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4064                          i * sizeof(u32), 1 << type);
4065                 ecore_wr(p_hwfn, p_ptt,
4066                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4067                 break;
4068         }
4069         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4070                 DP_NOTICE(p_hwfn, false,
4071                           "Failed to find an empty LLH filter to utilize\n");
4072                 return ECORE_NORESOURCES;
4073         }
4074         switch (type) {
4075         case ECORE_LLH_FILTER_ETHERTYPE:
4076                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4077                            "ETH type %x is added at %d\n",
4078                            source_port_or_eth_type, i);
4079                 break;
4080         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4081                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4082                            "TCP src port %x is added at %d\n",
4083                            source_port_or_eth_type, i);
4084                 break;
4085         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4086                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4087                            "UDP src port %x is added at %d\n",
4088                            source_port_or_eth_type, i);
4089                 break;
4090         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4091                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4092                            "TCP dst port %x is added at %d\n", dest_port, i);
4093                 break;
4094         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4095                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4096                            "UDP dst port %x is added at %d\n", dest_port, i);
4097                 break;
4098         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4099                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4100                            "TCP src/dst ports %x/%x are added at %d\n",
4101                            source_port_or_eth_type, dest_port, i);
4102                 break;
4103         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4104                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4105                            "UDP src/dst ports %x/%x are added at %d\n",
4106                            source_port_or_eth_type, dest_port, i);
4107                 break;
4108         }
4109         return ECORE_SUCCESS;
4110 }
4111
4112 void
4113 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4114                                  struct ecore_ptt *p_ptt,
4115                                  u16 source_port_or_eth_type,
4116                                  u16 dest_port,
4117                                  enum ecore_llh_port_filter_type_t type)
4118 {
4119         u32 high, low;
4120         int i;
4121
4122         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4123                 return;
4124
4125         high = 0;
4126         low = 0;
4127         switch (type) {
4128         case ECORE_LLH_FILTER_ETHERTYPE:
4129                 high = source_port_or_eth_type;
4130                 break;
4131         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4132         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4133                 low = source_port_or_eth_type << 16;
4134                 break;
4135         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4136         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4137                 low = dest_port;
4138                 break;
4139         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4140         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4141                 low = (source_port_or_eth_type << 16) | dest_port;
4142                 break;
4143         default:
4144                 DP_NOTICE(p_hwfn, true,
4145                           "Non valid LLH protocol filter type %d\n", type);
4146                 return;
4147         }
4148
4149         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4150                 if (!ecore_rd(p_hwfn, p_ptt,
4151                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4152                         continue;
4153                 if (!ecore_rd(p_hwfn, p_ptt,
4154                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4155                         continue;
4156                 if (!(ecore_rd(p_hwfn, p_ptt,
4157                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4158                                i * sizeof(u32)) & (1 << type)))
4159                         continue;
4160                 if (ecore_rd(p_hwfn, p_ptt,
4161                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4162                              2 * i * sizeof(u32)) != low)
4163                         continue;
4164                 if (ecore_rd(p_hwfn, p_ptt,
4165                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4166                              (2 * i + 1) * sizeof(u32)) != high)
4167                         continue;
4168
4169                 ecore_wr(p_hwfn, p_ptt,
4170                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4171                 ecore_wr(p_hwfn, p_ptt,
4172                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4173                 ecore_wr(p_hwfn, p_ptt,
4174                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4175                          i * sizeof(u32), 0);
4176                 ecore_wr(p_hwfn, p_ptt,
4177                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4178                          2 * i * sizeof(u32), 0);
4179                 ecore_wr(p_hwfn, p_ptt,
4180                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4181                          (2 * i + 1) * sizeof(u32), 0);
4182                 break;
4183         }
4184
4185         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4186                 DP_NOTICE(p_hwfn, false,
4187                           "Tried to remove a non-configured filter\n");
4188 }
4189
4190 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4191                                  struct ecore_ptt *p_ptt)
4192 {
4193         int i;
4194
4195         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4196                 return;
4197
4198         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4199                 ecore_wr(p_hwfn, p_ptt,
4200                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4201                 ecore_wr(p_hwfn, p_ptt,
4202                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4203                          2 * i * sizeof(u32), 0);
4204                 ecore_wr(p_hwfn, p_ptt,
4205                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4206                          (2 * i + 1) * sizeof(u32), 0);
4207         }
4208 }
4209
4210 enum _ecore_status_t
4211 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4212                                   struct ecore_ptt *p_ptt)
4213 {
4214         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4215                 ecore_wr(p_hwfn, p_ptt,
4216                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4217                          1 << p_hwfn->abs_pf_id / 2);
4218                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4219                 return ECORE_SUCCESS;
4220         }
4221
4222         DP_NOTICE(p_hwfn, false,
4223                   "This function can't be set as default\n");
4224         return ECORE_INVAL;
4225 }
4226
4227 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4228                                                struct ecore_ptt *p_ptt,
4229                                                u32 hw_addr, void *p_eth_qzone,
4230                                                osal_size_t eth_qzone_size,
4231                                                u8 timeset)
4232 {
4233         struct coalescing_timeset *p_coal_timeset;
4234
4235         if (IS_VF(p_hwfn->p_dev)) {
4236                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
4237                 return ECORE_INVAL;
4238         }
4239
4240         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4241                 DP_NOTICE(p_hwfn, true,
4242                           "Coalescing configuration not enabled\n");
4243                 return ECORE_INVAL;
4244         }
4245
4246         p_coal_timeset = p_eth_qzone;
4247         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4248         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4249         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4250         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4251
4252         return ECORE_SUCCESS;
4253 }
4254
4255 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4256                                             struct ecore_ptt *p_ptt,
4257                                             u16 coalesce, u16 qid, u16 sb_id)
4258 {
4259         struct ustorm_eth_queue_zone eth_qzone;
4260         u8 timeset, timer_res;
4261         u16 fw_qid = 0;
4262         u32 address;
4263         enum _ecore_status_t rc;
4264
4265         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4266         if (coalesce <= 0x7F) {
4267                 timer_res = 0;
4268         } else if (coalesce <= 0xFF) {
4269                 timer_res = 1;
4270         } else if (coalesce <= 0x1FF) {
4271                 timer_res = 2;
4272         } else {
4273                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4274                 return ECORE_INVAL;
4275         }
4276         timeset = (u8)(coalesce >> timer_res);
4277
4278         rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4279         if (rc != ECORE_SUCCESS)
4280                 return rc;
4281
4282         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
4283         if (rc != ECORE_SUCCESS)
4284                 goto out;
4285
4286         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4287
4288         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4289                                 sizeof(struct ustorm_eth_queue_zone), timeset);
4290         if (rc != ECORE_SUCCESS)
4291                 goto out;
4292
4293         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
4294 out:
4295         return rc;
4296 }
4297
4298 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4299                                             struct ecore_ptt *p_ptt,
4300                                             u16 coalesce, u16 qid, u16 sb_id)
4301 {
4302         struct xstorm_eth_queue_zone eth_qzone;
4303         u8 timeset, timer_res;
4304         u16 fw_qid = 0;
4305         u32 address;
4306         enum _ecore_status_t rc;
4307
4308         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4309         if (coalesce <= 0x7F) {
4310                 timer_res = 0;
4311         } else if (coalesce <= 0xFF) {
4312                 timer_res = 1;
4313         } else if (coalesce <= 0x1FF) {
4314                 timer_res = 2;
4315         } else {
4316                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4317                 return ECORE_INVAL;
4318         }
4319
4320         timeset = (u8)(coalesce >> timer_res);
4321
4322         rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4323         if (rc != ECORE_SUCCESS)
4324                 return rc;
4325
4326         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
4327         if (rc != ECORE_SUCCESS)
4328                 goto out;
4329
4330         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4331
4332         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4333                                 sizeof(struct xstorm_eth_queue_zone), timeset);
4334         if (rc != ECORE_SUCCESS)
4335                 goto out;
4336
4337         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
4338 out:
4339         return rc;
4340 }
4341
4342 /* Calculate final WFQ values for all vports and configure it.
4343  * After this configuration each vport must have
4344  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4345  */
4346 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4347                                                struct ecore_ptt *p_ptt,
4348                                                u32 min_pf_rate)
4349 {
4350         struct init_qm_vport_params *vport_params;
4351         int i;
4352
4353         vport_params = p_hwfn->qm_info.qm_vport_params;
4354
4355         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4356                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4357
4358                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4359                     min_pf_rate;
4360                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4361                                      vport_params[i].first_tx_pq_id,
4362                                      vport_params[i].vport_wfq);
4363         }
4364 }
4365
4366 static void
4367 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4368 {
4369         int i;
4370
4371         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4372                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4373 }
4374
4375 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4376                                              struct ecore_ptt *p_ptt,
4377                                              u32 min_pf_rate)
4378 {
4379         struct init_qm_vport_params *vport_params;
4380         int i;
4381
4382         vport_params = p_hwfn->qm_info.qm_vport_params;
4383
4384         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4385                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4386                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4387                                      vport_params[i].first_tx_pq_id,
4388                                      vport_params[i].vport_wfq);
4389         }
4390 }
4391
4392 /* This function performs several validations for WFQ
4393  * configuration and required min rate for a given vport
4394  * 1. req_rate must be greater than one percent of min_pf_rate.
4395  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4396  *    rates to get less than one percent of min_pf_rate.
4397  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4398  */
4399 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4400                                                  u16 vport_id, u32 req_rate,
4401                                                  u32 min_pf_rate)
4402 {
4403         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4404         int non_requested_count = 0, req_count = 0, i, num_vports;
4405
4406         num_vports = p_hwfn->qm_info.num_vports;
4407
4408 /* Accounting for the vports which are configured for WFQ explicitly */
4409
4410         for (i = 0; i < num_vports; i++) {
4411                 u32 tmp_speed;
4412
4413                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4414                         req_count++;
4415                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4416                         total_req_min_rate += tmp_speed;
4417                 }
4418         }
4419
4420         /* Include current vport data as well */
4421         req_count++;
4422         total_req_min_rate += req_rate;
4423         non_requested_count = num_vports - req_count;
4424
4425         /* validate possible error cases */
4426         if (req_rate > min_pf_rate) {
4427                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4428                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4429                            vport_id, req_rate, min_pf_rate);
4430                 return ECORE_INVAL;
4431         }
4432
4433         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4434                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4435                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4436                            vport_id, req_rate, min_pf_rate);
4437                 return ECORE_INVAL;
4438         }
4439
4440         /* TBD - for number of vports greater than 100 */
4441         if (num_vports > ECORE_WFQ_UNIT) {
4442                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4443                            "Number of vports is greater than %d\n",
4444                            ECORE_WFQ_UNIT);
4445                 return ECORE_INVAL;
4446         }
4447
4448         if (total_req_min_rate > min_pf_rate) {
4449                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4450                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4451                            total_req_min_rate, min_pf_rate);
4452                 return ECORE_INVAL;
4453         }
4454
4455         /* Data left for non requested vports */
4456         total_left_rate = min_pf_rate - total_req_min_rate;
4457         left_rate_per_vp = total_left_rate / non_requested_count;
4458
4459         /* validate if non requested get < 1% of min bw */
4460         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4461                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4462                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4463                            left_rate_per_vp, min_pf_rate);
4464                 return ECORE_INVAL;
4465         }
4466
4467         /* now req_rate for given vport passes all scenarios.
4468          * assign final wfq rates to all vports.
4469          */
4470         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4471         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4472
4473         for (i = 0; i < num_vports; i++) {
4474                 if (p_hwfn->qm_info.wfq_data[i].configured)
4475                         continue;
4476
4477                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4478         }
4479
4480         return ECORE_SUCCESS;
4481 }
4482
4483 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4484                                        struct ecore_ptt *p_ptt,
4485                                        u16 vp_id, u32 rate)
4486 {
4487         struct ecore_mcp_link_state *p_link;
4488         int rc = ECORE_SUCCESS;
4489
4490         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4491
4492         if (!p_link->min_pf_rate) {
4493                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4494                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4495                 return rc;
4496         }
4497
4498         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4499
4500         if (rc == ECORE_SUCCESS)
4501                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4502                                                    p_link->min_pf_rate);
4503         else
4504                 DP_NOTICE(p_hwfn, false,
4505                           "Validation failed while configuring min rate\n");
4506
4507         return rc;
4508 }
4509
4510 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4511                                                    struct ecore_ptt *p_ptt,
4512                                                    u32 min_pf_rate)
4513 {
4514         bool use_wfq = false;
4515         int rc = ECORE_SUCCESS;
4516         u16 i;
4517
4518         /* Validate all pre configured vports for wfq */
4519         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4520                 u32 rate;
4521
4522                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4523                         continue;
4524
4525                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4526                 use_wfq = true;
4527
4528                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4529                 if (rc != ECORE_SUCCESS) {
4530                         DP_NOTICE(p_hwfn, false,
4531                                   "WFQ validation failed while configuring min rate\n");
4532                         break;
4533                 }
4534         }
4535
4536         if (rc == ECORE_SUCCESS && use_wfq)
4537                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4538         else
4539                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4540
4541         return rc;
4542 }
4543
4544 /* Main API for ecore clients to configure vport min rate.
4545  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4546  * rate - Speed in Mbps needs to be assigned to a given vport.
4547  */
4548 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4549 {
4550         int i, rc = ECORE_INVAL;
4551
4552         /* TBD - for multiple hardware functions - that is 100 gig */
4553         if (p_dev->num_hwfns > 1) {
4554                 DP_NOTICE(p_dev, false,
4555                           "WFQ configuration is not supported for this device\n");
4556                 return rc;
4557         }
4558
4559         for_each_hwfn(p_dev, i) {
4560                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4561                 struct ecore_ptt *p_ptt;
4562
4563                 p_ptt = ecore_ptt_acquire(p_hwfn);
4564                 if (!p_ptt)
4565                         return ECORE_TIMEOUT;
4566
4567                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4568
4569                 if (rc != ECORE_SUCCESS) {
4570                         ecore_ptt_release(p_hwfn, p_ptt);
4571                         return rc;
4572                 }
4573
4574                 ecore_ptt_release(p_hwfn, p_ptt);
4575         }
4576
4577         return rc;
4578 }
4579
4580 /* API to configure WFQ from mcp link change */
4581 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4582                                            u32 min_pf_rate)
4583 {
4584         int i;
4585
4586         /* TBD - for multiple hardware functions - that is 100 gig */
4587         if (p_dev->num_hwfns > 1) {
4588                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4589                            "WFQ configuration is not supported for this device\n");
4590                 return;
4591         }
4592
4593         for_each_hwfn(p_dev, i) {
4594                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4595
4596                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4597                                                         p_hwfn->p_dpc_ptt,
4598                                                         min_pf_rate);
4599         }
4600 }
4601
4602 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4603                                        struct ecore_ptt *p_ptt,
4604                                        struct ecore_mcp_link_state *p_link,
4605                                        u8 max_bw)
4606 {
4607         int rc = ECORE_SUCCESS;
4608
4609         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4610
4611         if (!p_link->line_speed && (max_bw != 100))
4612                 return rc;
4613
4614         p_link->speed = (p_link->line_speed * max_bw) / 100;
4615         p_hwfn->qm_info.pf_rl = p_link->speed;
4616
4617         /* Since the limiter also affects Tx-switched traffic, we don't want it
4618          * to limit such traffic in case there's no actual limit.
4619          * In that case, set limit to imaginary high boundary.
4620          */
4621         if (max_bw == 100)
4622                 p_hwfn->qm_info.pf_rl = 100000;
4623
4624         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4625                               p_hwfn->qm_info.pf_rl);
4626
4627         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4628                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4629                    p_link->speed);
4630
4631         return rc;
4632 }
4633
4634 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4635 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4636 {
4637         int i, rc = ECORE_INVAL;
4638
4639         if (max_bw < 1 || max_bw > 100) {
4640                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4641                 return rc;
4642         }
4643
4644         for_each_hwfn(p_dev, i) {
4645                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4646                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4647                 struct ecore_mcp_link_state *p_link;
4648                 struct ecore_ptt *p_ptt;
4649
4650                 p_link = &p_lead->mcp_info->link_output;
4651
4652                 p_ptt = ecore_ptt_acquire(p_hwfn);
4653                 if (!p_ptt)
4654                         return ECORE_TIMEOUT;
4655
4656                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4657                                                         p_link, max_bw);
4658
4659                 ecore_ptt_release(p_hwfn, p_ptt);
4660
4661                 if (rc != ECORE_SUCCESS)
4662                         break;
4663         }
4664
4665         return rc;
4666 }
4667
4668 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4669                                        struct ecore_ptt *p_ptt,
4670                                        struct ecore_mcp_link_state *p_link,
4671                                        u8 min_bw)
4672 {
4673         int rc = ECORE_SUCCESS;
4674
4675         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4676         p_hwfn->qm_info.pf_wfq = min_bw;
4677
4678         if (!p_link->line_speed)
4679                 return rc;
4680
4681         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4682
4683         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4684
4685         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4686                    "Configured MIN bandwidth to be %d Mb/sec\n",
4687                    p_link->min_pf_rate);
4688
4689         return rc;
4690 }
4691
4692 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4693 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4694 {
4695         int i, rc = ECORE_INVAL;
4696
4697         if (min_bw < 1 || min_bw > 100) {
4698                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4699                 return rc;
4700         }
4701
4702         for_each_hwfn(p_dev, i) {
4703                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4704                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4705                 struct ecore_mcp_link_state *p_link;
4706                 struct ecore_ptt *p_ptt;
4707
4708                 p_link = &p_lead->mcp_info->link_output;
4709
4710                 p_ptt = ecore_ptt_acquire(p_hwfn);
4711                 if (!p_ptt)
4712                         return ECORE_TIMEOUT;
4713
4714                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4715                                                         p_link, min_bw);
4716                 if (rc != ECORE_SUCCESS) {
4717                         ecore_ptt_release(p_hwfn, p_ptt);
4718                         return rc;
4719                 }
4720
4721                 if (p_link->min_pf_rate) {
4722                         u32 min_rate = p_link->min_pf_rate;
4723
4724                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4725                                                                      p_ptt,
4726                                                                      min_rate);
4727                 }
4728
4729                 ecore_ptt_release(p_hwfn, p_ptt);
4730         }
4731
4732         return rc;
4733 }
4734
4735 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4736 {
4737         struct ecore_mcp_link_state *p_link;
4738
4739         p_link = &p_hwfn->mcp_info->link_output;
4740
4741         if (p_link->min_pf_rate)
4742                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4743                                                  p_link->min_pf_rate);
4744
4745         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4746                     sizeof(*p_hwfn->qm_info.wfq_data) *
4747                     p_hwfn->qm_info.num_vports);
4748 }
4749
4750 int ecore_device_num_engines(struct ecore_dev *p_dev)
4751 {
4752         return ECORE_IS_BB(p_dev) ? 2 : 1;
4753 }
4754
4755 int ecore_device_num_ports(struct ecore_dev *p_dev)
4756 {
4757         /* in CMT always only one port */
4758         if (p_dev->num_hwfns > 1)
4759                 return 1;
4760
4761         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4762 }
4763
4764 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4765                           __le16 *fw_mid,
4766                           __le16 *fw_lsb,
4767                           u8 *mac)
4768 {
4769         ((u8 *)fw_msb)[0] = mac[1];
4770         ((u8 *)fw_msb)[1] = mac[0];
4771         ((u8 *)fw_mid)[0] = mac[3];
4772         ((u8 *)fw_mid)[1] = mac[2];
4773         ((u8 *)fw_lsb)[0] = mac[5];
4774         ((u8 *)fw_lsb)[1] = mac[4];
4775 }