2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_mcp.h"
25 #include "ecore_hw_defs.h"
26 #include "mcp_public.h"
27 #include "ecore_iro.h"
29 #include "ecore_dev_api.h"
32 #define ECORE_MIN_DPIS (4) /* The minimal number of DPIs required
33 * load the driver. The number was
38 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
41 BAR_ID_0, /* used for GRC */
42 BAR_ID_1 /* Used for doorbells */
45 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
47 u32 bar_reg = (bar_id == BAR_ID_0 ?
48 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
49 u32 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
51 /* The above registers were updated in the past only in CMT mode. Since
52 * they were found to be useful MFW started updating them from 8.7.7.0.
53 * In older MFW versions they are set to 0 which means disabled.
56 if (p_hwfn->p_dev->num_hwfns > 1) {
57 DP_NOTICE(p_hwfn, false,
58 "BAR size not configured. Assuming BAR"
59 " size of 256kB for GRC and 512kB for DB\n");
60 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
63 DP_NOTICE(p_hwfn, false,
64 "BAR size not configured. Assuming BAR"
65 " size of 512kB for GRC and 512kB for DB\n");
69 return 1 << (val + 15);
72 void ecore_init_dp(struct ecore_dev *p_dev,
73 u32 dp_module, u8 dp_level, void *dp_ctx)
77 p_dev->dp_level = dp_level;
78 p_dev->dp_module = dp_module;
79 p_dev->dp_ctx = dp_ctx;
80 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
81 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
83 p_hwfn->dp_level = dp_level;
84 p_hwfn->dp_module = dp_module;
85 p_hwfn->dp_ctx = dp_ctx;
89 void ecore_init_struct(struct ecore_dev *p_dev)
93 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
94 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
96 p_hwfn->p_dev = p_dev;
98 p_hwfn->b_active = false;
100 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
101 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
104 /* hwfn 0 is always active */
105 p_dev->hwfns[0].b_active = true;
107 /* set the default cache alignment to 128 (may be overridden later) */
108 p_dev->cache_shift = 7;
111 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
113 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
115 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
116 qm_info->qm_pq_params = OSAL_NULL;
117 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
118 qm_info->qm_vport_params = OSAL_NULL;
119 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
120 qm_info->qm_port_params = OSAL_NULL;
121 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
122 qm_info->wfq_data = OSAL_NULL;
125 void ecore_resc_free(struct ecore_dev *p_dev)
129 OSAL_FREE(p_dev, p_dev->fw_data);
130 p_dev->fw_data = OSAL_NULL;
132 OSAL_FREE(p_dev, p_dev->reset_stats);
134 for_each_hwfn(p_dev, i) {
135 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
137 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
138 p_hwfn->p_tx_cids = OSAL_NULL;
139 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
140 p_hwfn->p_rx_cids = OSAL_NULL;
143 for_each_hwfn(p_dev, i) {
144 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
146 ecore_cxt_mngr_free(p_hwfn);
147 ecore_qm_info_free(p_hwfn);
148 ecore_spq_free(p_hwfn);
149 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
150 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
151 ecore_int_free(p_hwfn);
152 ecore_dmae_info_free(p_hwfn);
153 /* @@@TBD Flush work-queue ? */
157 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
160 u8 num_vports, vf_offset = 0, i, vport_id, num_ports;
161 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
162 struct init_qm_port_params *p_qm_port;
163 u16 num_pqs, multi_cos_tcs = 1;
166 OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
169 /* @TMP - Don't allocate QM queues for VFs on emulation */
170 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
171 DP_NOTICE(p_hwfn, false,
172 "Emulation - skip configuring QM queues for VFs\n");
177 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
178 num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
180 /* Sanity checking that setup requires legal number of resources */
181 if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
183 "Need too many Physical queues - 0x%04x when"
184 " only %04x are available\n",
185 num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
189 /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
190 * then special queues, then per-VF PQ.
192 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
193 b_sleepable ? GFP_KERNEL :
195 sizeof(struct init_qm_pq_params) *
197 if (!qm_info->qm_pq_params)
200 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
201 b_sleepable ? GFP_KERNEL :
204 init_qm_vport_params) *
206 if (!qm_info->qm_vport_params)
209 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
210 b_sleepable ? GFP_KERNEL :
212 sizeof(struct init_qm_port_params)
214 if (!qm_info->qm_port_params)
217 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
218 b_sleepable ? GFP_KERNEL :
220 sizeof(struct ecore_wfq_data) *
223 if (!qm_info->wfq_data)
226 vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
228 /* First init per-TC PQs */
229 for (i = 0; i < multi_cos_tcs; i++) {
230 struct init_qm_pq_params *params = &qm_info->qm_pq_params[i];
232 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
233 params->vport_id = vport_id;
234 params->tc_id = p_hwfn->hw_info.non_offload_tc;
235 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
237 params->vport_id = vport_id;
238 params->tc_id = p_hwfn->hw_info.offload_tc;
239 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
243 /* Then init pure-LB PQ */
244 qm_info->pure_lb_pq = i;
245 qm_info->qm_pq_params[i].vport_id =
246 (u8)RESC_START(p_hwfn, ECORE_VPORT);
247 qm_info->qm_pq_params[i].tc_id = PURE_LB_TC;
248 qm_info->qm_pq_params[i].wrr_group = 1;
251 /* Then init per-VF PQs */
253 for (i = 0; i < num_vfs; i++) {
254 /* First vport is used by the PF */
255 qm_info->qm_pq_params[vf_offset + i].vport_id = vport_id +
257 qm_info->qm_pq_params[vf_offset + i].tc_id =
258 p_hwfn->hw_info.non_offload_tc;
259 qm_info->qm_pq_params[vf_offset + i].wrr_group = 1;
262 qm_info->vf_queues_offset = vf_offset;
263 qm_info->num_pqs = num_pqs;
264 qm_info->num_vports = num_vports;
266 /* Initialize qm port parameters */
267 num_ports = p_hwfn->p_dev->num_ports_in_engines;
268 for (i = 0; i < num_ports; i++) {
269 p_qm_port = &qm_info->qm_port_params[i];
270 p_qm_port->active = 1;
272 p_qm_port->num_active_phys_tcs = 2;
274 p_qm_port->num_active_phys_tcs = 5;
275 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
276 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
279 if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
280 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
282 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
284 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
286 qm_info->num_vf_pqs = num_vfs;
287 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
289 for (i = 0; i < qm_info->num_vports; i++)
290 qm_info->qm_vport_params[i].vport_wfq = 1;
294 qm_info->vport_rl_en = 1;
295 qm_info->vport_wfq_en = 1;
297 return ECORE_SUCCESS;
300 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
301 ecore_qm_info_free(p_hwfn);
305 /* This function reconfigures the QM pf on the fly.
306 * For this purpose we:
307 * 1. reconfigure the QM database
308 * 2. set new values to runtime arrat
309 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
310 * 4. activate init tool in QM_PF stage
311 * 5. send an sdm_qm_cmd through rbc interface to release the QM
313 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
314 struct ecore_ptt *p_ptt)
316 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
317 enum _ecore_status_t rc;
320 /* qm_info is allocated in ecore_init_qm_info() which is already called
321 * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
322 * The allocated size may change each init, so we free it before next
325 ecore_qm_info_free(p_hwfn);
327 /* initialize ecore's qm data structure */
328 rc = ecore_init_qm_info(p_hwfn, false);
329 if (rc != ECORE_SUCCESS)
332 /* stop PF's qm queues */
333 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
334 qm_info->start_pq, qm_info->num_pqs);
338 /* clear the QM_PF runtime phase leftovers from previous init */
339 ecore_init_clear_rt_data(p_hwfn);
341 /* prepare QM portion of runtime array */
342 ecore_qm_init_pf(p_hwfn);
344 /* activate init tool on runtime array */
345 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
346 p_hwfn->hw_info.hw_mode);
347 if (rc != ECORE_SUCCESS)
350 /* start PF's qm queues */
351 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
352 qm_info->start_pq, qm_info->num_pqs);
356 return ECORE_SUCCESS;
359 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
361 enum _ecore_status_t rc = ECORE_SUCCESS;
362 struct ecore_consq *p_consq;
363 struct ecore_eq *p_eq;
366 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
367 sizeof(struct ecore_fw_data));
371 /* Allocate Memory for the Queue->CID mapping */
372 for_each_hwfn(p_dev, i) {
373 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
375 /* @@@TMP - resc management, change to actual required size */
376 int tx_size = sizeof(struct ecore_hw_cid_data) *
377 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
378 int rx_size = sizeof(struct ecore_hw_cid_data) *
379 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
381 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
383 if (!p_hwfn->p_tx_cids) {
384 DP_NOTICE(p_hwfn, true,
385 "Failed to allocate memory for Tx Cids\n");
389 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
391 if (!p_hwfn->p_rx_cids) {
392 DP_NOTICE(p_hwfn, true,
393 "Failed to allocate memory for Rx Cids\n");
398 for_each_hwfn(p_dev, i) {
399 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
401 /* First allocate the context manager structure */
402 rc = ecore_cxt_mngr_alloc(p_hwfn);
406 /* Set the HW cid/tid numbers (in the contest manager)
407 * Must be done prior to any further computations.
409 rc = ecore_cxt_set_pf_params(p_hwfn);
413 /* Prepare and process QM requirements */
414 rc = ecore_init_qm_info(p_hwfn, true);
418 /* Compute the ILT client partition */
419 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
423 /* CID map / ILT shadow table / T2
424 * The talbes sizes are determined by the computations above
426 rc = ecore_cxt_tables_alloc(p_hwfn);
430 /* SPQ, must follow ILT because initializes SPQ context */
431 rc = ecore_spq_alloc(p_hwfn);
435 /* SP status block allocation */
436 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
439 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
444 p_eq = ecore_eq_alloc(p_hwfn, 256);
449 p_consq = ecore_consq_alloc(p_hwfn);
452 p_hwfn->p_consq = p_consq;
454 /* DMA info initialization */
455 rc = ecore_dmae_info_alloc(p_hwfn);
457 DP_NOTICE(p_hwfn, true,
458 "Failed to allocate memory for"
459 " dmae_info structure\n");
464 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
465 sizeof(struct ecore_eth_stats));
466 if (!p_dev->reset_stats) {
467 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
471 return ECORE_SUCCESS;
476 ecore_resc_free(p_dev);
480 void ecore_resc_setup(struct ecore_dev *p_dev)
484 for_each_hwfn(p_dev, i) {
485 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
487 ecore_cxt_mngr_setup(p_hwfn);
488 ecore_spq_setup(p_hwfn);
489 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
490 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
492 /* Read shadow of current MFW mailbox */
493 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
494 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
495 p_hwfn->mcp_info->mfw_mb_cur,
496 p_hwfn->mcp_info->mfw_mb_length);
498 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
502 #define FINAL_CLEANUP_POLL_CNT (100)
503 #define FINAL_CLEANUP_POLL_TIME (10)
504 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
505 struct ecore_ptt *p_ptt,
508 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
509 enum _ecore_status_t rc = ECORE_TIMEOUT;
512 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
513 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
514 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
515 return ECORE_SUCCESS;
519 addr = GTT_BAR0_MAP_REG_USDM_RAM +
520 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
525 command |= X_FINAL_CLEANUP_AGG_INT <<
526 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
527 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
528 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
529 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
531 /* Make sure notification is not set before initiating final cleanup */
532 if (REG_RD(p_hwfn, addr)) {
533 DP_NOTICE(p_hwfn, false,
534 "Unexpected; Found final cleanup notification "
535 "before initiating final cleanup\n");
536 REG_WR(p_hwfn, addr, 0);
539 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
540 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
541 id, OSAL_CPU_TO_LE32(command));
543 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
544 OSAL_CPU_TO_LE32(command));
546 /* Poll until completion */
547 while (!REG_RD(p_hwfn, addr) && count--)
548 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
550 if (REG_RD(p_hwfn, addr))
553 DP_NOTICE(p_hwfn, true,
554 "Failed to receive FW final cleanup notification\n");
556 /* Cleanup afterwards */
557 REG_WR(p_hwfn, addr, 0);
562 static void ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
566 switch (ECORE_GET_TYPE(p_hwfn->p_dev)) {
568 hw_mode |= 1 << MODE_BB_A0;
571 hw_mode |= 1 << MODE_BB_B0;
574 hw_mode |= 1 << MODE_K2;
577 DP_NOTICE(p_hwfn, true, "Can't initialize chip ID %d\n",
578 ECORE_GET_TYPE(p_hwfn->p_dev));
582 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
583 switch (p_hwfn->p_dev->num_ports_in_engines) {
585 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
588 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
591 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
594 DP_NOTICE(p_hwfn, true,
595 "num_ports_in_engine = %d not supported\n",
596 p_hwfn->p_dev->num_ports_in_engines);
600 switch (p_hwfn->p_dev->mf_mode) {
601 case ECORE_MF_DEFAULT:
603 hw_mode |= 1 << MODE_MF_SI;
606 hw_mode |= 1 << MODE_MF_SD;
609 DP_NOTICE(p_hwfn, true,
610 "Unsupported MF mode, init as DEFAULT\n");
611 hw_mode |= 1 << MODE_MF_SI;
615 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
616 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
617 hw_mode |= 1 << MODE_FPGA;
619 if (p_hwfn->p_dev->b_is_emul_full)
620 hw_mode |= 1 << MODE_EMUL_FULL;
622 hw_mode |= 1 << MODE_EMUL_REDUCED;
626 hw_mode |= 1 << MODE_ASIC;
628 if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn))
629 hw_mode |= 1 << MODE_EAGLE_ENG1_WORKAROUND;
631 if (p_hwfn->p_dev->num_hwfns > 1)
632 hw_mode |= 1 << MODE_100G;
634 p_hwfn->hw_info.hw_mode = hw_mode;
636 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
637 "Configuring function for hw_mode: 0x%08x\n",
638 p_hwfn->hw_info.hw_mode);
642 /* MFW-replacement initializations for non-ASIC */
643 static void ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
644 struct ecore_ptt *p_ptt)
649 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
652 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
654 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
655 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
657 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
658 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
659 if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
660 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
662 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
663 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
664 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
665 (p_hwfn->p_dev->num_ports_in_engines >> 1));
667 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
668 p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
672 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
673 for (i = 0; i < 100; i++) {
675 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
679 DP_NOTICE(p_hwfn, true,
680 "RBC done failed to complete in PSWRQ2\n");
684 /* Init run time data for all PFs and their VFs on an engine.
685 * TBD - for VFs - Once we have parent PF info for each VF in
686 * shmem available as CAU requires knowledge of parent PF for each VF.
688 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
690 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
693 for_each_hwfn(p_dev, i) {
694 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
695 struct ecore_igu_info *p_igu_info;
696 struct ecore_igu_block *p_block;
697 struct cau_sb_entry sb_entry;
699 p_igu_info = p_hwfn->hw_info.p_igu_info;
701 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
703 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
708 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
709 p_block->function_id, 0, 0);
710 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
715 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
716 struct ecore_ptt *p_ptt,
719 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
720 enum _ecore_status_t rc = ECORE_SUCCESS;
721 struct ecore_dev *p_dev = p_hwfn->p_dev;
722 u8 vf_id, max_num_vfs;
726 ecore_init_cau_rt_data(p_dev);
728 /* Program GTT windows */
729 ecore_gtt_init(p_hwfn);
732 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
733 ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
736 if (p_hwfn->mcp_info) {
737 if (p_hwfn->mcp_info->func_info.bandwidth_max)
738 qm_info->pf_rl_en = 1;
739 if (p_hwfn->mcp_info->func_info.bandwidth_min)
740 qm_info->pf_wfq_en = 1;
743 ecore_qm_common_rt_init(p_hwfn,
744 p_hwfn->p_dev->num_ports_in_engines,
745 qm_info->max_phys_tcs_per_port,
746 qm_info->pf_rl_en, qm_info->pf_wfq_en,
747 qm_info->vport_rl_en, qm_info->vport_wfq_en,
748 qm_info->qm_port_params);
750 ecore_cxt_hw_init_common(p_hwfn);
752 /* Close gate from NIG to BRB/Storm; By default they are open, but
753 * we close them to prevent NIG from passing data to reset blocks.
754 * Should have been done in the ENGINE phase, but init-tool lacks
755 * proper port-pretend capabilities.
757 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
758 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
759 ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
760 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
761 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
762 ecore_port_unpretend(p_hwfn, p_ptt);
764 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
765 if (rc != ECORE_SUCCESS)
768 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
769 * need to decide with which value, maybe runtime
771 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
772 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
774 if (ECORE_IS_BB(p_hwfn->p_dev)) {
775 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
778 /* pretend to original PF */
779 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
782 /* Workaround for avoiding CCFC execution error when getting packets
783 * with CRC errors, and allowing instead the invoking of the FW error
785 * This is not done inside the init tool since it currently can't
786 * perform a pretending to VFs.
788 max_num_vfs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_VFS_K2
790 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
791 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
792 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
793 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
795 /* pretend to original PF */
796 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
802 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
803 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
805 #define PMEG_IF_BYTE_COUNT 8
807 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
808 struct ecore_ptt *p_ptt,
809 u32 addr, u64 data, u8 reg_type, u8 port)
811 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
812 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
813 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
814 (8 << PMEG_IF_BYTE_COUNT),
815 (reg_type << 25) | (addr << 8) | port,
816 (u32)((data >> 32) & 0xffffffff),
817 (u32)(data & 0xffffffff));
819 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
820 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
821 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
822 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
823 (reg_type << 25) | (addr << 8) | port);
824 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
826 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
827 (data >> 32) & 0xffffffff);
830 #define XLPORT_MODE_REG (0x20a)
831 #define XLPORT_MAC_CONTROL (0x210)
832 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
833 #define XLPORT_ENABLE_REG (0x20b)
835 #define XLMAC_CTRL (0x600)
836 #define XLMAC_MODE (0x601)
837 #define XLMAC_RX_MAX_SIZE (0x608)
838 #define XLMAC_TX_CTRL (0x604)
839 #define XLMAC_PAUSE_CTRL (0x60d)
840 #define XLMAC_PFC_CTRL (0x60e)
842 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
843 struct ecore_ptt *p_ptt)
845 u8 port = p_hwfn->port_id;
846 u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
848 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
849 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
850 (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
851 | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
853 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
854 1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
856 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
857 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
859 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
860 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
862 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
863 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
865 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
866 (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
867 (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
869 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
872 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
873 struct ecore_ptt *p_ptt)
875 u8 loopback = 0, port = p_hwfn->port_id * 2;
877 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
879 if (ECORE_IS_AH(p_hwfn->p_dev)) {
880 ecore_emul_link_init_ah(p_hwfn, p_ptt);
884 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
886 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
887 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
888 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
889 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
890 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
891 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
893 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
894 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
895 0x30ffffc000ULL, 0, port);
896 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
898 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x1003 | (loopback << 2),
900 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
901 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
904 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
905 struct ecore_ptt *p_ptt, u8 port)
907 int port_offset = port ? 0x800 : 0;
911 /* FIXME: move to common start */
912 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
913 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
915 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
916 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
918 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
920 /* Set the number of ports on the Warp Core to 10G */
921 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
923 /* Soft reset of XMAC */
924 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
925 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
927 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
928 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
930 /* FIXME: move to common end */
931 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
932 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
934 /* Set Max packet size: initialize XMAC block register for port 0 */
935 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
937 /* CRC append for Tx packets: init XMAC block register for port 1 */
938 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
940 /* Enable TX and RX: initialize XMAC block register for port 1 */
941 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
942 XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
943 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
944 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
945 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
949 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
950 struct ecore_ptt *p_ptt,
953 enum _ecore_status_t rc = ECORE_SUCCESS;
956 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
958 if (rc != ECORE_SUCCESS)
962 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
963 return ECORE_SUCCESS;
965 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
966 if (ECORE_IS_AH(p_hwfn->p_dev))
967 return ECORE_SUCCESS;
968 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
969 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
970 if (p_hwfn->p_dev->num_hwfns > 1) {
971 /* Activate OPTE in CMT */
974 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
976 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
977 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
978 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
979 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
980 ecore_wr(p_hwfn, p_ptt,
981 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
982 ecore_wr(p_hwfn, p_ptt,
983 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
984 ecore_wr(p_hwfn, p_ptt,
985 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
989 ecore_emul_link_init(p_hwfn, p_ptt);
991 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
998 static enum _ecore_status_t
999 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1000 struct ecore_ptt *p_ptt)
1002 u32 pwm_regsize, norm_regsize;
1003 u32 non_pwm_conn, min_addr_reg1;
1004 u32 db_bar_size, n_cpus;
1006 int rc = ECORE_SUCCESS;
1008 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1009 if (p_hwfn->p_dev->num_hwfns > 1)
1012 /* Calculate doorbell regions
1013 * -----------------------------------
1014 * The doorbell BAR is made of two regions. The first is called normal
1015 * region and the second is called PWM region. In the normal region
1016 * each ICID has its own set of addresses so that writing to that
1017 * specific address identifies the ICID. In the Process Window Mode
1018 * region the ICID is given in the data written to the doorbell. The
1019 * above per PF register denotes the offset in the doorbell BAR in which
1020 * the PWM region begins.
1021 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1022 * non-PWM connection. The calculation below computes the total non-PWM
1023 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1024 * in units of 4,096 bytes.
1026 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1027 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1029 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1030 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1031 min_addr_reg1 = norm_regsize / 4096;
1032 pwm_regsize = db_bar_size - norm_regsize;
1034 /* Check that the normal and PWM sizes are valid */
1035 if (db_bar_size < norm_regsize) {
1036 DP_ERR(p_hwfn->p_dev,
1037 "Doorbell BAR size 0x%x is too"
1038 " small (normal region is 0x%0x )\n",
1039 db_bar_size, norm_regsize);
1040 return ECORE_NORESOURCES;
1042 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1043 DP_ERR(p_hwfn->p_dev,
1044 "PWM region size 0x%0x is too small."
1045 " Should be at least 0x%0x (Doorbell BAR size"
1046 " is 0x%x and normal region size is 0x%0x)\n",
1047 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1049 return ECORE_NORESOURCES;
1053 p_hwfn->dpi_start_offset = norm_regsize; /* this is later used to
1054 * calculate the doorbell
1058 /* Update registers */
1059 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1060 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1061 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1062 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1065 "Doorbell size 0x%x, Normal region 0x%x, PWM region 0x%x\n",
1066 db_bar_size, norm_regsize, pwm_regsize);
1067 DP_INFO(p_hwfn, "DPI size 0x%x, DPI count 0x%x\n", p_hwfn->dpi_size,
1070 return ECORE_SUCCESS;
1073 static enum _ecore_status_t
1074 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1075 struct ecore_ptt *p_ptt,
1076 struct ecore_tunn_start_params *p_tunn,
1079 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1081 enum _ecore_status_t rc = ECORE_SUCCESS;
1082 u8 rel_pf_id = p_hwfn->rel_pf_id;
1088 if (p_hwfn->mcp_info) {
1089 struct ecore_mcp_function_info *p_info;
1091 p_info = &p_hwfn->mcp_info->func_info;
1092 if (p_info->bandwidth_min)
1093 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1095 /* Update rate limit once we'll actually have a link */
1096 p_hwfn->qm_info.pf_rl = 100;
1098 ecore_cxt_hw_init_pf(p_hwfn);
1100 ecore_int_igu_init_rt(p_hwfn); /* @@@TBD TODO MichalS multi hwfn ?? */
1102 /* Set VLAN in NIG if needed */
1103 if (hw_mode & (1 << MODE_MF_SD)) {
1104 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1105 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1106 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1107 p_hwfn->hw_info.ovlan);
1110 /* Enable classification by MAC if needed */
1111 if (hw_mode & (1 << MODE_MF_SI)) {
1112 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1113 "Configuring TAGMAC_CLS_TYPE\n");
1114 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1118 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1119 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
1121 /* perform debug configuration when chip is out of reset */
1122 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1124 /* Cleanup chip from previous driver if such remains exist */
1125 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1126 if (rc != ECORE_SUCCESS) {
1127 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1131 /* PF Init sequence */
1132 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1136 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1137 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1141 /* Pure runtime initializations - directly to the HW */
1142 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1144 /* PCI relaxed ordering causes a decrease in the performance on some
1145 * systems. Till a root cause is found, disable this attribute in the
1149 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1151 * DP_NOTICE(p_hwfn, true,
1152 * "Failed to find the PCI Express"
1153 * " Capability structure in the PCI config space\n");
1156 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL,
1158 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1159 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL,
1163 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1168 /* enable interrupts */
1169 ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1171 /* send function start command */
1172 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1173 allow_npar_tx_switch);
1175 DP_NOTICE(p_hwfn, true,
1176 "Function start ramrod failed\n");
1178 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1179 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1180 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1182 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1183 "PRS_REG_SEARCH register after start PFn\n");
1184 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1185 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1186 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1187 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1188 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1189 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1190 prs_reg = ecore_rd(p_hwfn, p_ptt,
1191 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1192 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1193 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1195 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1196 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1197 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1203 static enum _ecore_status_t
1204 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1205 struct ecore_ptt *p_ptt, u8 enable)
1207 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1209 /* Change PF in PXP */
1210 ecore_wr(p_hwfn, p_ptt,
1211 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1213 /* wait until value is set - try for 1 second every 50us */
1214 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1215 val = ecore_rd(p_hwfn, p_ptt,
1216 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1223 if (val != set_val) {
1224 DP_NOTICE(p_hwfn, true,
1225 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1226 return ECORE_UNKNOWN_ERROR;
1229 return ECORE_SUCCESS;
1232 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1233 struct ecore_ptt *p_main_ptt)
1235 /* Read shadow of current MFW mailbox */
1236 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1237 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1238 p_hwfn->mcp_info->mfw_mb_cur,
1239 p_hwfn->mcp_info->mfw_mb_length);
1242 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1243 struct ecore_tunn_start_params *p_tunn,
1245 enum ecore_int_mode int_mode,
1246 bool allow_npar_tx_switch,
1247 const u8 *bin_fw_data)
1249 enum _ecore_status_t rc, mfw_rc;
1250 u32 load_code, param;
1253 rc = ecore_init_fw_data(p_dev, bin_fw_data);
1254 if (rc != ECORE_SUCCESS)
1257 for_each_hwfn(p_dev, i) {
1258 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1260 /* Enable DMAE in PXP */
1261 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1263 ecore_calc_hw_mode(p_hwfn);
1264 /* @@@TBD need to add here:
1265 * Check for fan failure
1268 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1270 DP_NOTICE(p_hwfn, true,
1271 "Failed sending LOAD_REQ command\n");
1276 * When coming back from hiberbate state, the registers from
1277 * which shadow is read initially are not initialized. It turns
1278 * out that these registers get initialized during the call to
1279 * ecore_mcp_load_req request. So we need to reread them here
1280 * to get the proper shadow register value.
1281 * Note: This is a workaround for the missinginig MFW
1282 * initialization. It may be removed once the implementation
1285 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1287 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1288 "Load request was sent.Resp:0x%x, Load code: 0x%x\n",
1291 /* Only relevant for recovery:
1292 * Clear the indication after the LOAD_REQ command is responded
1295 p_dev->recov_in_prog = false;
1297 p_hwfn->first_on_engine = (load_code ==
1298 FW_MSG_CODE_DRV_LOAD_ENGINE);
1300 switch (load_code) {
1301 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1302 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1303 p_hwfn->hw_info.hw_mode);
1307 case FW_MSG_CODE_DRV_LOAD_PORT:
1308 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1309 p_hwfn->hw_info.hw_mode);
1313 if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
1314 struct init_nig_pri_tc_map_req tc_map;
1316 OSAL_MEM_ZERO(&tc_map, sizeof(tc_map));
1318 /* remove this once flow control is
1321 for (j = 0; j < NUM_OF_VLAN_PRIORITIES; j++) {
1322 tc_map.pri[j].tc_id = 0;
1323 tc_map.pri[j].valid = 1;
1325 ecore_init_nig_pri_tc_map(p_hwfn,
1330 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1331 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1332 p_tunn, p_hwfn->hw_info.hw_mode,
1333 b_hw_start, int_mode,
1334 allow_npar_tx_switch);
1341 if (rc != ECORE_SUCCESS)
1342 DP_NOTICE(p_hwfn, true,
1343 "init phase failed loadcode 0x%x (rc %d)\n",
1346 /* ACK mfw regardless of success or failure of initialization */
1347 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1348 DRV_MSG_CODE_LOAD_DONE,
1349 0, &load_code, ¶m);
1350 if (rc != ECORE_SUCCESS)
1352 if (mfw_rc != ECORE_SUCCESS) {
1353 DP_NOTICE(p_hwfn, true,
1354 "Failed sending LOAD_DONE command\n");
1358 p_hwfn->hw_init_done = true;
1361 return ECORE_SUCCESS;
1364 #define ECORE_HW_STOP_RETRY_LIMIT (10)
1365 static OSAL_INLINE void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1366 struct ecore_hwfn *p_hwfn,
1367 struct ecore_ptt *p_ptt)
1372 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1373 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1374 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT &&
1375 !p_dev->recov_in_prog; i++) {
1376 if ((!ecore_rd(p_hwfn, p_ptt,
1377 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1378 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1381 /* Dependent on number of connection/tasks, possibly
1382 * 1ms sleep is required between polls
1386 if (i == ECORE_HW_STOP_RETRY_LIMIT)
1387 DP_NOTICE(p_hwfn, true,
1388 "Timers linear scans are not over"
1389 " [Connection %02x Tasks %02x]\n",
1390 (u8)ecore_rd(p_hwfn, p_ptt,
1391 TM_REG_PF_SCAN_ACTIVE_CONN),
1392 (u8)ecore_rd(p_hwfn, p_ptt,
1393 TM_REG_PF_SCAN_ACTIVE_TASK));
1396 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1400 for_each_hwfn(p_dev, j) {
1401 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1402 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1404 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1408 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1410 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1413 for_each_hwfn(p_dev, j) {
1414 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1415 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1417 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1419 /* mark the hw as uninitialized... */
1420 p_hwfn->hw_init_done = false;
1422 rc = ecore_sp_pf_stop(p_hwfn);
1424 DP_NOTICE(p_hwfn, true,
1425 "Failed to close PF against FW. Continue to"
1426 " stop HW to prevent illegal host access"
1427 " by the device\n");
1429 /* perform debug action after PF stop was sent */
1430 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1432 /* close NIG to BRB gate */
1433 ecore_wr(p_hwfn, p_ptt,
1434 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1437 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1438 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1439 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1441 /* @@@TBD - clean transmission queues (5.b) */
1442 /* @@@TBD - clean BTB (5.c) */
1444 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1446 /* @@@TBD - verify DMAE requests are done (8) */
1448 /* Disable Attention Generation */
1449 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1450 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1451 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1452 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1453 /* Need to wait 1ms to guarantee SBs are cleared */
1457 /* Disable DMAE in PXP - in CMT, this should only be done for
1458 * first hw-function, and only after all transactions have
1459 * stopped for all active hw-functions.
1461 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1462 p_dev->hwfns[0].p_main_ptt, false);
1463 if (t_rc != ECORE_SUCCESS)
1469 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1473 for_each_hwfn(p_dev, j) {
1474 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1475 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1477 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1478 "Shutting down the fastpath\n");
1480 ecore_wr(p_hwfn, p_ptt,
1481 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1483 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1484 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1485 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1487 /* @@@TBD - clean transmission queues (5.b) */
1488 /* @@@TBD - clean BTB (5.c) */
1490 /* @@@TBD - verify DMAE requests are done (8) */
1492 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1493 /* Need to wait 1ms to guarantee SBs are cleared */
1498 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1500 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1502 /* Re-open incoming traffic */
1503 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1504 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1507 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1508 struct ecore_ptt *p_ptt, u32 reg,
1511 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1513 if (assert_val != expected) {
1514 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1516 return ECORE_UNKNOWN_ERROR;
1522 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1524 enum _ecore_status_t rc = ECORE_SUCCESS;
1525 u32 unload_resp, unload_param;
1528 for_each_hwfn(p_dev, i) {
1529 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1531 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1533 /* Check for incorrect states */
1534 if (!p_dev->recov_in_prog) {
1535 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1536 QM_REG_USG_CNT_PF_TX, 0);
1537 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1538 QM_REG_USG_CNT_PF_OTHER, 0);
1539 /* @@@TBD - assert on incorrect xCFC values (10.b) */
1542 /* Disable PF in HW blocks */
1543 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1544 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1545 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1546 TCFC_REG_STRONG_ENABLE_PF, 0);
1547 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1548 CCFC_REG_STRONG_ENABLE_PF, 0);
1550 if (p_dev->recov_in_prog) {
1551 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1552 "Recovery is in progress -> skip "
1553 "sending unload_req/done\n");
1557 /* Send unload command to MCP */
1558 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1559 DRV_MSG_CODE_UNLOAD_REQ,
1560 DRV_MB_PARAM_UNLOAD_WOL_MCP,
1561 &unload_resp, &unload_param);
1562 if (rc != ECORE_SUCCESS) {
1563 DP_NOTICE(p_hwfn, true,
1564 "ecore_hw_reset: UNLOAD_REQ failed\n");
1565 /* @@TBD - what to do? for now, assume ENG. */
1566 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1569 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1570 DRV_MSG_CODE_UNLOAD_DONE,
1571 0, &unload_resp, &unload_param);
1572 if (rc != ECORE_SUCCESS) {
1574 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
1575 /* @@@TBD - Should it really ASSERT here ? */
1583 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1584 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
1586 ecore_ptt_pool_free(p_hwfn);
1587 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
1590 /* Setup bar access */
1591 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
1593 /* clear indirect access */
1594 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1595 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1596 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1597 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1599 /* Clean Previous errors if such exist */
1600 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1601 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1603 /* enable internal target-read */
1604 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1605 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1608 static void get_function_id(struct ecore_hwfn *p_hwfn)
1611 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
1612 PXP_PF_ME_OPAQUE_ADDR);
1614 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1616 /* Bits 16-19 from the ME registers are the pf_num */
1617 /* @@ @TBD - check, may be wrong after B0 implementation for CMT */
1618 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1619 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1620 PXP_CONCRETE_FID_PFID);
1621 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1622 PXP_CONCRETE_FID_PORT);
1624 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1625 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1626 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
1629 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
1631 u32 *feat_num = p_hwfn->hw_info.feat_num;
1632 int num_features = 1;
1634 /* L2 Queues require each: 1 status block. 1 L2 queue */
1635 feat_num[ECORE_PF_L2_QUE] =
1637 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
1638 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
1640 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1641 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1642 feat_num[ECORE_PF_L2_QUE],
1643 RESC_NUM(p_hwfn, ECORE_SB), num_features);
1646 /* @@@TBD MK RESC: This info is currently hard code and set as if we were MF
1647 * need to read it from shmem...
1649 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn)
1651 u32 *resc_start = p_hwfn->hw_info.resc_start;
1652 u8 num_funcs = p_hwfn->num_funcs_on_engine;
1653 u32 *resc_num = p_hwfn->hw_info.resc_num;
1654 int i, max_vf_vlan_filters;
1655 struct ecore_sb_cnt_info sb_cnt_info;
1656 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
1658 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
1660 max_vf_vlan_filters = 0;
1662 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1663 resc_num[ECORE_SB] = OSAL_MIN_T(u32,
1664 (MAX_SB_PER_PATH_BB / num_funcs),
1665 sb_cnt_info.sb_cnt);
1667 resc_num[ECORE_L2_QUEUE] = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
1668 MAX_NUM_L2_QUEUES_BB) / num_funcs;
1669 resc_num[ECORE_VPORT] = (b_ah ? MAX_NUM_VPORTS_K2 :
1670 MAX_NUM_VPORTS_BB) / num_funcs;
1671 resc_num[ECORE_RSS_ENG] = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
1672 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
1673 resc_num[ECORE_PQ] = (b_ah ? MAX_QM_TX_QUEUES_K2 :
1674 MAX_QM_TX_QUEUES_BB) / num_funcs;
1675 resc_num[ECORE_RL] = 8;
1676 resc_num[ECORE_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1677 resc_num[ECORE_VLAN] = (ETH_NUM_VLAN_FILTERS -
1678 max_vf_vlan_filters +
1679 1 /*For vlan0 */) / num_funcs;
1681 /* TODO - there will be a problem in AH - there are only 11k lines */
1682 resc_num[ECORE_ILT] = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
1683 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
1686 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1687 /* Reduced build contains less PQs */
1688 if (!(p_hwfn->p_dev->b_is_emul_full))
1689 resc_num[ECORE_PQ] = 32;
1691 /* For AH emulation, since we have a possible maximal number of
1692 * 16 enabled PFs, in case there are not enough ILT lines -
1693 * allocate only first PF as RoCE and have all the other ETH
1694 * only with less ILT lines.
1696 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
1697 resc_num[ECORE_ILT] = resc_num[ECORE_ILT];
1701 for (i = 0; i < ECORE_MAX_RESC; i++)
1702 resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
1705 /* Correct the common ILT calculation if PF0 has more */
1706 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
1707 p_hwfn->p_dev->b_is_emul_full &&
1708 p_hwfn->rel_pf_id && resc_num[ECORE_ILT])
1709 resc_start[ECORE_ILT] += resc_num[ECORE_ILT];
1712 /* Sanity for ILT */
1713 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
1714 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
1715 DP_NOTICE(p_hwfn, true,
1716 "Can't assign ILT pages [%08x,...,%08x]\n",
1717 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
1723 ecore_hw_set_feat(p_hwfn);
1725 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1726 "The numbers for each resource are:\n"
1727 "SB = %d start = %d\n"
1728 "L2_QUEUE = %d start = %d\n"
1729 "VPORT = %d start = %d\n"
1730 "PQ = %d start = %d\n"
1731 "RL = %d start = %d\n"
1732 "MAC = %d start = %d\n"
1733 "VLAN = %d start = %d\n"
1734 "ILT = %d start = %d\n"
1735 "CMDQS_CQS = %d start = %d\n",
1736 RESC_NUM(p_hwfn, ECORE_SB), RESC_START(p_hwfn, ECORE_SB),
1737 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
1738 RESC_START(p_hwfn, ECORE_L2_QUEUE),
1739 RESC_NUM(p_hwfn, ECORE_VPORT),
1740 RESC_START(p_hwfn, ECORE_VPORT),
1741 RESC_NUM(p_hwfn, ECORE_PQ), RESC_START(p_hwfn, ECORE_PQ),
1742 RESC_NUM(p_hwfn, ECORE_RL), RESC_START(p_hwfn, ECORE_RL),
1743 RESC_NUM(p_hwfn, ECORE_MAC), RESC_START(p_hwfn, ECORE_MAC),
1744 RESC_NUM(p_hwfn, ECORE_VLAN),
1745 RESC_START(p_hwfn, ECORE_VLAN),
1746 RESC_NUM(p_hwfn, ECORE_ILT), RESC_START(p_hwfn, ECORE_ILT),
1747 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS),
1748 RESC_START(p_hwfn, ECORE_CMDQS_CQS));
1750 return ECORE_SUCCESS;
1753 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
1754 struct ecore_ptt *p_ptt)
1756 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1757 u32 port_cfg_addr, link_temp, device_capabilities;
1758 struct ecore_mcp_link_params *link;
1760 /* Read global nvm_cfg address */
1761 u32 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1763 /* Verify MCP has initialized it */
1764 if (nvm_cfg_addr == 0) {
1765 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
1769 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1770 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1772 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1773 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
1776 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
1778 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1779 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1780 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G:
1781 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
1783 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G:
1784 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
1786 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G:
1787 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
1789 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F:
1790 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
1792 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E:
1793 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
1795 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G:
1796 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
1798 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G:
1799 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
1801 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G:
1802 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
1804 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G:
1805 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
1808 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
1813 /* Read default link configuration */
1814 link = &p_hwfn->mcp_info->link_input;
1815 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1816 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1817 link_temp = ecore_rd(p_hwfn, p_ptt,
1819 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
1820 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1821 link->speed.advertised_speeds = link_temp;
1823 link_temp = link->speed.advertised_speeds;
1824 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
1826 link_temp = ecore_rd(p_hwfn, p_ptt,
1828 OFFSETOF(struct nvm_cfg1_port, link_settings));
1829 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1830 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1831 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1832 link->speed.autoneg = true;
1834 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1835 link->speed.forced_speed = 1000;
1837 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1838 link->speed.forced_speed = 10000;
1840 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1841 link->speed.forced_speed = 25000;
1843 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1844 link->speed.forced_speed = 40000;
1846 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1847 link->speed.forced_speed = 50000;
1849 case NVM_CFG1_PORT_DRV_LINK_SPEED_100G:
1850 link->speed.forced_speed = 100000;
1853 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
1856 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1857 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1858 link->pause.autoneg = !!(link_temp &
1859 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1860 link->pause.forced_rx = !!(link_temp &
1861 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1862 link->pause.forced_tx = !!(link_temp &
1863 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1864 link->loopback_mode = 0;
1866 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1867 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x,"
1868 " AN: 0x%02x, PAUSE AN: 0x%02x\n",
1869 link->speed.forced_speed, link->speed.advertised_speeds,
1870 link->speed.autoneg, link->pause.autoneg);
1872 /* Read Multi-function information from shmem */
1873 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1874 OFFSETOF(struct nvm_cfg1, glob) +
1875 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
1877 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
1879 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1880 NVM_CFG1_GLOB_MF_MODE_OFFSET;
1883 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1884 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
1886 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1887 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
1889 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1890 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
1893 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1894 p_hwfn->p_dev->mf_mode);
1896 /* Read Multi-function information from shmem */
1897 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1898 OFFSETOF(struct nvm_cfg1, glob) +
1899 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
1901 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
1902 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1903 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
1904 &p_hwfn->hw_info.device_capabilities);
1906 return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1909 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
1910 struct ecore_ptt *p_ptt)
1915 num_funcs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_PFS_K2
1918 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1919 * in the other bits are selected.
1920 * Bits 1-15 are for functions 1-15, respectively, and their value is
1921 * '0' only for enabled functions (function 0 always exists and
1923 * In case of CMT, only the "even" functions are enabled, and thus the
1924 * number of functions for both hwfns is learnt from the same bits.
1927 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1929 if (ECORE_PATH_ID(p_hwfn) && p_hwfn->p_dev->num_hwfns == 1) {
1937 tmp = (tmp ^ 0xffffffff) & mask;
1945 p_hwfn->num_funcs_on_engine = num_funcs;
1948 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1949 DP_NOTICE(p_hwfn, false,
1950 "FPGA: Limit number of PFs to 4 [would affect"
1951 " resource allocation, needed for IOV]\n");
1952 p_hwfn->num_funcs_on_engine = 4;
1956 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "num_funcs_on_engine = %d\n",
1957 p_hwfn->num_funcs_on_engine);
1960 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
1961 struct ecore_ptt *p_ptt)
1966 /* Read the port mode */
1967 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1969 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
1970 (p_hwfn->p_dev->num_hwfns > 1))
1971 /* In CMT on emulation, assume 1 port */
1975 port_mode = ecore_rd(p_hwfn, p_ptt,
1976 CNIG_REG_NW_PORT_MODE_BB_B0);
1978 if (port_mode < 3) {
1979 p_hwfn->p_dev->num_ports_in_engines = 1;
1980 } else if (port_mode <= 5) {
1981 p_hwfn->p_dev->num_ports_in_engines = 2;
1983 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
1984 p_hwfn->p_dev->num_ports_in_engines);
1986 /* Default num_ports_in_engines to something */
1987 p_hwfn->p_dev->num_ports_in_engines = 1;
1991 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
1992 struct ecore_ptt *p_ptt)
1997 p_hwfn->p_dev->num_ports_in_engines = 0;
1999 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2000 port = ecore_rd(p_hwfn, p_ptt,
2001 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2003 p_hwfn->p_dev->num_ports_in_engines++;
2007 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2008 struct ecore_ptt *p_ptt)
2010 if (ECORE_IS_BB(p_hwfn->p_dev))
2011 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2013 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2016 static enum _ecore_status_t
2017 ecore_get_hw_info(struct ecore_hwfn *p_hwfn,
2018 struct ecore_ptt *p_ptt,
2019 enum ecore_pci_personality personality)
2021 enum _ecore_status_t rc;
2023 /* TODO In get_hw_info, amoungst others:
2024 * Get MCP FW revision and determine according to it the supported
2025 * featrues (e.g. DCB)
2027 * ecore_get_pcie_width_speed, WOL capability.
2028 * Number of global CQ-s (for storage
2030 ecore_hw_info_port_num(p_hwfn, p_ptt);
2033 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2035 ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2037 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2042 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2044 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2045 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2048 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2050 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2051 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2055 if (ecore_mcp_is_init(p_hwfn)) {
2056 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2057 p_hwfn->hw_info.ovlan =
2058 p_hwfn->mcp_info->func_info.ovlan;
2060 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2063 if (personality != ECORE_PCI_DEFAULT)
2064 p_hwfn->hw_info.personality = personality;
2065 else if (ecore_mcp_is_init(p_hwfn))
2066 p_hwfn->hw_info.personality =
2067 p_hwfn->mcp_info->func_info.protocol;
2070 /* To overcome ILT lack for emulation, until at least until we'll have
2071 * a definite answer from system about it, allow only PF0 to be RoCE.
2073 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
2074 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2077 ecore_get_num_funcs(p_hwfn, p_ptt);
2079 /* Feat num is dependent on personality and on the number of functions
2080 * on the engine. Therefore it should be come after personality
2081 * initialization and after getting the number of functions.
2083 return ecore_hw_get_resc(p_hwfn);
2086 /* @TMP - this should move to a proper .h */
2087 #define CHIP_NUM_AH 0x8070
2089 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2091 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2094 /* Read Vendor Id / Device Id */
2095 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2097 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2100 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2101 MISCS_REG_CHIP_NUM);
2102 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2103 MISCS_REG_CHIP_REV);
2105 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2107 /* Determine type */
2108 if (p_dev->device_id == CHIP_NUM_AH)
2109 p_dev->type = ECORE_DEV_TYPE_AH;
2111 p_dev->type = ECORE_DEV_TYPE_BB;
2113 /* Learn number of HW-functions */
2114 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2115 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2117 if (tmp & (1 << p_hwfn->rel_pf_id)) {
2118 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2119 p_dev->num_hwfns = 2;
2121 p_dev->num_hwfns = 1;
2125 if (CHIP_REV_IS_EMUL(p_dev)) {
2126 /* For some reason we have problems with this register
2127 * in B0 emulation; Simply assume no CMT
2129 DP_NOTICE(p_dev->hwfns, false,
2130 "device on emul - assume no CMT\n");
2131 p_dev->num_hwfns = 1;
2135 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2136 MISCS_REG_CHIP_TEST_REG) >> 4;
2137 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2138 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2139 MISCS_REG_CHIP_METAL);
2140 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2141 DP_INFO(p_dev->hwfns,
2142 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x"
2144 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2145 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2146 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2149 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2150 DP_NOTICE(p_dev->hwfns, false,
2151 "The chip type/rev (BB A0) is not supported!\n");
2152 return ECORE_ABORTED;
2155 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2156 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2157 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2159 if (CHIP_REV_IS_EMUL(p_dev)) {
2160 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2161 MISCS_REG_ECO_RESERVED);
2162 if (tmp & (1 << 29)) {
2163 DP_NOTICE(p_hwfn, false,
2164 "Emulation: Running on a FULL build\n");
2165 p_dev->b_is_emul_full = true;
2167 DP_NOTICE(p_hwfn, false,
2168 "Emulation: Running on a REDUCED build\n");
2173 return ECORE_SUCCESS;
2176 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2180 for_each_hwfn(p_dev, j) {
2181 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2183 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2184 "Mark hw/fw uninitialized\n");
2186 p_hwfn->hw_init_done = false;
2187 p_hwfn->first_on_engine = false;
2191 static enum _ecore_status_t
2192 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
2193 void OSAL_IOMEM *p_regview,
2194 void OSAL_IOMEM *p_doorbells,
2195 enum ecore_pci_personality personality)
2197 enum _ecore_status_t rc = ECORE_SUCCESS;
2199 /* Split PCI bars evenly between hwfns */
2200 p_hwfn->regview = p_regview;
2201 p_hwfn->doorbells = p_doorbells;
2203 /* Validate that chip access is feasible */
2204 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2206 "Reading the ME register returns all Fs;"
2207 " Preventing further chip access\n");
2211 get_function_id(p_hwfn);
2213 /* Allocate PTT pool */
2214 rc = ecore_ptt_pool_alloc(p_hwfn);
2216 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2220 /* Allocate the main PTT */
2221 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2223 /* First hwfn learns basic information, e.g., number of hwfns */
2224 if (!p_hwfn->my_id) {
2225 rc = ecore_get_dev_info(p_hwfn->p_dev);
2226 if (rc != ECORE_SUCCESS)
2230 ecore_hw_hwfn_prepare(p_hwfn);
2232 /* Initialize MCP structure */
2233 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2235 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
2239 /* Read the device configuration information from the HW and SHMEM */
2240 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2242 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
2246 /* Allocate the init RT array and initialize the init-ops engine */
2247 rc = ecore_init_alloc(p_hwfn);
2249 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
2253 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2254 DP_NOTICE(p_hwfn, false,
2255 "FPGA: workaround; Prevent DMAE parities\n");
2256 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
2258 DP_NOTICE(p_hwfn, false,
2259 "FPGA: workaround: Set VF bar0 size\n");
2260 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2261 PGLUE_B_REG_VF_BAR0_SIZE, 4);
2267 ecore_mcp_free(p_hwfn);
2269 ecore_hw_hwfn_free(p_hwfn);
2274 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, int personality)
2276 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2277 enum _ecore_status_t rc;
2279 /* Store the precompiled init data ptrs */
2280 ecore_init_iro_array(p_dev);
2282 /* Initialize the first hwfn - will learn number of hwfns */
2283 rc = ecore_hw_prepare_single(p_hwfn,
2285 p_dev->doorbells, personality);
2286 if (rc != ECORE_SUCCESS)
2289 personality = p_hwfn->hw_info.personality;
2291 /* initialalize 2nd hwfn if necessary */
2292 if (p_dev->num_hwfns > 1) {
2293 void OSAL_IOMEM *p_regview, *p_doorbell;
2294 u8 OSAL_IOMEM *addr;
2296 /* adjust bar offset for second engine */
2297 addr = (u8 OSAL_IOMEM *)p_dev->regview +
2298 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
2299 p_regview = (void OSAL_IOMEM *)addr;
2301 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
2302 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
2303 p_doorbell = (void OSAL_IOMEM *)addr;
2305 /* prepare second hw function */
2306 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
2307 p_doorbell, personality);
2309 /* in case of error, need to free the previously
2310 * initialiazed hwfn 0
2312 if (rc != ECORE_SUCCESS) {
2313 ecore_init_free(p_hwfn);
2314 ecore_mcp_free(p_hwfn);
2315 ecore_hw_hwfn_free(p_hwfn);
2320 return ECORE_SUCCESS;
2323 void ecore_hw_remove(struct ecore_dev *p_dev)
2327 for_each_hwfn(p_dev, i) {
2328 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2330 ecore_init_free(p_hwfn);
2331 ecore_hw_hwfn_free(p_hwfn);
2332 ecore_mcp_free(p_hwfn);
2334 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
2338 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
2339 struct ecore_chain *p_chain)
2341 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
2342 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2343 struct ecore_chain_next *p_next;
2349 size = p_chain->elem_size * p_chain->usable_per_page;
2351 for (i = 0; i < p_chain->page_cnt; i++) {
2355 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
2356 p_virt_next = p_next->next_virt;
2357 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2359 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
2360 ECORE_CHAIN_PAGE_SIZE);
2362 p_virt = p_virt_next;
2363 p_phys = p_phys_next;
2367 static void ecore_chain_free_single(struct ecore_dev *p_dev,
2368 struct ecore_chain *p_chain)
2370 if (!p_chain->p_virt_addr)
2373 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
2374 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
2377 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
2378 struct ecore_chain *p_chain)
2380 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2381 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
2382 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
2384 if (!pp_virt_addr_tbl)
2387 if (!p_chain->pbl.p_virt_table)
2390 for (i = 0; i < page_cnt; i++) {
2391 if (!pp_virt_addr_tbl[i])
2394 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
2395 *(dma_addr_t *)p_pbl_virt,
2396 ECORE_CHAIN_PAGE_SIZE);
2398 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
2401 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
2402 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
2403 p_chain->pbl.p_phys_table, pbl_size);
2405 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
2408 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2410 switch (p_chain->mode) {
2411 case ECORE_CHAIN_MODE_NEXT_PTR:
2412 ecore_chain_free_next_ptr(p_dev, p_chain);
2414 case ECORE_CHAIN_MODE_SINGLE:
2415 ecore_chain_free_single(p_dev, p_chain);
2417 case ECORE_CHAIN_MODE_PBL:
2418 ecore_chain_free_pbl(p_dev, p_chain);
2423 static enum _ecore_status_t
2424 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
2425 enum ecore_chain_cnt_type cnt_type,
2426 osal_size_t elem_size, u32 page_cnt)
2428 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
2430 /* The actual chain size can be larger than the maximal possible value
2431 * after rounding up the requested elements number to pages, and after
2432 * taking into acount the unusuable elements (next-ptr elements).
2433 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
2434 * size/capacity fields are of a u32 type.
2436 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
2437 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
2438 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
2439 chain_size > ECORE_U32_MAX)) {
2440 DP_NOTICE(p_dev, true,
2441 "The actual chain size (0x%lx) is larger than"
2442 " the maximal possible value\n",
2443 (unsigned long)chain_size);
2447 return ECORE_SUCCESS;
2450 static enum _ecore_status_t
2451 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2453 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
2454 dma_addr_t p_phys = 0;
2457 for (i = 0; i < p_chain->page_cnt; i++) {
2458 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
2459 ECORE_CHAIN_PAGE_SIZE);
2461 DP_NOTICE(p_dev, true,
2462 "Failed to allocate chain memory\n");
2467 ecore_chain_init_mem(p_chain, p_virt, p_phys);
2468 ecore_chain_reset(p_chain);
2470 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2474 p_virt_prev = p_virt;
2476 /* Last page's next element should point to the beginning of the
2479 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2480 p_chain->p_virt_addr,
2481 p_chain->p_phys_addr);
2483 return ECORE_SUCCESS;
2486 static enum _ecore_status_t
2487 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2489 void *p_virt = OSAL_NULL;
2490 dma_addr_t p_phys = 0;
2492 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
2494 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
2498 ecore_chain_init_mem(p_chain, p_virt, p_phys);
2499 ecore_chain_reset(p_chain);
2501 return ECORE_SUCCESS;
2504 static enum _ecore_status_t ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
2505 struct ecore_chain *p_chain)
2507 void *p_virt = OSAL_NULL;
2508 u8 *p_pbl_virt = OSAL_NULL;
2509 void **pp_virt_addr_tbl = OSAL_NULL;
2510 dma_addr_t p_phys = 0, p_pbl_phys = 0;
2511 u32 page_cnt = p_chain->page_cnt, size, i;
2513 size = page_cnt * sizeof(*pp_virt_addr_tbl);
2514 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
2515 if (!pp_virt_addr_tbl) {
2516 DP_NOTICE(p_dev, true,
2517 "Failed to allocate memory for the chain"
2518 " virtual addresses table\n");
2521 OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
2523 /* The allocation of the PBL table is done with its full size, since it
2524 * is expected to be successive.
2526 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
2527 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
2529 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
2533 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2536 for (i = 0; i < page_cnt; i++) {
2537 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
2538 ECORE_CHAIN_PAGE_SIZE);
2540 DP_NOTICE(p_dev, true,
2541 "Failed to allocate chain memory\n");
2546 ecore_chain_init_mem(p_chain, p_virt, p_phys);
2547 ecore_chain_reset(p_chain);
2550 /* Fill the PBL table with the physical address of the page */
2551 *(dma_addr_t *)p_pbl_virt = p_phys;
2552 /* Keep the virtual address of the page */
2553 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2555 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
2558 return ECORE_SUCCESS;
2561 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
2562 enum ecore_chain_use_mode intended_use,
2563 enum ecore_chain_mode mode,
2564 enum ecore_chain_cnt_type cnt_type,
2565 u32 num_elems, osal_size_t elem_size,
2566 struct ecore_chain *p_chain)
2569 enum _ecore_status_t rc = ECORE_SUCCESS;
2571 if (mode == ECORE_CHAIN_MODE_SINGLE)
2574 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2576 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
2579 DP_NOTICE(p_dev, true,
2580 "Cannot allocate a chain with the given arguments:\n"
2581 " [use_mode %d, mode %d, cnt_type %d, num_elems %d,"
2582 " elem_size %zu]\n",
2583 intended_use, mode, cnt_type, num_elems, elem_size);
2587 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
2591 case ECORE_CHAIN_MODE_NEXT_PTR:
2592 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
2594 case ECORE_CHAIN_MODE_SINGLE:
2595 rc = ecore_chain_alloc_single(p_dev, p_chain);
2597 case ECORE_CHAIN_MODE_PBL:
2598 rc = ecore_chain_alloc_pbl(p_dev, p_chain);
2604 return ECORE_SUCCESS;
2607 ecore_chain_free(p_dev, p_chain);
2611 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
2612 u16 src_id, u16 *dst_id)
2614 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
2617 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
2618 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
2619 DP_NOTICE(p_hwfn, true,
2620 "l2_queue id [%d] is not valid, available"
2621 " indices [%d - %d]\n",
2627 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
2629 return ECORE_SUCCESS;
2632 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
2633 u8 src_id, u8 *dst_id)
2635 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
2638 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
2639 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
2640 DP_NOTICE(p_hwfn, true,
2641 "vport id [%d] is not valid, available"
2642 " indices [%d - %d]\n",
2648 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
2650 return ECORE_SUCCESS;
2653 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
2654 u8 src_id, u8 *dst_id)
2656 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
2659 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
2660 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
2661 DP_NOTICE(p_hwfn, true,
2662 "rss_eng id [%d] is not valid,avail idx [%d - %d]\n",
2668 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
2670 return ECORE_SUCCESS;
2673 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
2674 struct ecore_ptt *p_ptt,
2680 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2681 return ECORE_SUCCESS;
2683 high = p_filter[1] | (p_filter[0] << 8);
2684 low = p_filter[5] | (p_filter[4] << 8) |
2685 (p_filter[3] << 16) | (p_filter[2] << 24);
2687 /* Find a free entry and utilize it */
2688 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2689 en = ecore_rd(p_hwfn, p_ptt,
2690 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2693 ecore_wr(p_hwfn, p_ptt,
2694 NIG_REG_LLH_FUNC_FILTER_VALUE +
2695 2 * i * sizeof(u32), low);
2696 ecore_wr(p_hwfn, p_ptt,
2697 NIG_REG_LLH_FUNC_FILTER_VALUE +
2698 (2 * i + 1) * sizeof(u32), high);
2699 ecore_wr(p_hwfn, p_ptt,
2700 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2701 ecore_wr(p_hwfn, p_ptt,
2702 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2703 i * sizeof(u32), 0);
2704 ecore_wr(p_hwfn, p_ptt,
2705 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2708 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2709 DP_NOTICE(p_hwfn, false,
2710 "Failed to find an empty LLH filter to utilize\n");
2714 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2715 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
2716 p_filter[0], p_filter[1], p_filter[2],
2717 p_filter[3], p_filter[4], p_filter[5], i);
2719 return ECORE_SUCCESS;
2722 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
2723 struct ecore_ptt *p_ptt, u8 *p_filter)
2728 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2731 high = p_filter[1] | (p_filter[0] << 8);
2732 low = p_filter[5] | (p_filter[4] << 8) |
2733 (p_filter[3] << 16) | (p_filter[2] << 24);
2735 /* Find the entry and clean it */
2736 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2737 if (ecore_rd(p_hwfn, p_ptt,
2738 NIG_REG_LLH_FUNC_FILTER_VALUE +
2739 2 * i * sizeof(u32)) != low)
2741 if (ecore_rd(p_hwfn, p_ptt,
2742 NIG_REG_LLH_FUNC_FILTER_VALUE +
2743 (2 * i + 1) * sizeof(u32)) != high)
2746 ecore_wr(p_hwfn, p_ptt,
2747 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2748 ecore_wr(p_hwfn, p_ptt,
2749 NIG_REG_LLH_FUNC_FILTER_VALUE +
2750 2 * i * sizeof(u32), 0);
2751 ecore_wr(p_hwfn, p_ptt,
2752 NIG_REG_LLH_FUNC_FILTER_VALUE +
2753 (2 * i + 1) * sizeof(u32), 0);
2756 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2757 DP_NOTICE(p_hwfn, false,
2758 "Tried to remove a non-configured filter\n");
2761 enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn,
2762 struct ecore_ptt *p_ptt,
2768 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2769 return ECORE_SUCCESS;
2774 /* Find a free entry and utilize it */
2775 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2776 en = ecore_rd(p_hwfn, p_ptt,
2777 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2780 ecore_wr(p_hwfn, p_ptt,
2781 NIG_REG_LLH_FUNC_FILTER_VALUE +
2782 2 * i * sizeof(u32), low);
2783 ecore_wr(p_hwfn, p_ptt,
2784 NIG_REG_LLH_FUNC_FILTER_VALUE +
2785 (2 * i + 1) * sizeof(u32), high);
2786 ecore_wr(p_hwfn, p_ptt,
2787 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
2788 ecore_wr(p_hwfn, p_ptt,
2789 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2790 i * sizeof(u32), 1);
2791 ecore_wr(p_hwfn, p_ptt,
2792 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2795 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2796 DP_NOTICE(p_hwfn, false,
2797 "Failed to find an empty LLH filter to utilize\n");
2801 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2802 "ETH type: %x is added at %d\n", filter, i);
2804 return ECORE_SUCCESS;
2807 void ecore_llh_remove_ethertype_filter(struct ecore_hwfn *p_hwfn,
2808 struct ecore_ptt *p_ptt, u16 filter)
2813 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2819 /* Find the entry and clean it */
2820 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2821 if (ecore_rd(p_hwfn, p_ptt,
2822 NIG_REG_LLH_FUNC_FILTER_VALUE +
2823 2 * i * sizeof(u32)) != low)
2825 if (ecore_rd(p_hwfn, p_ptt,
2826 NIG_REG_LLH_FUNC_FILTER_VALUE +
2827 (2 * i + 1) * sizeof(u32)) != high)
2830 ecore_wr(p_hwfn, p_ptt,
2831 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2832 ecore_wr(p_hwfn, p_ptt,
2833 NIG_REG_LLH_FUNC_FILTER_VALUE +
2834 2 * i * sizeof(u32), 0);
2835 ecore_wr(p_hwfn, p_ptt,
2836 NIG_REG_LLH_FUNC_FILTER_VALUE +
2837 (2 * i + 1) * sizeof(u32), 0);
2840 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2841 DP_NOTICE(p_hwfn, false,
2842 "Tried to remove a non-configured filter\n");
2845 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
2846 struct ecore_ptt *p_ptt)
2850 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2853 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2854 ecore_wr(p_hwfn, p_ptt,
2855 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2856 ecore_wr(p_hwfn, p_ptt,
2857 NIG_REG_LLH_FUNC_FILTER_VALUE +
2858 2 * i * sizeof(u32), 0);
2859 ecore_wr(p_hwfn, p_ptt,
2860 NIG_REG_LLH_FUNC_FILTER_VALUE +
2861 (2 * i + 1) * sizeof(u32), 0);
2865 enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn,
2866 struct ecore_ptt *p_ptt)
2869 BRB_REG_HEADER_SIZE,
2870 BTB_REG_HEADER_SIZE,
2871 CAU_REG_LONG_TIMEOUT_THRESHOLD,
2872 CCFC_REG_ACTIVITY_COUNTER,
2873 CDU_REG_CID_ADDR_PARAMS,
2874 DBG_REG_CLIENT_ENABLE,
2878 IGU_REG_BLOCK_CONFIGURATION,
2880 MCP2_REG_DBG_DWORD_ENABLE,
2882 MISCS_REG_CLK_100G_MODE,
2883 MSDM_REG_ENABLE_IN1,
2888 PTU_REG_ATC_INIT_ARRAY,
2890 PGLUE_B_REG_ADMIN_PER_PF_REGION,
2891 PRM_REG_DISABLE_PRM,
2893 PSDM_REG_ENABLE_IN1,
2895 PSWRQ_REG_DBG_SELECT,
2896 PSWRQ2_REG_CDUT_P_SIZE,
2897 PSWHST_REG_DISCARD_INTERNAL_WRITES,
2898 PSWHST2_REG_DBGSYN_ALMOST_FULL_THR,
2899 PSWRD_REG_DBG_SELECT,
2901 PSWWR_REG_USDM_FULL_TH,
2902 PSWWR2_REG_CDU_FULL_TH2,
2904 RSS_REG_RSS_INIT_EN,
2905 RDIF_REG_STOP_ON_ERROR,
2907 TCFC_REG_ACTIVITY_COUNTER,
2909 TM_REG_PXP_READ_DATA_FIFO_INIT,
2910 TSDM_REG_ENABLE_IN1,
2912 TDIF_REG_STOP_ON_ERROR,
2914 UMAC_REG_IPG_HD_BKP_CNTL_BB_B0,
2915 USDM_REG_ENABLE_IN1,
2918 XSDM_REG_ENABLE_IN1,
2921 YSDM_REG_ENABLE_IN1,
2923 XYLD_REG_SCBD_STRICT_PRIO,
2924 TMLD_REG_SCBD_STRICT_PRIO,
2925 MULD_REG_SCBD_STRICT_PRIO,
2926 YULD_REG_SCBD_STRICT_PRIO,
2928 u32 test_val[] = { 0x0, 0x1 };
2929 u32 val, save_val, i, j;
2931 for (i = 0; i < OSAL_ARRAY_SIZE(test_val); i++) {
2932 for (j = 0; j < OSAL_ARRAY_SIZE(reg_tbl); j++) {
2933 save_val = ecore_rd(p_hwfn, p_ptt, reg_tbl[j]);
2934 ecore_wr(p_hwfn, p_ptt, reg_tbl[j], test_val[i]);
2935 val = ecore_rd(p_hwfn, p_ptt, reg_tbl[j]);
2936 /* Restore the original register's value */
2937 ecore_wr(p_hwfn, p_ptt, reg_tbl[j], save_val);
2938 if (val != test_val[i]) {
2939 DP_INFO(p_hwfn->p_dev,
2940 "offset 0x%x: val 0x%x != 0x%x\n",
2941 reg_tbl[j], val, test_val[i]);
2946 return ECORE_SUCCESS;
2949 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
2950 struct ecore_ptt *p_ptt,
2951 u32 hw_addr, void *p_qzone,
2952 osal_size_t qzone_size,
2955 struct coalescing_timeset *p_coalesce_timeset;
2957 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
2958 DP_NOTICE(p_hwfn, true,
2959 "Coalescing configuration not enabled\n");
2963 OSAL_MEMSET(p_qzone, 0, qzone_size);
2964 p_coalesce_timeset = p_qzone;
2965 p_coalesce_timeset->timeset = timeset;
2966 p_coalesce_timeset->valid = 1;
2967 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_qzone, qzone_size);
2969 return ECORE_SUCCESS;
2972 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
2973 struct ecore_ptt *p_ptt,
2974 u8 coalesce, u8 qid)
2976 struct ustorm_eth_queue_zone qzone;
2980 enum _ecore_status_t rc;
2982 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2983 if (rc != ECORE_SUCCESS)
2986 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2987 /* Translate the coalescing time into a timeset, according to:
2988 * Timeout[Rx] = TimeSet[Rx] << (TimerRes[Rx] + 1)
2990 timeset = coalesce >> (ECORE_CAU_DEF_RX_TIMER_RES + 1);
2992 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &qzone,
2993 sizeof(struct ustorm_eth_queue_zone), timeset);
2994 if (rc != ECORE_SUCCESS)
2997 p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3002 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3003 struct ecore_ptt *p_ptt,
3004 u8 coalesce, u8 qid)
3006 struct ystorm_eth_queue_zone qzone;
3010 enum _ecore_status_t rc;
3012 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3013 if (rc != ECORE_SUCCESS)
3016 address = BAR0_MAP_REG_YSDM_RAM + YSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3017 /* Translate the coalescing time into a timeset, according to:
3018 * Timeout[Tx] = TimeSet[Tx] << (TimerRes[Tx] + 1)
3020 timeset = coalesce >> (ECORE_CAU_DEF_TX_TIMER_RES + 1);
3022 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &qzone,
3023 sizeof(struct ystorm_eth_queue_zone), timeset);
3024 if (rc != ECORE_SUCCESS)
3027 p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3032 /* Calculate final WFQ values for all vports and configure it.
3033 * After this configuration each vport must have
3034 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3036 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3037 struct ecore_ptt *p_ptt,
3040 struct init_qm_vport_params *vport_params;
3043 vport_params = p_hwfn->qm_info.qm_vport_params;
3044 num_vports = p_hwfn->qm_info.num_vports;
3046 for (i = 0; i < num_vports; i++) {
3047 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3049 vport_params[i].vport_wfq =
3050 (wfq_speed * ECORE_WFQ_UNIT) / min_pf_rate;
3051 ecore_init_vport_wfq(p_hwfn, p_ptt,
3052 vport_params[i].first_tx_pq_id,
3053 vport_params[i].vport_wfq);
3058 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3063 num_vports = p_hwfn->qm_info.num_vports;
3064 min_speed = min_pf_rate / num_vports;
3066 for (i = 0; i < num_vports; i++) {
3067 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3068 p_hwfn->qm_info.wfq_data[i].default_min_speed = min_speed;
3072 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3073 struct ecore_ptt *p_ptt,
3076 struct init_qm_vport_params *vport_params;
3079 vport_params = p_hwfn->qm_info.qm_vport_params;
3080 num_vports = p_hwfn->qm_info.num_vports;
3082 for (i = 0; i < num_vports; i++) {
3083 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3084 ecore_init_vport_wfq(p_hwfn, p_ptt,
3085 vport_params[i].first_tx_pq_id,
3086 vport_params[i].vport_wfq);
3090 /* validate wfq for a given vport and required min rate */
3091 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3092 u16 vport_id, u32 req_rate,
3095 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3096 int non_requested_count = 0, req_count = 0, i, num_vports;
3098 num_vports = p_hwfn->qm_info.num_vports;
3100 /* Check pre-set data for some of the vports */
3101 for (i = 0; i < num_vports; i++) {
3104 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3106 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3107 total_req_min_rate += tmp_speed;
3111 /* Include current vport data as well */
3113 total_req_min_rate += req_rate;
3114 non_requested_count = p_hwfn->qm_info.num_vports - req_count;
3116 /* validate possible error cases */
3117 if (req_rate > min_pf_rate) {
3118 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3119 "Vport [%d] - Requested rate[%d Mbps] is greater"
3120 " than configured PF min rate[%d Mbps]\n",
3121 vport_id, req_rate, min_pf_rate);
3125 if (req_rate * ECORE_WFQ_UNIT / min_pf_rate < 1) {
3126 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3127 "Vport [%d] - Requested rate[%d Mbps] is less than"
3128 " one percent of configured PF min rate[%d Mbps]\n",
3129 vport_id, req_rate, min_pf_rate);
3133 /* TBD - for number of vports greater than 100 */
3134 if (ECORE_WFQ_UNIT / p_hwfn->qm_info.num_vports < 1) {
3135 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3136 "Number of vports are greater than 100\n");
3140 if (total_req_min_rate > min_pf_rate) {
3141 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3142 "Total requested min rate for all vports[%d Mbps]"
3143 "is greater than configured PF min rate[%d Mbps]\n",
3144 total_req_min_rate, min_pf_rate);
3148 /* Data left for non requested vports */
3149 total_left_rate = min_pf_rate - total_req_min_rate;
3150 left_rate_per_vp = total_left_rate / non_requested_count;
3152 /* validate if non requested get < 1% of min bw */
3153 if (left_rate_per_vp * ECORE_WFQ_UNIT / min_pf_rate < 1)
3156 /* now req_rate for given vport passes all scenarios.
3157 * assign final wfq rates to all vports.
3159 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3160 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3162 for (i = 0; i < num_vports; i++) {
3163 if (p_hwfn->qm_info.wfq_data[i].configured)
3166 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3169 return ECORE_SUCCESS;
3172 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
3173 struct ecore_ptt *p_ptt,
3174 u16 vp_id, u32 rate)
3176 struct ecore_mcp_link_state *p_link;
3177 int rc = ECORE_SUCCESS;
3179 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
3181 if (!p_link->min_pf_rate) {
3182 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3183 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3187 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3189 if (rc == ECORE_SUCCESS)
3190 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3191 p_link->min_pf_rate);
3193 DP_NOTICE(p_hwfn, false,
3194 "Validation failed while configuring min rate\n");
3199 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
3200 struct ecore_ptt *p_ptt,
3203 int rc = ECORE_SUCCESS;
3204 bool use_wfq = false;
3207 num_vports = p_hwfn->qm_info.num_vports;
3209 /* Validate all pre configured vports for wfq */
3210 for (i = 0; i < num_vports; i++) {
3211 if (p_hwfn->qm_info.wfq_data[i].configured) {
3212 u32 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3215 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3216 if (rc == ECORE_INVAL) {
3217 DP_NOTICE(p_hwfn, false,
3218 "Validation failed while"
3219 " configuring min rate\n");
3225 if (rc == ECORE_SUCCESS && use_wfq)
3226 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3228 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3233 /* Main API for ecore clients to configure vport min rate.
3234 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3235 * rate - Speed in Mbps needs to be assigned to a given vport.
3237 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
3239 int i, rc = ECORE_INVAL;
3241 /* TBD - for multiple hardware functions - that is 100 gig */
3242 if (p_dev->num_hwfns > 1) {
3243 DP_NOTICE(p_dev, false,
3244 "WFQ configuration is not supported for this dev\n");
3248 for_each_hwfn(p_dev, i) {
3249 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3250 struct ecore_ptt *p_ptt;
3252 p_ptt = ecore_ptt_acquire(p_hwfn);
3254 return ECORE_TIMEOUT;
3256 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3258 if (rc != ECORE_SUCCESS) {
3259 ecore_ptt_release(p_hwfn, p_ptt);
3263 ecore_ptt_release(p_hwfn, p_ptt);
3269 /* API to configure WFQ from mcp link change */
3270 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
3275 /* TBD - for multiple hardware functions - that is 100 gig */
3276 if (p_dev->num_hwfns > 1) {
3277 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
3278 "WFQ configuration is not supported for this dev\n");
3282 for_each_hwfn(p_dev, i) {
3283 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3285 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
3291 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
3292 struct ecore_ptt *p_ptt,
3293 struct ecore_mcp_link_state *p_link,
3296 int rc = ECORE_SUCCESS;
3298 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3300 if (!p_link->line_speed)
3303 p_link->speed = (p_link->line_speed * max_bw) / 100;
3305 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, p_link->speed);
3307 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3308 "Configured MAX bandwidth to be %08x Mb/sec\n",
3314 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3315 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
3317 int i, rc = ECORE_INVAL;
3319 if (max_bw < 1 || max_bw > 100) {
3320 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
3324 for_each_hwfn(p_dev, i) {
3325 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3326 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
3327 struct ecore_mcp_link_state *p_link;
3328 struct ecore_ptt *p_ptt;
3330 p_link = &p_lead->mcp_info->link_output;
3332 p_ptt = ecore_ptt_acquire(p_hwfn);
3334 return ECORE_TIMEOUT;
3336 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3338 if (rc != ECORE_SUCCESS) {
3339 ecore_ptt_release(p_hwfn, p_ptt);
3343 ecore_ptt_release(p_hwfn, p_ptt);
3349 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
3350 struct ecore_ptt *p_ptt,
3351 struct ecore_mcp_link_state *p_link,
3354 int rc = ECORE_SUCCESS;
3356 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3358 if (!p_link->line_speed)
3361 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3363 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3365 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3366 "Configured MIN bandwidth to be %d Mb/sec\n",
3367 p_link->min_pf_rate);
3372 /* Main API to configure PF min bandwidth where bw range is [1-100] */
3373 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
3375 int i, rc = ECORE_INVAL;
3377 if (min_bw < 1 || min_bw > 100) {
3378 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
3382 for_each_hwfn(p_dev, i) {
3383 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3384 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
3385 struct ecore_mcp_link_state *p_link;
3386 struct ecore_ptt *p_ptt;
3388 p_link = &p_lead->mcp_info->link_output;
3390 p_ptt = ecore_ptt_acquire(p_hwfn);
3392 return ECORE_TIMEOUT;
3394 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
3396 if (rc != ECORE_SUCCESS) {
3397 ecore_ptt_release(p_hwfn, p_ptt);
3401 if (p_link->min_pf_rate) {
3402 u32 min_rate = p_link->min_pf_rate;
3404 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
3409 ecore_ptt_release(p_hwfn, p_ptt);
3415 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
3417 struct ecore_mcp_link_state *p_link;
3419 p_link = &p_hwfn->mcp_info->link_output;
3421 if (p_link->min_pf_rate)
3422 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
3423 p_link->min_pf_rate);
3425 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
3426 sizeof(*p_hwfn->qm_info.wfq_data) *
3427 p_hwfn->qm_info.num_vports);
3430 int ecore_device_num_engines(struct ecore_dev *p_dev)
3432 return ECORE_IS_BB(p_dev) ? 2 : 1;
3435 int ecore_device_num_ports(struct ecore_dev *p_dev)
3437 /* in CMT always only one port */
3438 if (p_dev->num_hwfns > 1)
3441 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);