drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /* Configurable */
  45 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  46                                          * load the driver. The number was
  47                                          * arbitrarily set.
  48                                          */
  49
  50 /* Derived */
  51 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  52
  53 enum BAR_ID {
  54         BAR_ID_0,               /* used for GRC */
  55         BAR_ID_1                /* Used for doorbells */
  56 };
  57
  58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  59 {
  60         u32 bar_reg = (bar_id == BAR_ID_0 ?
  61                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  62         u32 val;
  63
  64         if (IS_VF(p_hwfn->p_dev)) {
  65                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  66                  * read from actual register, but we're currently not using
  67                  * it for actual doorbelling.
  68                  */
  69                 return 1 << 17;
  70         }
  71
  72         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  73         if (val)
  74                 return 1 << (val + 15);
  75
  76         /* The above registers were updated in the past only in CMT mode. Since
  77          * they were found to be useful MFW started updating them from 8.7.7.0.
  78          * In older MFW versions they are set to 0 which means disabled.
  79          */
  80         if (p_hwfn->p_dev->num_hwfns > 1) {
  81                 DP_NOTICE(p_hwfn, false,
  82                           "BAR size not configured. Assuming BAR size of 256kB"
  83                           " for GRC and 512kB for DB\n");
  84                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  85         } else {
  86                 DP_NOTICE(p_hwfn, false,
  87                           "BAR size not configured. Assuming BAR size of 512kB"
  88                           " for GRC and 512kB for DB\n");
  89                 val = 512 * 1024;
  90         }
  91
  92         return val;
  93 }
  94
  95 void ecore_init_dp(struct ecore_dev *p_dev,
  96                    u32 dp_module, u8 dp_level, void *dp_ctx)
  97 {
  98         u32 i;
  99
 100         p_dev->dp_level = dp_level;
 101         p_dev->dp_module = dp_module;
 102         p_dev->dp_ctx = dp_ctx;
 103         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 104                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 105
 106                 p_hwfn->dp_level = dp_level;
 107                 p_hwfn->dp_module = dp_module;
 108                 p_hwfn->dp_ctx = dp_ctx;
 109         }
 110 }
 111
 112 void ecore_init_struct(struct ecore_dev *p_dev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 118
 119                 p_hwfn->p_dev = p_dev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 124                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 125         }
 126
 127         /* hwfn 0 is always active */
 128         p_dev->hwfns[0].b_active = true;
 129
 130         /* set the default cache alignment to 128 (may be overridden later) */
 131         p_dev->cache_shift = 7;
 132 }
 133
 134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 135 {
 136         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 137
 138         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 142 }
 143
 144 void ecore_resc_free(struct ecore_dev *p_dev)
 145 {
 146         int i;
 147
 148         if (IS_VF(p_dev))
 149                 return;
 150
 151         OSAL_FREE(p_dev, p_dev->fw_data);
 152
 153         OSAL_FREE(p_dev, p_dev->reset_stats);
 154
 155         for_each_hwfn(p_dev, i) {
 156                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 157
 158                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 159                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 160         }
 161
 162         for_each_hwfn(p_dev, i) {
 163                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 164
 165                 ecore_cxt_mngr_free(p_hwfn);
 166                 ecore_qm_info_free(p_hwfn);
 167                 ecore_spq_free(p_hwfn);
 168                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 169                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 170                 ecore_int_free(p_hwfn);
 171 #ifdef CONFIG_ECORE_LL2
 172                 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 173 #endif
 174                 ecore_iov_free(p_hwfn);
 175                 ecore_dmae_info_free(p_hwfn);
 176                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 177                 /* @@@TBD Flush work-queue ? */
 178         }
 179 }
 180
 181 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
 182                                                bool b_sleepable)
 183 {
 184         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
 185         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 186         struct init_qm_port_params *p_qm_port;
 187         bool init_rdma_offload_pq = false;
 188         bool init_pure_ack_pq = false;
 189         bool init_ooo_pq = false;
 190         u16 num_pqs, protocol_pqs;
 191         u16 num_pf_rls = 0;
 192         u16 num_vfs = 0;
 193         u32 pf_rl;
 194         u8 pf_wfq;
 195
 196         /* @TMP - saving the existing min/max bw config before resetting the
 197          * qm_info to restore them.
 198          */
 199         pf_rl = qm_info->pf_rl;
 200         pf_wfq = qm_info->pf_wfq;
 201
 202 #ifdef CONFIG_ECORE_SRIOV
 203         if (p_hwfn->p_dev->p_iov_info)
 204                 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
 205 #endif
 206         OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
 207
 208 #ifndef ASIC_ONLY
 209         /* @TMP - Don't allocate QM queues for VFs on emulation */
 210         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 211                 DP_NOTICE(p_hwfn, false,
 212                           "Emulation - skip configuring QM queues for VFs\n");
 213                 num_vfs = 0;
 214         }
 215 #endif
 216
 217         /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
 218          * active, we want physical queues allocated for all of them, since we
 219          * don't have a good recycle flow. Non ethernet PFs require only a
 220          * single physical queue.
 221          */
 222         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 223             p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 224             p_hwfn->hw_info.personality == ECORE_PCI_ETH)
 225                 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
 226         else
 227                 protocol_pqs = 1;
 228
 229         num_pqs = protocol_pqs + num_vfs + 1;   /* The '1' is for pure-LB */
 230         num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
 231
 232         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 233                 num_pqs++;      /* for RoCE queue */
 234                 init_rdma_offload_pq = true;
 235                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
 236                         /* Due to FW assumption that rl==vport, we limit the
 237                          * number of rate limiters by the minimum between its
 238                          * allocated number and the allocated number of vports.
 239                          * Another limitation is the number of supported qps
 240                          * with rate limiters in FW.
 241                          */
 242                         num_pf_rls =
 243                             (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 244                                              RESC_NUM(p_hwfn, ECORE_VPORT));
 245
 246                         /* we subtract num_vfs because each one requires a rate
 247                          * limiter, and one default rate limiter.
 248                          */
 249                         if (num_pf_rls < num_vfs + 1) {
 250                                 DP_ERR(p_hwfn, "No RL for DCQCN");
 251                                 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
 252                                        num_pf_rls, num_vfs);
 253                                 return ECORE_INVAL;
 254                         }
 255                         num_pf_rls -= num_vfs + 1;
 256                 }
 257
 258                 num_pqs += num_pf_rls;
 259                 qm_info->num_pf_rls = (u8)num_pf_rls;
 260         }
 261
 262         if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
 263                 num_pqs += 3;   /* for iwarp queue / pure-ack / ooo */
 264                 init_rdma_offload_pq = true;
 265                 init_pure_ack_pq = true;
 266                 init_ooo_pq = true;
 267         }
 268
 269         if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 270                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 271                 init_pure_ack_pq = true;
 272                 init_ooo_pq = true;
 273         }
 274
 275         /* Sanity checking that setup requires legal number of resources */
 276         if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
 277                 DP_ERR(p_hwfn,
 278                        "Need too many Physical queues - 0x%04x avail %04x",
 279                        num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
 280                 return ECORE_INVAL;
 281         }
 282
 283         /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
 284          * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
 285          */
 286         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
 287                                             b_sleepable ? GFP_KERNEL :
 288                                             GFP_ATOMIC,
 289                                             sizeof(struct init_qm_pq_params) *
 290                                             num_pqs);
 291         if (!qm_info->qm_pq_params)
 292                 goto alloc_err;
 293
 294         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
 295                                                b_sleepable ? GFP_KERNEL :
 296                                                GFP_ATOMIC,
 297                                                sizeof(struct
 298                                                       init_qm_vport_params) *
 299                                                num_vports);
 300         if (!qm_info->qm_vport_params)
 301                 goto alloc_err;
 302
 303         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
 304                                               b_sleepable ? GFP_KERNEL :
 305                                               GFP_ATOMIC,
 306                                               sizeof(struct init_qm_port_params)
 307                                               * MAX_NUM_PORTS);
 308         if (!qm_info->qm_port_params)
 309                 goto alloc_err;
 310
 311         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
 312                                         b_sleepable ? GFP_KERNEL :
 313                                         GFP_ATOMIC,
 314                                         sizeof(struct ecore_wfq_data) *
 315                                         num_vports);
 316
 317         if (!qm_info->wfq_data)
 318                 goto alloc_err;
 319
 320         vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 321
 322         /* First init rate limited queues ( Due to RoCE assumption of
 323          * qpid=rlid )
 324          */
 325         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 326                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 327                 qm_info->qm_pq_params[curr_queue].tc_id =
 328                     p_hwfn->hw_info.offload_tc;
 329                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 330                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 331         };
 332
 333         /* Protocol PQs */
 334         for (i = 0; i < protocol_pqs; i++) {
 335                 struct init_qm_pq_params *params =
 336                     &qm_info->qm_pq_params[curr_queue++];
 337
 338                 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 339                     p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 340                     p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
 341                         params->vport_id = vport_id;
 342                         params->tc_id = i;
 343                         /* Note: this assumes that if we had a configuration
 344                          * with N tcs and subsequently another configuration
 345                          * With Fewer TCs, the in flight traffic (in QM queues,
 346                          * in FW, from driver to FW) will still trickle out and
 347                          * not get "stuck" in the QM. This is determined by the
 348                          * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
 349                          * supposed to be cleared in this map, allowing traffic
 350                          * to flush out. If this is not the case, we would need
 351                          * to set the TC of unused queues to 0, and reconfigure
 352                          * QM every time num of TCs changes. Unused queues in
 353                          * this context would mean those intended for TCs where
 354                          * tc_id > hw_info.num_active_tcs.
 355                          */
 356                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 357                 } else {
 358                         params->vport_id = vport_id;
 359                         params->tc_id = p_hwfn->hw_info.offload_tc;
 360                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 361                 }
 362         }
 363
 364         /* Then init pure-LB PQ */
 365         qm_info->pure_lb_pq = curr_queue;
 366         qm_info->qm_pq_params[curr_queue].vport_id =
 367             (u8)RESC_START(p_hwfn, ECORE_VPORT);
 368         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 369         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 370         curr_queue++;
 371
 372         qm_info->offload_pq = 0;        /* Already initialized for iSCSI/FCoE */
 373         if (init_rdma_offload_pq) {
 374                 qm_info->offload_pq = curr_queue;
 375                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 376                 qm_info->qm_pq_params[curr_queue].tc_id =
 377                     p_hwfn->hw_info.offload_tc;
 378                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 379                 curr_queue++;
 380         }
 381
 382         if (init_pure_ack_pq) {
 383                 qm_info->pure_ack_pq = curr_queue;
 384                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 385                 qm_info->qm_pq_params[curr_queue].tc_id =
 386                     p_hwfn->hw_info.offload_tc;
 387                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 388                 curr_queue++;
 389         }
 390
 391         if (init_ooo_pq) {
 392                 qm_info->ooo_pq = curr_queue;
 393                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 394                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 395                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 396                 curr_queue++;
 397         }
 398
 399         /* Then init per-VF PQs */
 400         vf_offset = curr_queue;
 401         for (i = 0; i < num_vfs; i++) {
 402                 /* First vport is used by the PF */
 403                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 404                 /* @@@TBD VF Multi-cos */
 405                 qm_info->qm_pq_params[curr_queue].tc_id = 0;
 406                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 407                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 408                 curr_queue++;
 409         };
 410
 411         qm_info->vf_queues_offset = vf_offset;
 412         qm_info->num_pqs = num_pqs;
 413         qm_info->num_vports = num_vports;
 414
 415         /* Initialize qm port parameters */
 416         num_ports = p_hwfn->p_dev->num_ports_in_engines;
 417         for (i = 0; i < num_ports; i++) {
 418                 p_qm_port = &qm_info->qm_port_params[i];
 419                 p_qm_port->active = 1;
 420                 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
 421                  * be in place
 422                  */
 423                 if (num_ports == 4)
 424                         p_qm_port->active_phys_tcs = 0xf;
 425                 else
 426                         p_qm_port->active_phys_tcs = 0x9f;
 427                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 428                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 429         }
 430
 431         if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
 432                 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
 433         else
 434                 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 435
 436         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 437
 438         qm_info->num_vf_pqs = num_vfs;
 439         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 440
 441         for (i = 0; i < qm_info->num_vports; i++)
 442                 qm_info->qm_vport_params[i].vport_wfq = 1;
 443
 444         qm_info->vport_rl_en = 1;
 445         qm_info->vport_wfq_en = 1;
 446         qm_info->pf_rl = pf_rl;
 447         qm_info->pf_wfq = pf_wfq;
 448
 449         return ECORE_SUCCESS;
 450
 451  alloc_err:
 452         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 453         ecore_qm_info_free(p_hwfn);
 454         return ECORE_NOMEM;
 455 }
 456
 457 /* This function reconfigures the QM pf on the fly.
 458  * For this purpose we:
 459  * 1. reconfigure the QM database
 460  * 2. set new values to runtime arrat
 461  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 462  * 4. activate init tool in QM_PF stage
 463  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 464  */
 465 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 466                                      struct ecore_ptt *p_ptt)
 467 {
 468         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 469         bool b_rc;
 470         enum _ecore_status_t rc;
 471
 472         /* qm_info is allocated in ecore_init_qm_info() which is already called
 473          * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
 474          * The allocated size may change each init, so we free it before next
 475          * allocation.
 476          */
 477         ecore_qm_info_free(p_hwfn);
 478
 479         /* initialize ecore's qm data structure */
 480         rc = ecore_init_qm_info(p_hwfn, false);
 481         if (rc != ECORE_SUCCESS)
 482                 return rc;
 483
 484         /* stop PF's qm queues */
 485         OSAL_SPIN_LOCK(&qm_lock);
 486         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 487                                       qm_info->start_pq, qm_info->num_pqs);
 488         OSAL_SPIN_UNLOCK(&qm_lock);
 489         if (!b_rc)
 490                 return ECORE_INVAL;
 491
 492         /* clear the QM_PF runtime phase leftovers from previous init */
 493         ecore_init_clear_rt_data(p_hwfn);
 494
 495         /* prepare QM portion of runtime array */
 496         ecore_qm_init_pf(p_hwfn);
 497
 498         /* activate init tool on runtime array */
 499         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 500                             p_hwfn->hw_info.hw_mode);
 501         if (rc != ECORE_SUCCESS)
 502                 return rc;
 503
 504         /* start PF's qm queues */
 505         OSAL_SPIN_LOCK(&qm_lock);
 506         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 507                                       qm_info->start_pq, qm_info->num_pqs);
 508         OSAL_SPIN_UNLOCK(&qm_lock);
 509         if (!b_rc)
 510                 return ECORE_INVAL;
 511
 512         return ECORE_SUCCESS;
 513 }
 514
 515 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 516 {
 517         struct ecore_consq *p_consq;
 518         struct ecore_eq *p_eq;
 519 #ifdef  CONFIG_ECORE_LL2
 520         struct ecore_ll2_info *p_ll2_info;
 521 #endif
 522         enum _ecore_status_t rc = ECORE_SUCCESS;
 523         int i;
 524
 525         if (IS_VF(p_dev))
 526                 return rc;
 527
 528         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 529                                      sizeof(*p_dev->fw_data));
 530         if (!p_dev->fw_data)
 531                 return ECORE_NOMEM;
 532
 533         /* Allocate Memory for the Queue->CID mapping */
 534         for_each_hwfn(p_dev, i) {
 535                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 536                 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 537                 int tx_size, rx_size;
 538
 539                 /* @@@TMP - resc management, change to actual required size */
 540                 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
 541                         num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
 542                 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
 543                 rx_size = sizeof(struct ecore_hw_cid_data) *
 544                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 545
 546                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 547                                                 tx_size);
 548                 if (!p_hwfn->p_tx_cids) {
 549                         DP_NOTICE(p_hwfn, true,
 550                                   "Failed to allocate memory for Tx Cids\n");
 551                         goto alloc_no_mem;
 552                 }
 553
 554                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 555                                                 rx_size);
 556                 if (!p_hwfn->p_rx_cids) {
 557                         DP_NOTICE(p_hwfn, true,
 558                                   "Failed to allocate memory for Rx Cids\n");
 559                         goto alloc_no_mem;
 560                 }
 561         }
 562
 563         for_each_hwfn(p_dev, i) {
 564                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 565                 u32 n_eqes, num_cons;
 566
 567                 /* First allocate the context manager structure */
 568                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 569                 if (rc)
 570                         goto alloc_err;
 571
 572                 /* Set the HW cid/tid numbers (in the contest manager)
 573                  * Must be done prior to any further computations.
 574                  */
 575                 rc = ecore_cxt_set_pf_params(p_hwfn);
 576                 if (rc)
 577                         goto alloc_err;
 578
 579                 /* Prepare and process QM requirements */
 580                 rc = ecore_init_qm_info(p_hwfn, true);
 581                 if (rc)
 582                         goto alloc_err;
 583
 584                 /* Compute the ILT client partition */
 585                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 586                 if (rc)
 587                         goto alloc_err;
 588
 589                 /* CID map / ILT shadow table / T2
 590                  * The talbes sizes are determined by the computations above
 591                  */
 592                 rc = ecore_cxt_tables_alloc(p_hwfn);
 593                 if (rc)
 594                         goto alloc_err;
 595
 596                 /* SPQ, must follow ILT because initializes SPQ context */
 597                 rc = ecore_spq_alloc(p_hwfn);
 598                 if (rc)
 599                         goto alloc_err;
 600
 601                 /* SP status block allocation */
 602                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 603                                                            RESERVED_PTT_DPC);
 604
 605                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 606                 if (rc)
 607                         goto alloc_err;
 608
 609                 rc = ecore_iov_alloc(p_hwfn);
 610                 if (rc)
 611                         goto alloc_err;
 612
 613                 /* EQ */
 614                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 615                 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
 616                     (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
 617                         /* Calculate the EQ size
 618                          * ---------------------
 619                          * Each ICID may generate up to one event at a time i.e.
 620                          * the event must be handled/cleared before a new one
 621                          * can be generated. We calculate the sum of events per
 622                          * protocol and create an EQ deep enough to handle the
 623                          * worst case:
 624                          * - Core - according to SPQ.
 625                          * - RoCE - per QP there are a couple of ICIDs, one
 626                          *          responder and one requester, each can
 627                          *          generate an EQE => n_eqes_qp = 2 * n_qp.
 628                          *          Each CQ can generate an EQE. There are 2 CQs
 629                          *          per QP => n_eqes_cq = 2 * n_qp.
 630                          *          Hence the RoCE total is 4 * n_qp or
 631                          *          2 * num_cons.
 632                          * - ENet - There can be up to two events per VF. One
 633                          *          for VF-PF channel and another for VF FLR
 634                          *          initial cleanup. The number of VFs is
 635                          *          bounded by MAX_NUM_VFS_BB, and is much
 636                          *          smaller than RoCE's so we avoid exact
 637                          *          calculation.
 638                          */
 639                         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 640                                 num_cons =
 641                                     ecore_cxt_get_proto_cid_count(
 642                                                 p_hwfn,
 643                                                 PROTOCOLID_ROCE,
 644                                                 0);
 645                                 num_cons *= 2;
 646                         } else {
 647                                 num_cons = ecore_cxt_get_proto_cid_count(
 648                                                 p_hwfn,
 649                                                 PROTOCOLID_IWARP,
 650                                                 0);
 651                         }
 652                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 653                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 654                         num_cons =
 655                             ecore_cxt_get_proto_cid_count(p_hwfn,
 656                                                           PROTOCOLID_ISCSI, 0);
 657                         n_eqes += 2 * num_cons;
 658                 }
 659
 660                 if (n_eqes > 0xFFFF) {
 661                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 662                                        "The maximum of a u16 chain is 0x%x\n",
 663                                n_eqes, 0xFFFF);
 664                         goto alloc_no_mem;
 665                 }
 666
 667                 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 668                 if (!p_eq)
 669                         goto alloc_no_mem;
 670                 p_hwfn->p_eq = p_eq;
 671
 672                 p_consq = ecore_consq_alloc(p_hwfn);
 673                 if (!p_consq)
 674                         goto alloc_no_mem;
 675                 p_hwfn->p_consq = p_consq;
 676
 677 #ifdef CONFIG_ECORE_LL2
 678                 if (p_hwfn->using_ll2) {
 679                         p_ll2_info = ecore_ll2_alloc(p_hwfn);
 680                         if (!p_ll2_info)
 681                                 goto alloc_no_mem;
 682                         p_hwfn->p_ll2_info = p_ll2_info;
 683                 }
 684 #endif
 685
 686                 /* DMA info initialization */
 687                 rc = ecore_dmae_info_alloc(p_hwfn);
 688                 if (rc) {
 689                         DP_NOTICE(p_hwfn, true,
 690                                   "Failed to allocate memory for dmae_info structure\n");
 691                         goto alloc_err;
 692                 }
 693
 694                 /* DCBX initialization */
 695                 rc = ecore_dcbx_info_alloc(p_hwfn);
 696                 if (rc) {
 697                         DP_NOTICE(p_hwfn, true,
 698                                   "Failed to allocate memory for dcbx structure\n");
 699                         goto alloc_err;
 700                 }
 701         }
 702
 703         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 704                                          sizeof(*p_dev->reset_stats));
 705         if (!p_dev->reset_stats) {
 706                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 707                 goto alloc_no_mem;
 708         }
 709
 710         return ECORE_SUCCESS;
 711
 712  alloc_no_mem:
 713         rc = ECORE_NOMEM;
 714  alloc_err:
 715         ecore_resc_free(p_dev);
 716         return rc;
 717 }
 718
 719 void ecore_resc_setup(struct ecore_dev *p_dev)
 720 {
 721         int i;
 722
 723         if (IS_VF(p_dev))
 724                 return;
 725
 726         for_each_hwfn(p_dev, i) {
 727                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 728
 729                 ecore_cxt_mngr_setup(p_hwfn);
 730                 ecore_spq_setup(p_hwfn);
 731                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
 732                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
 733
 734                 /* Read shadow of current MFW mailbox */
 735                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 736                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
 737                             p_hwfn->mcp_info->mfw_mb_cur,
 738                             p_hwfn->mcp_info->mfw_mb_length);
 739
 740                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 741
 742                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 743 #ifdef CONFIG_ECORE_LL2
 744                 if (p_hwfn->using_ll2)
 745                         ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
 746 #endif
 747         }
 748 }
 749
 750 #define FINAL_CLEANUP_POLL_CNT  (100)
 751 #define FINAL_CLEANUP_POLL_TIME (10)
 752 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
 753                                          struct ecore_ptt *p_ptt,
 754                                          u16 id, bool is_vf)
 755 {
 756         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 757         enum _ecore_status_t rc = ECORE_TIMEOUT;
 758
 759 #ifndef ASIC_ONLY
 760         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
 761             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 762                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
 763                 return ECORE_SUCCESS;
 764         }
 765 #endif
 766
 767         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 768             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 769
 770         if (is_vf)
 771                 id += 0x10;
 772
 773         command |= X_FINAL_CLEANUP_AGG_INT <<
 774             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 775         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 776         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 777         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 778
 779 /* Make sure notification is not set before initiating final cleanup */
 780
 781         if (REG_RD(p_hwfn, addr)) {
 782                 DP_NOTICE(p_hwfn, false,
 783                           "Unexpected; Found final cleanup notification");
 784                 DP_NOTICE(p_hwfn, false,
 785                           " before initiating final cleanup\n");
 786                 REG_WR(p_hwfn, addr, 0);
 787         }
 788
 789         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
 790                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 791                    id, OSAL_CPU_TO_LE32(command));
 792
 793         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
 794                  OSAL_CPU_TO_LE32(command));
 795
 796         /* Poll until completion */
 797         while (!REG_RD(p_hwfn, addr) && count--)
 798                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
 799
 800         if (REG_RD(p_hwfn, addr))
 801                 rc = ECORE_SUCCESS;
 802         else
 803                 DP_NOTICE(p_hwfn, true,
 804                           "Failed to receive FW final cleanup notification\n");
 805
 806         /* Cleanup afterwards */
 807         REG_WR(p_hwfn, addr, 0);
 808
 809         return rc;
 810 }
 811
 812 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
 813 {
 814         int hw_mode = 0;
 815
 816         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
 817                 hw_mode |= 1 << MODE_BB_B0;
 818         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
 819                 hw_mode |= 1 << MODE_K2;
 820         } else {
 821                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
 822                           p_hwfn->p_dev->type);
 823                 return ECORE_INVAL;
 824         }
 825
 826         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
 827         switch (p_hwfn->p_dev->num_ports_in_engines) {
 828         case 1:
 829                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 830                 break;
 831         case 2:
 832                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 833                 break;
 834         case 4:
 835                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 836                 break;
 837         default:
 838                 DP_NOTICE(p_hwfn, true,
 839                           "num_ports_in_engine = %d not supported\n",
 840                           p_hwfn->p_dev->num_ports_in_engines);
 841                 return ECORE_INVAL;
 842         }
 843
 844         switch (p_hwfn->p_dev->mf_mode) {
 845         case ECORE_MF_DEFAULT:
 846         case ECORE_MF_NPAR:
 847                 hw_mode |= 1 << MODE_MF_SI;
 848                 break;
 849         case ECORE_MF_OVLAN:
 850                 hw_mode |= 1 << MODE_MF_SD;
 851                 break;
 852         default:
 853                 DP_NOTICE(p_hwfn, true,
 854                           "Unsupported MF mode, init as DEFAULT\n");
 855                 hw_mode |= 1 << MODE_MF_SI;
 856         }
 857
 858 #ifndef ASIC_ONLY
 859         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 860                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 861                         hw_mode |= 1 << MODE_FPGA;
 862                 } else {
 863                         if (p_hwfn->p_dev->b_is_emul_full)
 864                                 hw_mode |= 1 << MODE_EMUL_FULL;
 865                         else
 866                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
 867                 }
 868         } else
 869 #endif
 870                 hw_mode |= 1 << MODE_ASIC;
 871
 872         if (p_hwfn->p_dev->num_hwfns > 1)
 873                 hw_mode |= 1 << MODE_100G;
 874
 875         p_hwfn->hw_info.hw_mode = hw_mode;
 876
 877         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
 878                    "Configuring function for hw_mode: 0x%08x\n",
 879                    p_hwfn->hw_info.hw_mode);
 880
 881         return ECORE_SUCCESS;
 882 }
 883
 884 #ifndef ASIC_ONLY
 885 /* MFW-replacement initializations for non-ASIC */
 886 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
 887                                                struct ecore_ptt *p_ptt)
 888 {
 889         u32 pl_hv = 1;
 890         int i;
 891
 892         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 893                 pl_hv |= 0x600;
 894
 895         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
 896
 897         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 898                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
 899
 900         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
 901         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
 902         if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
 903                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
 904
 905         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
 906                 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
 907                 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
 908                          (p_hwfn->p_dev->num_ports_in_engines >> 1));
 909
 910                 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
 911                          p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
 912         }
 913
 914         /* Poll on RBC */
 915         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
 916         for (i = 0; i < 100; i++) {
 917                 OSAL_UDELAY(50);
 918                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
 919                         break;
 920         }
 921         if (i == 100)
 922                 DP_NOTICE(p_hwfn, true,
 923                           "RBC done failed to complete in PSWRQ2\n");
 924
 925         return ECORE_SUCCESS;
 926 }
 927 #endif
 928
 929 /* Init run time data for all PFs and their VFs on an engine.
 930  * TBD - for VFs - Once we have parent PF info for each VF in
 931  * shmem available as CAU requires knowledge of parent PF for each VF.
 932  */
 933 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
 934 {
 935         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 936         int i, sb_id;
 937
 938         for_each_hwfn(p_dev, i) {
 939                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 940                 struct ecore_igu_info *p_igu_info;
 941                 struct ecore_igu_block *p_block;
 942                 struct cau_sb_entry sb_entry;
 943
 944                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 945
 946                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
 947                      sb_id++) {
 948                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 949
 950                         if (!p_block->is_pf)
 951                                 continue;
 952
 953                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
 954                                                 p_block->function_id, 0, 0);
 955                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 956                 }
 957         }
 958 }
 959
 960 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
 961                                                  struct ecore_ptt *p_ptt,
 962                                                  int hw_mode)
 963 {
 964         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 965         struct ecore_dev *p_dev = p_hwfn->p_dev;
 966         u8 vf_id, max_num_vfs;
 967         u16 num_pfs, pf_id;
 968         u32 concrete_fid;
 969         enum _ecore_status_t rc = ECORE_SUCCESS;
 970
 971         ecore_init_cau_rt_data(p_dev);
 972
 973         /* Program GTT windows */
 974         ecore_gtt_init(p_hwfn);
 975
 976 #ifndef ASIC_ONLY
 977         if (CHIP_REV_IS_EMUL(p_dev)) {
 978                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
 979                 if (rc != ECORE_SUCCESS)
 980                         return rc;
 981         }
 982 #endif
 983
 984         if (p_hwfn->mcp_info) {
 985                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 986                         qm_info->pf_rl_en = 1;
 987                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 988                         qm_info->pf_wfq_en = 1;
 989         }
 990
 991         ecore_qm_common_rt_init(p_hwfn,
 992                                 p_dev->num_ports_in_engines,
 993                                 qm_info->max_phys_tcs_per_port,
 994                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
 995                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
 996                                 qm_info->qm_port_params);
 997
 998         ecore_cxt_hw_init_common(p_hwfn);
 999
1000         /* Close gate from NIG to BRB/Storm; By default they are open, but
1001          * we close them to prevent NIG from passing data to reset blocks.
1002          * Should have been done in the ENGINE phase, but init-tool lacks
1003          * proper port-pretend capabilities.
1004          */
1005         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1006         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1007         ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1008         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1009         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1010         ecore_port_unpretend(p_hwfn, p_ptt);
1011
1012         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1013         if (rc != ECORE_SUCCESS)
1014                 return rc;
1015
1016         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1017          * need to decide with which value, maybe runtime
1018          */
1019         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1020         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1021
1022         if (ECORE_IS_BB(p_dev)) {
1023                 /* Workaround clears ROCE search for all functions to prevent
1024                  * involving non initialized function in processing ROCE packet.
1025                  */
1026                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1027                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1028                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1029                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1030                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1031                 }
1032                 /* pretend to original PF */
1033                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1034         }
1035
1036         /* Workaround for avoiding CCFC execution error when getting packets
1037          * with CRC errors, and allowing instead the invoking of the FW error
1038          * handler.
1039          * This is not done inside the init tool since it currently can't
1040          * perform a pretending to VFs.
1041          */
1042         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1043         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1044                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1045                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1046                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1047                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1048                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1049                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1050         }
1051         /* pretend to original PF */
1052         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1053
1054         return rc;
1055 }
1056
1057 #ifndef ASIC_ONLY
1058 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1059 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1060
1061 #define PMEG_IF_BYTE_COUNT      8
1062
1063 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1064                              struct ecore_ptt *p_ptt,
1065                              u32 addr, u64 data, u8 reg_type, u8 port)
1066 {
1067         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1068                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1069                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
1070                    (8 << PMEG_IF_BYTE_COUNT),
1071                    (reg_type << 25) | (addr << 8) | port,
1072                    (u32)((data >> 32) & 0xffffffff),
1073                    (u32)(data & 0xffffffff));
1074
1075         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
1076                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
1077                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1078         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
1079                  (reg_type << 25) | (addr << 8) | port);
1080         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1081                  data & 0xffffffff);
1082         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1083                  (data >> 32) & 0xffffffff);
1084 }
1085
1086 #define XLPORT_MODE_REG (0x20a)
1087 #define XLPORT_MAC_CONTROL (0x210)
1088 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1089 #define XLPORT_ENABLE_REG (0x20b)
1090
1091 #define XLMAC_CTRL (0x600)
1092 #define XLMAC_MODE (0x601)
1093 #define XLMAC_RX_MAX_SIZE (0x608)
1094 #define XLMAC_TX_CTRL (0x604)
1095 #define XLMAC_PAUSE_CTRL (0x60d)
1096 #define XLMAC_PFC_CTRL (0x60e)
1097
1098 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
1099                                     struct ecore_ptt *p_ptt)
1100 {
1101         u8 port = p_hwfn->port_id;
1102         u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
1103
1104         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
1105                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
1106                  (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
1107                  | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
1108
1109         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
1110                  1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
1111
1112         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
1113                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
1114
1115         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
1116                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
1117
1118         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
1119                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
1120
1121         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
1122                  (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
1123                  (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
1124
1125         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
1126 }
1127
1128 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1129                                  struct ecore_ptt *p_ptt)
1130 {
1131         u8 loopback = 0, port = p_hwfn->port_id * 2;
1132
1133         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1134
1135         if (ECORE_IS_AH(p_hwfn->p_dev)) {
1136                 ecore_emul_link_init_ah(p_hwfn, p_ptt);
1137                 return;
1138         }
1139
1140         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1141         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1142                          port);
1143         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1144         /* XLMAC: SOFT RESET */
1145         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1146         /* XLMAC: Port Speed >= 10Gbps */
1147         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1148         /* XLMAC: Max Size */
1149         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1150         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1151                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1152                          0, port);
1153         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1154         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1155                          0x30ffffc000ULL, 0, port);
1156         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1157                          port); /* XLMAC: TX_EN, RX_EN */
1158         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1159         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1160                          0x1003 | (loopback << 2), 0, port);
1161         /* Enabled Parallel PFC interface */
1162         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1163
1164         /* XLPORT port enable */
1165         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1166 }
1167
1168 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
1169                             struct ecore_ptt *p_ptt, u8 port)
1170 {
1171         int port_offset = port ? 0x800 : 0;
1172         u32 xmac_rxctrl = 0;
1173
1174         /* Reset of XMAC */
1175         /* FIXME: move to common start */
1176         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1177                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1178         OSAL_MSLEEP(1);
1179         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1180                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1181
1182         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1183
1184         /* Set the number of ports on the Warp Core to 10G */
1185         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1186
1187         /* Soft reset of XMAC */
1188         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1189                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1190         OSAL_MSLEEP(1);
1191         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1192                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1193
1194         /* FIXME: move to common end */
1195         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1196                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
1197
1198         /* Set Max packet size: initialize XMAC block register for port 0 */
1199         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
1200
1201         /* CRC append for Tx packets: init XMAC block register for port 1 */
1202         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
1203
1204         /* Enable TX and RX: initialize XMAC block register for port 1 */
1205         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
1206                  XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
1207         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
1208         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
1209         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
1210 }
1211 #endif
1212
1213 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1214                                                struct ecore_ptt *p_ptt,
1215                                                int hw_mode)
1216 {
1217         enum _ecore_status_t rc = ECORE_SUCCESS;
1218
1219         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1220                             hw_mode);
1221         if (rc != ECORE_SUCCESS)
1222                 return rc;
1223 #ifndef ASIC_ONLY
1224         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1225                 return ECORE_SUCCESS;
1226
1227         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1228                 if (ECORE_IS_AH(p_hwfn->p_dev))
1229                         return ECORE_SUCCESS;
1230                 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1231         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1232                 if (p_hwfn->p_dev->num_hwfns > 1) {
1233                         /* Activate OPTE in CMT */
1234                         u32 val;
1235
1236                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1237                         val |= 0x10;
1238                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1239                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1240                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1241                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1242                         ecore_wr(p_hwfn, p_ptt,
1243                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1244                         ecore_wr(p_hwfn, p_ptt,
1245                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1246                         ecore_wr(p_hwfn, p_ptt,
1247                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1248                                  0x55555555);
1249                 }
1250
1251                 ecore_emul_link_init(p_hwfn, p_ptt);
1252         } else {
1253                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1254         }
1255 #endif
1256
1257         return rc;
1258 }
1259
1260 static enum _ecore_status_t
1261 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1262                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1263 {
1264         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1265         u32 dpi_bit_shift, dpi_count;
1266         u32 min_dpis;
1267
1268         /* Calculate DPI size
1269          * ------------------
1270          * The PWM region contains Doorbell Pages. The first is reserverd for
1271          * the kernel for, e.g, L2. The others are free to be used by non-
1272          * trusted applications, typically from user space. Each page, called a
1273          * doorbell page is sectioned into windows that allow doorbells to be
1274          * issued in parallel by the kernel/application. The size of such a
1275          * window (a.k.a. WID) is 1kB.
1276          * Summary:
1277          *    1kB WID x N WIDS = DPI page size
1278          *    DPI page size x N DPIs = PWM region size
1279          * Notes:
1280          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1281          * in order to ensure that two applications won't share the same page.
1282          * It also must contain at least one WID per CPU to allow parallelism.
1283          * It also must be a power of 2, since it is stored as a bit shift.
1284          *
1285          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1286          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1287          * containing 4 WIDs.
1288          */
1289         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1290         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1291         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1292         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1293         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1294
1295         dpi_count = pwm_region_size / dpi_page_size;
1296
1297         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1298         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1299
1300         /* Update hwfn */
1301         p_hwfn->dpi_size = dpi_page_size;
1302         p_hwfn->dpi_count = dpi_count;
1303
1304         /* Update registers */
1305         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1306
1307         if (dpi_count < min_dpis)
1308                 return ECORE_NORESOURCES;
1309
1310         return ECORE_SUCCESS;
1311 }
1312
1313 enum ECORE_ROCE_EDPM_MODE {
1314         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1315         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1316         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1317 };
1318
1319 static enum _ecore_status_t
1320 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1321                               struct ecore_ptt *p_ptt)
1322 {
1323         u32 pwm_regsize, norm_regsize;
1324         u32 non_pwm_conn, min_addr_reg1;
1325         u32 db_bar_size, n_cpus;
1326         u32 roce_edpm_mode;
1327         u32 pf_dems_shift;
1328         int rc = ECORE_SUCCESS;
1329         u8 cond;
1330
1331         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1332         if (p_hwfn->p_dev->num_hwfns > 1)
1333                 db_bar_size /= 2;
1334
1335         /* Calculate doorbell regions
1336          * -----------------------------------
1337          * The doorbell BAR is made of two regions. The first is called normal
1338          * region and the second is called PWM region. In the normal region
1339          * each ICID has its own set of addresses so that writing to that
1340          * specific address identifies the ICID. In the Process Window Mode
1341          * region the ICID is given in the data written to the doorbell. The
1342          * above per PF register denotes the offset in the doorbell BAR in which
1343          * the PWM region begins.
1344          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1345          * non-PWM connection. The calculation below computes the total non-PWM
1346          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1347          * in units of 4,096 bytes.
1348          */
1349         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1350             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1351                                           OSAL_NULL) +
1352             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1353         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1354         min_addr_reg1 = norm_regsize / 4096;
1355         pwm_regsize = db_bar_size - norm_regsize;
1356
1357         /* Check that the normal and PWM sizes are valid */
1358         if (db_bar_size < norm_regsize) {
1359                 DP_ERR(p_hwfn->p_dev,
1360                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1361                        db_bar_size, norm_regsize);
1362                 return ECORE_NORESOURCES;
1363         }
1364         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1365                 DP_ERR(p_hwfn->p_dev,
1366                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1367                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1368                        norm_regsize);
1369                 return ECORE_NORESOURCES;
1370         }
1371
1372         /* Calculate number of DPIs */
1373         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1374         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1375             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1376                 /* Either EDPM is mandatory, or we are attempting to allocate a
1377                  * WID per CPU.
1378                  */
1379                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1380                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1381         }
1382
1383         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1384             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1385         if (cond || p_hwfn->dcbx_no_edpm) {
1386                 /* Either EDPM is disabled from user configuration, or it is
1387                  * disabled via DCBx, or it is not mandatory and we failed to
1388                  * allocated a WID per CPU.
1389                  */
1390                 n_cpus = 1;
1391                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1392
1393                 /* If we entered this flow due to DCBX then the DPM register is
1394                  * already configured.
1395                  */
1396         }
1397
1398         DP_INFO(p_hwfn,
1399                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1400                 norm_regsize, pwm_regsize);
1401         DP_INFO(p_hwfn,
1402                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1403                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1404                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1405                 "disabled" : "enabled");
1406
1407         /* Check return codes from above calls */
1408         if (rc) {
1409                 DP_ERR(p_hwfn,
1410                        "Failed to allocate enough DPIs\n");
1411                 return ECORE_NORESOURCES;
1412         }
1413
1414         /* Update hwfn */
1415         p_hwfn->dpi_start_offset = norm_regsize;
1416
1417         /* Update registers */
1418         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1419         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1420         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1421         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1422
1423         return ECORE_SUCCESS;
1424 }
1425
1426 static enum _ecore_status_t
1427 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1428                  struct ecore_ptt *p_ptt,
1429                  struct ecore_tunn_start_params *p_tunn,
1430                  int hw_mode,
1431                  bool b_hw_start,
1432                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1433 {
1434         u8 rel_pf_id = p_hwfn->rel_pf_id;
1435         u32 prs_reg;
1436         enum _ecore_status_t rc = ECORE_SUCCESS;
1437         u16 ctrl;
1438         int pos;
1439
1440         if (p_hwfn->mcp_info) {
1441                 struct ecore_mcp_function_info *p_info;
1442
1443                 p_info = &p_hwfn->mcp_info->func_info;
1444                 if (p_info->bandwidth_min)
1445                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1446
1447                 /* Update rate limit once we'll actually have a link */
1448                 p_hwfn->qm_info.pf_rl = 100000;
1449         }
1450         ecore_cxt_hw_init_pf(p_hwfn);
1451
1452         ecore_int_igu_init_rt(p_hwfn);
1453
1454         /* Set VLAN in NIG if needed */
1455         if (hw_mode & (1 << MODE_MF_SD)) {
1456                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1457                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1458                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1459                              p_hwfn->hw_info.ovlan);
1460         }
1461
1462         /* Enable classification by MAC if needed */
1463         if (hw_mode & (1 << MODE_MF_SI)) {
1464                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1465                            "Configuring TAGMAC_CLS_TYPE\n");
1466                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1467                              1);
1468         }
1469
1470         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1471         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1472                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1473         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1474                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1475         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1476
1477         /* perform debug configuration when chip is out of reset */
1478         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1479
1480         /* Cleanup chip from previous driver if such remains exist */
1481         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1482         if (rc != ECORE_SUCCESS) {
1483                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1484                 return rc;
1485         }
1486
1487         /* PF Init sequence */
1488         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1489         if (rc)
1490                 return rc;
1491
1492         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1493         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1494         if (rc)
1495                 return rc;
1496
1497         /* Pure runtime initializations - directly to the HW  */
1498         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1499
1500         /* PCI relaxed ordering causes a decrease in the performance on some
1501          * systems. Till a root cause is found, disable this attribute in the
1502          * PCI config space.
1503          */
1504         /* Not in use @DPDK
1505         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1506         * if (!pos) {
1507         *       DP_NOTICE(p_hwfn, true,
1508         *                 "Failed to find the PCIe Cap\n");
1509         *       return ECORE_IO;
1510         * }
1511         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1512         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1513         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1514         */
1515
1516         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1517         if (rc)
1518                 return rc;
1519         if (b_hw_start) {
1520                 /* enable interrupts */
1521                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1522                 if (rc != ECORE_SUCCESS)
1523                         return rc;
1524
1525                 /* send function start command */
1526                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1527                                        allow_npar_tx_switch);
1528                 if (rc) {
1529                         DP_NOTICE(p_hwfn, true,
1530                                   "Function start ramrod failed\n");
1531                 } else {
1532                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1533                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1534                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1535
1536                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1537                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1538                                          (1 << 2));
1539                                 ecore_wr(p_hwfn, p_ptt,
1540                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1541                                     0x100);
1542                         }
1543                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1544                                    "PRS_REG_SEARCH registers after start PFn\n");
1545                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1546                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1547                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1548                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1549                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1550                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1551                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1552                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1553                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1554                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1555                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1556                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1557                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1558                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1559                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1560                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1561                                    prs_reg);
1562                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1563                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1564                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1565                 }
1566         }
1567         return rc;
1568 }
1569
1570 static enum _ecore_status_t
1571 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1572                       struct ecore_ptt *p_ptt, u8 enable)
1573 {
1574         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1575
1576         /* Change PF in PXP */
1577         ecore_wr(p_hwfn, p_ptt,
1578                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1579
1580         /* wait until value is set - try for 1 second every 50us */
1581         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1582                 val = ecore_rd(p_hwfn, p_ptt,
1583                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1584                 if (val == set_val)
1585                         break;
1586
1587                 OSAL_UDELAY(50);
1588         }
1589
1590         if (val != set_val) {
1591                 DP_NOTICE(p_hwfn, true,
1592                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1593                 return ECORE_UNKNOWN_ERROR;
1594         }
1595
1596         return ECORE_SUCCESS;
1597 }
1598
1599 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1600                                   struct ecore_ptt *p_main_ptt)
1601 {
1602         /* Read shadow of current MFW mailbox */
1603         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1604         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1605                     p_hwfn->mcp_info->mfw_mb_cur,
1606                     p_hwfn->mcp_info->mfw_mb_length);
1607 }
1608
1609 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1610                                    struct ecore_hw_init_params *p_params)
1611 {
1612         enum _ecore_status_t rc, mfw_rc;
1613         u32 load_code, param;
1614         int i;
1615
1616         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1617             (p_dev->num_hwfns > 1)) {
1618                 DP_NOTICE(p_dev, false,
1619                           "MSI mode is not supported for CMT devices\n");
1620                 return ECORE_INVAL;
1621         }
1622
1623         if (IS_PF(p_dev)) {
1624                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1625                 if (rc != ECORE_SUCCESS)
1626                         return rc;
1627         }
1628
1629         for_each_hwfn(p_dev, i) {
1630                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1631
1632                 if (IS_VF(p_dev)) {
1633                         p_hwfn->b_int_enabled = 1;
1634                         continue;
1635                 }
1636
1637                 /* Enable DMAE in PXP */
1638                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1639                 if (rc != ECORE_SUCCESS)
1640                         return rc;
1641
1642                 rc = ecore_calc_hw_mode(p_hwfn);
1643                 if (rc != ECORE_SUCCESS)
1644                         return rc;
1645
1646                 /* @@@TBD need to add here:
1647                  * Check for fan failure
1648                  * Prev_unload
1649                  */
1650                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1651                 if (rc) {
1652                         DP_NOTICE(p_hwfn, true,
1653                                   "Failed sending LOAD_REQ command\n");
1654                         return rc;
1655                 }
1656
1657                 /* CQ75580:
1658                  * When coming back from hiberbate state, the registers from
1659                  * which shadow is read initially are not initialized. It turns
1660                  * out that these registers get initialized during the call to
1661                  * ecore_mcp_load_req request. So we need to reread them here
1662                  * to get the proper shadow register value.
1663                  * Note: This is a workaround for the missinginig MFW
1664                  * initialization. It may be removed once the implementation
1665                  * is done.
1666                  */
1667                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1668
1669                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1670                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1671                            rc, load_code);
1672
1673                 /* Only relevant for recovery:
1674                  * Clear the indication after the LOAD_REQ command is responded
1675                  * by the MFW.
1676                  */
1677                 p_dev->recov_in_prog = false;
1678
1679                 p_hwfn->first_on_engine = (load_code ==
1680                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1681
1682                 if (!qm_lock_init) {
1683                         OSAL_SPIN_LOCK_INIT(&qm_lock);
1684                         qm_lock_init = true;
1685                 }
1686
1687                 switch (load_code) {
1688                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1689                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1690                                                   p_hwfn->hw_info.hw_mode);
1691                         if (rc)
1692                                 break;
1693                         /* Fall into */
1694                 case FW_MSG_CODE_DRV_LOAD_PORT:
1695                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1696                                                 p_hwfn->hw_info.hw_mode);
1697                         if (rc)
1698                                 break;
1699                         /* Fall into */
1700                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1701                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1702                                               p_params->p_tunn,
1703                                               p_hwfn->hw_info.hw_mode,
1704                                               p_params->b_hw_start,
1705                                               p_params->int_mode,
1706                                               p_params->allow_npar_tx_switch);
1707                         break;
1708                 default:
1709                         rc = ECORE_NOTIMPL;
1710                         break;
1711                 }
1712
1713                 if (rc != ECORE_SUCCESS)
1714                         DP_NOTICE(p_hwfn, true,
1715                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1716                                   load_code, rc);
1717
1718                 /* ACK mfw regardless of success or failure of initialization */
1719                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1720                                        DRV_MSG_CODE_LOAD_DONE,
1721                                        0, &load_code, &param);
1722                 if (rc != ECORE_SUCCESS)
1723                         return rc;
1724                 if (mfw_rc != ECORE_SUCCESS) {
1725                         DP_NOTICE(p_hwfn, true,
1726                                   "Failed sending LOAD_DONE command\n");
1727                         return mfw_rc;
1728                 }
1729
1730                 /* send DCBX attention request command */
1731                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1732                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1733                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1734                                        DRV_MSG_CODE_SET_DCBX,
1735                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1736                                        &load_code, &param);
1737                 if (mfw_rc != ECORE_SUCCESS) {
1738                         DP_NOTICE(p_hwfn, true,
1739                                   "Failed to send DCBX attention request\n");
1740                         return mfw_rc;
1741                 }
1742
1743                 p_hwfn->hw_init_done = true;
1744         }
1745
1746         return ECORE_SUCCESS;
1747 }
1748
1749 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
1750 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1751                                  struct ecore_hwfn *p_hwfn,
1752                                  struct ecore_ptt *p_ptt)
1753 {
1754         int i;
1755
1756         /* close timers */
1757         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1758         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1759         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1760                                                                         i++) {
1761                 if ((!ecore_rd(p_hwfn, p_ptt,
1762                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1763                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1764                         break;
1765
1766                 /* Dependent on number of connection/tasks, possibly
1767                  * 1ms sleep is required between polls
1768                  */
1769                 OSAL_MSLEEP(1);
1770         }
1771
1772         if (i < ECORE_HW_STOP_RETRY_LIMIT)
1773                 return;
1774
1775         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
1776                   " [Connection %02x Tasks %02x]\n",
1777                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1778                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1779 }
1780
1781 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1782 {
1783         int j;
1784
1785         for_each_hwfn(p_dev, j) {
1786                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1787                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1788
1789                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1790         }
1791 }
1792
1793 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1794 {
1795         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1796         int j;
1797
1798         for_each_hwfn(p_dev, j) {
1799                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1800                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1801
1802                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1803
1804                 if (IS_VF(p_dev)) {
1805                         ecore_vf_pf_int_cleanup(p_hwfn);
1806                         continue;
1807                 }
1808
1809                 /* mark the hw as uninitialized... */
1810                 p_hwfn->hw_init_done = false;
1811
1812                 rc = ecore_sp_pf_stop(p_hwfn);
1813                 if (rc)
1814                         DP_NOTICE(p_hwfn, true,
1815                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1816
1817                 /* perform debug action after PF stop was sent */
1818                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1819
1820                 /* close NIG to BRB gate */
1821                 ecore_wr(p_hwfn, p_ptt,
1822                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1823
1824                 /* close parser */
1825                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1826                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1827                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1828                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1829                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1830
1831                 /* @@@TBD - clean transmission queues (5.b) */
1832                 /* @@@TBD - clean BTB (5.c) */
1833
1834                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1835
1836                 /* @@@TBD - verify DMAE requests are done (8) */
1837
1838                 /* Disable Attention Generation */
1839                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1840                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1841                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1842                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1843                 /* Need to wait 1ms to guarantee SBs are cleared */
1844                 OSAL_MSLEEP(1);
1845         }
1846
1847         if (IS_PF(p_dev)) {
1848                 /* Disable DMAE in PXP - in CMT, this should only be done for
1849                  * first hw-function, and only after all transactions have
1850                  * stopped for all active hw-functions.
1851                  */
1852                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1853                                              p_dev->hwfns[0].p_main_ptt, false);
1854                 if (t_rc != ECORE_SUCCESS)
1855                         rc = t_rc;
1856         }
1857
1858         return rc;
1859 }
1860
1861 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1862 {
1863         int j;
1864
1865         for_each_hwfn(p_dev, j) {
1866                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1867                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1868
1869                 if (IS_VF(p_dev)) {
1870                         ecore_vf_pf_int_cleanup(p_hwfn);
1871                         continue;
1872                 }
1873
1874                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1875                            "Shutting down the fastpath\n");
1876
1877                 ecore_wr(p_hwfn, p_ptt,
1878                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1879
1880                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1881                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1882                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1883                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1884                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1885
1886                 /* @@@TBD - clean transmission queues (5.b) */
1887                 /* @@@TBD - clean BTB (5.c) */
1888
1889                 /* @@@TBD - verify DMAE requests are done (8) */
1890
1891                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1892                 /* Need to wait 1ms to guarantee SBs are cleared */
1893                 OSAL_MSLEEP(1);
1894         }
1895 }
1896
1897 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1898 {
1899         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1900
1901         if (IS_VF(p_hwfn->p_dev))
1902                 return;
1903
1904         /* If roce info is allocated it means roce is initialized and should
1905          * be enabled in searcher.
1906          */
1907         if (p_hwfn->p_rdma_info) {
1908                 if (p_hwfn->b_rdma_enabled_in_prs)
1909                         ecore_wr(p_hwfn, p_ptt,
1910                                  p_hwfn->rdma_prs_search_reg, 0x1);
1911                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1912         }
1913
1914         /* Re-open incoming traffic */
1915         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1916                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1917 }
1918
1919 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1920                                              struct ecore_ptt *p_ptt, u32 reg,
1921                                              bool expected)
1922 {
1923         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1924
1925         if (assert_val != expected) {
1926                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1927                           reg, expected);
1928                 return ECORE_UNKNOWN_ERROR;
1929         }
1930
1931         return 0;
1932 }
1933
1934 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1935 {
1936         enum _ecore_status_t rc = ECORE_SUCCESS;
1937         u32 unload_resp, unload_param;
1938         int i;
1939
1940         for_each_hwfn(p_dev, i) {
1941                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1942
1943                 if (IS_VF(p_dev)) {
1944                         rc = ecore_vf_pf_reset(p_hwfn);
1945                         if (rc)
1946                                 return rc;
1947                         continue;
1948                 }
1949
1950                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1951
1952                 /* Check for incorrect states */
1953                 if (!p_dev->recov_in_prog) {
1954                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1955                                          QM_REG_USG_CNT_PF_TX, 0);
1956                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1957                                          QM_REG_USG_CNT_PF_OTHER, 0);
1958                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
1959                 }
1960
1961                 /* Disable PF in HW blocks */
1962                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1963                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1964
1965                 if (p_dev->recov_in_prog) {
1966                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1967                                    "Recovery is in progress -> skip sending unload_req/done\n");
1968                         break;
1969                 }
1970
1971                 /* Send unload command to MCP */
1972                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1973                                    DRV_MSG_CODE_UNLOAD_REQ,
1974                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
1975                                    &unload_resp, &unload_param);
1976                 if (rc != ECORE_SUCCESS) {
1977                         DP_NOTICE(p_hwfn, true,
1978                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
1979                         /* @@TBD - what to do? for now, assume ENG. */
1980                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1981                 }
1982
1983                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1984                                    DRV_MSG_CODE_UNLOAD_DONE,
1985                                    0, &unload_resp, &unload_param);
1986                 if (rc != ECORE_SUCCESS) {
1987                         DP_NOTICE(p_hwfn,
1988                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
1989                         /* @@@TBD - Should it really ASSERT here ? */
1990                         return rc;
1991                 }
1992         }
1993
1994         return rc;
1995 }
1996
1997 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1998 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
1999 {
2000         ecore_ptt_pool_free(p_hwfn);
2001         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2002 }
2003
2004 /* Setup bar access */
2005 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2006 {
2007         /* clear indirect access */
2008         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2009                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2010                          PGLUE_B_REG_PGL_ADDR_E8_F0, 0);
2011                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2012                          PGLUE_B_REG_PGL_ADDR_EC_F0, 0);
2013                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2014                          PGLUE_B_REG_PGL_ADDR_F0_F0, 0);
2015                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2016                          PGLUE_B_REG_PGL_ADDR_F4_F0, 0);
2017         } else {
2018                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2019                          PGLUE_B_REG_PGL_ADDR_88_F0, 0);
2020                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2021                          PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
2022                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2023                          PGLUE_B_REG_PGL_ADDR_90_F0, 0);
2024                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2025                          PGLUE_B_REG_PGL_ADDR_94_F0, 0);
2026         }
2027
2028         /* Clean Previous errors if such exist */
2029         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2030                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2031
2032         /* enable internal target-read */
2033         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2034                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2035 }
2036
2037 static void get_function_id(struct ecore_hwfn *p_hwfn)
2038 {
2039         /* ME Register */
2040         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2041                                                   PXP_PF_ME_OPAQUE_ADDR);
2042
2043         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2044
2045         /* Bits 16-19 from the ME registers are the pf_num */
2046         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2047         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2048                                       PXP_CONCRETE_FID_PFID);
2049         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2050                                     PXP_CONCRETE_FID_PORT);
2051
2052         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2053                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2054                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2055 }
2056
2057 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2058 {
2059         u32 *feat_num = p_hwfn->hw_info.feat_num;
2060         int num_features = 1;
2061
2062         /* L2 Queues require each: 1 status block. 1 L2 queue */
2063         feat_num[ECORE_PF_L2_QUE] =
2064             OSAL_MIN_T(u32,
2065                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2066                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2067
2068         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2069                    "#PF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2070                    feat_num[ECORE_PF_L2_QUE],
2071                    feat_num[ECORE_RDMA_CNQ],
2072                    RESC_NUM(p_hwfn, ECORE_SB), num_features);
2073 }
2074
2075 static enum resource_id_enum
2076 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2077 {
2078         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2079
2080         switch (res_id) {
2081         case ECORE_SB:
2082                 mfw_res_id = RESOURCE_NUM_SB_E;
2083                 break;
2084         case ECORE_L2_QUEUE:
2085                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2086                 break;
2087         case ECORE_VPORT:
2088                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2089                 break;
2090         case ECORE_RSS_ENG:
2091                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2092                 break;
2093         case ECORE_PQ:
2094                 mfw_res_id = RESOURCE_NUM_PQ_E;
2095                 break;
2096         case ECORE_RL:
2097                 mfw_res_id = RESOURCE_NUM_RL_E;
2098                 break;
2099         case ECORE_MAC:
2100         case ECORE_VLAN:
2101                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2102                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2103                 break;
2104         case ECORE_ILT:
2105                 mfw_res_id = RESOURCE_ILT_E;
2106                 break;
2107         case ECORE_LL2_QUEUE:
2108                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2109                 break;
2110         case ECORE_RDMA_CNQ_RAM:
2111         case ECORE_CMDQS_CQS:
2112                 /* CNQ/CMDQS are the same resource */
2113                 mfw_res_id = RESOURCE_CQS_E;
2114                 break;
2115         case ECORE_RDMA_STATS_QUEUE:
2116                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2117                 break;
2118         default:
2119                 break;
2120         }
2121
2122         return mfw_res_id;
2123 }
2124
2125 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2126                                       enum ecore_resources res_id)
2127 {
2128         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2129         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2130         struct ecore_sb_cnt_info sb_cnt_info;
2131         u32 dflt_resc_num = 0;
2132
2133         switch (res_id) {
2134         case ECORE_SB:
2135                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2136                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2137                 dflt_resc_num = sb_cnt_info.sb_cnt;
2138                 break;
2139         case ECORE_L2_QUEUE:
2140                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2141                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2142                 break;
2143         case ECORE_VPORT:
2144                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2145                                  MAX_NUM_VPORTS_BB) / num_funcs;
2146                 break;
2147         case ECORE_RSS_ENG:
2148                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2149                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2150                 break;
2151         case ECORE_PQ:
2152                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2153                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2154                 break;
2155         case ECORE_RL:
2156                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2157                 break;
2158         case ECORE_MAC:
2159         case ECORE_VLAN:
2160                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2161                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2162                 break;
2163         case ECORE_ILT:
2164                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2165                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2166                 break;
2167         case ECORE_LL2_QUEUE:
2168                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2169                 break;
2170         case ECORE_RDMA_CNQ_RAM:
2171         case ECORE_CMDQS_CQS:
2172                 /* CNQ/CMDQS are the same resource */
2173                 /* @DPDK */
2174                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2175                 break;
2176         case ECORE_RDMA_STATS_QUEUE:
2177                 /* @DPDK */
2178                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2179                                  MAX_NUM_VPORTS_BB) / num_funcs;
2180                 break;
2181         default:
2182                 break;
2183         }
2184
2185         return dflt_resc_num;
2186 }
2187
2188 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2189 {
2190         switch (res_id) {
2191         case ECORE_SB:
2192                 return "SB";
2193         case ECORE_L2_QUEUE:
2194                 return "L2_QUEUE";
2195         case ECORE_VPORT:
2196                 return "VPORT";
2197         case ECORE_RSS_ENG:
2198                 return "RSS_ENG";
2199         case ECORE_PQ:
2200                 return "PQ";
2201         case ECORE_RL:
2202                 return "RL";
2203         case ECORE_MAC:
2204                 return "MAC";
2205         case ECORE_VLAN:
2206                 return "VLAN";
2207         case ECORE_RDMA_CNQ_RAM:
2208                 return "RDMA_CNQ_RAM";
2209         case ECORE_ILT:
2210                 return "ILT";
2211         case ECORE_LL2_QUEUE:
2212                 return "LL2_QUEUE";
2213         case ECORE_CMDQS_CQS:
2214                 return "CMDQS_CQS";
2215         case ECORE_RDMA_STATS_QUEUE:
2216                 return "RDMA_STATS_QUEUE";
2217         default:
2218                 return "UNKNOWN_RESOURCE";
2219         }
2220 }
2221
2222 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2223                                                    enum ecore_resources res_id,
2224                                                    bool drv_resc_alloc)
2225 {
2226         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2227         u32 *p_resc_num, *p_resc_start;
2228         struct resource_info resc_info;
2229         enum _ecore_status_t rc;
2230
2231         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2232         p_resc_start = &RESC_START(p_hwfn, res_id);
2233
2234         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2235         if (!dflt_resc_num) {
2236                 DP_ERR(p_hwfn,
2237                        "Failed to get default amount for resource %d [%s]\n",
2238                         res_id, ecore_hw_get_resc_name(res_id));
2239                 return ECORE_INVAL;
2240         }
2241         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2242
2243 #ifndef ASIC_ONLY
2244         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2245                 *p_resc_num = dflt_resc_num;
2246                 *p_resc_start = dflt_resc_start;
2247                 goto out;
2248         }
2249 #endif
2250
2251         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2252         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2253         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2254                 DP_ERR(p_hwfn,
2255                        "Failed to match resource %d with MFW resources\n",
2256                        res_id);
2257                 return ECORE_INVAL;
2258         }
2259
2260         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2261                                      &mcp_resp, &mcp_param);
2262         if (rc != ECORE_SUCCESS) {
2263                 DP_NOTICE(p_hwfn, true,
2264                           "MFW response failure for an allocation request for"
2265                           " resource %d [%s]\n",
2266                           res_id, ecore_hw_get_resc_name(res_id));
2267                 return rc;
2268         }
2269
2270         /* Default driver values are applied in the following cases:
2271          * - The resource allocation MB command is not supported by the MFW
2272          * - There is an internal error in the MFW while processing the request
2273          * - The resource ID is unknown to the MFW
2274          */
2275         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2276             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2277                 /* @DPDK */
2278                 DP_INFO(p_hwfn,
2279                         "Resource %d [%s]: No allocation info was received"
2280                         " [mcp_resp 0x%x]. Applying default values"
2281                         " [num %d, start %d].\n",
2282                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2283                         dflt_resc_num, dflt_resc_start);
2284
2285                 *p_resc_num = dflt_resc_num;
2286                 *p_resc_start = dflt_resc_start;
2287                 goto out;
2288         }
2289
2290         /* TBD - remove this when revising the handling of the SB resource */
2291         if (res_id == ECORE_SB) {
2292                 /* Excluding the slowpath SB */
2293                 resc_info.size -= 1;
2294                 resc_info.offset -= p_hwfn->enabled_func_idx;
2295         }
2296
2297         *p_resc_num = resc_info.size;
2298         *p_resc_start = resc_info.offset;
2299
2300         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2301                 DP_INFO(p_hwfn,
2302                         "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2303                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2304                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2305                         drv_resc_alloc ? " - Applying default values" : "");
2306                 if (drv_resc_alloc) {
2307                         *p_resc_num = dflt_resc_num;
2308                         *p_resc_start = dflt_resc_start;
2309                 }
2310         }
2311  out:
2312         return ECORE_SUCCESS;
2313 }
2314
2315 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2316                                               bool drv_resc_alloc)
2317 {
2318         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2319         enum _ecore_status_t rc;
2320         u8 res_id;
2321 #ifndef ASIC_ONLY
2322         u32 *resc_start = p_hwfn->hw_info.resc_start;
2323         u32 *resc_num = p_hwfn->hw_info.resc_num;
2324         /* For AH, an equal share of the ILT lines between the maximal number of
2325          * PFs is not enough for RoCE. This would be solved by the future
2326          * resource allocation scheme, but isn't currently present for
2327          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2328          * to work - the BB number of ILT lines divided by its max PFs number.
2329          */
2330         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2331 #endif
2332
2333         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2334                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2335                 if (rc != ECORE_SUCCESS)
2336                         return rc;
2337         }
2338
2339 #ifndef ASIC_ONLY
2340         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2341                 /* Reduced build contains less PQs */
2342                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2343                         resc_num[ECORE_PQ] = 32;
2344                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2345                             p_hwfn->enabled_func_idx;
2346                 }
2347
2348                 /* For AH emulation, since we have a possible maximal number of
2349                  * 16 enabled PFs, in case there are not enough ILT lines -
2350                  * allocate only first PF as RoCE and have all the other ETH
2351                  * only with less ILT lines.
2352                  */
2353                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2354                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2355                                                          resc_num[ECORE_ILT],
2356                                                          roce_min_ilt_lines);
2357         }
2358
2359         /* Correct the common ILT calculation if PF0 has more */
2360         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2361             p_hwfn->p_dev->b_is_emul_full &&
2362             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2363                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2364                     resc_num[ECORE_ILT];
2365 #endif
2366
2367         /* Sanity for ILT */
2368         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2369             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2370                 DP_NOTICE(p_hwfn, true,
2371                           "Can't assign ILT pages [%08x,...,%08x]\n",
2372                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2373                                                                   ECORE_ILT) -
2374                           1);
2375                 return ECORE_INVAL;
2376         }
2377
2378         ecore_hw_set_feat(p_hwfn);
2379
2380         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2381                    "The numbers for each resource are:\n");
2382         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2383                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2384                            ecore_hw_get_resc_name(res_id),
2385                            RESC_NUM(p_hwfn, res_id),
2386                            RESC_START(p_hwfn, res_id));
2387
2388         return ECORE_SUCCESS;
2389 }
2390
2391 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2392                                                   struct ecore_ptt *p_ptt)
2393 {
2394         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2395         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2396         struct ecore_mcp_link_params *link;
2397
2398         /* Read global nvm_cfg address */
2399         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2400
2401         /* Verify MCP has initialized it */
2402         if (!nvm_cfg_addr) {
2403                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2404                 return ECORE_INVAL;
2405         }
2406
2407 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2408
2409         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2410
2411         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2412             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2413                                                        core_cfg);
2414
2415         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2416
2417         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2418                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2419         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2420                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2421                 break;
2422         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2423                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2424                 break;
2425         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2426                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2427                 break;
2428         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2429                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2430                 break;
2431         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2432                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2433                 break;
2434         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2435                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2436                 break;
2437         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2438                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2439                 break;
2440         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2441                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2442                 break;
2443         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2444                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2445                 break;
2446         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2447                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2448                 break;
2449         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2450                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2451                 break;
2452         default:
2453                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2454                           core_cfg);
2455                 break;
2456         }
2457
2458         /* Read DCBX configuration */
2459         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2460                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2461         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2462                              port_cfg_addr +
2463                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2464         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2465                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2466         switch (dcbx_mode) {
2467         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2468                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2469                 break;
2470         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2471                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2472                 break;
2473         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2474                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2475                 break;
2476         default:
2477                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2478         }
2479
2480         /* Read default link configuration */
2481         link = &p_hwfn->mcp_info->link_input;
2482         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2483             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2484         link_temp = ecore_rd(p_hwfn, p_ptt,
2485                              port_cfg_addr +
2486                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2487         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2488         link->speed.advertised_speeds = link_temp;
2489
2490         link_temp = link->speed.advertised_speeds;
2491         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2492
2493         link_temp = ecore_rd(p_hwfn, p_ptt,
2494                              port_cfg_addr +
2495                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2496         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2497                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2498         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2499                 link->speed.autoneg = true;
2500                 break;
2501         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2502                 link->speed.forced_speed = 1000;
2503                 break;
2504         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2505                 link->speed.forced_speed = 10000;
2506                 break;
2507         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2508                 link->speed.forced_speed = 25000;
2509                 break;
2510         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2511                 link->speed.forced_speed = 40000;
2512                 break;
2513         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2514                 link->speed.forced_speed = 50000;
2515                 break;
2516         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2517                 link->speed.forced_speed = 100000;
2518                 break;
2519         default:
2520                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2521         }
2522
2523         p_hwfn->mcp_info->link_capabilities.default_speed =
2524             link->speed.forced_speed;
2525         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2526             link->speed.autoneg;
2527
2528         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2529         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2530         link->pause.autoneg = !!(link_temp &
2531                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2532         link->pause.forced_rx = !!(link_temp &
2533                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2534         link->pause.forced_tx = !!(link_temp &
2535                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2536         link->loopback_mode = 0;
2537
2538         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2539                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2540                    link->speed.forced_speed, link->speed.advertised_speeds,
2541                    link->speed.autoneg, link->pause.autoneg);
2542
2543         /* Read Multi-function information from shmem */
2544         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2545             OFFSETOF(struct nvm_cfg1, glob) +
2546             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2547
2548         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2549
2550         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2551             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2552
2553         switch (mf_mode) {
2554         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2555                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2556                 break;
2557         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2558                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2559                 break;
2560         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2561                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2562                 break;
2563         }
2564         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2565                 p_hwfn->p_dev->mf_mode);
2566
2567         /* Read Multi-function information from shmem */
2568         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2569             OFFSETOF(struct nvm_cfg1, glob) +
2570             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2571
2572         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2573         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2574                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2575                              &p_hwfn->hw_info.device_capabilities);
2576         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2577                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2578                              &p_hwfn->hw_info.device_capabilities);
2579         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2580                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2581                              &p_hwfn->hw_info.device_capabilities);
2582         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2583                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2584                              &p_hwfn->hw_info.device_capabilities);
2585         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2586                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2587                              &p_hwfn->hw_info.device_capabilities);
2588
2589         return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2590 }
2591
2592 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2593                                 struct ecore_ptt *p_ptt)
2594 {
2595         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2596         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2597         struct ecore_dev *p_dev = p_hwfn->p_dev;
2598
2599         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2600
2601         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2602          * in the other bits are selected.
2603          * Bits 1-15 are for functions 1-15, respectively, and their value is
2604          * '0' only for enabled functions (function 0 always exists and
2605          * enabled).
2606          * In case of CMT in BB, only the "even" functions are enabled, and thus
2607          * the number of functions for both hwfns is learnt from the same bits.
2608          */
2609         reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2610
2611         if (reg_function_hide & 0x1) {
2612                 if (ECORE_IS_BB(p_dev)) {
2613                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2614                                 num_funcs = 0;
2615                                 eng_mask = 0xaaaa;
2616                         } else {
2617                                 num_funcs = 1;
2618                                 eng_mask = 0x5554;
2619                         }
2620                 } else {
2621                         num_funcs = 1;
2622                         eng_mask = 0xfffe;
2623                 }
2624
2625                 /* Get the number of the enabled functions on the engine */
2626                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2627                 while (tmp) {
2628                         if (tmp & 0x1)
2629                                 num_funcs++;
2630                         tmp >>= 0x1;
2631                 }
2632
2633                 /* Get the PF index within the enabled functions */
2634                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2635                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2636                 while (tmp) {
2637                         if (tmp & 0x1)
2638                                 enabled_func_idx--;
2639                         tmp >>= 0x1;
2640                 }
2641         }
2642
2643         p_hwfn->num_funcs_on_engine = num_funcs;
2644         p_hwfn->enabled_func_idx = enabled_func_idx;
2645
2646 #ifndef ASIC_ONLY
2647         if (CHIP_REV_IS_FPGA(p_dev)) {
2648                 DP_NOTICE(p_hwfn, false,
2649                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2650                 p_hwfn->num_funcs_on_engine = 4;
2651         }
2652 #endif
2653
2654         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2655                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2656                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2657                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2658 }
2659
2660 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2661                                       struct ecore_ptt *p_ptt)
2662 {
2663         u32 port_mode;
2664
2665 #ifndef ASIC_ONLY
2666         /* Read the port mode */
2667         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2668                 port_mode = 4;
2669         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2670                  (p_hwfn->p_dev->num_hwfns > 1))
2671                 /* In CMT on emulation, assume 1 port */
2672                 port_mode = 1;
2673         else
2674 #endif
2675                 port_mode = ecore_rd(p_hwfn, p_ptt,
2676                                      CNIG_REG_NW_PORT_MODE_BB_B0);
2677
2678         if (port_mode < 3) {
2679                 p_hwfn->p_dev->num_ports_in_engines = 1;
2680         } else if (port_mode <= 5) {
2681                 p_hwfn->p_dev->num_ports_in_engines = 2;
2682         } else {
2683                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2684                           p_hwfn->p_dev->num_ports_in_engines);
2685
2686                 /* Default num_ports_in_engines to something */
2687                 p_hwfn->p_dev->num_ports_in_engines = 1;
2688         }
2689 }
2690
2691 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2692                                       struct ecore_ptt *p_ptt)
2693 {
2694         u32 port;
2695         int i;
2696
2697         p_hwfn->p_dev->num_ports_in_engines = 0;
2698
2699 #ifndef ASIC_ONLY
2700         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2701                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2702                 switch ((port & 0xf000) >> 12) {
2703                 case 1:
2704                         p_hwfn->p_dev->num_ports_in_engines = 1;
2705                         break;
2706                 case 3:
2707                         p_hwfn->p_dev->num_ports_in_engines = 2;
2708                         break;
2709                 case 0xf:
2710                         p_hwfn->p_dev->num_ports_in_engines = 4;
2711                         break;
2712                 default:
2713                         DP_NOTICE(p_hwfn, false,
2714                                   "Unknown port mode in ECO_RESERVED %08x\n",
2715                                   port);
2716                 }
2717         } else
2718 #endif
2719                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2720                         port = ecore_rd(p_hwfn, p_ptt,
2721                                         CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2722                         if (port & 1)
2723                                 p_hwfn->p_dev->num_ports_in_engines++;
2724                 }
2725 }
2726
2727 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2728                                    struct ecore_ptt *p_ptt)
2729 {
2730         if (ECORE_IS_BB(p_hwfn->p_dev))
2731                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2732         else
2733                 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2734 }
2735
2736 static enum _ecore_status_t
2737 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2738                   enum ecore_pci_personality personality, bool drv_resc_alloc)
2739 {
2740         enum _ecore_status_t rc;
2741
2742         /* Since all information is common, only first hwfns should do this */
2743         if (IS_LEAD_HWFN(p_hwfn)) {
2744                 rc = ecore_iov_hw_info(p_hwfn);
2745                 if (rc != ECORE_SUCCESS)
2746                         return rc;
2747         }
2748
2749         /* TODO In get_hw_info, amoungst others:
2750          * Get MCP FW revision and determine according to it the supported
2751          * featrues (e.g. DCB)
2752          * Get boot mode
2753          * ecore_get_pcie_width_speed, WOL capability.
2754          * Number of global CQ-s (for storage
2755          */
2756         ecore_hw_info_port_num(p_hwfn, p_ptt);
2757
2758 #ifndef ASIC_ONLY
2759         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
2760 #endif
2761         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2762         if (rc != ECORE_SUCCESS)
2763                 return rc;
2764 #ifndef ASIC_ONLY
2765         }
2766 #endif
2767
2768         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2769         if (rc != ECORE_SUCCESS)
2770                 return rc;
2771
2772 #ifndef ASIC_ONLY
2773         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2774 #endif
2775                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2776                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2777 #ifndef ASIC_ONLY
2778         } else {
2779                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2780
2781                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2782                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2783         }
2784 #endif
2785
2786         if (ecore_mcp_is_init(p_hwfn)) {
2787                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2788                         p_hwfn->hw_info.ovlan =
2789                             p_hwfn->mcp_info->func_info.ovlan;
2790
2791                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2792         }
2793
2794         if (personality != ECORE_PCI_DEFAULT) {
2795                 p_hwfn->hw_info.personality = personality;
2796         } else if (ecore_mcp_is_init(p_hwfn)) {
2797                 enum ecore_pci_personality protocol;
2798
2799                 protocol = p_hwfn->mcp_info->func_info.protocol;
2800                 p_hwfn->hw_info.personality = protocol;
2801         }
2802
2803 #ifndef ASIC_ONLY
2804         /* To overcome ILT lack for emulation, until at least until we'll have
2805          * a definite answer from system about it, allow only PF0 to be RoCE.
2806          */
2807         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2808                 if (!p_hwfn->rel_pf_id)
2809                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2810                 else
2811                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2812         }
2813 #endif
2814
2815         /* although in BB some constellations may support more than 4 tcs,
2816          * that can result in performance penalty in some cases. 4
2817          * represents a good tradeoff between performance and flexibility.
2818          */
2819         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2820
2821         /* start out with a single active tc. This can be increased either
2822          * by dcbx negotiation or by upper layer driver
2823          */
2824         p_hwfn->hw_info.num_active_tc = 1;
2825
2826         ecore_get_num_funcs(p_hwfn, p_ptt);
2827
2828         /* In case of forcing the driver's default resource allocation, calling
2829          * ecore_hw_get_resc() should come after initializing the personality
2830          * and after getting the number of functions, since the calculation of
2831          * the resources/features depends on them.
2832          * This order is not harmful if not forcing.
2833          */
2834         return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2835 }
2836
2837 #define ECORE_DEV_ID_MASK       0xff00
2838 #define ECORE_DEV_ID_MASK_BB    0x1600
2839 #define ECORE_DEV_ID_MASK_AH    0x8000
2840
2841 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2842 {
2843         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2844         u32 tmp;
2845
2846         /* Read Vendor Id / Device Id */
2847         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2848                                   &p_dev->vendor_id);
2849         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2850                                   &p_dev->device_id);
2851
2852         /* Determine type */
2853         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2854                 p_dev->type = ECORE_DEV_TYPE_AH;
2855         else
2856                 p_dev->type = ECORE_DEV_TYPE_BB;
2857
2858         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2859                                          MISCS_REG_CHIP_NUM);
2860         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2861                                          MISCS_REG_CHIP_REV);
2862
2863         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2864
2865         /* Learn number of HW-functions */
2866         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2867                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
2868
2869         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2870                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2871                 p_dev->num_hwfns = 2;
2872         } else {
2873                 p_dev->num_hwfns = 1;
2874         }
2875
2876 #ifndef ASIC_ONLY
2877         if (CHIP_REV_IS_EMUL(p_dev)) {
2878                 /* For some reason we have problems with this register
2879                  * in B0 emulation; Simply assume no CMT
2880                  */
2881                 DP_NOTICE(p_dev->hwfns, false,
2882                           "device on emul - assume no CMT\n");
2883                 p_dev->num_hwfns = 1;
2884         }
2885 #endif
2886
2887         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2888                                        MISCS_REG_CHIP_TEST_REG) >> 4;
2889         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2890         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2891                                            MISCS_REG_CHIP_METAL);
2892         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2893         DP_INFO(p_dev->hwfns,
2894                 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2895                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2896                 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2897                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2898                 p_dev->chip_metal);
2899
2900         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2901                 DP_NOTICE(p_dev->hwfns, false,
2902                           "The chip type/rev (BB A0) is not supported!\n");
2903                 return ECORE_ABORTED;
2904         }
2905 #ifndef ASIC_ONLY
2906         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2907                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2908                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2909
2910         if (CHIP_REV_IS_EMUL(p_dev)) {
2911                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2912                                MISCS_REG_ECO_RESERVED);
2913                 if (tmp & (1 << 29)) {
2914                         DP_NOTICE(p_hwfn, false,
2915                                   "Emulation: Running on a FULL build\n");
2916                         p_dev->b_is_emul_full = true;
2917                 } else {
2918                         DP_NOTICE(p_hwfn, false,
2919                                   "Emulation: Running on a REDUCED build\n");
2920                 }
2921         }
2922 #endif
2923
2924         return ECORE_SUCCESS;
2925 }
2926
2927 #ifndef LINUX_REMOVE
2928 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2929 {
2930         int j;
2931
2932         if (IS_VF(p_dev))
2933                 return;
2934
2935         for_each_hwfn(p_dev, j) {
2936                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2937
2938                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2939                            "Mark hw/fw uninitialized\n");
2940
2941                 p_hwfn->hw_init_done = false;
2942                 p_hwfn->first_on_engine = false;
2943
2944                 ecore_ptt_invalidate(p_hwfn);
2945         }
2946 }
2947 #endif
2948
2949 static enum _ecore_status_t
2950 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
2951                         void OSAL_IOMEM * p_regview,
2952                         void OSAL_IOMEM * p_doorbells,
2953                         struct ecore_hw_prepare_params *p_params)
2954 {
2955         struct ecore_dev *p_dev = p_hwfn->p_dev;
2956         struct ecore_mdump_info mdump_info;
2957         enum _ecore_status_t rc = ECORE_SUCCESS;
2958
2959         /* Split PCI bars evenly between hwfns */
2960         p_hwfn->regview = p_regview;
2961         p_hwfn->doorbells = p_doorbells;
2962
2963         if (IS_VF(p_dev))
2964                 return ecore_vf_hw_prepare(p_hwfn);
2965
2966         /* Validate that chip access is feasible */
2967         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2968                 DP_ERR(p_hwfn,
2969                        "Reading the ME register returns all Fs; Preventing further chip access\n");
2970                 return ECORE_INVAL;
2971         }
2972
2973         get_function_id(p_hwfn);
2974
2975         /* Allocate PTT pool */
2976         rc = ecore_ptt_pool_alloc(p_hwfn);
2977         if (rc) {
2978                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2979                 goto err0;
2980         }
2981
2982         /* Allocate the main PTT */
2983         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2984
2985         /* First hwfn learns basic information, e.g., number of hwfns */
2986         if (!p_hwfn->my_id) {
2987                 rc = ecore_get_dev_info(p_dev);
2988                 if (rc != ECORE_SUCCESS)
2989                         goto err1;
2990         }
2991
2992         ecore_hw_hwfn_prepare(p_hwfn);
2993
2994         /* Initialize MCP structure */
2995         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2996         if (rc) {
2997                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
2998                 goto err1;
2999         }
3000
3001         /* Read the device configuration information from the HW and SHMEM */
3002         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3003                                p_params->personality, p_params->drv_resc_alloc);
3004         if (rc) {
3005                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3006                 goto err2;
3007         }
3008
3009         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3010          * called, since among others it sets the ports number in an engine.
3011          */
3012         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3013             !p_dev->recov_in_prog) {
3014                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3015                 if (rc != ECORE_SUCCESS)
3016                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3017         }
3018
3019         /* Check if mdump logs are present and update the epoch value */
3020         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3021                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3022                                               &mdump_info);
3023                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3024                         DP_NOTICE(p_hwfn, false,
3025                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3026                 }
3027
3028                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3029                                            p_params->epoch);
3030         }
3031
3032         /* Allocate the init RT array and initialize the init-ops engine */
3033         rc = ecore_init_alloc(p_hwfn);
3034         if (rc) {
3035                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3036                 goto err2;
3037         }
3038 #ifndef ASIC_ONLY
3039         if (CHIP_REV_IS_FPGA(p_dev)) {
3040                 DP_NOTICE(p_hwfn, false,
3041                           "FPGA: workaround; Prevent DMAE parities\n");
3042                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
3043
3044                 DP_NOTICE(p_hwfn, false,
3045                           "FPGA: workaround: Set VF bar0 size\n");
3046                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3047                          PGLUE_B_REG_VF_BAR0_SIZE, 4);
3048         }
3049 #endif
3050
3051         return rc;
3052  err2:
3053         if (IS_LEAD_HWFN(p_hwfn))
3054                 ecore_iov_free_hw_info(p_dev);
3055         ecore_mcp_free(p_hwfn);
3056  err1:
3057         ecore_hw_hwfn_free(p_hwfn);
3058  err0:
3059         return rc;
3060 }
3061
3062 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3063                                       struct ecore_hw_prepare_params *p_params)
3064 {
3065         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3066         enum _ecore_status_t rc;
3067
3068         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3069
3070         /* Store the precompiled init data ptrs */
3071         if (IS_PF(p_dev))
3072                 ecore_init_iro_array(p_dev);
3073
3074         /* Initialize the first hwfn - will learn number of hwfns */
3075         rc = ecore_hw_prepare_single(p_hwfn,
3076                                      p_dev->regview,
3077                                      p_dev->doorbells, p_params);
3078         if (rc != ECORE_SUCCESS)
3079                 return rc;
3080
3081         p_params->personality = p_hwfn->hw_info.personality;
3082
3083         /* initilalize 2nd hwfn if necessary */
3084         if (p_dev->num_hwfns > 1) {
3085                 void OSAL_IOMEM *p_regview, *p_doorbell;
3086                 u8 OSAL_IOMEM *addr;
3087
3088                 /* adjust bar offset for second engine */
3089                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3090                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3091                 p_regview = (void OSAL_IOMEM *)addr;
3092
3093                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3094                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3095                 p_doorbell = (void OSAL_IOMEM *)addr;
3096
3097                 /* prepare second hw function */
3098                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3099                                              p_doorbell, p_params);
3100
3101                 /* in case of error, need to free the previously
3102                  * initiliazed hwfn 0.
3103                  */
3104                 if (rc != ECORE_SUCCESS) {
3105                         if (IS_PF(p_dev)) {
3106                                 ecore_init_free(p_hwfn);
3107                                 ecore_mcp_free(p_hwfn);
3108                                 ecore_hw_hwfn_free(p_hwfn);
3109                         } else {
3110                                 DP_NOTICE(p_dev, true,
3111                                           "What do we need to free when VF hwfn1 init fails\n");
3112                         }
3113                         return rc;
3114                 }
3115         }
3116
3117         return rc;
3118 }
3119
3120 void ecore_hw_remove(struct ecore_dev *p_dev)
3121 {
3122         int i;
3123
3124         for_each_hwfn(p_dev, i) {
3125                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3126
3127                 if (IS_VF(p_dev)) {
3128                         ecore_vf_pf_release(p_hwfn);
3129                         continue;
3130                 }
3131
3132                 ecore_init_free(p_hwfn);
3133                 ecore_hw_hwfn_free(p_hwfn);
3134                 ecore_mcp_free(p_hwfn);
3135
3136                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3137         }
3138
3139         ecore_iov_free_hw_info(p_dev);
3140 }
3141
3142 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3143                                       struct ecore_chain *p_chain)
3144 {
3145         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3146         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3147         struct ecore_chain_next *p_next;
3148         u32 size, i;
3149
3150         if (!p_virt)
3151                 return;
3152
3153         size = p_chain->elem_size * p_chain->usable_per_page;
3154
3155         for (i = 0; i < p_chain->page_cnt; i++) {
3156                 if (!p_virt)
3157                         break;
3158
3159                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3160                 p_virt_next = p_next->next_virt;
3161                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3162
3163                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3164                                        ECORE_CHAIN_PAGE_SIZE);
3165
3166                 p_virt = p_virt_next;
3167                 p_phys = p_phys_next;
3168         }
3169 }
3170
3171 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3172                                     struct ecore_chain *p_chain)
3173 {
3174         if (!p_chain->p_virt_addr)
3175                 return;
3176
3177         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3178                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3179 }
3180
3181 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3182                                  struct ecore_chain *p_chain)
3183 {
3184         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3185         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3186         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3187
3188         if (!pp_virt_addr_tbl)
3189                 return;
3190
3191         if (!p_chain->pbl.p_virt_table)
3192                 goto out;
3193
3194         for (i = 0; i < page_cnt; i++) {
3195                 if (!pp_virt_addr_tbl[i])
3196                         break;
3197
3198                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3199                                        *(dma_addr_t *)p_pbl_virt,
3200                                        ECORE_CHAIN_PAGE_SIZE);
3201
3202                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3203         }
3204
3205         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3206
3207         if (!p_chain->pbl.external)
3208                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3209                                        p_chain->pbl.p_phys_table, pbl_size);
3210  out:
3211         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3212 }
3213
3214 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3215 {
3216         switch (p_chain->mode) {
3217         case ECORE_CHAIN_MODE_NEXT_PTR:
3218                 ecore_chain_free_next_ptr(p_dev, p_chain);
3219                 break;
3220         case ECORE_CHAIN_MODE_SINGLE:
3221                 ecore_chain_free_single(p_dev, p_chain);
3222                 break;
3223         case ECORE_CHAIN_MODE_PBL:
3224                 ecore_chain_free_pbl(p_dev, p_chain);
3225                 break;
3226         }
3227 }
3228
3229 static enum _ecore_status_t
3230 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3231                                enum ecore_chain_cnt_type cnt_type,
3232                                osal_size_t elem_size, u32 page_cnt)
3233 {
3234         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3235
3236         /* The actual chain size can be larger than the maximal possible value
3237          * after rounding up the requested elements number to pages, and after
3238          * taking into acount the unusuable elements (next-ptr elements).
3239          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3240          * size/capacity fields are of a u32 type.
3241          */
3242         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3243              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3244             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3245              chain_size > ECORE_U32_MAX)) {
3246                 DP_NOTICE(p_dev, true,
3247                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3248                           (unsigned long)chain_size);
3249                 return ECORE_INVAL;
3250         }
3251
3252         return ECORE_SUCCESS;
3253 }
3254
3255 static enum _ecore_status_t
3256 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3257 {
3258         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3259         dma_addr_t p_phys = 0;
3260         u32 i;
3261
3262         for (i = 0; i < p_chain->page_cnt; i++) {
3263                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3264                                                  ECORE_CHAIN_PAGE_SIZE);
3265                 if (!p_virt) {
3266                         DP_NOTICE(p_dev, true,
3267                                   "Failed to allocate chain memory\n");
3268                         return ECORE_NOMEM;
3269                 }
3270
3271                 if (i == 0) {
3272                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3273                         ecore_chain_reset(p_chain);
3274                 } else {
3275                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3276                                                        p_virt, p_phys);
3277                 }
3278
3279                 p_virt_prev = p_virt;
3280         }
3281         /* Last page's next element should point to the beginning of the
3282          * chain.
3283          */
3284         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3285                                        p_chain->p_virt_addr,
3286                                        p_chain->p_phys_addr);
3287
3288         return ECORE_SUCCESS;
3289 }
3290
3291 static enum _ecore_status_t
3292 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3293 {
3294         dma_addr_t p_phys = 0;
3295         void *p_virt = OSAL_NULL;
3296
3297         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3298         if (!p_virt) {
3299                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3300                 return ECORE_NOMEM;
3301         }
3302
3303         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3304         ecore_chain_reset(p_chain);
3305
3306         return ECORE_SUCCESS;
3307 }
3308
3309 static enum _ecore_status_t
3310 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3311                       struct ecore_chain *p_chain,
3312                       struct ecore_chain_ext_pbl *ext_pbl)
3313 {
3314         void *p_virt = OSAL_NULL;
3315         u8 *p_pbl_virt = OSAL_NULL;
3316         void **pp_virt_addr_tbl = OSAL_NULL;
3317         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3318         u32 page_cnt = p_chain->page_cnt, size, i;
3319
3320         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3321         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3322         if (!pp_virt_addr_tbl) {
3323                 DP_NOTICE(p_dev, true,
3324                           "Failed to allocate memory for the chain virtual addresses table\n");
3325                 return ECORE_NOMEM;
3326         }
3327         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3328
3329         /* The allocation of the PBL table is done with its full size, since it
3330          * is expected to be successive.
3331          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3332          * failure, since pp_virt_addr_tbl was previously allocated, and it
3333          * should be saved to allow its freeing during the error flow.
3334          */
3335         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3336
3337         if (ext_pbl == OSAL_NULL) {
3338                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3339         } else {
3340                 p_pbl_virt = ext_pbl->p_pbl_virt;
3341                 p_pbl_phys = ext_pbl->p_pbl_phys;
3342                 p_chain->pbl.external = true;
3343         }
3344
3345         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3346                                  pp_virt_addr_tbl);
3347         if (!p_pbl_virt) {
3348                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3349                 return ECORE_NOMEM;
3350         }
3351
3352         for (i = 0; i < page_cnt; i++) {
3353                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3354                                                  ECORE_CHAIN_PAGE_SIZE);
3355                 if (!p_virt) {
3356                         DP_NOTICE(p_dev, true,
3357                                   "Failed to allocate chain memory\n");
3358                         return ECORE_NOMEM;
3359                 }
3360
3361                 if (i == 0) {
3362                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3363                         ecore_chain_reset(p_chain);
3364                 }
3365
3366                 /* Fill the PBL table with the physical address of the page */
3367                 *(dma_addr_t *)p_pbl_virt = p_phys;
3368                 /* Keep the virtual address of the page */
3369                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3370
3371                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3372         }
3373
3374         return ECORE_SUCCESS;
3375 }
3376
3377 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3378                                        enum ecore_chain_use_mode intended_use,
3379                                        enum ecore_chain_mode mode,
3380                                        enum ecore_chain_cnt_type cnt_type,
3381                                        u32 num_elems, osal_size_t elem_size,
3382                                        struct ecore_chain *p_chain,
3383                                        struct ecore_chain_ext_pbl *ext_pbl)
3384 {
3385         u32 page_cnt;
3386         enum _ecore_status_t rc = ECORE_SUCCESS;
3387
3388         if (mode == ECORE_CHAIN_MODE_SINGLE)
3389                 page_cnt = 1;
3390         else
3391                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3392
3393         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3394                                             page_cnt);
3395         if (rc) {
3396                 DP_NOTICE(p_dev, true,
3397                           "Cannot allocate a chain with the given arguments:\n"
3398                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3399                           intended_use, mode, cnt_type, num_elems, elem_size);
3400                 return rc;
3401         }
3402
3403         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3404                                 mode, cnt_type, p_dev->dp_ctx);
3405
3406         switch (mode) {
3407         case ECORE_CHAIN_MODE_NEXT_PTR:
3408                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3409                 break;
3410         case ECORE_CHAIN_MODE_SINGLE:
3411                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3412                 break;
3413         case ECORE_CHAIN_MODE_PBL:
3414                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3415                 break;
3416         }
3417         if (rc)
3418                 goto nomem;
3419
3420         return ECORE_SUCCESS;
3421
3422  nomem:
3423         ecore_chain_free(p_dev, p_chain);
3424         return rc;
3425 }
3426
3427 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3428                                        u16 src_id, u16 *dst_id)
3429 {
3430         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3431                 u16 min, max;
3432
3433                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3434                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3435                 DP_NOTICE(p_hwfn, true,
3436                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3437                           src_id, min, max);
3438
3439                 return ECORE_INVAL;
3440         }
3441
3442         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3443
3444         return ECORE_SUCCESS;
3445 }
3446
3447 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3448                                     u8 src_id, u8 *dst_id)
3449 {
3450         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3451                 u8 min, max;
3452
3453                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3454                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3455                 DP_NOTICE(p_hwfn, true,
3456                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3457                           src_id, min, max);
3458
3459                 return ECORE_INVAL;
3460         }
3461
3462         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3463
3464         return ECORE_SUCCESS;
3465 }
3466
3467 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3468                                       u8 src_id, u8 *dst_id)
3469 {
3470         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3471                 u8 min, max;
3472
3473                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3474                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3475                 DP_NOTICE(p_hwfn, true,
3476                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3477                           src_id, min, max);
3478
3479                 return ECORE_INVAL;
3480         }
3481
3482         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3483
3484         return ECORE_SUCCESS;
3485 }
3486
3487 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3488                                               struct ecore_ptt *p_ptt,
3489                                               u8 *p_filter)
3490 {
3491         u32 high, low, en;
3492         int i;
3493
3494         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3495                 return ECORE_SUCCESS;
3496
3497         high = p_filter[1] | (p_filter[0] << 8);
3498         low = p_filter[5] | (p_filter[4] << 8) |
3499             (p_filter[3] << 16) | (p_filter[2] << 24);
3500
3501         /* Find a free entry and utilize it */
3502         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3503                 en = ecore_rd(p_hwfn, p_ptt,
3504                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3505                 if (en)
3506                         continue;
3507                 ecore_wr(p_hwfn, p_ptt,
3508                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3509                          2 * i * sizeof(u32), low);
3510                 ecore_wr(p_hwfn, p_ptt,
3511                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3512                          (2 * i + 1) * sizeof(u32), high);
3513                 ecore_wr(p_hwfn, p_ptt,
3514                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3515                 ecore_wr(p_hwfn, p_ptt,
3516                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3517                          i * sizeof(u32), 0);
3518                 ecore_wr(p_hwfn, p_ptt,
3519                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3520                 break;
3521         }
3522         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3523                 DP_NOTICE(p_hwfn, false,
3524                           "Failed to find an empty LLH filter to utilize\n");
3525                 return ECORE_INVAL;
3526         }
3527
3528         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3529                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3530                    p_filter[0], p_filter[1], p_filter[2],
3531                    p_filter[3], p_filter[4], p_filter[5], i);
3532
3533         return ECORE_SUCCESS;
3534 }
3535
3536 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3537                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3538 {
3539         u32 high, low;
3540         int i;
3541
3542         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3543                 return;
3544
3545         high = p_filter[1] | (p_filter[0] << 8);
3546         low = p_filter[5] | (p_filter[4] << 8) |
3547             (p_filter[3] << 16) | (p_filter[2] << 24);
3548
3549         /* Find the entry and clean it */
3550         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3551                 if (ecore_rd(p_hwfn, p_ptt,
3552                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3553                              2 * i * sizeof(u32)) != low)
3554                         continue;
3555                 if (ecore_rd(p_hwfn, p_ptt,
3556                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3557                              (2 * i + 1) * sizeof(u32)) != high)
3558                         continue;
3559
3560                 ecore_wr(p_hwfn, p_ptt,
3561                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3562                 ecore_wr(p_hwfn, p_ptt,
3563                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3564                          2 * i * sizeof(u32), 0);
3565                 ecore_wr(p_hwfn, p_ptt,
3566                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3567                          (2 * i + 1) * sizeof(u32), 0);
3568                 break;
3569         }
3570         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3571                 DP_NOTICE(p_hwfn, false,
3572                           "Tried to remove a non-configured filter\n");
3573 }
3574
3575 enum _ecore_status_t
3576 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3577                               struct ecore_ptt *p_ptt,
3578                               u16 source_port_or_eth_type,
3579                               u16 dest_port,
3580                               enum ecore_llh_port_filter_type_t type)
3581 {
3582         u32 high, low, en;
3583         int i;
3584
3585         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3586                 return ECORE_SUCCESS;
3587
3588         high = 0;
3589         low = 0;
3590         switch (type) {
3591         case ECORE_LLH_FILTER_ETHERTYPE:
3592                 high = source_port_or_eth_type;
3593                 break;
3594         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3595         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3596                 low = source_port_or_eth_type << 16;
3597                 break;
3598         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3599         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3600                 low = dest_port;
3601                 break;
3602         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3603         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3604                 low = (source_port_or_eth_type << 16) | dest_port;
3605                 break;
3606         default:
3607                 DP_NOTICE(p_hwfn, true,
3608                           "Non valid LLH protocol filter type %d\n", type);
3609                 return ECORE_INVAL;
3610         }
3611         /* Find a free entry and utilize it */
3612         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3613                 en = ecore_rd(p_hwfn, p_ptt,
3614                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3615                 if (en)
3616                         continue;
3617                 ecore_wr(p_hwfn, p_ptt,
3618                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3619                          2 * i * sizeof(u32), low);
3620                 ecore_wr(p_hwfn, p_ptt,
3621                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3622                          (2 * i + 1) * sizeof(u32), high);
3623                 ecore_wr(p_hwfn, p_ptt,
3624                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3625                 ecore_wr(p_hwfn, p_ptt,
3626                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3627                          i * sizeof(u32), 1 << type);
3628                 ecore_wr(p_hwfn, p_ptt,
3629                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3630                 break;
3631         }
3632         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3633                 DP_NOTICE(p_hwfn, false,
3634                           "Failed to find an empty LLH filter to utilize\n");
3635                 return ECORE_NORESOURCES;
3636         }
3637         switch (type) {
3638         case ECORE_LLH_FILTER_ETHERTYPE:
3639                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3640                            "ETH type %x is added at %d\n",
3641                            source_port_or_eth_type, i);
3642                 break;
3643         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3644                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3645                            "TCP src port %x is added at %d\n",
3646                            source_port_or_eth_type, i);
3647                 break;
3648         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3649                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3650                            "UDP src port %x is added at %d\n",
3651                            source_port_or_eth_type, i);
3652                 break;
3653         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3654                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3655                            "TCP dst port %x is added at %d\n", dest_port, i);
3656                 break;
3657         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3658                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3659                            "UDP dst port %x is added at %d\n", dest_port, i);
3660                 break;
3661         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3662                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3663                            "TCP src/dst ports %x/%x are added at %d\n",
3664                            source_port_or_eth_type, dest_port, i);
3665                 break;
3666         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3667                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3668                            "UDP src/dst ports %x/%x are added at %d\n",
3669                            source_port_or_eth_type, dest_port, i);
3670                 break;
3671         }
3672         return ECORE_SUCCESS;
3673 }
3674
3675 void
3676 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3677                                  struct ecore_ptt *p_ptt,
3678                                  u16 source_port_or_eth_type,
3679                                  u16 dest_port,
3680                                  enum ecore_llh_port_filter_type_t type)
3681 {
3682         u32 high, low;
3683         int i;
3684
3685         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3686                 return;
3687
3688         high = 0;
3689         low = 0;
3690         switch (type) {
3691         case ECORE_LLH_FILTER_ETHERTYPE:
3692                 high = source_port_or_eth_type;
3693                 break;
3694         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3695         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3696                 low = source_port_or_eth_type << 16;
3697                 break;
3698         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3699         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3700                 low = dest_port;
3701                 break;
3702         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3703         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3704                 low = (source_port_or_eth_type << 16) | dest_port;
3705                 break;
3706         default:
3707                 DP_NOTICE(p_hwfn, true,
3708                           "Non valid LLH protocol filter type %d\n", type);
3709                 return;
3710         }
3711
3712         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3713                 if (!ecore_rd(p_hwfn, p_ptt,
3714                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3715                         continue;
3716                 if (!ecore_rd(p_hwfn, p_ptt,
3717                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3718                         continue;
3719                 if (!(ecore_rd(p_hwfn, p_ptt,
3720                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3721                                i * sizeof(u32)) & (1 << type)))
3722                         continue;
3723                 if (ecore_rd(p_hwfn, p_ptt,
3724                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3725                              2 * i * sizeof(u32)) != low)
3726                         continue;
3727                 if (ecore_rd(p_hwfn, p_ptt,
3728                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3729                              (2 * i + 1) * sizeof(u32)) != high)
3730                         continue;
3731
3732                 ecore_wr(p_hwfn, p_ptt,
3733                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3734                 ecore_wr(p_hwfn, p_ptt,
3735                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3736                 ecore_wr(p_hwfn, p_ptt,
3737                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3738                          i * sizeof(u32), 0);
3739                 ecore_wr(p_hwfn, p_ptt,
3740                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3741                          2 * i * sizeof(u32), 0);
3742                 ecore_wr(p_hwfn, p_ptt,
3743                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3744                          (2 * i + 1) * sizeof(u32), 0);
3745                 break;
3746         }
3747
3748         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3749                 DP_NOTICE(p_hwfn, false,
3750                           "Tried to remove a non-configured filter\n");
3751 }
3752
3753 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3754                                  struct ecore_ptt *p_ptt)
3755 {
3756         int i;
3757
3758         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3759                 return;
3760
3761         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3762                 ecore_wr(p_hwfn, p_ptt,
3763                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3764                 ecore_wr(p_hwfn, p_ptt,
3765                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3766                          2 * i * sizeof(u32), 0);
3767                 ecore_wr(p_hwfn, p_ptt,
3768                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3769                          (2 * i + 1) * sizeof(u32), 0);
3770         }
3771 }
3772
3773 enum _ecore_status_t
3774 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3775                                   struct ecore_ptt *p_ptt)
3776 {
3777         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3778                 ecore_wr(p_hwfn, p_ptt,
3779                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3780                          1 << p_hwfn->abs_pf_id / 2);
3781                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3782                 return ECORE_SUCCESS;
3783         }
3784
3785         DP_NOTICE(p_hwfn, false,
3786                   "This function can't be set as default\n");
3787         return ECORE_INVAL;
3788 }
3789
3790 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3791                                                struct ecore_ptt *p_ptt,
3792                                                u32 hw_addr, void *p_eth_qzone,
3793                                                osal_size_t eth_qzone_size,
3794                                                u8 timeset)
3795 {
3796         struct coalescing_timeset *p_coal_timeset;
3797
3798         if (IS_VF(p_hwfn->p_dev)) {
3799                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3800                 return ECORE_INVAL;
3801         }
3802
3803         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3804                 DP_NOTICE(p_hwfn, true,
3805                           "Coalescing configuration not enabled\n");
3806                 return ECORE_INVAL;
3807         }
3808
3809         p_coal_timeset = p_eth_qzone;
3810         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3811         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3812         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3813         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3814
3815         return ECORE_SUCCESS;
3816 }
3817
3818 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3819                                             struct ecore_ptt *p_ptt,
3820                                             u16 coalesce, u8 qid, u16 sb_id)
3821 {
3822         struct ustorm_eth_queue_zone eth_qzone;
3823         u8 timeset, timer_res;
3824         u16 fw_qid = 0;
3825         u32 address;
3826         enum _ecore_status_t rc;
3827
3828         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3829         if (coalesce <= 0x7F) {
3830                 timer_res = 0;
3831         } else if (coalesce <= 0xFF) {
3832                 timer_res = 1;
3833         } else if (coalesce <= 0x1FF) {
3834                 timer_res = 2;
3835         } else {
3836                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3837                 return ECORE_INVAL;
3838         }
3839         timeset = (u8)(coalesce >> timer_res);
3840
3841         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3842         if (rc != ECORE_SUCCESS)
3843                 return rc;
3844
3845         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3846         if (rc != ECORE_SUCCESS)
3847                 goto out;
3848
3849         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3850
3851         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3852                                 sizeof(struct ustorm_eth_queue_zone), timeset);
3853         if (rc != ECORE_SUCCESS)
3854                 goto out;
3855
3856         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3857  out:
3858         return rc;
3859 }
3860
3861 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3862                                             struct ecore_ptt *p_ptt,
3863                                             u16 coalesce, u8 qid, u16 sb_id)
3864 {
3865         struct xstorm_eth_queue_zone eth_qzone;
3866         u8 timeset, timer_res;
3867         u16 fw_qid = 0;
3868         u32 address;
3869         enum _ecore_status_t rc;
3870
3871         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3872         if (coalesce <= 0x7F) {
3873                 timer_res = 0;
3874         } else if (coalesce <= 0xFF) {
3875                 timer_res = 1;
3876         } else if (coalesce <= 0x1FF) {
3877                 timer_res = 2;
3878         } else {
3879                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3880                 return ECORE_INVAL;
3881         }
3882
3883         timeset = (u8)(coalesce >> timer_res);
3884
3885         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3886         if (rc != ECORE_SUCCESS)
3887                 return rc;
3888
3889         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3890         if (rc != ECORE_SUCCESS)
3891                 goto out;
3892
3893         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3894
3895         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3896                                 sizeof(struct xstorm_eth_queue_zone), timeset);
3897         if (rc != ECORE_SUCCESS)
3898                 goto out;
3899
3900         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3901  out:
3902         return rc;
3903 }
3904
3905 /* Calculate final WFQ values for all vports and configure it.
3906  * After this configuration each vport must have
3907  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3908  */
3909 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3910                                                struct ecore_ptt *p_ptt,
3911                                                u32 min_pf_rate)
3912 {
3913         struct init_qm_vport_params *vport_params;
3914         int i;
3915
3916         vport_params = p_hwfn->qm_info.qm_vport_params;
3917
3918         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3919                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3920
3921                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3922                     min_pf_rate;
3923                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3924                                      vport_params[i].first_tx_pq_id,
3925                                      vport_params[i].vport_wfq);
3926         }
3927 }
3928
3929 static void
3930 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3931 {
3932         int i;
3933
3934         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3935                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3936 }
3937
3938 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3939                                              struct ecore_ptt *p_ptt,
3940                                              u32 min_pf_rate)
3941 {
3942         struct init_qm_vport_params *vport_params;
3943         int i;
3944
3945         vport_params = p_hwfn->qm_info.qm_vport_params;
3946
3947         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3948                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3949                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3950                                      vport_params[i].first_tx_pq_id,
3951                                      vport_params[i].vport_wfq);
3952         }
3953 }
3954
3955 /* This function performs several validations for WFQ
3956  * configuration and required min rate for a given vport
3957  * 1. req_rate must be greater than one percent of min_pf_rate.
3958  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3959  *    rates to get less than one percent of min_pf_rate.
3960  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3961  */
3962 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3963                                                  u16 vport_id, u32 req_rate,
3964                                                  u32 min_pf_rate)
3965 {
3966         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3967         int non_requested_count = 0, req_count = 0, i, num_vports;
3968
3969         num_vports = p_hwfn->qm_info.num_vports;
3970
3971 /* Accounting for the vports which are configured for WFQ explicitly */
3972
3973         for (i = 0; i < num_vports; i++) {
3974                 u32 tmp_speed;
3975
3976                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3977                         req_count++;
3978                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3979                         total_req_min_rate += tmp_speed;
3980                 }
3981         }
3982
3983         /* Include current vport data as well */
3984         req_count++;
3985         total_req_min_rate += req_rate;
3986         non_requested_count = num_vports - req_count;
3987
3988         /* validate possible error cases */
3989         if (req_rate > min_pf_rate) {
3990                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3991                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3992                            vport_id, req_rate, min_pf_rate);
3993                 return ECORE_INVAL;
3994         }
3995
3996         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
3997                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3998                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3999                            vport_id, req_rate, min_pf_rate);
4000                 return ECORE_INVAL;
4001         }
4002
4003         /* TBD - for number of vports greater than 100 */
4004         if (num_vports > ECORE_WFQ_UNIT) {
4005                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4006                            "Number of vports is greater than %d\n",
4007                            ECORE_WFQ_UNIT);
4008                 return ECORE_INVAL;
4009         }
4010
4011         if (total_req_min_rate > min_pf_rate) {
4012                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4013                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4014                            total_req_min_rate, min_pf_rate);
4015                 return ECORE_INVAL;
4016         }
4017
4018         /* Data left for non requested vports */
4019         total_left_rate = min_pf_rate - total_req_min_rate;
4020         left_rate_per_vp = total_left_rate / non_requested_count;
4021
4022         /* validate if non requested get < 1% of min bw */
4023         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4024                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4025                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4026                            left_rate_per_vp, min_pf_rate);
4027                 return ECORE_INVAL;
4028         }
4029
4030         /* now req_rate for given vport passes all scenarios.
4031          * assign final wfq rates to all vports.
4032          */
4033         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4034         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4035
4036         for (i = 0; i < num_vports; i++) {
4037                 if (p_hwfn->qm_info.wfq_data[i].configured)
4038                         continue;
4039
4040                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4041         }
4042
4043         return ECORE_SUCCESS;
4044 }
4045
4046 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4047                                        struct ecore_ptt *p_ptt,
4048                                        u16 vp_id, u32 rate)
4049 {
4050         struct ecore_mcp_link_state *p_link;
4051         int rc = ECORE_SUCCESS;
4052
4053         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4054
4055         if (!p_link->min_pf_rate) {
4056                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4057                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4058                 return rc;
4059         }
4060
4061         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4062
4063         if (rc == ECORE_SUCCESS)
4064                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4065                                                    p_link->min_pf_rate);
4066         else
4067                 DP_NOTICE(p_hwfn, false,
4068                           "Validation failed while configuring min rate\n");
4069
4070         return rc;
4071 }
4072
4073 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4074                                                    struct ecore_ptt *p_ptt,
4075                                                    u32 min_pf_rate)
4076 {
4077         bool use_wfq = false;
4078         int rc = ECORE_SUCCESS;
4079         u16 i;
4080
4081         /* Validate all pre configured vports for wfq */
4082         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4083                 u32 rate;
4084
4085                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4086                         continue;
4087
4088                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4089                 use_wfq = true;
4090
4091                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4092                 if (rc != ECORE_SUCCESS) {
4093                         DP_NOTICE(p_hwfn, false,
4094                                   "WFQ validation failed while configuring min rate\n");
4095                         break;
4096                 }
4097         }
4098
4099         if (rc == ECORE_SUCCESS && use_wfq)
4100                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4101         else
4102                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4103
4104         return rc;
4105 }
4106
4107 /* Main API for ecore clients to configure vport min rate.
4108  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4109  * rate - Speed in Mbps needs to be assigned to a given vport.
4110  */
4111 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4112 {
4113         int i, rc = ECORE_INVAL;
4114
4115         /* TBD - for multiple hardware functions - that is 100 gig */
4116         if (p_dev->num_hwfns > 1) {
4117                 DP_NOTICE(p_dev, false,
4118                           "WFQ configuration is not supported for this device\n");
4119                 return rc;
4120         }
4121
4122         for_each_hwfn(p_dev, i) {
4123                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4124                 struct ecore_ptt *p_ptt;
4125
4126                 p_ptt = ecore_ptt_acquire(p_hwfn);
4127                 if (!p_ptt)
4128                         return ECORE_TIMEOUT;
4129
4130                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4131
4132                 if (rc != ECORE_SUCCESS) {
4133                         ecore_ptt_release(p_hwfn, p_ptt);
4134                         return rc;
4135                 }
4136
4137                 ecore_ptt_release(p_hwfn, p_ptt);
4138         }
4139
4140         return rc;
4141 }
4142
4143 /* API to configure WFQ from mcp link change */
4144 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4145                                            u32 min_pf_rate)
4146 {
4147         int i;
4148
4149         /* TBD - for multiple hardware functions - that is 100 gig */
4150         if (p_dev->num_hwfns > 1) {
4151                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4152                            "WFQ configuration is not supported for this device\n");
4153                 return;
4154         }
4155
4156         for_each_hwfn(p_dev, i) {
4157                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4158
4159                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4160                                                         p_hwfn->p_dpc_ptt,
4161                                                         min_pf_rate);
4162         }
4163 }
4164
4165 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4166                                        struct ecore_ptt *p_ptt,
4167                                        struct ecore_mcp_link_state *p_link,
4168                                        u8 max_bw)
4169 {
4170         int rc = ECORE_SUCCESS;
4171
4172         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4173
4174         if (!p_link->line_speed && (max_bw != 100))
4175                 return rc;
4176
4177         p_link->speed = (p_link->line_speed * max_bw) / 100;
4178         p_hwfn->qm_info.pf_rl = p_link->speed;
4179
4180         /* Since the limiter also affects Tx-switched traffic, we don't want it
4181          * to limit such traffic in case there's no actual limit.
4182          * In that case, set limit to imaginary high boundary.
4183          */
4184         if (max_bw == 100)
4185                 p_hwfn->qm_info.pf_rl = 100000;
4186
4187         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4188                               p_hwfn->qm_info.pf_rl);
4189
4190         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4191                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4192                    p_link->speed);
4193
4194         return rc;
4195 }
4196
4197 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4198 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4199 {
4200         int i, rc = ECORE_INVAL;
4201
4202         if (max_bw < 1 || max_bw > 100) {
4203                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4204                 return rc;
4205         }
4206
4207         for_each_hwfn(p_dev, i) {
4208                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4209                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4210                 struct ecore_mcp_link_state *p_link;
4211                 struct ecore_ptt *p_ptt;
4212
4213                 p_link = &p_lead->mcp_info->link_output;
4214
4215                 p_ptt = ecore_ptt_acquire(p_hwfn);
4216                 if (!p_ptt)
4217                         return ECORE_TIMEOUT;
4218
4219                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4220                                                         p_link, max_bw);
4221
4222                 ecore_ptt_release(p_hwfn, p_ptt);
4223
4224                 if (rc != ECORE_SUCCESS)
4225                         break;
4226         }
4227
4228         return rc;
4229 }
4230
4231 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4232                                        struct ecore_ptt *p_ptt,
4233                                        struct ecore_mcp_link_state *p_link,
4234                                        u8 min_bw)
4235 {
4236         int rc = ECORE_SUCCESS;
4237
4238         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4239         p_hwfn->qm_info.pf_wfq = min_bw;
4240
4241         if (!p_link->line_speed)
4242                 return rc;
4243
4244         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4245
4246         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4247
4248         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4249                    "Configured MIN bandwidth to be %d Mb/sec\n",
4250                    p_link->min_pf_rate);
4251
4252         return rc;
4253 }
4254
4255 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4256 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4257 {
4258         int i, rc = ECORE_INVAL;
4259
4260         if (min_bw < 1 || min_bw > 100) {
4261                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4262                 return rc;
4263         }
4264
4265         for_each_hwfn(p_dev, i) {
4266                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4267                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4268                 struct ecore_mcp_link_state *p_link;
4269                 struct ecore_ptt *p_ptt;
4270
4271                 p_link = &p_lead->mcp_info->link_output;
4272
4273                 p_ptt = ecore_ptt_acquire(p_hwfn);
4274                 if (!p_ptt)
4275                         return ECORE_TIMEOUT;
4276
4277                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4278                                                         p_link, min_bw);
4279                 if (rc != ECORE_SUCCESS) {
4280                         ecore_ptt_release(p_hwfn, p_ptt);
4281                         return rc;
4282                 }
4283
4284                 if (p_link->min_pf_rate) {
4285                         u32 min_rate = p_link->min_pf_rate;
4286
4287                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4288                                                                      p_ptt,
4289                                                                      min_rate);
4290                 }
4291
4292                 ecore_ptt_release(p_hwfn, p_ptt);
4293         }
4294
4295         return rc;
4296 }
4297
4298 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4299 {
4300         struct ecore_mcp_link_state *p_link;
4301
4302         p_link = &p_hwfn->mcp_info->link_output;
4303
4304         if (p_link->min_pf_rate)
4305                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4306                                                  p_link->min_pf_rate);
4307
4308         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4309                     sizeof(*p_hwfn->qm_info.wfq_data) *
4310                     p_hwfn->qm_info.num_vports);
4311 }
4312
4313 int ecore_device_num_engines(struct ecore_dev *p_dev)
4314 {
4315         return ECORE_IS_BB(p_dev) ? 2 : 1;
4316 }
4317
4318 int ecore_device_num_ports(struct ecore_dev *p_dev)
4319 {
4320         /* in CMT always only one port */
4321         if (p_dev->num_hwfns > 1)
4322                 return 1;
4323
4324         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4325 }
4326
4327 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4328                           __le16 *fw_mid,
4329                           __le16 *fw_lsb,
4330                           u8 *mac)
4331 {
4332         ((u8 *)fw_msb)[0] = mac[1];
4333         ((u8 *)fw_msb)[1] = mac[0];
4334         ((u8 *)fw_mid)[0] = mac[3];
4335         ((u8 *)fw_mid)[1] = mac[2];
4336         ((u8 *)fw_lsb)[0] = mac[5];
4337         ((u8 *)fw_lsb)[1] = mac[4];
4338 }