2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_attn_values.h"
33 #include "ecore_dcbx.h"
36 #define ECORE_MIN_DPIS (4) /* The minimal number of DPIs required
37 * load the driver. The number was
42 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
45 BAR_ID_0, /* used for GRC */
46 BAR_ID_1 /* Used for doorbells */
49 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
51 u32 bar_reg = (bar_id == BAR_ID_0 ?
52 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
53 u32 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
55 /* The above registers were updated in the past only in CMT mode. Since
56 * they were found to be useful MFW started updating them from 8.7.7.0.
57 * In older MFW versions they are set to 0 which means disabled.
60 if (p_hwfn->p_dev->num_hwfns > 1) {
61 DP_NOTICE(p_hwfn, false,
62 "BAR size not configured. Assuming BAR"
63 " size of 256kB for GRC and 512kB for DB\n");
64 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
67 DP_NOTICE(p_hwfn, false,
68 "BAR size not configured. Assuming BAR"
69 " size of 512kB for GRC and 512kB for DB\n");
73 return 1 << (val + 15);
76 void ecore_init_dp(struct ecore_dev *p_dev,
77 u32 dp_module, u8 dp_level, void *dp_ctx)
81 p_dev->dp_level = dp_level;
82 p_dev->dp_module = dp_module;
83 p_dev->dp_ctx = dp_ctx;
84 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
85 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
87 p_hwfn->dp_level = dp_level;
88 p_hwfn->dp_module = dp_module;
89 p_hwfn->dp_ctx = dp_ctx;
93 void ecore_init_struct(struct ecore_dev *p_dev)
97 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
98 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
100 p_hwfn->p_dev = p_dev;
102 p_hwfn->b_active = false;
104 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
105 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
108 /* hwfn 0 is always active */
109 p_dev->hwfns[0].b_active = true;
111 /* set the default cache alignment to 128 (may be overridden later) */
112 p_dev->cache_shift = 7;
115 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
117 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
119 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
120 qm_info->qm_pq_params = OSAL_NULL;
121 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
122 qm_info->qm_vport_params = OSAL_NULL;
123 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
124 qm_info->qm_port_params = OSAL_NULL;
125 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
126 qm_info->wfq_data = OSAL_NULL;
129 void ecore_resc_free(struct ecore_dev *p_dev)
136 OSAL_FREE(p_dev, p_dev->fw_data);
137 p_dev->fw_data = OSAL_NULL;
139 OSAL_FREE(p_dev, p_dev->reset_stats);
141 for_each_hwfn(p_dev, i) {
142 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
144 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
145 p_hwfn->p_tx_cids = OSAL_NULL;
146 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
147 p_hwfn->p_rx_cids = OSAL_NULL;
150 for_each_hwfn(p_dev, i) {
151 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
153 ecore_cxt_mngr_free(p_hwfn);
154 ecore_qm_info_free(p_hwfn);
155 ecore_spq_free(p_hwfn);
156 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
157 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
158 ecore_int_free(p_hwfn);
159 ecore_iov_free(p_hwfn);
160 ecore_dmae_info_free(p_hwfn);
161 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
162 /* @@@TBD Flush work-queue ? */
166 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
169 u8 num_vports, vf_offset = 0, i, vport_id, num_ports;
170 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
171 struct init_qm_port_params *p_qm_port;
172 u16 num_pqs, multi_cos_tcs = 1;
173 #ifdef CONFIG_ECORE_SRIOV
174 u16 num_vfs = p_hwfn->p_dev->sriov_info.total_vfs;
179 OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
182 /* @TMP - Don't allocate QM queues for VFs on emulation */
183 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
184 DP_NOTICE(p_hwfn, false,
185 "Emulation - skip configuring QM queues for VFs\n");
190 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
191 num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
193 /* Sanity checking that setup requires legal number of resources */
194 if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
196 "Need too many Physical queues - 0x%04x when"
197 " only %04x are available\n",
198 num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
202 /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
203 * then special queues, then per-VF PQ.
205 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
206 b_sleepable ? GFP_KERNEL :
208 sizeof(struct init_qm_pq_params) *
210 if (!qm_info->qm_pq_params)
213 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
214 b_sleepable ? GFP_KERNEL :
217 init_qm_vport_params) *
219 if (!qm_info->qm_vport_params)
222 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
223 b_sleepable ? GFP_KERNEL :
225 sizeof(struct init_qm_port_params)
227 if (!qm_info->qm_port_params)
230 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
231 b_sleepable ? GFP_KERNEL :
233 sizeof(struct ecore_wfq_data) *
236 if (!qm_info->wfq_data)
239 vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
241 /* First init per-TC PQs */
242 for (i = 0; i < multi_cos_tcs; i++) {
243 struct init_qm_pq_params *params = &qm_info->qm_pq_params[i];
245 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
246 params->vport_id = vport_id;
247 params->tc_id = p_hwfn->hw_info.non_offload_tc;
248 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
250 params->vport_id = vport_id;
251 params->tc_id = p_hwfn->hw_info.offload_tc;
252 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
256 /* Then init pure-LB PQ */
257 qm_info->pure_lb_pq = i;
258 qm_info->qm_pq_params[i].vport_id =
259 (u8)RESC_START(p_hwfn, ECORE_VPORT);
260 qm_info->qm_pq_params[i].tc_id = PURE_LB_TC;
261 qm_info->qm_pq_params[i].wrr_group = 1;
264 /* Then init per-VF PQs */
266 for (i = 0; i < num_vfs; i++) {
267 /* First vport is used by the PF */
268 qm_info->qm_pq_params[vf_offset + i].vport_id = vport_id +
270 qm_info->qm_pq_params[vf_offset + i].tc_id =
271 p_hwfn->hw_info.non_offload_tc;
272 qm_info->qm_pq_params[vf_offset + i].wrr_group = 1;
275 qm_info->vf_queues_offset = vf_offset;
276 qm_info->num_pqs = num_pqs;
277 qm_info->num_vports = num_vports;
279 /* Initialize qm port parameters */
280 num_ports = p_hwfn->p_dev->num_ports_in_engines;
281 for (i = 0; i < num_ports; i++) {
282 p_qm_port = &qm_info->qm_port_params[i];
283 p_qm_port->active = 1;
284 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
285 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
288 if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
289 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
291 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
293 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
295 qm_info->num_vf_pqs = num_vfs;
296 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
298 for (i = 0; i < qm_info->num_vports; i++)
299 qm_info->qm_vport_params[i].vport_wfq = 1;
303 qm_info->vport_rl_en = 1;
304 qm_info->vport_wfq_en = 1;
306 return ECORE_SUCCESS;
309 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
310 ecore_qm_info_free(p_hwfn);
314 /* This function reconfigures the QM pf on the fly.
315 * For this purpose we:
316 * 1. reconfigure the QM database
317 * 2. set new values to runtime arrat
318 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
319 * 4. activate init tool in QM_PF stage
320 * 5. send an sdm_qm_cmd through rbc interface to release the QM
322 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
323 struct ecore_ptt *p_ptt)
325 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
326 enum _ecore_status_t rc;
329 /* qm_info is allocated in ecore_init_qm_info() which is already called
330 * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
331 * The allocated size may change each init, so we free it before next
334 ecore_qm_info_free(p_hwfn);
336 /* initialize ecore's qm data structure */
337 rc = ecore_init_qm_info(p_hwfn, false);
338 if (rc != ECORE_SUCCESS)
341 /* stop PF's qm queues */
342 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
343 qm_info->start_pq, qm_info->num_pqs);
347 /* clear the QM_PF runtime phase leftovers from previous init */
348 ecore_init_clear_rt_data(p_hwfn);
350 /* prepare QM portion of runtime array */
351 ecore_qm_init_pf(p_hwfn);
353 /* activate init tool on runtime array */
354 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
355 p_hwfn->hw_info.hw_mode);
356 if (rc != ECORE_SUCCESS)
359 /* start PF's qm queues */
360 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
361 qm_info->start_pq, qm_info->num_pqs);
365 return ECORE_SUCCESS;
368 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
370 enum _ecore_status_t rc = ECORE_SUCCESS;
371 struct ecore_consq *p_consq;
372 struct ecore_eq *p_eq;
378 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
379 sizeof(struct ecore_fw_data));
383 /* Allocate Memory for the Queue->CID mapping */
384 for_each_hwfn(p_dev, i) {
385 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
387 /* @@@TMP - resc management, change to actual required size */
388 int tx_size = sizeof(struct ecore_hw_cid_data) *
389 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
390 int rx_size = sizeof(struct ecore_hw_cid_data) *
391 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
393 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
395 if (!p_hwfn->p_tx_cids) {
396 DP_NOTICE(p_hwfn, true,
397 "Failed to allocate memory for Tx Cids\n");
401 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
403 if (!p_hwfn->p_rx_cids) {
404 DP_NOTICE(p_hwfn, true,
405 "Failed to allocate memory for Rx Cids\n");
410 for_each_hwfn(p_dev, i) {
411 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
413 /* First allocate the context manager structure */
414 rc = ecore_cxt_mngr_alloc(p_hwfn);
418 /* Set the HW cid/tid numbers (in the contest manager)
419 * Must be done prior to any further computations.
421 rc = ecore_cxt_set_pf_params(p_hwfn);
425 /* Prepare and process QM requirements */
426 rc = ecore_init_qm_info(p_hwfn, true);
430 /* Compute the ILT client partition */
431 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
435 /* CID map / ILT shadow table / T2
436 * The talbes sizes are determined by the computations above
438 rc = ecore_cxt_tables_alloc(p_hwfn);
442 /* SPQ, must follow ILT because initializes SPQ context */
443 rc = ecore_spq_alloc(p_hwfn);
447 /* SP status block allocation */
448 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
451 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
455 rc = ecore_iov_alloc(p_hwfn);
460 p_eq = ecore_eq_alloc(p_hwfn, 256);
465 p_consq = ecore_consq_alloc(p_hwfn);
468 p_hwfn->p_consq = p_consq;
470 /* DMA info initialization */
471 rc = ecore_dmae_info_alloc(p_hwfn);
473 DP_NOTICE(p_hwfn, true,
474 "Failed to allocate memory for"
475 " dmae_info structure\n");
479 /* DCBX initialization */
480 rc = ecore_dcbx_info_alloc(p_hwfn);
482 DP_NOTICE(p_hwfn, true,
483 "Failed to allocate memory for dcbxstruct\n");
488 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
489 sizeof(struct ecore_eth_stats));
490 if (!p_dev->reset_stats) {
491 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
495 return ECORE_SUCCESS;
500 ecore_resc_free(p_dev);
504 void ecore_resc_setup(struct ecore_dev *p_dev)
511 for_each_hwfn(p_dev, i) {
512 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
514 ecore_cxt_mngr_setup(p_hwfn);
515 ecore_spq_setup(p_hwfn);
516 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
517 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
519 /* Read shadow of current MFW mailbox */
520 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
521 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
522 p_hwfn->mcp_info->mfw_mb_cur,
523 p_hwfn->mcp_info->mfw_mb_length);
525 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
527 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
531 #define FINAL_CLEANUP_POLL_CNT (100)
532 #define FINAL_CLEANUP_POLL_TIME (10)
533 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
534 struct ecore_ptt *p_ptt,
537 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
538 enum _ecore_status_t rc = ECORE_TIMEOUT;
541 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
542 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
543 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
544 return ECORE_SUCCESS;
548 addr = GTT_BAR0_MAP_REG_USDM_RAM +
549 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
554 command |= X_FINAL_CLEANUP_AGG_INT <<
555 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
556 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
557 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
558 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
560 /* Make sure notification is not set before initiating final cleanup */
561 if (REG_RD(p_hwfn, addr)) {
562 DP_NOTICE(p_hwfn, false,
563 "Unexpected; Found final cleanup notification "
564 " before initiating final cleanup\n");
565 REG_WR(p_hwfn, addr, 0);
568 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
569 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
570 id, OSAL_CPU_TO_LE32(command));
572 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
573 OSAL_CPU_TO_LE32(command));
575 /* Poll until completion */
576 while (!REG_RD(p_hwfn, addr) && count--)
577 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
579 if (REG_RD(p_hwfn, addr))
582 DP_NOTICE(p_hwfn, true,
583 "Failed to receive FW final cleanup notification\n");
585 /* Cleanup afterwards */
586 REG_WR(p_hwfn, addr, 0);
591 static void ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
595 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
596 hw_mode |= 1 << MODE_BB_A0;
597 } else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
598 hw_mode |= 1 << MODE_BB_B0;
599 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
600 hw_mode |= 1 << MODE_K2;
602 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
603 p_hwfn->p_dev->type);
607 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
608 switch (p_hwfn->p_dev->num_ports_in_engines) {
610 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
613 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
616 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
619 DP_NOTICE(p_hwfn, true,
620 "num_ports_in_engine = %d not supported\n",
621 p_hwfn->p_dev->num_ports_in_engines);
625 switch (p_hwfn->p_dev->mf_mode) {
626 case ECORE_MF_DEFAULT:
628 hw_mode |= 1 << MODE_MF_SI;
631 hw_mode |= 1 << MODE_MF_SD;
634 DP_NOTICE(p_hwfn, true,
635 "Unsupported MF mode, init as DEFAULT\n");
636 hw_mode |= 1 << MODE_MF_SI;
640 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
641 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
642 hw_mode |= 1 << MODE_FPGA;
644 if (p_hwfn->p_dev->b_is_emul_full)
645 hw_mode |= 1 << MODE_EMUL_FULL;
647 hw_mode |= 1 << MODE_EMUL_REDUCED;
651 hw_mode |= 1 << MODE_ASIC;
653 if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn))
654 hw_mode |= 1 << MODE_EAGLE_ENG1_WORKAROUND;
656 if (p_hwfn->p_dev->num_hwfns > 1)
657 hw_mode |= 1 << MODE_100G;
659 p_hwfn->hw_info.hw_mode = hw_mode;
661 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
662 "Configuring function for hw_mode: 0x%08x\n",
663 p_hwfn->hw_info.hw_mode);
667 /* MFW-replacement initializations for non-ASIC */
668 static void ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
669 struct ecore_ptt *p_ptt)
674 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
677 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
679 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
680 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
682 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
683 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
684 if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
685 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
687 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
688 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
689 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
690 (p_hwfn->p_dev->num_ports_in_engines >> 1));
692 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
693 p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
697 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
698 for (i = 0; i < 100; i++) {
700 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
704 DP_NOTICE(p_hwfn, true,
705 "RBC done failed to complete in PSWRQ2\n");
709 /* Init run time data for all PFs and their VFs on an engine.
710 * TBD - for VFs - Once we have parent PF info for each VF in
711 * shmem available as CAU requires knowledge of parent PF for each VF.
713 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
715 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
718 for_each_hwfn(p_dev, i) {
719 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
720 struct ecore_igu_info *p_igu_info;
721 struct ecore_igu_block *p_block;
722 struct cau_sb_entry sb_entry;
724 p_igu_info = p_hwfn->hw_info.p_igu_info;
726 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
728 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
733 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
734 p_block->function_id, 0, 0);
735 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
740 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
741 struct ecore_ptt *p_ptt,
744 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
745 enum _ecore_status_t rc = ECORE_SUCCESS;
746 struct ecore_dev *p_dev = p_hwfn->p_dev;
747 u8 vf_id, max_num_vfs;
751 ecore_init_cau_rt_data(p_dev);
753 /* Program GTT windows */
754 ecore_gtt_init(p_hwfn);
757 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
758 ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
761 if (p_hwfn->mcp_info) {
762 if (p_hwfn->mcp_info->func_info.bandwidth_max)
763 qm_info->pf_rl_en = 1;
764 if (p_hwfn->mcp_info->func_info.bandwidth_min)
765 qm_info->pf_wfq_en = 1;
768 ecore_qm_common_rt_init(p_hwfn,
769 p_hwfn->p_dev->num_ports_in_engines,
770 qm_info->max_phys_tcs_per_port,
771 qm_info->pf_rl_en, qm_info->pf_wfq_en,
772 qm_info->vport_rl_en, qm_info->vport_wfq_en,
773 qm_info->qm_port_params);
775 ecore_cxt_hw_init_common(p_hwfn);
777 /* Close gate from NIG to BRB/Storm; By default they are open, but
778 * we close them to prevent NIG from passing data to reset blocks.
779 * Should have been done in the ENGINE phase, but init-tool lacks
780 * proper port-pretend capabilities.
782 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
783 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
784 ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
785 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
786 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
787 ecore_port_unpretend(p_hwfn, p_ptt);
789 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
790 if (rc != ECORE_SUCCESS)
793 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
794 * need to decide with which value, maybe runtime
796 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
797 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
799 if (ECORE_IS_BB(p_hwfn->p_dev)) {
800 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
803 /* pretend to original PF */
804 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
807 /* Workaround for avoiding CCFC execution error when getting packets
808 * with CRC errors, and allowing instead the invoking of the FW error
810 * This is not done inside the init tool since it currently can't
811 * perform a pretending to VFs.
813 max_num_vfs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_VFS_K2
815 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
816 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
817 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
818 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
820 /* pretend to original PF */
821 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
827 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
828 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
830 #define PMEG_IF_BYTE_COUNT 8
832 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
833 struct ecore_ptt *p_ptt,
834 u32 addr, u64 data, u8 reg_type, u8 port)
836 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
837 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
838 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
839 (8 << PMEG_IF_BYTE_COUNT),
840 (reg_type << 25) | (addr << 8) | port,
841 (u32)((data >> 32) & 0xffffffff),
842 (u32)(data & 0xffffffff));
844 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
845 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
846 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
847 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
848 (reg_type << 25) | (addr << 8) | port);
849 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
851 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
852 (data >> 32) & 0xffffffff);
855 #define XLPORT_MODE_REG (0x20a)
856 #define XLPORT_MAC_CONTROL (0x210)
857 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
858 #define XLPORT_ENABLE_REG (0x20b)
860 #define XLMAC_CTRL (0x600)
861 #define XLMAC_MODE (0x601)
862 #define XLMAC_RX_MAX_SIZE (0x608)
863 #define XLMAC_TX_CTRL (0x604)
864 #define XLMAC_PAUSE_CTRL (0x60d)
865 #define XLMAC_PFC_CTRL (0x60e)
867 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
868 struct ecore_ptt *p_ptt)
870 u8 port = p_hwfn->port_id;
871 u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
873 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
874 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
875 (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
876 | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
878 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
879 1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
881 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
882 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
884 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
885 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
887 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
888 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
890 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
891 (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
892 (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
894 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
897 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
898 struct ecore_ptt *p_ptt)
900 u8 loopback = 0, port = p_hwfn->port_id * 2;
902 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
904 if (ECORE_IS_AH(p_hwfn->p_dev)) {
905 ecore_emul_link_init_ah(p_hwfn, p_ptt);
909 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
911 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
912 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
913 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
914 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
915 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
916 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
918 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
919 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
920 0x30ffffc000ULL, 0, port);
921 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
923 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x1003 | (loopback << 2),
925 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
926 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
929 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
930 struct ecore_ptt *p_ptt, u8 port)
932 int port_offset = port ? 0x800 : 0;
936 /* FIXME: move to common start */
937 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
938 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
940 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
941 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
943 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
945 /* Set the number of ports on the Warp Core to 10G */
946 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
948 /* Soft reset of XMAC */
949 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
950 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
952 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
953 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
955 /* FIXME: move to common end */
956 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
957 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
959 /* Set Max packet size: initialize XMAC block register for port 0 */
960 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
962 /* CRC append for Tx packets: init XMAC block register for port 1 */
963 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
965 /* Enable TX and RX: initialize XMAC block register for port 1 */
966 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
967 XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
968 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
969 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
970 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
974 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
975 struct ecore_ptt *p_ptt,
978 enum _ecore_status_t rc = ECORE_SUCCESS;
981 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
983 if (rc != ECORE_SUCCESS)
987 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
988 return ECORE_SUCCESS;
990 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
991 if (ECORE_IS_AH(p_hwfn->p_dev))
992 return ECORE_SUCCESS;
993 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
994 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
995 if (p_hwfn->p_dev->num_hwfns > 1) {
996 /* Activate OPTE in CMT */
999 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1001 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1002 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1003 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1004 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1005 ecore_wr(p_hwfn, p_ptt,
1006 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1007 ecore_wr(p_hwfn, p_ptt,
1008 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1009 ecore_wr(p_hwfn, p_ptt,
1010 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1014 ecore_emul_link_init(p_hwfn, p_ptt);
1016 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1023 static enum _ecore_status_t
1024 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1025 struct ecore_ptt *p_ptt)
1027 u32 pwm_regsize, norm_regsize;
1028 u32 non_pwm_conn, min_addr_reg1;
1029 u32 db_bar_size, n_cpus;
1031 int rc = ECORE_SUCCESS;
1033 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1034 if (p_hwfn->p_dev->num_hwfns > 1)
1037 /* Calculate doorbell regions
1038 * -----------------------------------
1039 * The doorbell BAR is made of two regions. The first is called normal
1040 * region and the second is called PWM region. In the normal region
1041 * each ICID has its own set of addresses so that writing to that
1042 * specific address identifies the ICID. In the Process Window Mode
1043 * region the ICID is given in the data written to the doorbell. The
1044 * above per PF register denotes the offset in the doorbell BAR in which
1045 * the PWM region begins.
1046 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1047 * non-PWM connection. The calculation below computes the total non-PWM
1048 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1049 * in units of 4,096 bytes.
1051 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1052 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1054 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1055 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1056 min_addr_reg1 = norm_regsize / 4096;
1057 pwm_regsize = db_bar_size - norm_regsize;
1059 /* Check that the normal and PWM sizes are valid */
1060 if (db_bar_size < norm_regsize) {
1061 DP_ERR(p_hwfn->p_dev,
1062 "Doorbell BAR size 0x%x is too"
1063 " small (normal region is 0x%0x )\n",
1064 db_bar_size, norm_regsize);
1065 return ECORE_NORESOURCES;
1067 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1068 DP_ERR(p_hwfn->p_dev,
1069 "PWM region size 0x%0x is too small."
1070 " Should be at least 0x%0x (Doorbell BAR size"
1071 " is 0x%x and normal region size is 0x%0x)\n",
1072 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1074 return ECORE_NORESOURCES;
1078 p_hwfn->dpi_start_offset = norm_regsize; /* this is later used to
1079 * calculate the doorbell
1083 /* Update registers */
1084 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1085 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1086 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1087 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1090 "Doorbell size 0x%x, Normal region 0x%x, PWM region 0x%x\n",
1091 db_bar_size, norm_regsize, pwm_regsize);
1092 DP_INFO(p_hwfn, "DPI size 0x%x, DPI count 0x%x\n", p_hwfn->dpi_size,
1095 return ECORE_SUCCESS;
1098 static enum _ecore_status_t
1099 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1100 struct ecore_ptt *p_ptt,
1101 struct ecore_tunn_start_params *p_tunn,
1104 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1106 enum _ecore_status_t rc = ECORE_SUCCESS;
1107 u8 rel_pf_id = p_hwfn->rel_pf_id;
1113 if (p_hwfn->mcp_info) {
1114 struct ecore_mcp_function_info *p_info;
1116 p_info = &p_hwfn->mcp_info->func_info;
1117 if (p_info->bandwidth_min)
1118 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1120 /* Update rate limit once we'll actually have a link */
1121 p_hwfn->qm_info.pf_rl = 100;
1123 ecore_cxt_hw_init_pf(p_hwfn);
1125 ecore_int_igu_init_rt(p_hwfn); /* @@@TBD TODO MichalS multi hwfn ?? */
1127 /* Set VLAN in NIG if needed */
1128 if (hw_mode & (1 << MODE_MF_SD)) {
1129 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1130 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1131 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1132 p_hwfn->hw_info.ovlan);
1135 /* Enable classification by MAC if needed */
1136 if (hw_mode & (1 << MODE_MF_SI)) {
1137 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1138 "Configuring TAGMAC_CLS_TYPE\n");
1139 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1143 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1144 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
1146 /* perform debug configuration when chip is out of reset */
1147 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1149 /* Cleanup chip from previous driver if such remains exist */
1150 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1151 if (rc != ECORE_SUCCESS) {
1152 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1156 /* PF Init sequence */
1157 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1161 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1162 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1166 /* Pure runtime initializations - directly to the HW */
1167 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1169 /* PCI relaxed ordering causes a decrease in the performance on some
1170 * systems. Till a root cause is found, disable this attribute in the
1174 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1176 * DP_NOTICE(p_hwfn, true,
1177 * "Failed to find the PCI Express"
1178 * " Capability structure in the PCI config space\n");
1181 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL,
1183 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1184 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL,
1188 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1193 /* enable interrupts */
1194 ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1196 /* send function start command */
1197 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1198 allow_npar_tx_switch);
1200 DP_NOTICE(p_hwfn, true,
1201 "Function start ramrod failed\n");
1203 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1204 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1205 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1207 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1208 "PRS_REG_SEARCH register after start PFn\n");
1209 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1210 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1211 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1212 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1213 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1214 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1215 prs_reg = ecore_rd(p_hwfn, p_ptt,
1216 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1217 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1218 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1220 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1221 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1222 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1228 static enum _ecore_status_t
1229 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1230 struct ecore_ptt *p_ptt, u8 enable)
1232 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1234 /* Change PF in PXP */
1235 ecore_wr(p_hwfn, p_ptt,
1236 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1238 /* wait until value is set - try for 1 second every 50us */
1239 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1240 val = ecore_rd(p_hwfn, p_ptt,
1241 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1248 if (val != set_val) {
1249 DP_NOTICE(p_hwfn, true,
1250 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1251 return ECORE_UNKNOWN_ERROR;
1254 return ECORE_SUCCESS;
1257 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1258 struct ecore_ptt *p_main_ptt)
1260 /* Read shadow of current MFW mailbox */
1261 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1262 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1263 p_hwfn->mcp_info->mfw_mb_cur,
1264 p_hwfn->mcp_info->mfw_mb_length);
1267 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1268 struct ecore_tunn_start_params *p_tunn,
1270 enum ecore_int_mode int_mode,
1271 bool allow_npar_tx_switch,
1272 const u8 *bin_fw_data)
1274 enum _ecore_status_t rc, mfw_rc;
1275 u32 load_code, param;
1279 rc = ecore_init_fw_data(p_dev, bin_fw_data);
1280 if (rc != ECORE_SUCCESS)
1284 for_each_hwfn(p_dev, i) {
1285 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1288 rc = ecore_vf_pf_init(p_hwfn);
1294 /* Enable DMAE in PXP */
1295 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1297 ecore_calc_hw_mode(p_hwfn);
1298 /* @@@TBD need to add here:
1299 * Check for fan failure
1302 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1304 DP_NOTICE(p_hwfn, true,
1305 "Failed sending LOAD_REQ command\n");
1310 * When coming back from hiberbate state, the registers from
1311 * which shadow is read initially are not initialized. It turns
1312 * out that these registers get initialized during the call to
1313 * ecore_mcp_load_req request. So we need to reread them here
1314 * to get the proper shadow register value.
1315 * Note: This is a workaround for the missinginig MFW
1316 * initialization. It may be removed once the implementation
1319 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1321 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1322 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1325 /* Only relevant for recovery:
1326 * Clear the indication after the LOAD_REQ command is responded
1329 p_dev->recov_in_prog = false;
1331 p_hwfn->first_on_engine = (load_code ==
1332 FW_MSG_CODE_DRV_LOAD_ENGINE);
1334 switch (load_code) {
1335 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1336 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1337 p_hwfn->hw_info.hw_mode);
1341 case FW_MSG_CODE_DRV_LOAD_PORT:
1342 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1343 p_hwfn->hw_info.hw_mode);
1347 if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
1348 struct init_nig_pri_tc_map_req tc_map;
1350 OSAL_MEM_ZERO(&tc_map, sizeof(tc_map));
1352 /* remove this once flow control is
1355 for (j = 0; j < NUM_OF_VLAN_PRIORITIES; j++) {
1356 tc_map.pri[j].tc_id = 0;
1357 tc_map.pri[j].valid = 1;
1359 ecore_init_nig_pri_tc_map(p_hwfn,
1364 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1365 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1366 p_tunn, p_hwfn->hw_info.hw_mode,
1367 b_hw_start, int_mode,
1368 allow_npar_tx_switch);
1375 if (rc != ECORE_SUCCESS)
1376 DP_NOTICE(p_hwfn, true,
1377 "init phase failed loadcode 0x%x (rc %d)\n",
1380 /* ACK mfw regardless of success or failure of initialization */
1381 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1382 DRV_MSG_CODE_LOAD_DONE,
1383 0, &load_code, ¶m);
1384 if (rc != ECORE_SUCCESS)
1386 if (mfw_rc != ECORE_SUCCESS) {
1387 DP_NOTICE(p_hwfn, true,
1388 "Failed sending LOAD_DONE command\n");
1392 /* send DCBX attention request command */
1393 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1394 "sending phony dcbx set command to trigger DCBx"
1395 " attention handling\n");
1396 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1397 DRV_MSG_CODE_SET_DCBX,
1398 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1399 &load_code, ¶m);
1400 if (mfw_rc != ECORE_SUCCESS) {
1401 DP_NOTICE(p_hwfn, true,
1402 "Failed to send DCBX attention request\n");
1406 p_hwfn->hw_init_done = true;
1409 return ECORE_SUCCESS;
1412 #define ECORE_HW_STOP_RETRY_LIMIT (10)
1413 static OSAL_INLINE void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1414 struct ecore_hwfn *p_hwfn,
1415 struct ecore_ptt *p_ptt)
1420 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1421 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1422 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT &&
1423 !p_dev->recov_in_prog; i++) {
1424 if ((!ecore_rd(p_hwfn, p_ptt,
1425 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1426 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1429 /* Dependent on number of connection/tasks, possibly
1430 * 1ms sleep is required between polls
1434 if (i == ECORE_HW_STOP_RETRY_LIMIT)
1435 DP_NOTICE(p_hwfn, true,
1436 "Timers linear scans are not over"
1437 " [Connection %02x Tasks %02x]\n",
1438 (u8)ecore_rd(p_hwfn, p_ptt,
1439 TM_REG_PF_SCAN_ACTIVE_CONN),
1440 (u8)ecore_rd(p_hwfn, p_ptt,
1441 TM_REG_PF_SCAN_ACTIVE_TASK));
1444 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1448 for_each_hwfn(p_dev, j) {
1449 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1450 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1452 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1456 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1458 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1461 for_each_hwfn(p_dev, j) {
1462 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1463 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1465 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1468 ecore_vf_pf_int_cleanup(p_hwfn);
1472 /* mark the hw as uninitialized... */
1473 p_hwfn->hw_init_done = false;
1475 rc = ecore_sp_pf_stop(p_hwfn);
1477 DP_NOTICE(p_hwfn, true,
1478 "Failed to close PF against FW. Continue to"
1479 " stop HW to prevent illegal host access"
1480 " by the device\n");
1482 /* perform debug action after PF stop was sent */
1483 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1485 /* close NIG to BRB gate */
1486 ecore_wr(p_hwfn, p_ptt,
1487 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1490 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1491 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1492 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1494 /* @@@TBD - clean transmission queues (5.b) */
1495 /* @@@TBD - clean BTB (5.c) */
1497 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1499 /* @@@TBD - verify DMAE requests are done (8) */
1501 /* Disable Attention Generation */
1502 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1503 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1504 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1505 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1506 /* Need to wait 1ms to guarantee SBs are cleared */
1511 /* Disable DMAE in PXP - in CMT, this should only be done for
1512 * first hw-function, and only after all transactions have
1513 * stopped for all active hw-functions.
1515 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1516 p_dev->hwfns[0].p_main_ptt, false);
1517 if (t_rc != ECORE_SUCCESS)
1524 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1528 for_each_hwfn(p_dev, j) {
1529 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1530 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1533 ecore_vf_pf_int_cleanup(p_hwfn);
1537 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1538 "Shutting down the fastpath\n");
1540 ecore_wr(p_hwfn, p_ptt,
1541 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1543 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1544 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1545 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1547 /* @@@TBD - clean transmission queues (5.b) */
1548 /* @@@TBD - clean BTB (5.c) */
1550 /* @@@TBD - verify DMAE requests are done (8) */
1552 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1553 /* Need to wait 1ms to guarantee SBs are cleared */
1558 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1560 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1562 if (IS_VF(p_hwfn->p_dev))
1565 /* Re-open incoming traffic */
1566 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1567 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1570 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1571 struct ecore_ptt *p_ptt, u32 reg,
1574 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1576 if (assert_val != expected) {
1577 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1579 return ECORE_UNKNOWN_ERROR;
1585 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1587 enum _ecore_status_t rc = ECORE_SUCCESS;
1588 u32 unload_resp, unload_param;
1591 for_each_hwfn(p_dev, i) {
1592 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1595 rc = ecore_vf_pf_reset(p_hwfn);
1601 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1603 /* Check for incorrect states */
1604 if (!p_dev->recov_in_prog) {
1605 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1606 QM_REG_USG_CNT_PF_TX, 0);
1607 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1608 QM_REG_USG_CNT_PF_OTHER, 0);
1609 /* @@@TBD - assert on incorrect xCFC values (10.b) */
1612 /* Disable PF in HW blocks */
1613 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1614 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1615 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1616 TCFC_REG_STRONG_ENABLE_PF, 0);
1617 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1618 CCFC_REG_STRONG_ENABLE_PF, 0);
1620 if (p_dev->recov_in_prog) {
1621 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1622 "Recovery is in progress -> skip "
1623 "sending unload_req/done\n");
1627 /* Send unload command to MCP */
1628 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1629 DRV_MSG_CODE_UNLOAD_REQ,
1630 DRV_MB_PARAM_UNLOAD_WOL_MCP,
1631 &unload_resp, &unload_param);
1632 if (rc != ECORE_SUCCESS) {
1633 DP_NOTICE(p_hwfn, true,
1634 "ecore_hw_reset: UNLOAD_REQ failed\n");
1635 /* @@TBD - what to do? for now, assume ENG. */
1636 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1639 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1640 DRV_MSG_CODE_UNLOAD_DONE,
1641 0, &unload_resp, &unload_param);
1642 if (rc != ECORE_SUCCESS) {
1644 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
1645 /* @@@TBD - Should it really ASSERT here ? */
1653 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1654 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
1656 ecore_ptt_pool_free(p_hwfn);
1657 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
1660 /* Setup bar access */
1661 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
1663 /* clear indirect access */
1664 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1665 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1666 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1667 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1669 /* Clean Previous errors if such exist */
1670 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1671 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1673 /* enable internal target-read */
1674 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1675 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1678 static void get_function_id(struct ecore_hwfn *p_hwfn)
1681 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
1682 PXP_PF_ME_OPAQUE_ADDR);
1684 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1686 /* Bits 16-19 from the ME registers are the pf_num */
1687 /* @@ @TBD - check, may be wrong after B0 implementation for CMT */
1688 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1689 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1690 PXP_CONCRETE_FID_PFID);
1691 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1692 PXP_CONCRETE_FID_PORT);
1694 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1695 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1696 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
1699 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
1701 u32 *feat_num = p_hwfn->hw_info.feat_num;
1702 int num_features = 1;
1704 /* L2 Queues require each: 1 status block. 1 L2 queue */
1705 feat_num[ECORE_PF_L2_QUE] =
1707 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
1708 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
1710 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1711 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1712 feat_num[ECORE_PF_L2_QUE],
1713 RESC_NUM(p_hwfn, ECORE_SB), num_features);
1716 /* @@@TBD MK RESC: This info is currently hard code and set as if we were MF
1717 * need to read it from shmem...
1719 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn)
1721 u32 *resc_start = p_hwfn->hw_info.resc_start;
1722 u8 num_funcs = p_hwfn->num_funcs_on_engine;
1723 u32 *resc_num = p_hwfn->hw_info.resc_num;
1724 int i, max_vf_vlan_filters;
1725 struct ecore_sb_cnt_info sb_cnt_info;
1726 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
1728 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
1730 #ifdef CONFIG_ECORE_SRIOV
1731 max_vf_vlan_filters = ECORE_ETH_MAX_VF_NUM_VLAN_FILTERS;
1733 max_vf_vlan_filters = 0;
1736 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1737 resc_num[ECORE_SB] = OSAL_MIN_T(u32,
1738 (MAX_SB_PER_PATH_BB / num_funcs),
1739 sb_cnt_info.sb_cnt);
1741 resc_num[ECORE_L2_QUEUE] = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
1742 MAX_NUM_L2_QUEUES_BB) / num_funcs;
1743 resc_num[ECORE_VPORT] = (b_ah ? MAX_NUM_VPORTS_K2 :
1744 MAX_NUM_VPORTS_BB) / num_funcs;
1745 resc_num[ECORE_RSS_ENG] = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
1746 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
1747 resc_num[ECORE_PQ] = (b_ah ? MAX_QM_TX_QUEUES_K2 :
1748 MAX_QM_TX_QUEUES_BB) / num_funcs;
1749 resc_num[ECORE_RL] = 8;
1750 resc_num[ECORE_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1751 resc_num[ECORE_VLAN] = (ETH_NUM_VLAN_FILTERS -
1752 max_vf_vlan_filters +
1753 1 /*For vlan0 */) / num_funcs;
1755 /* TODO - there will be a problem in AH - there are only 11k lines */
1756 resc_num[ECORE_ILT] = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
1757 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
1760 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1761 /* Reduced build contains less PQs */
1762 if (!(p_hwfn->p_dev->b_is_emul_full))
1763 resc_num[ECORE_PQ] = 32;
1765 /* For AH emulation, since we have a possible maximal number of
1766 * 16 enabled PFs, in case there are not enough ILT lines -
1767 * allocate only first PF as RoCE and have all the other ETH
1768 * only with less ILT lines.
1770 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
1771 resc_num[ECORE_ILT] = resc_num[ECORE_ILT];
1775 for (i = 0; i < ECORE_MAX_RESC; i++)
1776 resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
1779 /* Correct the common ILT calculation if PF0 has more */
1780 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
1781 p_hwfn->p_dev->b_is_emul_full &&
1782 p_hwfn->rel_pf_id && resc_num[ECORE_ILT])
1783 resc_start[ECORE_ILT] += resc_num[ECORE_ILT];
1786 /* Sanity for ILT */
1787 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
1788 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
1789 DP_NOTICE(p_hwfn, true,
1790 "Can't assign ILT pages [%08x,...,%08x]\n",
1791 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
1797 ecore_hw_set_feat(p_hwfn);
1799 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1800 "The numbers for each resource are:\n"
1801 "SB = %d start = %d\n"
1802 "L2_QUEUE = %d start = %d\n"
1803 "VPORT = %d start = %d\n"
1804 "PQ = %d start = %d\n"
1805 "RL = %d start = %d\n"
1806 "MAC = %d start = %d\n"
1807 "VLAN = %d start = %d\n"
1808 "ILT = %d start = %d\n"
1809 "CMDQS_CQS = %d start = %d\n",
1810 RESC_NUM(p_hwfn, ECORE_SB), RESC_START(p_hwfn, ECORE_SB),
1811 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
1812 RESC_START(p_hwfn, ECORE_L2_QUEUE),
1813 RESC_NUM(p_hwfn, ECORE_VPORT),
1814 RESC_START(p_hwfn, ECORE_VPORT),
1815 RESC_NUM(p_hwfn, ECORE_PQ), RESC_START(p_hwfn, ECORE_PQ),
1816 RESC_NUM(p_hwfn, ECORE_RL), RESC_START(p_hwfn, ECORE_RL),
1817 RESC_NUM(p_hwfn, ECORE_MAC), RESC_START(p_hwfn, ECORE_MAC),
1818 RESC_NUM(p_hwfn, ECORE_VLAN),
1819 RESC_START(p_hwfn, ECORE_VLAN),
1820 RESC_NUM(p_hwfn, ECORE_ILT), RESC_START(p_hwfn, ECORE_ILT),
1821 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS),
1822 RESC_START(p_hwfn, ECORE_CMDQS_CQS));
1824 return ECORE_SUCCESS;
1827 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
1828 struct ecore_ptt *p_ptt)
1830 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1831 u32 port_cfg_addr, link_temp, device_capabilities;
1832 struct ecore_mcp_link_params *link;
1834 /* Read global nvm_cfg address */
1835 u32 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1837 /* Verify MCP has initialized it */
1838 if (nvm_cfg_addr == 0) {
1839 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
1843 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1844 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1846 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1847 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
1850 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
1852 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1853 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1854 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G:
1855 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
1857 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G:
1858 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
1860 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G:
1861 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
1863 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F:
1864 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
1866 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E:
1867 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
1869 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G:
1870 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
1872 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G:
1873 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
1875 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G:
1876 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
1878 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G:
1879 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
1882 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
1887 /* Read default link configuration */
1888 link = &p_hwfn->mcp_info->link_input;
1889 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1890 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1891 link_temp = ecore_rd(p_hwfn, p_ptt,
1893 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
1894 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1895 link->speed.advertised_speeds = link_temp;
1897 link_temp = link->speed.advertised_speeds;
1898 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
1900 link_temp = ecore_rd(p_hwfn, p_ptt,
1902 OFFSETOF(struct nvm_cfg1_port, link_settings));
1903 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1904 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1905 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1906 link->speed.autoneg = true;
1908 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1909 link->speed.forced_speed = 1000;
1911 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1912 link->speed.forced_speed = 10000;
1914 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1915 link->speed.forced_speed = 25000;
1917 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1918 link->speed.forced_speed = 40000;
1920 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1921 link->speed.forced_speed = 50000;
1923 case NVM_CFG1_PORT_DRV_LINK_SPEED_100G:
1924 link->speed.forced_speed = 100000;
1927 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
1930 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1931 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1932 link->pause.autoneg = !!(link_temp &
1933 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1934 link->pause.forced_rx = !!(link_temp &
1935 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1936 link->pause.forced_tx = !!(link_temp &
1937 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1938 link->loopback_mode = 0;
1940 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1941 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x,"
1942 " AN: 0x%02x, PAUSE AN: 0x%02x\n",
1943 link->speed.forced_speed, link->speed.advertised_speeds,
1944 link->speed.autoneg, link->pause.autoneg);
1946 /* Read Multi-function information from shmem */
1947 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1948 OFFSETOF(struct nvm_cfg1, glob) +
1949 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
1951 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
1953 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1954 NVM_CFG1_GLOB_MF_MODE_OFFSET;
1957 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1958 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
1960 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1961 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
1963 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1964 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
1967 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1968 p_hwfn->p_dev->mf_mode);
1970 /* Read Multi-function information from shmem */
1971 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1972 OFFSETOF(struct nvm_cfg1, glob) +
1973 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
1975 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
1976 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1977 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
1978 &p_hwfn->hw_info.device_capabilities);
1980 return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1983 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
1984 struct ecore_ptt *p_ptt)
1989 num_funcs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_PFS_K2
1992 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1993 * in the other bits are selected.
1994 * Bits 1-15 are for functions 1-15, respectively, and their value is
1995 * '0' only for enabled functions (function 0 always exists and
1997 * In case of CMT, only the "even" functions are enabled, and thus the
1998 * number of functions for both hwfns is learnt from the same bits.
2001 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2003 if (ECORE_PATH_ID(p_hwfn) && p_hwfn->p_dev->num_hwfns == 1) {
2011 tmp = (tmp ^ 0xffffffff) & mask;
2019 p_hwfn->num_funcs_on_engine = num_funcs;
2022 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2023 DP_NOTICE(p_hwfn, false,
2024 "FPGA: Limit number of PFs to 4 [would affect"
2025 " resource allocation, needed for IOV]\n");
2026 p_hwfn->num_funcs_on_engine = 4;
2030 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "num_funcs_on_engine = %d\n",
2031 p_hwfn->num_funcs_on_engine);
2034 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2035 struct ecore_ptt *p_ptt)
2040 /* Read the port mode */
2041 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2043 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2044 (p_hwfn->p_dev->num_hwfns > 1))
2045 /* In CMT on emulation, assume 1 port */
2049 port_mode = ecore_rd(p_hwfn, p_ptt,
2050 CNIG_REG_NW_PORT_MODE_BB_B0);
2052 if (port_mode < 3) {
2053 p_hwfn->p_dev->num_ports_in_engines = 1;
2054 } else if (port_mode <= 5) {
2055 p_hwfn->p_dev->num_ports_in_engines = 2;
2057 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2058 p_hwfn->p_dev->num_ports_in_engines);
2060 /* Default num_ports_in_engines to something */
2061 p_hwfn->p_dev->num_ports_in_engines = 1;
2065 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2066 struct ecore_ptt *p_ptt)
2071 p_hwfn->p_dev->num_ports_in_engines = 0;
2073 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2074 port = ecore_rd(p_hwfn, p_ptt,
2075 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2077 p_hwfn->p_dev->num_ports_in_engines++;
2081 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2082 struct ecore_ptt *p_ptt)
2084 if (ECORE_IS_BB(p_hwfn->p_dev))
2085 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2087 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2090 static enum _ecore_status_t
2091 ecore_get_hw_info(struct ecore_hwfn *p_hwfn,
2092 struct ecore_ptt *p_ptt,
2093 enum ecore_pci_personality personality)
2095 enum _ecore_status_t rc;
2097 rc = ecore_iov_hw_info(p_hwfn, p_hwfn->p_main_ptt);
2101 /* TODO In get_hw_info, amoungst others:
2102 * Get MCP FW revision and determine according to it the supported
2103 * featrues (e.g. DCB)
2105 * ecore_get_pcie_width_speed, WOL capability.
2106 * Number of global CQ-s (for storage
2108 ecore_hw_info_port_num(p_hwfn, p_ptt);
2111 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2113 ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2115 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2120 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2122 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2123 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2126 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2128 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2129 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2133 if (ecore_mcp_is_init(p_hwfn)) {
2134 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2135 p_hwfn->hw_info.ovlan =
2136 p_hwfn->mcp_info->func_info.ovlan;
2138 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2141 if (personality != ECORE_PCI_DEFAULT)
2142 p_hwfn->hw_info.personality = personality;
2143 else if (ecore_mcp_is_init(p_hwfn))
2144 p_hwfn->hw_info.personality =
2145 p_hwfn->mcp_info->func_info.protocol;
2148 /* To overcome ILT lack for emulation, until at least until we'll have
2149 * a definite answer from system about it, allow only PF0 to be RoCE.
2151 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
2152 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2155 ecore_get_num_funcs(p_hwfn, p_ptt);
2157 /* Feat num is dependent on personality and on the number of functions
2158 * on the engine. Therefore it should be come after personality
2159 * initialization and after getting the number of functions.
2161 return ecore_hw_get_resc(p_hwfn);
2164 /* @TMP - this should move to a proper .h */
2165 #define CHIP_NUM_AH 0x8070
2167 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2169 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2172 /* Read Vendor Id / Device Id */
2173 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2175 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2178 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2179 MISCS_REG_CHIP_NUM);
2180 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2181 MISCS_REG_CHIP_REV);
2183 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2185 /* Determine type */
2186 if (p_dev->device_id == CHIP_NUM_AH)
2187 p_dev->type = ECORE_DEV_TYPE_AH;
2189 p_dev->type = ECORE_DEV_TYPE_BB;
2191 /* Learn number of HW-functions */
2192 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2193 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2195 if (tmp & (1 << p_hwfn->rel_pf_id)) {
2196 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2197 p_dev->num_hwfns = 2;
2199 p_dev->num_hwfns = 1;
2203 if (CHIP_REV_IS_EMUL(p_dev)) {
2204 /* For some reason we have problems with this register
2205 * in B0 emulation; Simply assume no CMT
2207 DP_NOTICE(p_dev->hwfns, false,
2208 "device on emul - assume no CMT\n");
2209 p_dev->num_hwfns = 1;
2213 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2214 MISCS_REG_CHIP_TEST_REG) >> 4;
2215 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2216 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2217 MISCS_REG_CHIP_METAL);
2218 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2219 DP_INFO(p_dev->hwfns,
2220 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x"
2222 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2223 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2224 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2227 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2228 DP_NOTICE(p_dev->hwfns, false,
2229 "The chip type/rev (BB A0) is not supported!\n");
2230 return ECORE_ABORTED;
2233 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2234 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2235 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2237 if (CHIP_REV_IS_EMUL(p_dev)) {
2238 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2239 MISCS_REG_ECO_RESERVED);
2240 if (tmp & (1 << 29)) {
2241 DP_NOTICE(p_hwfn, false,
2242 "Emulation: Running on a FULL build\n");
2243 p_dev->b_is_emul_full = true;
2245 DP_NOTICE(p_hwfn, false,
2246 "Emulation: Running on a REDUCED build\n");
2251 return ECORE_SUCCESS;
2254 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2261 for_each_hwfn(p_dev, j) {
2262 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2264 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2265 "Mark hw/fw uninitialized\n");
2267 p_hwfn->hw_init_done = false;
2268 p_hwfn->first_on_engine = false;
2272 static enum _ecore_status_t
2273 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
2274 void OSAL_IOMEM *p_regview,
2275 void OSAL_IOMEM *p_doorbells,
2276 enum ecore_pci_personality personality)
2278 enum _ecore_status_t rc = ECORE_SUCCESS;
2280 /* Split PCI bars evenly between hwfns */
2281 p_hwfn->regview = p_regview;
2282 p_hwfn->doorbells = p_doorbells;
2284 /* Validate that chip access is feasible */
2285 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2287 "Reading the ME register returns all Fs;"
2288 " Preventing further chip access\n");
2292 get_function_id(p_hwfn);
2294 /* Allocate PTT pool */
2295 rc = ecore_ptt_pool_alloc(p_hwfn);
2297 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2301 /* Allocate the main PTT */
2302 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2304 /* First hwfn learns basic information, e.g., number of hwfns */
2305 if (!p_hwfn->my_id) {
2306 rc = ecore_get_dev_info(p_hwfn->p_dev);
2307 if (rc != ECORE_SUCCESS)
2311 ecore_hw_hwfn_prepare(p_hwfn);
2313 /* Initialize MCP structure */
2314 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2316 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
2320 /* Read the device configuration information from the HW and SHMEM */
2321 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2323 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
2327 /* Allocate the init RT array and initialize the init-ops engine */
2328 rc = ecore_init_alloc(p_hwfn);
2330 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
2334 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2335 DP_NOTICE(p_hwfn, false,
2336 "FPGA: workaround; Prevent DMAE parities\n");
2337 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
2339 DP_NOTICE(p_hwfn, false,
2340 "FPGA: workaround: Set VF bar0 size\n");
2341 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2342 PGLUE_B_REG_VF_BAR0_SIZE, 4);
2348 ecore_mcp_free(p_hwfn);
2350 ecore_hw_hwfn_free(p_hwfn);
2355 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, int personality)
2357 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2358 enum _ecore_status_t rc;
2361 return ecore_vf_hw_prepare(p_dev);
2363 /* Store the precompiled init data ptrs */
2364 ecore_init_iro_array(p_dev);
2366 /* Initialize the first hwfn - will learn number of hwfns */
2367 rc = ecore_hw_prepare_single(p_hwfn,
2369 p_dev->doorbells, personality);
2370 if (rc != ECORE_SUCCESS)
2373 personality = p_hwfn->hw_info.personality;
2375 /* initialalize 2nd hwfn if necessary */
2376 if (p_dev->num_hwfns > 1) {
2377 void OSAL_IOMEM *p_regview, *p_doorbell;
2378 u8 OSAL_IOMEM *addr;
2380 /* adjust bar offset for second engine */
2381 addr = (u8 OSAL_IOMEM *)p_dev->regview +
2382 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
2383 p_regview = (void OSAL_IOMEM *)addr;
2385 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
2386 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
2387 p_doorbell = (void OSAL_IOMEM *)addr;
2389 /* prepare second hw function */
2390 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
2391 p_doorbell, personality);
2393 /* in case of error, need to free the previously
2394 * initialiazed hwfn 0
2396 if (rc != ECORE_SUCCESS) {
2397 ecore_init_free(p_hwfn);
2398 ecore_mcp_free(p_hwfn);
2399 ecore_hw_hwfn_free(p_hwfn);
2404 return ECORE_SUCCESS;
2407 void ecore_hw_remove(struct ecore_dev *p_dev)
2411 for_each_hwfn(p_dev, i) {
2412 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2415 ecore_vf_pf_release(p_hwfn);
2419 ecore_init_free(p_hwfn);
2420 ecore_hw_hwfn_free(p_hwfn);
2421 ecore_mcp_free(p_hwfn);
2423 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
2427 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
2428 struct ecore_chain *p_chain)
2430 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
2431 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2432 struct ecore_chain_next *p_next;
2438 size = p_chain->elem_size * p_chain->usable_per_page;
2440 for (i = 0; i < p_chain->page_cnt; i++) {
2444 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
2445 p_virt_next = p_next->next_virt;
2446 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2448 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
2449 ECORE_CHAIN_PAGE_SIZE);
2451 p_virt = p_virt_next;
2452 p_phys = p_phys_next;
2456 static void ecore_chain_free_single(struct ecore_dev *p_dev,
2457 struct ecore_chain *p_chain)
2459 if (!p_chain->p_virt_addr)
2462 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
2463 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
2466 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
2467 struct ecore_chain *p_chain)
2469 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2470 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
2471 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
2473 if (!pp_virt_addr_tbl)
2476 if (!p_chain->pbl.p_virt_table)
2479 for (i = 0; i < page_cnt; i++) {
2480 if (!pp_virt_addr_tbl[i])
2483 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
2484 *(dma_addr_t *)p_pbl_virt,
2485 ECORE_CHAIN_PAGE_SIZE);
2487 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
2490 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
2491 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
2492 p_chain->pbl.p_phys_table, pbl_size);
2494 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
2497 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2499 switch (p_chain->mode) {
2500 case ECORE_CHAIN_MODE_NEXT_PTR:
2501 ecore_chain_free_next_ptr(p_dev, p_chain);
2503 case ECORE_CHAIN_MODE_SINGLE:
2504 ecore_chain_free_single(p_dev, p_chain);
2506 case ECORE_CHAIN_MODE_PBL:
2507 ecore_chain_free_pbl(p_dev, p_chain);
2512 static enum _ecore_status_t
2513 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
2514 enum ecore_chain_cnt_type cnt_type,
2515 osal_size_t elem_size, u32 page_cnt)
2517 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
2519 /* The actual chain size can be larger than the maximal possible value
2520 * after rounding up the requested elements number to pages, and after
2521 * taking into acount the unusuable elements (next-ptr elements).
2522 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
2523 * size/capacity fields are of a u32 type.
2525 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
2526 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
2527 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
2528 chain_size > ECORE_U32_MAX)) {
2529 DP_NOTICE(p_dev, true,
2530 "The actual chain size (0x%lx) is larger than"
2531 " the maximal possible value\n",
2532 (unsigned long)chain_size);
2536 return ECORE_SUCCESS;
2539 static enum _ecore_status_t
2540 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2542 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
2543 dma_addr_t p_phys = 0;
2546 for (i = 0; i < p_chain->page_cnt; i++) {
2547 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
2548 ECORE_CHAIN_PAGE_SIZE);
2550 DP_NOTICE(p_dev, true,
2551 "Failed to allocate chain memory\n");
2556 ecore_chain_init_mem(p_chain, p_virt, p_phys);
2557 ecore_chain_reset(p_chain);
2559 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2563 p_virt_prev = p_virt;
2565 /* Last page's next element should point to the beginning of the
2568 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2569 p_chain->p_virt_addr,
2570 p_chain->p_phys_addr);
2572 return ECORE_SUCCESS;
2575 static enum _ecore_status_t
2576 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2578 void *p_virt = OSAL_NULL;
2579 dma_addr_t p_phys = 0;
2581 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
2583 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
2587 ecore_chain_init_mem(p_chain, p_virt, p_phys);
2588 ecore_chain_reset(p_chain);
2590 return ECORE_SUCCESS;
2593 static enum _ecore_status_t ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
2594 struct ecore_chain *p_chain)
2596 void *p_virt = OSAL_NULL;
2597 u8 *p_pbl_virt = OSAL_NULL;
2598 void **pp_virt_addr_tbl = OSAL_NULL;
2599 dma_addr_t p_phys = 0, p_pbl_phys = 0;
2600 u32 page_cnt = p_chain->page_cnt, size, i;
2602 size = page_cnt * sizeof(*pp_virt_addr_tbl);
2603 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
2604 if (!pp_virt_addr_tbl) {
2605 DP_NOTICE(p_dev, true,
2606 "Failed to allocate memory for the chain"
2607 " virtual addresses table\n");
2610 OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
2612 /* The allocation of the PBL table is done with its full size, since it
2613 * is expected to be successive.
2615 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
2616 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
2618 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
2622 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2625 for (i = 0; i < page_cnt; i++) {
2626 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
2627 ECORE_CHAIN_PAGE_SIZE);
2629 DP_NOTICE(p_dev, true,
2630 "Failed to allocate chain memory\n");
2635 ecore_chain_init_mem(p_chain, p_virt, p_phys);
2636 ecore_chain_reset(p_chain);
2639 /* Fill the PBL table with the physical address of the page */
2640 *(dma_addr_t *)p_pbl_virt = p_phys;
2641 /* Keep the virtual address of the page */
2642 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2644 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
2647 return ECORE_SUCCESS;
2650 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
2651 enum ecore_chain_use_mode intended_use,
2652 enum ecore_chain_mode mode,
2653 enum ecore_chain_cnt_type cnt_type,
2654 u32 num_elems, osal_size_t elem_size,
2655 struct ecore_chain *p_chain)
2658 enum _ecore_status_t rc = ECORE_SUCCESS;
2660 if (mode == ECORE_CHAIN_MODE_SINGLE)
2663 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2665 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
2668 DP_NOTICE(p_dev, true,
2669 "Cannot allocate a chain with the given arguments:\n"
2670 " [use_mode %d, mode %d, cnt_type %d, num_elems %d,"
2671 " elem_size %zu]\n",
2672 intended_use, mode, cnt_type, num_elems, elem_size);
2676 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
2680 case ECORE_CHAIN_MODE_NEXT_PTR:
2681 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
2683 case ECORE_CHAIN_MODE_SINGLE:
2684 rc = ecore_chain_alloc_single(p_dev, p_chain);
2686 case ECORE_CHAIN_MODE_PBL:
2687 rc = ecore_chain_alloc_pbl(p_dev, p_chain);
2693 return ECORE_SUCCESS;
2696 ecore_chain_free(p_dev, p_chain);
2700 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
2701 u16 src_id, u16 *dst_id)
2703 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
2706 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
2707 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
2708 DP_NOTICE(p_hwfn, true,
2709 "l2_queue id [%d] is not valid, available"
2710 " indices [%d - %d]\n",
2716 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
2718 return ECORE_SUCCESS;
2721 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
2722 u8 src_id, u8 *dst_id)
2724 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
2727 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
2728 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
2729 DP_NOTICE(p_hwfn, true,
2730 "vport id [%d] is not valid, available"
2731 " indices [%d - %d]\n",
2737 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
2739 return ECORE_SUCCESS;
2742 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
2743 u8 src_id, u8 *dst_id)
2745 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
2748 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
2749 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
2750 DP_NOTICE(p_hwfn, true,
2751 "rss_eng id [%d] is not valid,avail idx [%d - %d]\n",
2757 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
2759 return ECORE_SUCCESS;
2762 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
2763 struct ecore_ptt *p_ptt,
2769 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2770 return ECORE_SUCCESS;
2772 high = p_filter[1] | (p_filter[0] << 8);
2773 low = p_filter[5] | (p_filter[4] << 8) |
2774 (p_filter[3] << 16) | (p_filter[2] << 24);
2776 /* Find a free entry and utilize it */
2777 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2778 en = ecore_rd(p_hwfn, p_ptt,
2779 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2782 ecore_wr(p_hwfn, p_ptt,
2783 NIG_REG_LLH_FUNC_FILTER_VALUE +
2784 2 * i * sizeof(u32), low);
2785 ecore_wr(p_hwfn, p_ptt,
2786 NIG_REG_LLH_FUNC_FILTER_VALUE +
2787 (2 * i + 1) * sizeof(u32), high);
2788 ecore_wr(p_hwfn, p_ptt,
2789 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2790 ecore_wr(p_hwfn, p_ptt,
2791 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2792 i * sizeof(u32), 0);
2793 ecore_wr(p_hwfn, p_ptt,
2794 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2797 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2798 DP_NOTICE(p_hwfn, false,
2799 "Failed to find an empty LLH filter to utilize\n");
2803 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2804 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
2805 p_filter[0], p_filter[1], p_filter[2],
2806 p_filter[3], p_filter[4], p_filter[5], i);
2808 return ECORE_SUCCESS;
2811 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
2812 struct ecore_ptt *p_ptt, u8 *p_filter)
2817 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2820 high = p_filter[1] | (p_filter[0] << 8);
2821 low = p_filter[5] | (p_filter[4] << 8) |
2822 (p_filter[3] << 16) | (p_filter[2] << 24);
2824 /* Find the entry and clean it */
2825 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2826 if (ecore_rd(p_hwfn, p_ptt,
2827 NIG_REG_LLH_FUNC_FILTER_VALUE +
2828 2 * i * sizeof(u32)) != low)
2830 if (ecore_rd(p_hwfn, p_ptt,
2831 NIG_REG_LLH_FUNC_FILTER_VALUE +
2832 (2 * i + 1) * sizeof(u32)) != high)
2835 ecore_wr(p_hwfn, p_ptt,
2836 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2837 ecore_wr(p_hwfn, p_ptt,
2838 NIG_REG_LLH_FUNC_FILTER_VALUE +
2839 2 * i * sizeof(u32), 0);
2840 ecore_wr(p_hwfn, p_ptt,
2841 NIG_REG_LLH_FUNC_FILTER_VALUE +
2842 (2 * i + 1) * sizeof(u32), 0);
2845 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2846 DP_NOTICE(p_hwfn, false,
2847 "Tried to remove a non-configured filter\n");
2850 enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn,
2851 struct ecore_ptt *p_ptt,
2857 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2858 return ECORE_SUCCESS;
2863 /* Find a free entry and utilize it */
2864 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2865 en = ecore_rd(p_hwfn, p_ptt,
2866 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2869 ecore_wr(p_hwfn, p_ptt,
2870 NIG_REG_LLH_FUNC_FILTER_VALUE +
2871 2 * i * sizeof(u32), low);
2872 ecore_wr(p_hwfn, p_ptt,
2873 NIG_REG_LLH_FUNC_FILTER_VALUE +
2874 (2 * i + 1) * sizeof(u32), high);
2875 ecore_wr(p_hwfn, p_ptt,
2876 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
2877 ecore_wr(p_hwfn, p_ptt,
2878 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2879 i * sizeof(u32), 1);
2880 ecore_wr(p_hwfn, p_ptt,
2881 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2884 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2885 DP_NOTICE(p_hwfn, false,
2886 "Failed to find an empty LLH filter to utilize\n");
2890 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2891 "ETH type: %x is added at %d\n", filter, i);
2893 return ECORE_SUCCESS;
2896 void ecore_llh_remove_ethertype_filter(struct ecore_hwfn *p_hwfn,
2897 struct ecore_ptt *p_ptt, u16 filter)
2902 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2908 /* Find the entry and clean it */
2909 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2910 if (ecore_rd(p_hwfn, p_ptt,
2911 NIG_REG_LLH_FUNC_FILTER_VALUE +
2912 2 * i * sizeof(u32)) != low)
2914 if (ecore_rd(p_hwfn, p_ptt,
2915 NIG_REG_LLH_FUNC_FILTER_VALUE +
2916 (2 * i + 1) * sizeof(u32)) != high)
2919 ecore_wr(p_hwfn, p_ptt,
2920 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2921 ecore_wr(p_hwfn, p_ptt,
2922 NIG_REG_LLH_FUNC_FILTER_VALUE +
2923 2 * i * sizeof(u32), 0);
2924 ecore_wr(p_hwfn, p_ptt,
2925 NIG_REG_LLH_FUNC_FILTER_VALUE +
2926 (2 * i + 1) * sizeof(u32), 0);
2929 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2930 DP_NOTICE(p_hwfn, false,
2931 "Tried to remove a non-configured filter\n");
2934 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
2935 struct ecore_ptt *p_ptt)
2939 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2942 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2943 ecore_wr(p_hwfn, p_ptt,
2944 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2945 ecore_wr(p_hwfn, p_ptt,
2946 NIG_REG_LLH_FUNC_FILTER_VALUE +
2947 2 * i * sizeof(u32), 0);
2948 ecore_wr(p_hwfn, p_ptt,
2949 NIG_REG_LLH_FUNC_FILTER_VALUE +
2950 (2 * i + 1) * sizeof(u32), 0);
2954 enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn,
2955 struct ecore_ptt *p_ptt)
2958 BRB_REG_HEADER_SIZE,
2959 BTB_REG_HEADER_SIZE,
2960 CAU_REG_LONG_TIMEOUT_THRESHOLD,
2961 CCFC_REG_ACTIVITY_COUNTER,
2962 CDU_REG_CID_ADDR_PARAMS,
2963 DBG_REG_CLIENT_ENABLE,
2967 IGU_REG_BLOCK_CONFIGURATION,
2969 MCP2_REG_DBG_DWORD_ENABLE,
2971 MISCS_REG_CLK_100G_MODE,
2972 MSDM_REG_ENABLE_IN1,
2977 PTU_REG_ATC_INIT_ARRAY,
2979 PGLUE_B_REG_ADMIN_PER_PF_REGION,
2980 PRM_REG_DISABLE_PRM,
2982 PSDM_REG_ENABLE_IN1,
2984 PSWRQ_REG_DBG_SELECT,
2985 PSWRQ2_REG_CDUT_P_SIZE,
2986 PSWHST_REG_DISCARD_INTERNAL_WRITES,
2987 PSWHST2_REG_DBGSYN_ALMOST_FULL_THR,
2988 PSWRD_REG_DBG_SELECT,
2990 PSWWR_REG_USDM_FULL_TH,
2991 PSWWR2_REG_CDU_FULL_TH2,
2993 RSS_REG_RSS_INIT_EN,
2994 RDIF_REG_STOP_ON_ERROR,
2996 TCFC_REG_ACTIVITY_COUNTER,
2998 TM_REG_PXP_READ_DATA_FIFO_INIT,
2999 TSDM_REG_ENABLE_IN1,
3001 TDIF_REG_STOP_ON_ERROR,
3003 UMAC_REG_IPG_HD_BKP_CNTL_BB_B0,
3004 USDM_REG_ENABLE_IN1,
3007 XSDM_REG_ENABLE_IN1,
3010 YSDM_REG_ENABLE_IN1,
3012 XYLD_REG_SCBD_STRICT_PRIO,
3013 TMLD_REG_SCBD_STRICT_PRIO,
3014 MULD_REG_SCBD_STRICT_PRIO,
3015 YULD_REG_SCBD_STRICT_PRIO,
3017 u32 test_val[] = { 0x0, 0x1 };
3018 u32 val, save_val, i, j;
3020 for (i = 0; i < OSAL_ARRAY_SIZE(test_val); i++) {
3021 for (j = 0; j < OSAL_ARRAY_SIZE(reg_tbl); j++) {
3022 save_val = ecore_rd(p_hwfn, p_ptt, reg_tbl[j]);
3023 ecore_wr(p_hwfn, p_ptt, reg_tbl[j], test_val[i]);
3024 val = ecore_rd(p_hwfn, p_ptt, reg_tbl[j]);
3025 /* Restore the original register's value */
3026 ecore_wr(p_hwfn, p_ptt, reg_tbl[j], save_val);
3027 if (val != test_val[i]) {
3028 DP_INFO(p_hwfn->p_dev,
3029 "offset 0x%x: val 0x%x != 0x%x\n",
3030 reg_tbl[j], val, test_val[i]);
3035 return ECORE_SUCCESS;
3038 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3039 struct ecore_ptt *p_ptt,
3040 u32 hw_addr, void *p_qzone,
3041 osal_size_t qzone_size,
3044 struct coalescing_timeset *p_coalesce_timeset;
3046 if (IS_VF(p_hwfn->p_dev)) {
3047 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3051 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3052 DP_NOTICE(p_hwfn, true,
3053 "Coalescing configuration not enabled\n");
3057 OSAL_MEMSET(p_qzone, 0, qzone_size);
3058 p_coalesce_timeset = p_qzone;
3059 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_qzone, qzone_size);
3061 return ECORE_SUCCESS;
3064 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3065 struct ecore_ptt *p_ptt,
3066 u8 coalesce, u8 qid)
3068 struct ustorm_eth_queue_zone qzone;
3072 enum _ecore_status_t rc;
3074 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3075 if (rc != ECORE_SUCCESS)
3078 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3079 /* Translate the coalescing time into a timeset, according to:
3080 * Timeout[Rx] = TimeSet[Rx] << (TimerRes[Rx] + 1)
3082 timeset = coalesce >> (ECORE_CAU_DEF_RX_TIMER_RES + 1);
3084 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &qzone,
3085 sizeof(struct ustorm_eth_queue_zone), timeset);
3086 if (rc != ECORE_SUCCESS)
3089 p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3094 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3095 struct ecore_ptt *p_ptt,
3096 u8 coalesce, u8 qid)
3098 struct ystorm_eth_queue_zone qzone;
3102 enum _ecore_status_t rc;
3104 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3105 if (rc != ECORE_SUCCESS)
3108 address = BAR0_MAP_REG_YSDM_RAM + YSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3109 /* Translate the coalescing time into a timeset, according to:
3110 * Timeout[Tx] = TimeSet[Tx] << (TimerRes[Tx] + 1)
3112 timeset = coalesce >> (ECORE_CAU_DEF_TX_TIMER_RES + 1);
3114 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &qzone,
3115 sizeof(struct ystorm_eth_queue_zone), timeset);
3116 if (rc != ECORE_SUCCESS)
3119 p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3124 /* Calculate final WFQ values for all vports and configure it.
3125 * After this configuration each vport must have
3126 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3128 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3129 struct ecore_ptt *p_ptt,
3132 struct init_qm_vport_params *vport_params;
3135 vport_params = p_hwfn->qm_info.qm_vport_params;
3136 num_vports = p_hwfn->qm_info.num_vports;
3138 for (i = 0; i < num_vports; i++) {
3139 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3141 vport_params[i].vport_wfq =
3142 (wfq_speed * ECORE_WFQ_UNIT) / min_pf_rate;
3143 ecore_init_vport_wfq(p_hwfn, p_ptt,
3144 vport_params[i].first_tx_pq_id,
3145 vport_params[i].vport_wfq);
3150 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3155 num_vports = p_hwfn->qm_info.num_vports;
3156 min_speed = min_pf_rate / num_vports;
3158 for (i = 0; i < num_vports; i++) {
3159 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3160 p_hwfn->qm_info.wfq_data[i].default_min_speed = min_speed;
3164 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3165 struct ecore_ptt *p_ptt,
3168 struct init_qm_vport_params *vport_params;
3171 vport_params = p_hwfn->qm_info.qm_vport_params;
3172 num_vports = p_hwfn->qm_info.num_vports;
3174 for (i = 0; i < num_vports; i++) {
3175 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3176 ecore_init_vport_wfq(p_hwfn, p_ptt,
3177 vport_params[i].first_tx_pq_id,
3178 vport_params[i].vport_wfq);
3182 /* validate wfq for a given vport and required min rate */
3183 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3184 u16 vport_id, u32 req_rate,
3187 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3188 int non_requested_count = 0, req_count = 0, i, num_vports;
3190 num_vports = p_hwfn->qm_info.num_vports;
3192 /* Check pre-set data for some of the vports */
3193 for (i = 0; i < num_vports; i++) {
3196 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3198 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3199 total_req_min_rate += tmp_speed;
3203 /* Include current vport data as well */
3205 total_req_min_rate += req_rate;
3206 non_requested_count = p_hwfn->qm_info.num_vports - req_count;
3208 /* validate possible error cases */
3209 if (req_rate > min_pf_rate) {
3210 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3211 "Vport [%d] - Requested rate[%d Mbps] is greater"
3212 " than configured PF min rate[%d Mbps]\n",
3213 vport_id, req_rate, min_pf_rate);
3217 if (req_rate * ECORE_WFQ_UNIT / min_pf_rate < 1) {
3218 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3219 "Vport [%d] - Requested rate[%d Mbps] is less than"
3220 " one percent of configured PF min rate[%d Mbps]\n",
3221 vport_id, req_rate, min_pf_rate);
3225 /* TBD - for number of vports greater than 100 */
3226 if (ECORE_WFQ_UNIT / p_hwfn->qm_info.num_vports < 1) {
3227 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3228 "Number of vports are greater than 100\n");
3232 if (total_req_min_rate > min_pf_rate) {
3233 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3234 "Total requested min rate for all vports[%d Mbps]"
3235 "is greater than configured PF min rate[%d Mbps]\n",
3236 total_req_min_rate, min_pf_rate);
3240 /* Data left for non requested vports */
3241 total_left_rate = min_pf_rate - total_req_min_rate;
3242 left_rate_per_vp = total_left_rate / non_requested_count;
3244 /* validate if non requested get < 1% of min bw */
3245 if (left_rate_per_vp * ECORE_WFQ_UNIT / min_pf_rate < 1)
3248 /* now req_rate for given vport passes all scenarios.
3249 * assign final wfq rates to all vports.
3251 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3252 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3254 for (i = 0; i < num_vports; i++) {
3255 if (p_hwfn->qm_info.wfq_data[i].configured)
3258 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3261 return ECORE_SUCCESS;
3264 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
3265 struct ecore_ptt *p_ptt,
3266 u16 vp_id, u32 rate)
3268 struct ecore_mcp_link_state *p_link;
3269 int rc = ECORE_SUCCESS;
3271 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
3273 if (!p_link->min_pf_rate) {
3274 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3275 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3279 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3281 if (rc == ECORE_SUCCESS)
3282 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3283 p_link->min_pf_rate);
3285 DP_NOTICE(p_hwfn, false,
3286 "Validation failed while configuring min rate\n");
3291 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
3292 struct ecore_ptt *p_ptt,
3295 int rc = ECORE_SUCCESS;
3296 bool use_wfq = false;
3299 num_vports = p_hwfn->qm_info.num_vports;
3301 /* Validate all pre configured vports for wfq */
3302 for (i = 0; i < num_vports; i++) {
3303 if (p_hwfn->qm_info.wfq_data[i].configured) {
3304 u32 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3307 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3308 if (rc == ECORE_INVAL) {
3309 DP_NOTICE(p_hwfn, false,
3310 "Validation failed while"
3311 " configuring min rate\n");
3317 if (rc == ECORE_SUCCESS && use_wfq)
3318 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3320 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3325 /* Main API for ecore clients to configure vport min rate.
3326 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3327 * rate - Speed in Mbps needs to be assigned to a given vport.
3329 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
3331 int i, rc = ECORE_INVAL;
3333 /* TBD - for multiple hardware functions - that is 100 gig */
3334 if (p_dev->num_hwfns > 1) {
3335 DP_NOTICE(p_dev, false,
3336 "WFQ configuration is not supported for this dev\n");
3340 for_each_hwfn(p_dev, i) {
3341 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3342 struct ecore_ptt *p_ptt;
3344 p_ptt = ecore_ptt_acquire(p_hwfn);
3346 return ECORE_TIMEOUT;
3348 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3350 if (rc != ECORE_SUCCESS) {
3351 ecore_ptt_release(p_hwfn, p_ptt);
3355 ecore_ptt_release(p_hwfn, p_ptt);
3361 /* API to configure WFQ from mcp link change */
3362 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
3367 /* TBD - for multiple hardware functions - that is 100 gig */
3368 if (p_dev->num_hwfns > 1) {
3369 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
3370 "WFQ configuration is not supported for this dev\n");
3374 for_each_hwfn(p_dev, i) {
3375 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3377 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
3383 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
3384 struct ecore_ptt *p_ptt,
3385 struct ecore_mcp_link_state *p_link,
3388 int rc = ECORE_SUCCESS;
3390 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3392 if (!p_link->line_speed)
3395 p_link->speed = (p_link->line_speed * max_bw) / 100;
3397 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, p_link->speed);
3399 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3400 "Configured MAX bandwidth to be %08x Mb/sec\n",
3406 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3407 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
3409 int i, rc = ECORE_INVAL;
3411 if (max_bw < 1 || max_bw > 100) {
3412 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
3416 for_each_hwfn(p_dev, i) {
3417 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3418 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
3419 struct ecore_mcp_link_state *p_link;
3420 struct ecore_ptt *p_ptt;
3422 p_link = &p_lead->mcp_info->link_output;
3424 p_ptt = ecore_ptt_acquire(p_hwfn);
3426 return ECORE_TIMEOUT;
3428 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3430 if (rc != ECORE_SUCCESS) {
3431 ecore_ptt_release(p_hwfn, p_ptt);
3435 ecore_ptt_release(p_hwfn, p_ptt);
3441 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
3442 struct ecore_ptt *p_ptt,
3443 struct ecore_mcp_link_state *p_link,
3446 int rc = ECORE_SUCCESS;
3448 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3450 if (!p_link->line_speed)
3453 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3455 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3457 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3458 "Configured MIN bandwidth to be %d Mb/sec\n",
3459 p_link->min_pf_rate);
3464 /* Main API to configure PF min bandwidth where bw range is [1-100] */
3465 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
3467 int i, rc = ECORE_INVAL;
3469 if (min_bw < 1 || min_bw > 100) {
3470 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
3474 for_each_hwfn(p_dev, i) {
3475 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3476 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
3477 struct ecore_mcp_link_state *p_link;
3478 struct ecore_ptt *p_ptt;
3480 p_link = &p_lead->mcp_info->link_output;
3482 p_ptt = ecore_ptt_acquire(p_hwfn);
3484 return ECORE_TIMEOUT;
3486 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
3488 if (rc != ECORE_SUCCESS) {
3489 ecore_ptt_release(p_hwfn, p_ptt);
3493 if (p_link->min_pf_rate) {
3494 u32 min_rate = p_link->min_pf_rate;
3496 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
3501 ecore_ptt_release(p_hwfn, p_ptt);
3507 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
3509 struct ecore_mcp_link_state *p_link;
3511 p_link = &p_hwfn->mcp_info->link_output;
3513 if (p_link->min_pf_rate)
3514 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
3515 p_link->min_pf_rate);
3517 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
3518 sizeof(*p_hwfn->qm_info.wfq_data) *
3519 p_hwfn->qm_info.num_vports);
3522 int ecore_device_num_engines(struct ecore_dev *p_dev)
3524 return ECORE_IS_BB(p_dev) ? 2 : 1;
3527 int ecore_device_num_ports(struct ecore_dev *p_dev)
3529 /* in CMT always only one port */
3530 if (p_dev->num_hwfns > 1)
3533 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);